L9908TR

L9908 Datasheet Automotive 3-Phase motor gate driver unit Features TQFP48 (exposed pad down) • • • • • • • • Product status link L9908 Product summary Order code L9908 L9908-TR • Package Packing TQFP48 (exp. pad down) Tray Tape&Reel • AEC-Q100 qualified Full ISO26262 compliant, ASIL-D systems ready VDH motor supply voltage range from 4.5 V to 75 V for working in single (12 V systems), double (24 V systems) and 48 V battery applications 3.3 V internal supply voltage generated from 5 V on VDD pin Digital I/O compatible to 3.3 V/5 V logics 6 separate N-channel FET pre-drivers: – dedicated source connection to each FET – the device can withstand -14 V to 95 V on motor connection pins – 0% to 100% duty cycle operation support – dedicated PWM input pin for each gate driver 3 differential high accuracy current monitors for ground referred current measurements: – ADC/DAC architecture – SPI adjustable Gain Factor and Output Offset – built-in error calibration – the device can withstand -14 V to 6 V on input sensing pins – SPI readable current measurement – 0 to 4.6 V DAC output dynamic range 3 real time phase voltage monitor channels: – SPI programmable phase voltage feedback; – SPI readable phase duty cycle measurement; 32-bit - 10 MHz SPI interface with 5-bit CRC and 1bit frame counter for internal setting, self-test and full diagnostics Protection and diagnostic: – SPI programmable VDS diagnostic and protection in on-state – SPI programmable Dead Time protection – SPI programmable Shoot-through diagnostic and protection – Open load, short to GND and short to battery diagnostic in off-state – Over-temperature diagnostic and protection with SPI programmable warning flag – SPI readable Tj measurement – Ground loss diagnostic – System clock monitoring – Power supply pins VDD, VDH, VBP over-voltage and under-voltage diagnostic – FET driver supply VPRE and VCP under-voltage and over-voltage diagnostic – SPI Window Watchdog – Fault status flag output DS13546 - Rev 3 - March 2022 For further information contact your local STMicroelectronics sales office. www.st.com L9908 Application • • • • • EPS – Electronic Power Steering HVAC Blowers – Heating, ventilation, and air conditioning Engine Cooling Fans Electronic Brake Booster EWP, EFP, EOP Description L9908 is a gate driver unit (GDU) for controlling 6 N-channel FETs for brushless motors in automotive applications. Each one of the 3 half bridge drivers channels (HS/LS couples) can be independently configured allowing different load driving and is able to withstand -14 V to 95 V excursion on motor`s pins. Through 6 dedicated parallel inputs the pre-driver stages can be controlled independently supporting duty cycle operations from 0% to 100% and allowing to implement all kinds of electric motor control strategy. A dedicated combination of regulators, charge pumps and bootstrap circuits allows L9908 to be suitable to operate in passenger, commercial or hybrid vehicles. Safe operation of half bridges is ensured by shoot-through diagnosis, dead-time, short to battery, short to ground and open load detection plus a real time phase voltage monitoring. L9908 is equipped with 3 independent high accuracy current monitor channels with SPI-configurable input differential voltage ranges for ground referenced current measurements, with 5 V/3.3 V output dynamic range compatibility. L9908 implements diagnostics on external and internal supply, ground level, internal temperature. A 32-bit out of frame SPI-slave interface is implemented for communication up to 10 MHz between L9908 and uC. SPI communication is safe-guarded by 5-bit CRC, 1bit frame counter, frame length check and an SPI-configurable Window Watchdog. DS13546 - Rev 3 page 2/153 L9908 Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram DS13546 - Rev 3 page 3/153 L9908 Block diagram and pin description Figure 2. Pin connection diagram (top view) Legenda: I = Input, O = Output, P = Power Supply, G = Ground, I/O = Input/Output Table 1. Pin list description Pin # Pin name 1 NCS 2 Pin type Class SPI Chip Select Input (Active LOW) I Local SCLK SPI Serial Clock Input I Local 3 SDI SPI Serial Data Input I Local 4 SDO SPI Serial Data Output O Local 5 VIO Power supply for digital output P Local O Local 6 DS13546 - Rev 3 Description CSO3/PVM Current monitor 3 analog output. Phase voltage feedback output 7 CSO2 Current monitor 2 analog output O Local 8 CSO1 Current monitor 1 analog output O Local 9 VDD Power supply input for internal circuitry and current monitors analog output (CSOn) P Local 10 SGND Signal Ground (Analog, Digital, Reference) G Local 11 EN_BR Bridge Enable Input (Active HIGH) I Local page 4/153 L9908 Block diagram and pin description Pin # Pin name 12 NDIS 13 Description Pin type Class Safe switch-off activation Input (Active LOW) I Local IS3- Current monitor 3 negative input I Local 14 IS3+ Current monitor 3 positive input I Local 15 IS2- Current monitor 2 negative input I Local 16 IS2+ Current monitor 2 positive input I Local 17 IS1- Current monitor 1 negative input I Local 18 IS1+ Current monitor 1 positive input I Local 19 SLS_3 Source connection of LS FET, phase 3 I/O Local 20 GLS_3 Gate connection of LS FET, phase 3 I/O Local 21 SLS_2 Source connection of LS FET, phase 2 I/O Local 22 GLS_2 Gate connection of LS FET, phase 2 I/O Local 23 SLS_1 Source connection of LS FET, phase 1 I/O Local 24 GLS_1 Gate connection of LS FET, phase 1 I/O Local 25 CBS_3 Bootstrap capacitor of HS, phase 3 I/O Local 26 GHS_3 Gate connection of HS FET, phase 3 I/O Local 27 SHS_3 Source connection of HS FET, phase 3 I/O Global 28 CBS_2 Bootstrap capacitor of HS, phase 2 I/O Local 29 GHS_2 Gate connection of HS FET, phase 2 I/O Local 30 SHS_2 Source connection of HS FET, phase 2 I/O Global 31 CBS_1 Bootstrap capacitor of HS, phase 1 I/O Local 32 GHS_1 Gate connection of HS FET, phase 1 I/O Local 33 SHS_1 Source connection of HS FET, phase 1 I/O Global 34 VDH Drain connection of HS FETs P Global 35 CP2P Charge Pump 2 positive input of fly capacitance I/O Local 36 CP2M Charge Pump 2 negative input of fly capacitance I/O Local 37 VBP P Global 38 CP1M Charge Pump 1 negative input of fly capacitance I/O Local Pre-regulation stage power supply 39 PGND Power Ground (Charge Pump 1 and 2) G Local 40 CP1P Charge Pump 1 positive input of fly capacitance I/O Local 41 VPRE Pre-regulated voltage for HS/LS Vgs driving I/O Local 42 INH3 PWM command for HS, phase 3 (Active HIGH) I Local 43 INH2 PWM command for HS, phase 2 (Active HIGH) I Local 44 INH1 PWM command for HS, phase 1 (Active HIGH) I Local 45 INL3 PWM command for LS, phase 3 (Active HIGH) I Local 46 INL2 PWM command for LS, phase 2 (Active HIGH) I Local 47 INL1 PWM command for LS, phase 1 (Active HIGH) I Local 48 FS_FLAG Fault status flag output (Active LOW) O Local Exp. PAD Cooling pad not electrically connected. Connect to GND plane on PCB Safety Related pin NDIS and EN_BR have the following characteristics: DS13546 - Rev 3 page 5/153 L9908 Block diagram and pin description Table 2. Safety related digital input pins functional partitioning Pins Default State Description NDIS Type B – Internal Resistance Pull-down SPI Pin (SPI communication related pin) EN_BR Type B – Internal Resistance Pull-down SPI Pin (SPI communication related pin) Table 3. NDIS and EN_BR electrical characteristics Symbol Parameter Test Condition Min Typ Max Unit Notes NDIS_ll_th NDIS Input Low Level -0.3 - 0.8 V - NDIS_hl_th NDIS Input High Level 2 - 65 V - NDIS filtering time 1 2.5 5 μs Analog filter -65 -40 -15 μA - T_ndis_flt NDIS_in_ipd NDIS Pull Down Current EN_BR_ll_th EN_BR Input Low Level -0.3 - 0.8 V - EN_BR _hl_th EN_BR Input High Level 2 - 65 V - EN_BR filtering time 1 2.5 5 μs Digital filter -65 -40 -15 μA - T_en_br_flt EN_BR _in_ipd EN_BR Pull Down Current NDIS = VIO EN_BR = VIO The state of Safety control pins EN_BR and NDIS is echoed into dedicated SPI readable bits EN_BR_ECHO and NDIS_ECHO in the register GEN_STATUS2. DS13546 - Rev 3 page 6/153 L9908 Absolute maximum ratings 2 Absolute maximum ratings In the following section the voltage ranges of each pin are described by dividing them into three categories: Functional Operating Range, Parametrical Operating Range and Absolute maximum rating. Figure 3. Pin voltage ranges 2.1 2.1.1 Maximum Operating Range (MOR) Functional Operating Range Within these operating ranges the part operates as specified in the circuit description, electrical characteristics are guaranteed only in the parametrical operating range, between these two ranges parametrical deviation may occur. The device may not operate properly if functional operating range conditions are exceeded. Once taken beyond the functional operative ratings and returned back within, the part will recover with no damage or degradation (provided that AMR range is not exceeded). All analog and digital voltages are related to the potential at signal ground SGND. All currents are assumed to be positive when current flows into the pin. Table 4. Functional operating conditions Symbol Parameter Min Typ Max Unit Notes VBP UV - VBP OV V Thermally limited VBP UV + HYST - V Power-Up VDH UV - V - VDH UV + HYST - V Power-Up VDD UV - V - VDD UV + HYST - V Power-Up 2.5 - 5.5 V - Power Supply VBP_MOR VBP_MOR_PU VDH_MOR VDH_MOR_PU VDD_MOR VDD_MOR_PU VIO_MOR VBP: voltage range VBP: voltage range for power up VDH: voltage range VDH: voltage range for power up VDD: voltage range VDD: voltage range for power up VIO: voltage range VDH OV VDD OV Gate Driver Supply d_CP1P_CP1M_MOR VPRE_MOR d_CP2P_CP2M_MOR DS13546 - Rev 3 CP1P - CP1M: Charge Pump1 external capacitance terminals differential voltage VPRE UV - VPRE OV V - VPRE: voltage range VPRE UV - VPRE OV V - CP2P – CP2M: Charge Pump2 external capacitance terminals differential voltage VPRE UV - VPRE OV V - page 7/153 L9908 Maximum Operating Range (MOR) Symbol Parameter Min Typ Max Unit Notes V Charge through BT charge limiter 1 only [n=1,2,3] Gate Drivers CBS_n – SHS_n: differential voltage d_CBSN_SHSN_MOR_BT1_MOR between CBS_n and SHS_n VPRE UV CBS_n – SHS_n: differential voltage d_CBSN_SHSN_MOR_BT2_MOR between CBS_n and SHS_n - VPRE OV BT_lim2_vlim (MIN) - BT_lim2_vlim (MAX) V Charge through BT charge limiter 2 only [n=1,2,3] d_GHSN_SHSN_MOR GHS_n – SHS_n: differential voltage between GHS_n and SHS_n 0 - CBS_n-SHS_n V [n=1,2,3] SHSN_MOR SHS_n: voltage range -12 - VDH +12 V [n=1,2,3] d_GLSN_SLSN_MOR GLS_n – SLS_n: differential voltage between GLS_n and SLS_n 0 - VPRE-SLS_n V [n=1,2,3] d_SLSN_MOR SLS_n: voltage range -12 - 2 V [n=1,2,3] -0.3 - 0.3 V [n=1,2,3] Current Monitors ISN_MOR ISn+ – ISn-: differential voltage between ISn+ and IS-n ISN_MOR ISn+/ISn-: common mode voltage range -2 - 2 V [n=1,2,3] CSON_MOR CSOn: voltage range 0 - VDD-0.4 V [n=1,2,3] Digital I/O Note: DS13546 - Rev 3 DO_MOR SDO, PVM, FS_FLAG: voltage range 0 - VIO V - DI_MOR NCS, SCLK, SDI, EN_BR, NDIS, INHn, INLn: voltage range 0 - VIO V [n=1,2,3] undershoot spikes at motor`s phase (SHS_n) take place when the high side is switched off and the load current must flow through the low-side freewheeling diode. page 8/153 L9908 Maximum Operating Range (MOR) Figure 4. 14 V pulse scenario - applicative condition The negative peak voltage reached during such a transition can be described by the following formula: SHSn peak = Vd_peak + LPAR_TOT dILOAD R + RPAR_TOT Iload tfall + sℎunt SHSn peak ≈ LPAR_TOT (1) dILOAD tfall (2) The first term Vd_peak is the transient peak voltage of the LS FET body diode, the second is due to transient response of the parasitic inductances between SHS_n and GND while the third is related to path resistance drop. Given the maximum current conducted, the application shall limit the maximum undershoot peak voltage by minimizing the ratio: LPAR_TOT tfall (3) (Ex: if Iload = 100 A then LPAR_TOT = 4 nH then tfall must be kept higher than 33 ns) The above-mentioned considerations also apply to SHS_n positive pulse which takes place when the inverter is working in generator mode. 2.1.2 Parametrical Operating Range Within these operating ranges the part operates as specified and without parameter deviations. The device may show parameters deviation if parametrical operating conditions are exceeded. Once taken beyond the operative ratings and returned back within, the part will recover with no damage or degradation (provided that AMR range is not exceeded). All analog and digital voltages are related to the potential at signal ground SGND. All currents are assumed to be positive when current flows into the pin. DS13546 - Rev 3 page 9/153 L9908 Absolute Maximum Ratings (AMR) Table 5. Parametrical operating conditions Symbol Parameter Test Condition Min Typ Max Unit Notes Power Supply VBP_MOR_PAR VBP: voltage range t ≤ 15 min 4.5 - 36 V - 36 - 48 V Jump Start Pulse 48 - 60 V Load Dump Pulse VBP_MOR_PAR_EXT1 VBP: extended voltage range 1 VBP_MOR_PAR_EXT2 VBP: extended voltage range 2 VDD_MOR_PAR_CSON VDD: voltage range (CSOn related parameter) - 4.85 5 5.15 V - VDD_MOR_PAR VDD: voltage range - 4. 5 5 5.5 V - VIO_MOR_PAR VIO: voltage range - 2.5 - 5.5 V - VPRE: voltage range - 7 - 15 V - VDH: voltage range - 4.5 - 52 V - 52 - 60 V Long Term Overvoltage 60 - 70 V Transient Overvoltage VPRE_MOR_PAR VDH_MOR_PAR VDH_MOR_PAR_EXT1 VDH: extended voltage range 1 VDH_MOR_PAR_EXT2 VDH: extended voltage range 2 Tamb = 25°C t ≤ 400 ms Tamb = 25°C t ≤ 60 min Tamb = 25°C t ≤ 40 ms Tamb = 25°C Note: All parameters are guaranteed and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. 2.2 Absolute Maximum Ratings (AMR) Maximum ratings are absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All analog and digital voltages are related to the potential at signal ground SGND. All currents are assumed to be positive when current flows into the pin. Table 6. Absolute maximum ratings Symbol Parameter Test Condition Min Typ Max Unit Notes -0.3 - 65(1) V - -1 - 65(1) V Not subject to production test -0.3 - 75(2) V -1 - 90 V Not subject to production test Power Supply VBP_AMR_DC VBP: DC voltage range VBP_AMR_AC VBP: transient voltage range VDH_AMR_DC VDH: DC voltage range. VDH_AMR_AC VDH: transient voltage range. t ≤ 400 ns; IVBP ≤ 500 mA t ≤ 400 ns; IVDH ≤ 500 mA VDH - VBP Differential voltage between VDH and VBP - -65 - 75 V - VDD_AMR VDD: voltage range - -0.3 - 20 V - VIO_AMR VIO: voltage range - -0.3 - 20 V - -0.3 - 65 V - d_VDH_VBP_AMR Gate Driver Supply CP1M_AMR DS13546 - Rev 3 CP1M: voltage range page 10/153 L9908 Absolute Maximum Ratings (AMR) Symbol Parameter Min Typ Max Unit Notes d_VBP_CP1M_AMR VBP - CP1M: Charge Pump1 external differential voltage between VBP and CP1M - -0.3 - 65 V - CP1P: voltage range - -0.3 - 20 V - d_CP1P_CP1M_AMR CP1P - CP1M: Charge Pump1 external capacitance terminals differential voltage - -65 - 20 V - d_VBP_CP1P_AMR VBP - CP1P: Charge Pump1 external differential voltage between VBP and CP1P - -20 - 65 V - d_VPRE_CP1P_AMR VPRE – CP1P: Charge Pump1 external differential voltage between VPRE and CP1P - -0.3 - 20 V - VPRE_AMR VPRE: voltage range - -0.3 - 20 V - CP2M_AMR CP2M: voltage range - -0.3 - 75 V - VPRE – CP2M: Charge Pump2 external differential voltage between VPRE and CP2M - -75 - 20 V - CP2P: voltage range - -0.3 - 95 V - d_CP2P_CP2M_AMR CP2P – CP2M: Charge Pump2 external capacitance terminals differential voltage - -20 - 75 V - d_VPRE_CP2P_AMR VPRE – CP2P: Charge Pump2 external differential voltage between VPRE and CP2P - -75 - 20 V - VDH – CP2P: Charge Pump2 external differential voltage between VDH and CP2P - -95 - 0.3 V - VDH+VPRE-SHS_n: constraint on simultaneous voltage on VDH, VPRE and SHS_n/GHS_n - - - 100(3) V Application information CP1P_AMR d_VPRE_CP2M_AMR CP2P_AMR d_VDH_CP2P_AMR d_VDH_VPRE_SHSN_AMR Test Condition [n=1,2,3] Gate Drivers CBS_n: DC voltage range in RESET VDD < VDD UV + HYST -0.3 - 95 V [n=1,2,3] CBS_AMR_DC CBS_n: DC voltage range VDD≥VDD UV + HYST -7(1) - 95 V [n=1,2,3] CBS_AMR_AC CBS_n: transient voltage range -14(1) - 95 V [n=1,2,3] Not subject to production test CBS_AMR_DC_RES DS13546 - Rev 3 VDD ≥ VDD UV + HYST t ≤ 200 ns d_CBSN_CP2P_AMR CBS_n - CP2P: differential voltage between CBS_n and CP2P terminals - -95 - 20 V [n=1,2,3] GHS_N_AMR_DC_RES GHS_n: DC voltage range in RESET VDD < VDD UV + HYST -0.3 - 95 V [n=1,2,3] GHS_N_AMR_DC GHS_n: DC voltage range VDD ≥ VDD UV + HYST -7 - 95 V [n=1,2,3] GHS_N_AMR_AC GHS_n: transient voltage range -14 - 95 V [n=1,2,3] Not subject to production test VDD ≥ VDD UV + HYST t ≤ 200 ns page 11/153 L9908 Absolute Maximum Ratings (AMR) Symbol Test Condition Min Typ Max Unit Notes SHS_n: DC voltage range in RESET VDD < VDD UV + HYST -0.3 - 95 V [n=1,2,3] SHS_N_AMR_DC SHS_n: DC voltage range VDD ≥ VDD UV + HYST -7 - 75 V [n=1,2,3] SHS_N_AMR_AC SHS_n: transient voltage range -14 - 95 V [n=1,2,3] Not subject to production test - - 20 V [n=1,2,3] Not subject to production test SHS_N_AMR_DC_RES SHS_N_AMR_SR VDD ≥ VDD UV + HYST t ≤ 200 ns SHS_n: transient slew rate SR ≤ 1V/ns d_CBSN_GHSN_AMR CBS_n - GHS_n: differential voltage between CBS_n and GHS_n terminals - -0.3 - 20 V [n=1,2,3] d_CBSN_SHSN_AMR CBS_n - SHS_n: Differential voltage between CBS_n and SHS_n - -0.3 - 20 V [n=1,2,3] d_GHSN_SHSN_AMR_DC GHS _n - SHS_n: Differential DC voltage between GHS_n and SHS_n - -0.3 - 20 V [n=1,2,3] d_GHSN_SHSN_AMR_AC GHS _n - SHS_n: Differential transient voltage between GHS_n and SHS_n t ≤ 200 ns; IGHS_n ≤ - 2A -2 - 20 V [n=1,2,3] Not subject to production test d_VDH_SHSN_AMR_RES VDH - SHS_n: Differential voltage between VDH and SHS_n in RESET VDD < VDD UV + HYST -0.3 - 95 V - d_VDH_SHSN_AMR VDH - SHS_n: Differential voltage between VDH and SHS_n VDD ≥ VDD UV + HYST -14 - 95 V [n=1,2,3] GLS_n: DC voltage range in RESET VDD < VDD UV + HYST -0.3 - 95 V [n=1,2,3] GLS_N_AMR GLS_n: DC voltage range VDD ≥ VDD UV + HYST -7 - 20 V [n=1,2,3] GLS_N_AMR_AC GLS_n: transient voltage range -14 - 20 V [n=1,2,3] Not subject to production test GLS_N_AMR_RES VDD ≥ VDD UV + HYST t ≤ 200 ns SLS_n: DC voltage range in RESET VDD < VDD UV + HYST -0.3 - 95 V [n=1,2,3] SLS_N_AMR_DC SLS_n: DC voltage range VDD ≥ VDD UV + HYST -7 - 20 V [n=1,2,3] SLS_N_AMR_AC SLS_n: transient voltage range -14 - 20 V [n=1,2,3] Not subject to production test SLS_N_AMR_DC_RES DS13546 - Rev 3 Parameter VDD ≥ VDD UV + HYST t ≤ 200 ns d_VPRE_GLSN_AMR VPRE - GLS_n: Differential voltage between VPRE and GLS_n - -0.3 - 35 V [n=1,2,3] d_VPRE_SLSN_AMR VPRE - SLS_n: Differential voltage between VPRE and SLS_n - -0.3 - 35 V [n=1,2,3] d_GLSN_SLSN_AMR_DC GLS_n - SLS_n: Differential voltage between GLS_n and SLS_n - 0(1) - 20 V [n=1,2,3] page 12/153 L9908 Absolute Maximum Ratings (AMR) Symbol d_GLSN_SLSN_AMR_AC Parameter GLS_n - SLS_n: Differential voltage between GLS_n and SLS_n Test Condition Min Typ Max Unit Notes t ≤ 200 ns; IGLS_n ≤-2A -2(1) - 20 V [n=1,2,3] Not subject to production test Current Monitors IS_AMR_DC_RES ISn+/ISn-: DC voltage range in RESET VDD < VDD UV + HYST -0.3 - 20 V [n=1,2,3] IS_AMR_DC ISn+/ISn-: DC common mode voltage range VDD ≥ VDD UV + HYST -7 - 20 V [n=1,2,3] IS_AMR_AC ISn+/ISn-: transient common mode voltage range -14 - 20 V [n=1,2,3] Not subject to production test VDD ≥ VDD UV + HYST t ≤ 200 ns ISn+ - ISn-: Differential voltage between ISn+ and ISn- - -5 - 5 V [n=1,2,3] VPRE - ISn+/ISn: Differential voltage between VPRE and ISn+/ISn - 0 - 40 V [n=1,2,3] Not subject to production test IS_AMR_SR ISn+/ISn-: common mode transient slew rate SR ≤ 1V/ns - - 20 V [n=1,2,3] Not subject to production test CSON_AMR CSOn: voltage range - -0.3 - 20 V [n=1,2,3] VIO – CSOn: differential voltage between VIO supply and CSOn outputs - -0.3 - 20 V [n=1,2,3] d_ISMPN_ISMN_AMR d_VPRE_IS_AMR d_VIO_CSON_AMR SPI Interface NCS_AMR NCS: voltage range - -0.3 - 20 V - SCLK_AMR SCLK: voltage range - -0.3 - 20 V - SDI_AMR SDI: voltage range - -0.3 - 20 V - SDO_AMR SDO: voltage range - -0.3 - 20 V - Digital I/O d_VIO_SDO_AMR VIO – SDO: differential voltage between VIO supply and SDO outputs - -0.3 - 20 V - d_VIO_PVF_AMR VIO – PVF: differential voltage between VIO supply and PVF outputs - -20 - 20 V - d_VIO_FSFLAG_AMR VIO – FS_FLAG: differential voltage between VIO supply and FS_FLAG outputs - -0.3 - 20 V - PVF_AMR PVF: voltage range - -0.3 - 20 V - FS_FLAG FS_FLAG: voltage range - -0.3 - 20 V - INHN_AMR INHn: voltage range - -0.3 - 20 V [n=1,2,3] INLN_AMR INLn: voltage range - -0.3 - 20 V [n=1,2,3] EN_BR: voltage range - -0.3 - 65 V - NDIS: voltage range - -0.3 - 65 V - -0.6 - 0.6 V - EN_BR _AMR NDIS _AMR Grounds GND_AMR SGND, PGND - 1. 36 V AMR over life-time. 48 V ≥ AMR ≥ 36 V for Jump Start transient pulse E-02 as defined in LV 124 standard and AMR ≥ 48 V for Load Dump Test B transient pulse as defined in ISO 16750-2 standard. DS13546 - Rev 3 page 13/153 L9908 ESD resistivity 2. 52 V AMR over life-time. 60 V ≥ AMR ≥ 52 V for E48-01a transient pulse, AMR ≥ 60 V for E48-02 transients pulse as defined in VDA_320/LV 148 standard. 3. The maximum voltage drop experienced by internal structures has to be limited to 100V in order to avoid damages. The HS pre-driver stage may experience together the maximum voltage and the minimum voltage all over L9908 respectively imposed by CP2 output voltage or CBS_n and SHS_n negative pulses. HS pre-driver then must be protected by ensuring that the absolute maximum voltage on CP2 or on CBS_n never takes place simultaneously with the absolute minimum voltage on SHS_n so that: VDH * VPRE - SHSn ≤ 100 W Note: Integrated protection and diagnostics are designed to prevent device damage under the fault conditions defined in the functional description. Fault conditions are considered to be out of normal operating range. Protection functions are not designed for a continuous repetitive operation. 2.3 ESD resistivity Table 7. ESD resistivity (pin level) Symbol HBM_LOC_ESD Parameter HBM (Local HBM_GLO_ESD HBM (Global CDM _ESD (1) CDM_COR_ESD LUT CDM Test Condition Min Typ Max Unit Notes -2 - 2 kV Class 2 VBP, VDH, SHS_n -4 - 4 kV Class 3A All pins -500 - 500 V Class C3 Corner pins -750 - 750 V Class C4 All pins -100 - 100 mA - Pins)(1) Pins)(1) All CDM (1) Latch Up (3) pins(2) 1. According to AEC-Q100-011 2. Pins are all GND connected together. 3. According to AEC-Q100-004 2.4 Temperature ranges and thermal data Table 8. Temperature ranges and thermal data Symbol Parameter Min Typ Max Unit Notes Tamb Operating temperature (ECU environment) -40 - 150 °C - T (1) j Operating junction temperature -40 - 150 °C - Tj Extended operating junction temperature -40 - 175 °C 200h over life time Storage temperature -55 - 150 °C - 31 - °C/W Homogeneous internal power distribution (3) - 2.1 - °C/W Homogeneous internal power distribution Tsto (2) RthJ-A Thermal resistance junction-to-ambient RThj-cb(2) Thermal resistance junction-to-case-bottom 1. All parameters are guaranteed and tested, in the temperature range Tj -40 ÷ 150°C unless otherwise specified. The device is still operative and functional at higher temperatures (up to Tj 175°C). Device functionality at high temperature is guaranteed by bench validation, electrical parameters are guaranteed by correlation with ATE tests at reduced temperature and adjusted limits (if needed). 2. Not subject to production test, guaranteed by design. 3. RthJA value is retrieved according to Jedec JESD51-2,-5,-7 guideline with a 2s2p board. DS13546 - Rev 3 page 14/153 L9908 Temperature ranges and thermal data Figure 5. 2s2p PCB with thermal vias Note: DS13546 - Rev 3 In “2s2p”, the “s” suffix stands for “Signal” and the number before indicates how many PCB layers are dedicated to signal wires. The “p” suffix stands for “Power” and the number before indicates how many PCB layers are dedicated to power planes. page 15/153 L9908 Current consumption 3 Current consumption Table 9. Quiescent current consumption in reset mode Symbol Parameter Test Condition IQ_VBP1 Quiescent consumption for VBP in reset mode IQ_VBP2 Quiescent consumption for VBP in reset mode IQ_VBP3 Quiescent consumption for VBP in reset mode IQ_VBP4 Quiescent consumption for VBP in reset mode IQ_VDH1 Quiescent consumption for VDH in reset mode IQ_VDH2 Quiescent consumption for VDH in reset mode IQ_VDH3 Quiescent consumption for VDH in reset mode IQ_VDH4 Quiescent consumption for VDH in reset mode IQ_VIO1 Quiescent consumption for VIO in reset mode IQ_VIO2 Quiescent consumption for VIO in reset mode VBP = 14 V, -40° ≤ Tj ≤ 25°C VDD = 0 V VBP = 14 V, 25°C < Tj ≤ 150°C VDD = 0 V VBP = 60 V, -40°C ≤ Tj ≤ 25°C VDD = 0 V VBP = 60 V, 25°C < Tj ≤ 150°C VDD = 0 V VDH = 14 V, -40°C ≤ Tj ≤ 25°C VDD = 0 V VDH = 14 V, 25°C IPD_TOT_PHy + IPD_TOT_PHz (21) Where: Ipu_totx is the equivalent pull-up current injected into the phase x (assuming phase x being configured as OFD_EN = 01) Ipd_toty and Ipd_totz are the equivalent pull-down currents injected respectively into the phase y and z (assuming phase y and z being configured as OFD_EN = 10) Figure 66. OFD currents in motor phases Blanking and Filtering To avoid false error detections during the diagnosis settling time and to increase noise robustness, the OSD implements a two-step digital filtering: an Up/Down counter of length equal to T_ofd_flt on the comparator`s output filters out the high frequency noise while a blanking time masks the filters output by a programmable delay time T_ofd_blank. Figure 67. OFD enabling and masking time start - IPU example DS13546 - Rev 3 page 92/153 L9908 Off State Diagnosis (OFD) Figure 68. OFD Masking and deglitch filtering - LSn_OFD Example Figure 69. OFD Masking and deglitch filtering - LSn_OFD Example with multiple glitches The T_ofd_blank can be configured by dedicated SPI bits as follows: Table 86. OFD blanking time configuration bits DS13546 - Rev 3 OFD_BLANK1 OFD_BLANK0 0 0 T_ofd_blank = 10 ms 0 1 T_ofd_blank = 25 ms 1 0 T_ofd_blank = 50 ms (Default) 1 1 T_ofd_blank = 100 ms Description page 93/153 L9908 On State Diagnosis (OND) Note: The application software must configure T_ofd_blank to ensure that the motor is not running and the phases are not energized. For some applications the maximum available T_ofd_blank configuration could be too short, the application SW then shall enable the OFD circuit with an additional delay after disabling the bridge drivers. Table 87. OFD electrical characteristics Symbol Parameter Test Condition Min Typ Max Unit Notes 2 2.7 3.1 V - - - 0.9 V - OFD_rvef OFD phase reference voltage in with no fault OFDn_EN = 01 OFD_vpd_ol OFD open load voltage in pd mode OFDn_EN = 10 OFD_ipu OFD pull up current capability OFDn_EN = 01 2.25 - 3.3 mA - OFD_ipd OFD pull down current capability OFDn_EN = 10 0.6 0.75 0.9 mA It includes ILEAK contribution OFD_scb_th OFD_SCB detection threshold - - SLS_n+1.7 - V Not subject to production test OFD_scg_th OFD_SCG detection threshold - - VDH-0.7 - V Not subject to production test T_ofd_flt OFD Fault detection filter time - 85 100 115 μs Digital filter CLK_SSM_EN = 0 -15 - 15 % - T_ofd_blank_acc OFD Blanking Time accuracy OFDi,j_EN = 10 SHS_n = No Load Note: All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. 5.15 On State Diagnosis (OND) L9908 implements a monitoring unit to detect failure condition affecting the load during the half bridges ON state by monitoring the voltage drain-source drop across the Ext. FET. The ON state diagnosis unit is composed by a dedicated VDS comparator for each HS and LS Ext. FET that constantly monitors the voltage drop during FET`s ON state. ON State Load Failure Mode Detection: • Short-circuit to ground at one SHS_n terminals → HSn_STG flag is set to 1 • Short-circuit to battery at one SHS_n terminals → LSn_STB flag is set to 1 The ON state diagnosis can be disabled by a dedicated SPI bit as follows: Table 88. OND enable bits ONDn_DIS Description 0 ON State diagnosis enabled on n-th HS and LS (Default) 1 ON State diagnosis disabled on n-th HS and LS When the OND monitoring is disabled while having the fault flag set, the flag will not be cleared until SPI read. If VDH-SHS_n ≥ V_ond_hs_th occurs for an interval longer than T_ond_flt filter time, the HSn_STG flag is set. The error flag remains set until the failure condition is removed and the flag is cleared by the SPI command. If SHS_n-SLSn ≥ V_ond_ls_th occurs for an interval longer than T_ond_flt filter time, the LSn_STB flag is set. The error flag remains set until the failure condition is removed and the flag is cleared by the SPI command. DS13546 - Rev 3 page 94/153 L9908 On State Diagnosis (OND) Figure 70. ON State Diagnosis simplified block diagram Threshold configuration The reference thresholds for the OND unit V_ond_th are generated through two 6-bit Current Steering DAC, one for HS and one for LS FETs. Diagnosis thresholds can be configured through dedicated SPI bits as follows: VOND_TH_HS = ΔLSB × VDS_HS_TH 5: 0 (22) VOND_TH_LS = ΔLSB × VDS_LS_TH 5: 0 (23) Where: ΔLSB is the minimum voltage step and VDS_HS_TH/VDS_LS_TH [5:0] in the register GEN_CFG2 there are the dedicated SPI configuration bits. Default value is VDS_HS_TH = VDS_LS_TH = 0x00. The default code equals the first non-zero code 0x01 which corresponds to a Vond_hs_th = 1LSB = 27 mV Blanking and Filtering The OND fault detection is based on the correlation between Vds voltage with the current conducted through ohm`s law; it turns out that a correct detection can be performed only when Ext. FET is in full RdsON mode. In order to prevent spurious short circuit detections due to an internal circuit voltage compression, the n-th OND monitor circuit is masked by the VDH UV diagnosis assertion. During a VDH UV condition OND fault detection is always prevented. In order to prevent spurious short circuit detections due to a non-linear operation region, the n-th OND monitor circuit is masked according to the internal n-th gate drive signal: • masking is removed after a programmable blanking time T_ond_blank from gate drive signal rising edge; • masking is re-activated soon after gate drive signal falling edge. The T_ond_blank can be configured by dedicated SPI bits as follows: Table 89. OND blanking time configuration bits DS13546 - Rev 3 OND_BLANK2 OND_BLANK1 OND_BLANK0 0 0 0 T_ond_blank = 0.7 μs 0 0 1 T_ond_blank = 1 μs 0 1 0 T_ond_blank = 1.5 μs (Default) 0 1 1 T_ond_blank = 2 μs 1 0 0 T_ond_blank = 2.5 μs Description page 95/153 L9908 On State Diagnosis (OND) Note: OND_BLANK2 OND_BLANK1 OND_BLANK0 Description 1 0 1 T_ond_blank = 3.5 μs 1 1 0 T_ond_blank = 5 μs 1 1 1 T_ond_blank = 8 μs The PWM ON time must be longer than T_ond_blank, else way the short circuit condition cannot be detected. In order to remove glitches and increase the detection capability of the system also at low Duty Cycles a cascaded filtering is introduced. Filtering action is developed by a digital up/down counter, incrementing the count at fault present and decrementing it at fault absent cumulating detections all over PWM cycles. The T_ond_flt can be configured by dedicated SPI bits as follows: Table 90. OND filtering time configuration bits OND_FLT1 OND_FLT0 Description 0 0 T_ond_flt= 1 μs 0 1 T_ond_flt = 2.5 μs 1 0 T_ond_flt = 4 μs (Default) 1 1 T_ond_flt = 8 μs Figure 71. OND blanking and filtering (VDS_LSn example), multiple fault DS13546 - Rev 3 page 96/153 L9908 On State Diagnosis (OND) Figure 72. OND blanking and filtering (VDS_LSn example), single fault Where: 1. LSn gate drive rising edge → T_ond_blank is elapsed comparator output masking is released; VSLn-VSHn > VDS_ond_th → LSn_STB comparator output is set to 1;T_ond_flt counter +1; LSn gate drive falling edge → comparator output masking is enabled → T_ond_flt counter freeze. 2. LSn gate drive rising edge → T_ond_blank is elapsed comparator output masking is released; VSLn-VSHn < VDS_ond_th → LSn_STB comparator output is set to 0; T_ond_flt counter -1; LSn gate drive falling edge → comparator output masking is enabled → T_ond_flt counter freeze. The correct operation OND stage is safety relevant and then a self-check procedure is implemented. Table 91. OND electrical characteristics Symbol Parameter OND_th_lsb VDS monitoring threshold step Test Condition - Min Typ Max Unit Notes - 27 - mV Not subject to production test -4.5 - 4.5 % 16x < VDS_HS/LH_TH < 3Fx -6 - 6 % Cx < VDS_HS/LH_TH < 16x -10 - 10 % 6x < VDS_HS/LH_TH < Cx -15 - 15 % 4x < VDS_HS/LH_TH < 6x 0.594 V < VDH OND_th_acc1 VDS monitoring thresholds accuracy 1 SHS_n < 1.7 V 0.594 V < SHS_nSLS_n < 1.7 V 0.324 V < VDH- OND_th_acc2 VDS monitoring thresholds accuracy 2 SHS_n < 0.594 V 0.324 V < SHS_nSLS_n < 0.594 V 0.162 V < VDH- OND_th_acc3 VDS monitoring thresholds accuracy 3 SHS_n < 0.324 V 0.162 V < SHS_nSLS_n < 0.324 V 0.081 V < VDH- OND_th_acc4 VDS monitoring thresholds accuracy 4 SHS_n < 0.162 V 0.081 V < SHS_nSLS_n < 0.162 V DS13546 - Rev 3 page 97/153 L9908 Phase Voltage Feedback (PVF) Symbol Parameter Test Condition Min Typ Max Unit Notes VDH-SHS_n VDS monitoring thresholds accuracy 5 OND_th_acc5 ≤ 0.081 V -12 - 12 mV OND Filtering Time accuracy CLK_SSM_EN = 0 -15 - 15 % - T_ond_blank_acc OND Blanking Time accuracy CLK_SSM_EN = 0 -15 - 15 % - SHS_n-SLS_n 0x < VDS_HS/LH_TH < 3x ≤ 0.081 V T_ond_flt_acc Note: All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. 5.16 Phase Voltage Feedback (PVF) L9908 implements three symmetric hysteretic comparators to monitor the level each motor phase voltage. This function allows a real time feedback on half bridges behavior in terms of phase voltage level and transition timing and actual phase’s duty cycle. Figure 73. Off State Diagnosis block diagram Each phase voltage comparator converts the output phase voltage into a digital signal by comparing it against a threshold proportional to VDH voltage so that: VDH-SHS_n ≥ PVFn_th_h: PVFn is set to 1. VDH-SHS_n ≤ PVFn_th_l: PVFn is set to 0. PVFn_th_h and PVFn_th_l are referred to as a specific percentage of the VDH voltage and can be configured by PVF_TH_CFG bits in the register GEN_CFG4, as follows: Table 92. PVF threshold selection bits PVF_TH_CFG 0 DS13546 - Rev 3 Description VPVF_TH_H = VDH*0.75 (Default) VPVF_TH_L = VDH*0.25 page 98/153 L9908 Phase Voltage Feedback (PVF) PVF_TH_CFG 1 Description VPVF_TH_H = VDH*0.6 VPVF_TH_L = VDH*0.4 Table 93. PVF electrical characteristics Symbol Min Typ Max Unit Notes PPVF_th_acc PVF thresholds accuracy -6.5 - 6.5 % - PPVF_th_match PVF thresholds matching -8 - 8 % - PPVF_htol_dly PVF high to low propagation delay - - 200 ns - PPVF_ltoh_dly PVF low to high propagation delay - - 200 ns - PVF propagation delay matching (phase vs. phase) - 10 30 ns - PVF propagation delay matching (single phase - rise to fall) - 20 35 ns - PPVF_dly_match PPVF_htol_ltoh_dly_match Note: Parameter All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. Figure 74. Phase voltage feedback behavior The state of PVF comparators is echoed into dedicated SPI readable registers PVFn_ECHO, in the register GEN_STATUS3. To save pin-count the phase comparator outputs are multiplexed to one single output pin CSO3/PVM. The selection of which phase comparators output can be configured by means of a dedicated SPI bit set as follows: DS13546 - Rev 3 page 99/153 L9908 Actuation Timers (ACT) Table 94. PVF output redirection selection bit 5.16.1 PVF_OUT_CFG0 PVF_OUT_CFG0 Description 0 0 PVF1 xor PVF2 xor PVF3 is output (Default) 0 1 PVF1 is output 1 0 PVF2 is output 1 1 PVF3 is output CSO3 - PVF multiplexing For pin saving purpose PVF and CSO3 outputs are multiplexed on the same pin and can be selected by CSO3_DIS bit in the register SAFETY_RELEVANT2: Table 95. CSO3-PVFn output multiplexing selection bits CSO3_DIS 5.17 Description 0 CSO3/PVM pin used a CM3 output (Default) 1 CSO3/PVM pin used a PVFn output Actuation Timers (ACT) L9908 implements an additional built-in feature which measures cycle by cycle the on or the off time windows applied to each phase either on INLn or on PVFn signals. This feature is performed by three dedicated 11-bit accumulators which count the number of clock cycles (CLK/8) fitting the time window. Figure 75. Actuation Timer simplified block diagram To allow the maximum flexibility against the time window to be measured, either positive or negative, timers can be configured by a proper SPI bit set to be run in negative or positive polarity so that the time is triggered respectively by the falling or the rising of the reference signal and stopped by the opposite edge. Table 96. Actuation Timers configuration bits DS13546 - Rev 3 ACT_CFG1 ACT_CFG0 0 0 PVF Negative Polarity (Default) 0 1 PVF Positive Polarity 1 0 INL Negative Polarity 1 1 INL Positive Polarity Description page 100/153 L9908 Actuation Timers (ACT) Figure 76. Actuation Timers timing diagram on ACT (positive & negative polarity) The content of the count is stored into a dedicated 11bit SPI read-only register ACTn. Reconstruction formula: TON − OFF = ΔACT_LSB × DACTn (24) Where: DACTn is the digital word stored in ACTn and ∆ACT_LSB is the ACT counter quantization step. Example: DACTn = 10001010101 (binary) à 1109 (decimal) ACT_CFG = 01 TON_PVF = 1109 *0.4 μs = 443.6 us ±50 ns In case the measured time window will exceed the maximum count allowed the counter overflow is flagged by setting to ‘1’ a dedicated SPI read-only register ACTn_OVF. Note: when ACT overflow condition is reached on n-th counter the ACTn value keeps the full-scale value until another counting window is started or the disabling of ACT function. The ACT function can be enabled according to the following SPI bits: Table 97. Actuation Timers enable bits ACT_EN Description 0 ACT Disabled (Default) 1 ACT Enabled Table 98. Actuation Timers electrical characteristics Symbol Parameter Test Condition Min Typ Max Unit Notes ACT_res ACT resolution - - 11 - bits Not subject to production test ACT_lsb ACT LSB - - 0.4 - μs Not subject to production test ACT_in_acc ACT accuracy CLK_SSM_EN = 0 -50 - 50 μs Not subject to production test Note: All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. Note: Internal counter is a 14-bit counter with LSB equal to 50 ns. ACT readout and TSYNC configuration however are available only through the internal counter 11MSB. DS13546 - Rev 3 page 101/153 L9908 Ground Loss Monitor (GLM) 5.18 Ground Loss Monitor (GLM) L9908 implements two ground reference pins, a Power Ground (PGND) dedicated as reference for the noisy, high power gate supply circuitry (CP1, CP2) and a Signal Ground (SGND) dedicated to the low power internal analog/digital circuitry. For EMI robustness the GND pin is internally split in two GND reference PADs: GND_ANA (ground reference for analog circuitry supplied from V3V3_ANA) and GND_DIG (ground reference for digital circuitry supplied by V3V3_DIG), GND_ANA is connected to the ESD GND ring by means of a direct metal connection and bias the substrate through SUB Plugs placed all around IC border. GND_ANA and PGND are connected to the ESD GND by means of a standard ESD protection for ground pins composed by a double couple of anti-parallel LV diodes. Figure 77. Ground pins inter-connection L9908 implements a monitoring unit to detect disconnection affecting ground references. If VPGND-VGND_ANA ≥ VTH_GND occurs for an interval longer than T_glm_loss_flt filtering time, the PGND_LOSS flag is set. If VGND_DIG-VGND_ANA ≥ VTH_GND occurs for an interval longer than T_glm_loss_flt filtering time, the DGND_LOSS flag is set. If VGND_DIG-VPGND ≥ VTH_GND occurs for an interval longer than T_glm_loss_flt filtering time, the AGND_LOSS flag is set. The correct operation Ground Loss Monitor stage is safety relevant and then a self-check procedure is implemented. Table 99. GLM electrical characteristics Symbol GLM_th T_glm_loss_flt Parameter GLM detection threshold VTH_GND GLM filter time Min Typ Max Unit 0.24 0.4 0.55 V 1 1.25 1.5 ms Notes Digital Filter Note: All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. 5.19 Temperature Monitor (OTM) L9908 implements a monitoring unit of the average junction temperature able to detect excessive over-heating conditions affecting the device. DS13546 - Rev 3 page 102/153 L9908 Temperature Monitor (OTM) Figure 78. Temperature monitor ADC characteristics The temperature measurement data are stored in a dedicated register and can be retrieved by SPI readout of TEMP_READ in the register GEN_TEMP_STATUS. The temperature can be retrieved by the following formula: T j ∘C = 1.37∘C × DTEMP_READ − 77.4∘C (25) Where: DTEMP_READ is the digital word stored in TEMP_READ. The digitized temperature information is compared by two hysteresis comparators with selectable threshold based on the following scheme: If DTEMP ≥ DTEMP_WR_TH occurs for an interval longer than T_otm_wr_flt filtering time, the OTM_WR flag is set. The error flag remains set until the failure condition is removed. If DTEMP ≥ DTEMP_SD_TH (= 185deg.) occurs for an interval longer than T_otm_sd_flt filtering time, the OTM_SD flag is set. The error flag remains set until the failure condition is removed and the flag is cleared by the SPI command. The thermal Warning threshold can be configured by the following SPI bit sets: Table 100. Thermal warning configuration bits TWN_CFG1 0 DS13546 - Rev 3 TWN_CFG0 0 Description 130 deg. page 103/153 L9908 Serial Peripheral Interface (SPI) TWN_CFG1 TWN_CFG0 Description 0 1 140 deg. (Default) 1 0 150 deg. 1 1 160 deg. Figure 79. Junction temperature ranges Temperature Range: Parametrical/Functional Range L9908 is in NORMAL mode: Gate Driver Supply is active, Half Bridge Gate Drivers stage is enabled, monitoring units are enabled and SPI registers are out of reset. No damage affects L9908 and no wrong operation takes place. All static and dynamic parameters stay within specification limits. Temperature Range: Critical OT Range L9908 is set into SAFE- OFF mode: Gate Driver Supply is disabled, Half Bridge Gate Drivers stage is disabled. No damage affects L9908 and no wrong operation takes place. Static and dynamic parameters may deviate from specification limits. Exposure to critical OT conditions for extended periods may affect device reliability. Table 101. OTM electrical characteristics Symbol Min Typ Max Unit OTM detection threshold hysteresis 5 10 15 °C Not subject to production test T_otm_wr_flt Thermal Warning filter time 10 20 30 μs Digital Filter T_otm_sd_flt Thermal Shutdown filter time 7 13 17.5 μs Digital Filter OTM_readout_res OTM Readout Resolution - 8 - - Not subject to production test OTM_readout_lsb OTM Readout LSB - 1.37 - °C Not subject to production test OTM ADC conversion accuracy -5 - 5 °C Temperature Read out accuracy OTM-sr OTM ADC sample rate - - 1 kHz Not subject to production test T_otm_start_up OTM ADC start up time - - 3 ms Not subject to production test OTM_th OTM_acc Note: 5.20 Parameter Notes All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. Serial Peripheral Interface (SPI) L9908 implements a standard 4-pin Serial Peripheral Interface (SPI) to access both IC configuration and diagnosis/status registers up to 10 MHz Baud Rate (up/down-stream). DS13546 - Rev 3 page 104/153 L9908 Serial Peripheral Interface (SPI) 5.20.1 Protocol description L9908 implement a SPI-slave interface based on a 32-bit protocol. This slave interface then always requires a SPI-master device (ex. uC) which is responsible to generate the selection and the synchronization signals (NCS, SCLK) necessary to the data transmission. The interface supports star mode connections along with other SPI-slave devices while it does not support daisy-chain mode connections (input data aren`t transmitted directly to output port). Figure 80. SPI connection modes "a" star connection (supported) "b" daisy-chain connection (not supported) The data exchange has an out-of-frame structure: each MISO output frame is related to the previously transmitted MOSI frame. SPI-master can directly verify if the previous frame has been received and processed correctly. NCS pin (chip select) is used by the SPI-master to enable/disable the data communication. Communication starts with the NCS falling edge while is stopped with the NCS rising edge. As long as NCS is high any transition at the SCLK and SDI pins (including glitches) is ignored and SDO is forced into a high impedance state. SCLK pin (Synchronous Serial Clock) is used by the SPI-master to synchronize the data communication. Each correct communication shall contain 32 SCLK pulses. At each SCLK rising edge SDI and SDO data are updated respectively by SPI-master and L9908 (shift), at each SCLK falling edge SDI and SDO data are sampled respectively by L9908 and SPI-master (capture). SCLK has to be low during NCS transition. SDI pin (Serial Data Input) is used by the SPI-master to deliver the 32-bit input frame to L9908. In MOSI communication the first bit expected is MSB while the last is LSB. SDO pin (Serial Data Output) is used by L9908 to transmit the 32-bit data output. In MISO communication the first bit transmitted is MSB while the last is LSB. Figure 81. SPI timing diagram Table 102. SPI timing characteristics Symbol SPI_fclk DS13546 - Rev 3 Parameter Transfer Frequency Test Condition 50% duty cycle(1) Min Typ Max Unit - 10 10.2 MHz page 105/153 L9908 Serial Peripheral Interface (SPI) Symbol Parameter Test Condition Min Typ Max Unit SCLK to data at SDO is valid SPI_tpcld_tsdo_trans Propagation delay Cload_max = 200 pF Including parasitics - - 100 ns NCS=LOW to data at SDO active Cload_max = 200 pF Inlcuding parasitics - - 200 ns SPI_tpchdz NCS L/H to SDO at high impedance Cload_max = 200 pF Including parasitics - - 200 ns SPI_tsclch SCLK before NCS low (2) 50 - - ns SPI_thclcl SCLK change L/H after NCS=LOW (2) 130 - - ns SPI_tsclcl SCLK low before NCS high (2) 50 - - ns SCLK high after NCS high (2) 50 - - ns SDI input setup time (2) 20 - - ns SPI_thcld SDI input hold time (2) - - 20 ns SPI_tonNCS NCS min. high time (2) 650 - - ns SPI_tclh Minimum Time SCLK=HIGH (2) 45 - - ns SPI_tcll Minimum Time SCLK=LOW (2) 45 - - ns Input pin capacitance (2) - - 30 pF MISO output pin capacitance in tri-state (2) - - 50 pF SPI_tcsdv SPI_thclch SPI_tscld SPI_Cin SPI_Cout_hiz 1. SPI max frequency may be less depending on the total capacitive load or MCU timing requirements. 2. Not subject to production test, guaranteed by design. Note: DS13546 - Rev 3 All parameters are guaranteed, and tested, in the voltage ranges reported above in Table 5 unless otherwise specified. Where not specified the parametrical operating range equals the functional operating range. page 106/153 L9908 Serial Peripheral Interface (SPI) 5.20.2 Frame description The 32-bit SPI frames content is divided as follows: Table 103. MOSI - SPI frame description Bit 31 30-23 22 21 20-5 4-0 MOSI R/W ADDRESS RSV/TM FC DATA WRITE CRC MOSI Stream: [31] R/W Flag. Selects if the current operation is a read (0) operation or write (1) operation. [30-23] SPI register address [22] Test Mode Flag [21] Frame Counter [20-5] Data Write [4-0] CRC checksum generated by SPI-master Table 104. MISO - SPI frame description Bit 31 30-29 28-21 20-5 4-0 MISO SPI ERR IC ERR ADDRESS FB DATA READ CRC MISO Stream: [31] SPI Error Flag. Provide information related to the previous stream. [30-29] IC Error Flag. Provide information related to IC high level error. [28-21] SPI register address feedback. Last received valid frame address feedback. [20-5] Data Read. Data contents of SPI register addressed by last received valid frame. [4-0] CRC checksum generated by SPI-slave 5.20.2.1 Write-Read operations 1st Frame: Write Access to R/W Register X As the NCS rising edge is detected, if it is valid, the command is processed and the R/W register X is updated with data Y. After the register X is updated correctly the output buffer is updated as well. 2nd Frame: Read Access As the NCS falling edge is detected, the register X with data Y is started being shifted out on MISO bus. The X register data remains unchanged as R/W bit is zero, the following MISO frame will be updated with the same data. The first SPI frame after an internal reset (i.e. INT_RST) will have a fixed content: • IC_ERR and SPI_ERR flag all 0 • Address Feedback all = 0 • Data all = 0 DS13546 - Rev 3 page 107/153 L9908 Serial Peripheral Interface (SPI) Figure 82. SPI Write-Read operation 5.20.2.2 Read-Read operations 1st Frame: Read Access to Register X As the NCS rising edge is detected, if it is valid, the command is processed but the R/W register X register data remains unchanged as R/W bit is zero and the output buffer is updated with data Y1. 2nd Frame: Read Access to Register X As the NCS falling edge is detected, the register X with data Y1 is started being shifted out on MISO bus. The X register data remains unchanged as R/W bit is zero, the following MISO frame will be updated with the data Y2. Figure 83. SPI Read-Read operation 5.20.2.3 Clear on Read Operations 1st Frame: Read Access to Register X As the NCS rising edge is detected, if it is valid, the command is processed but the R/W register X register data remains unchanged as R/W bit is zero and the output buffer is updated with data Y1. After the output buffer is updated correctly the X register flags are cleared. 2nd Frame: Read Access to Register X As NCS falling edge is detected, the register X with data Y1 is started being shifted out on MISO bus. DS13546 - Rev 3 page 108/153 L9908 Serial Peripheral Interface (SPI) Figure 84. SPI Clear on Read operation DS13546 - Rev 3 page 109/153 L9908 Serial Peripheral Interface (SPI) 5.20.3 Frame monitoring Correct SPI communication is safety relevant and then the following safety mechanism is implemented. Cyclic Redundancy Check (CRC) MISO/MOSI SPI data are protected with a 5-bit CRC using the following polynomial expression: G x = x5 + x2 + 1 (26) The initial value to be used is 11111 (0x1F). CRC is calculated over bit 5-31 except bit 21 (Hamming distance of 3 over 26 bit data), MSB First. Example: Read register 0x4A command (data = 0) Frame: [0 0100:1010 0 0 0000:0000:0000:0000 10001] (0x25000011) Frame: [0 0100:1010 0 1 0000:0000:0000:0000 10001] (0x25200011) CRC is 10001 independently on FC value. Write 0xABCD to register 0xC7 command Frame: [1 1100:0111 0 0 1010:1011:1100:1101 11000] (0xE39579B8) Frame: [1 1100:0111 0 1 1010:1011:1100:1101 11000] (0xE3B579B8) CRC is 11000b independently on FC value. Frame Counter Check (FC) A 1-bit frame counter is transmitted by the SPI-master within every MOSI frame to support the detection of failures in the communication channel (ex. corrupted or missing frames). The initial value to be used is 0. Clock Counter Check L9908 implements two separate clock counters for the rising and the falling edges of SCLK clock to check the length of the MOSI frame to be equal to 32. The clock counters reset is generated from the detection of a rising edge of NCS. 5.20.4 Error handling In case of an error either regarding the SPI word length (clock counter), frame counter bit value (FC) or wrong CRC check, the SPI_ERR bit is set to ‘1’ and the frame is ignored by L9908. The SPI error bit always refers to the previous SPI frame. The register SPI_CMM_FAULT contains specific bits indicating which SPI fault occurred on the previous frame. After reading, register value will be reset. Refer to the next section for details. 5.20.5 Register description Legenda: Safety Description: • NSR = Non-safety Relevant Register • SLR = Safety Latent Register • SSR = Safety Relevant Register Operation Type: • RW = Read/Write • RO = Read Only • CR = Clear on Read Reset Source: • A = INT_RST • B = INT_RST || CFG_RST • D = INT_RST (excluded CLK1_TIMEOUT) Table 105. CHIPID DS13546 - Rev 3 Register Name Address CHIPID 0x0 Field Name UNUSED_9 Type Bit Offset Bit Width Reset Value Reset RO 15 1 0x0 B page 110/153 L9908 Serial Peripheral Interface (SPI) Register Name Address NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_8 RO 14 1 0x0 B UNUSED_7 RO 13 1 0x0 B UNUSED_6 RO 12 1 0x0 B UNUSED_5 RO 11 1 0x0 B UNUSED_4 RO 10 1 0x0 B UNUSED_3 RO 9 1 0x0 B UNUSED_2 RO 8 1 0x0 B UNUSED_1 RO 7 1 0x0 B UNUSED_0 RO 6 1 0x0 B METAL_ID RO 3 3 0x0 B SILICON_ID RO 0 3 0x1 B Table 106. GEN_CFG1 Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 15 1 0x0 B RW 14 1 0x0 B RW 13 1 0x0 B RW 11 2 0x01 B RW 8 3 0x0 B RW 5 3 0x2 B WDT_EN GEN_CFG1 0x2 0: Watchdog disabled (Default) 1: Watchdog enabled CLK_SSM_EN 0: Clock SSM Disabled (Default) 1: Clock SSM Enabled CSM_OUT_RANGE_CFG CSM_SSPV_PH_CFG 00: No synchronization 01: TSYNC based on Phase 1 (Default) 10: TSYNC based on Phase 2 11: TSYNC based on Phase 3 CSM_LP_CFG 000: No filtering (Default) 001: 91kHz SLR 010: 37kHz 011: 17kHz 100: 8kHz 101: 4kHz 110: 2kHz 111: 1kHz DTP_CFG 000: 0us - DTP Disabled 001: 0.25us 010: 0.35us 011: 0.5us 100: 1us - Default 101: 1.5us DS13546 - Rev 3 page 111/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 4 1 0x0 B RW 3 1 0x0 B RW 2 1 0x0 B RW 1 1 0x0 B RW 0 1 0x0 B 110: 2us 111: 4us SR_CRC_FAIL_REDIRECT_CFG VBP_OV_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked VBP_UV_REDIRECT_CFG SLR 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked VDH_OV_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked VDH_UV_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked Table 107. GEN_CFG2 Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 14 2 0x0 B RW 12 2 0x2 B VDS_HS_TH RW 6 6 0x0 B VDS_LS_TH RW 0 6 0x0 B ACT_CFG 00: PVF Negative Polarity (Default) GEN_CFG2 0x3 01: PVF Positive Polarity 10: INL Negative Polarity 11: INL Positive Polarity OFD_BLANK 00: T_ofd_blank = 10ms 01: T_ofd_blank = 25ms 10: T_ofd_blank = 50ms (Default) SLR 11: T_ofd_blank = 100ms Table 108. GE_CFG3 Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 14 2 0x1 B RW 13 1 0x0 B TWN_CFG 00: 130deg. GEN_CFG3 0x4 01: 140deg. (Default) 10: 150deg. 11: 160deg. STP3_VGS_DIS SLR DS13546 - Rev 3 0: Shoot-through protection on FET Vgs enabled (Default) page 112/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 12 1 0x0 B RW 11 1 0x0 B RW 10 1 0x0 B RW 9 1 0x0 B RW 8 1 0x0 B RW 6 2 0x0 B RW 5 1 0x0 B RW 3 2 0x2 B RW 0 3 0x2 B 1: Shoot-through protection on FET Vgs disabled STP2_VGS_DIS 0: Shoot-through protection on FET Vgs enabled (Default) 1: Shoot-through protection on FET Vgs disabled STP1_VGS_DIS 0: Shoot-through protection on FET Vgs enabled (Default) 1: Shoot-through protection on FET Vgs disabled STP3_PWM_DIS 0: Shoot-through protection on PWM input enabled (Default) 1: Shoot-through protection on PWM input disabled STP2_PWM_DIS 0: Shoot-through protection on PWM input enabled (Default) 1: Shoot-through protection on PWM input disabled STP1_PWM_DIS 0: Shoot-through protection on PWM input enabled (Default) SLR 1: Shoot-through protection on PWM input disabled UNUSED_0 BT1_DIS 0: Bootstrap Limiter 1 Enabled (Default) 1: Bootstrap Limiter 1 Disabled OND_FLT 00: T_ond_flt = 1 μs 01: T_ond_flt = 2.5 μs 10: T_ond_flt = 4 μs (Default) 11: T_ond_flt = 8 μs OND_BLANK 000: T_ond_blank = 0.7u 001: T_ond_blank = 1 μs 010: T_ond_blank = 1.5 μs (Default) 011: T_ond_blank = 2 μs 100: T_ond_blank = 2.5 μs 101: T_ond_blank = 3.5 μs 110: T_ond_blank = 5 μs 111: T_ond_blank = 8 μs Table 109. GEN_CFG4 DS13546 - Rev 3 Register Name Address GEN_CFG4 0x5 Field Name PVF_OUT_CFG Type Bit Offset Bit Width Reset Value Reset RW 14 2 0x0 B page 113/153 L9908 Serial Peripheral Interface (SPI) Register Name Type Bit Offset Bit Width Reset Value Reset RW 13 1 0x0 B RW 12 1 0x0 B RW 11 1 0x1 B RW 6 5 0x1F B HB3_ACK RW 5 1 0x1 B HB2_ACK RW 4 1 0x1 B HB1_ACK RW 3 1 0x1 B RW 2 1 0x0 B RW 1 1 0x0 B RW 0 1 0x0 B Address Field Name 00: PVF1 xor PVF2 xor PVF3 is output (Default) 01: PVF1 is output 10: PVF2 is output 11: PVF3 is output PVF_TH_CFG 0: VPVF_TH_H = VDH*0.75 (Default) VPVF_TH_L = VDH*0.25 1: VPVF_TH_H = VDH*0.6 VPVF_TH_L = VDH*0.4 UNUSED_0 DRV_HIZ 0: Pre-drivers in NO high impedance 1: Pre-drivers in high impedance (Default) SELF_TEST_CFG4 0: OND LS Self-Test Not Active 1: OND LS Self-Test Active (Default) SELF_TEST_CFG3 0: OND HS Self-Test Not Active 1: OND HS Self-Test Active (Default) SELF_TEST_CFG2 0: Supply Monitors Self-Test Not Active 1: Supply Monitors Self-Test Active (Default) SLR SELF_TEST_CFG1 0: SW Off Path Self-Test Not Active 1: SW Off Path Self-Test Active (Default) SELF_TEST_CFG0 0: Clock Monitor Self-Test Not Active 1: Clock Monitor Self-Test Active (Default) HB3_DIS 0: 3rd HS/LS drivers is enabled (Default) 1: 3rd HS/LS drivers is disabled HB2_DIS 0: 2nd HS/LS drivers is enabled (Default) 1: 2nd HS/LS drivers is disabled HB1_DIS 0: 1st HS/LS drivers is enabled (Default) 1: 1st HS/LS drivers is disabled DS13546 - Rev 3 page 114/153 L9908 Serial Peripheral Interface (SPI) Table 110. GEN_STATUS1 Register Name Address GEN_STATUS1 0x6 NSR Field Name Type Bit Offset Bit Width Reset Value Reset AGND_LOSS CR 15 1 0x0 A DGND_LOSS CR 14 1 0x0 A PGND_LOSS CR 13 1 0x0 A NVM_CRC_FAIL RO 12 1 0x0 A VDD_OV CR 11 1 0x0 A SELF_TEST_STATUS RO 9 2 0x0 D SR_CRC_FAIL CR 8 1 0x0 A CLK2_ERR CR 7 1 0x0 A UNUSED_0 RO 6 1 0x0 A CLK1_ERR CR 5 1 0x0 A CLK2_TIMEOUT CR 4 1 0x0 A CLK1_TIMEOUT CR 3 1 0x0 D SAFE_STATE RO 2 1 0x1 A CFG_RST CR 1 1 0x1 B INT_RST CR 0 1 0x1 A Table 111. GEN_STATUS2 Register Name Address GEN_STATUS2 0x7 NSR Field Name Type Bit Offset Bit Width Reset Value Reset INL3_ECHO RO 15 1 0x0 A INL2_ECHO RO 14 1 0x0 A INL1_ECHO RO 13 1 0x0 A INH3_ECHO RO 12 1 0x0 A INH2_ECHO RO 11 1 0x0 A INH1_ECHO RO 10 1 0x0 A NDIS_ECHO RO 9 1 0x1 A EN_BR_ECHO RO 8 1 0x0 A VBP_OV CR 7 1 0x0 A VBP_UV CR 6 1 0x0 A VDH_OV CR 5 1 0x0 A VDH_UV CR 4 1 0x0 A VCP_OV CR 3 1 0x0 A VCP_UV CR 2 1 0x0 A VPRE_OV CR 1 1 0x0 A VPRE_UV CR 0 1 0x0 A Table 112. GEN_STATUS3 Register Name Address GEN_STATUS3 0x8 NSR DS13546 - Rev 3 Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_4 RO 15 1 0x0 A UNUSED_3 RO 14 1 0x0 A page 115/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset CP2_EN_ECHO RO 13 1 0x1 A CP1_EN_ECHO RO 12 1 0x1 A HB3_EN_ECHO RO 11 1 0x1 A HB2_EN_ECHO RO 10 1 0x1 A HB1_EN_ECHO RO 9 1 0x1 A UNUSED_0 RO 6 3 0x0 A RO 3 3 0x0 A PVF3_ECHO RO 2 1 0x0 A PVF2_ECHO RO 1 1 0x0 A PVF1_ECHO RO 0 1 0x0 A OPERATION_MODE 000: RESET Mode 001: NVM Read Mode NSR 010: SAFE OFF Mode 011: NORMAL Mode 100: CFG Mode 101: SELF TEST Mode 110: RESET Mode 111: RESET Mode Table 113. GEN_TEMP_STATUS Register Name Address GEN_TEMP_STATUS 0x9 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_5 RO 15 1 0x0 A UNUSED_4 RO 14 1 0x0 A UNUSED_3 RO 13 1 0x0 A UNUSED_2 RO 12 1 0x0 A UNUSED_1 RO 11 1 0x0 A UNUSED_0 RO 10 1 0x0 A OTM_SD CR 9 1 0x0 A OTM_WR CR 8 1 0x0 A TEMP_READ RO 0 8 0x0 A Table 114. SW_RESET Register Name Address SW_RESET 0xA NSR DS13546 - Rev 3 Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_7 RO 15 1 0x0 A UNUSED_6 RO 14 1 0x0 A UNUSED_5 RO 13 1 0x0 A UNUSED_4 RO 12 1 0x0 A UNUSED_3 RO 11 1 0x0 A UNUSED_2 RO 10 1 0x0 A UNUSED_1 RO 9 1 0x0 A UNUSED_0 RO 8 1 0x0 A page 116/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 0 8 0x0 A Type Bit Offset Bit Width Reset Value Reset UNUSED_2 RO 15 1 0x0 A UNUSED_1 RO 14 1 0x0 A RW 12 2 0x1 A RW 10 2 0x3 A RW 8 2 0x1 A WDT_GRAY RO 4 4 0x0 A WDT_BINARY RW 0 4 0x0 A SW_RESET_KEY NSR 0xCC: SW Reset Activation Table 115. WDT_CFG_CMD Register Name Address WDT_CFG_CMD 0xB Field Name WDT_RESET 00: NO Reset 01: NO Reset (Default) 10: Reset 11: NO Reset WDT_FAIL_COUNT_CFG 00: 1 01: 1 NSR 10: 2 11: 3 (Default) WDT_OVF_CFG 00: 11.26 ms 01: 22.52 ms (Default) 10: 45.04 ms 11: 90.11 ms Table 116. WDT_STATUS Register Name Address WDT_STATUS 0xC NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_4 RO 15 1 0x0 A UNUSED_3 RO 14 1 0x0 A UNUSED_2 RO 13 1 0x0 A UNUSED_1 RO 12 1 0x0 A UNUSED_0 RO 11 1 0x0 A WDT_FAIL_COUNT_STATUS RO 9 2 0x0 A WDT_OVF_STATUS RO 3 6 0x0 A WD_ON_STATUS RO 2 1 0x0 A WDT_DATA_FAIL RO 1 1 0x0 A WDT_OVF_FAIL RO 0 1 0x0 A Table 117. BIST_KEY DS13546 - Rev 3 Register Name Address BIST_KEY 0xD Field Name UNUSED_7 Type Bit Offset Bit Width Reset Value Reset RO 15 1 0x0 B page 117/153 L9908 Serial Peripheral Interface (SPI) Register Name Address NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_6 RO 14 1 0x0 B UNUSED_5 RO 13 1 0x0 B UNUSED_4 RO 12 1 0x0 B UNUSED_3 RO 11 1 0x0 B UNUSED_2 RO 10 1 0x0 B UNUSED_1 RO 9 1 0x0 B UNUSED_0 RO 8 1 0x0 B RW 0 8 0x0 B BIST_KEY 0x55 --> 0x33 SELF TEST Mode Access Table 118. CFG_EN_UNLOCK Register Name Address CFG_EN_UNLOCK 0xE NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_7 RO 15 1 0x0 B UNUSED_6 RO 14 1 0x0 B UNUSED_5 RO 13 1 0x0 B UNUSED_4 RO 12 1 0x0 B UNUSED_3 RO 11 1 0x0 B UNUSED_2 RO 10 1 0x0 B UNUSED_1 RO 9 1 0x0 B UNUSED_0 RO 8 1 0x0 B RW 0 8 0x0 B CFG_EN_UNLOCK 0x55 --> 0x33: CONFIG Mode Access 0xAA: CONFIG Mode Exit Table 119. SAFETY_RELEVANT1 Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 15 1 0x0 B RW 13 2 0x0 B RW 11 2 0x0 B RW 9 2 0x0 B FS_FLAG_CFG SAFETY_RELEVANT1 0x10 0: Push-pull (Default) 1: Open-drain UNUSED_0 VBP_OV_REACT_CFG 00: Full SW Off – disable all HB drivers and CPs, device is sent in SAFE-OFF mode (Default) SSR 01: Reduced Operation Mode – disable failing HB only, device remains in NORMAL mode 10: Flag only – down-rate fault to simple warning, device remains in NORMAL mode 11: Flag only – down-rate fault to simple warning, device remains in NORMAL mode VBP_UV_REACT_CFG DS13546 - Rev 3 page 118/153 L9908 Serial Peripheral Interface (SPI) Register Name Type Bit Offset Bit Width Reset Value Reset VDH_OV_REACT_CFG RW 7 2 0x0 B VDH_UV_REACT_CFG RW 5 2 0x0 B CRC RW 0 5 0x17 B Type Bit Offset Bit Width Reset Value Reset RW 15 1 0x0 B RW 14 1 0x0 B RW 13 1 0x0 B RW 12 1 0x0 B RW 10 2 0x0 B RW 7 3 0x7 B RW 5 2 0x0 B RW 0 5 0x17 B Address SSR Field Name Table 120. SAFETY_RELEVANT2 Register Name Address Field Name CSO3_DIS SAFETY_RELEVANT2 0x11 0: CSO3/PVM pin used a CM3 output (Default) 1: CSO3/PVM pin used a PVFn output CS3_DIS 0: current monitor enabled (Default) 1: current monitor disabled CS2_DIS 0: current monitor enabled (Default) 1: current monitor disabled CS1_DIS 0: current monitor enabled (Default) 1: current monitor disabled VDH_FLT_CFG 00: 12.25 μs (Defaults) 01: 25 μs 10: 50 μs 11: 100 μs SSR VDH_OV_CFG 000: 12 V Systems 1 001: 12 V Systems 2 010: 24 V Systems 1 011: 24 V Systems 2 100: 48 V Systems 1 101: 48 V Systems 2 110: 48 V Systems 3 111: 48 V Systems 4 (Defaults) VDH_UV_CFG 00: 12 V Systems (Defaults) 01: 24 V Systems 10: 48 V Systems 11: VDH UV Disabled CRC DS13546 - Rev 3 page 119/153 L9908 Serial Peripheral Interface (SPI) Table 121. SAFETY_RELEVANT3 Register Name Address SAFETY_RELEVANT3 0x12 Field Name Type Bit Offset Bit Width Reset Value Reset CP2_DIS 0: Charge Pump 2 Enabled (Default) RW 15 1 0x0 B RW 14 1 0x0 B UNUSED_2 RW 13 1 0x0 B UNUSED_1 RW 12 1 0x0 B UNUSED_0 RW 11 1 0x0 B RW 9 2 0x0 B RW 7 2 0x0 B RW 5 2 0x0 B RW 0 5 0x17 B 1: Charge Pump 2 Disabled CP1_DIS 0: Charge Pump 1 Enabled (Default) 1: Charge Pump 1 Disabled VBP_FLT_CFG 00: 12.25 μs (Defaults) 01: 25 μs 10: 50 μs 11: 100 μs SSR VBP_OV_CFG 00: 12 V Systems 1 01: 12 V Systems 2 10: 24 V Systems 1 11: 24 V Systems 2 (Defaults) VBP_UV_CFG 00: 12 V Systems (Defaults) 01: 24 V Systems 10: 48 V Systems 11: VBP UV Disabled CRC Table 122. CH1_STATUS1 Register Name Address CH1_STATUS1 0x20 NSR DS13546 - Rev 3 Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_7 RO 15 1 0x0 A UNUSED_6 RO 14 1 0x0 A UNUSED_5 RO 13 1 0x0 A UNUSED_4 RO 12 1 0x0 A UNUSED_3 RO 11 1 0x0 A UNUSED_2 RO 10 1 0x0 A LS1_OFF RO 9 1 0x0 A HS1_OFF RO 8 1 0x0 A LS1_STB CR 7 1 0x0 A HS1_STG CR 6 1 0x0 A LS1_OFD RO 5 1 0x0 A HS1_OFD RO 4 1 0x0 A UNUSED_1 CR 3 1 0x0 A page 120/153 L9908 Serial Peripheral Interface (SPI) Register Name Address NSR Field Name Type Bit Offset Bit Width Reset Value Reset STP_VGS_1 CR 2 1 0x0 A STP_PWM_1 CR 1 1 0x0 A UNUSED_0 RO 0 1 0x0 A Table 123. CH1_STATUS2 Register Name Address CH1_STATUS2 0x21 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_0 RO 15 1 0x0 A CM1_READ RO 0 15 0x0 A Table 124. CH1_CFG1 Register Name Address CH1_CFG1 0x22 Field Name UNUSED_1 Type Bit Offset Bit Width Reset Value Reset RW 11 5 0x0 B RW 9 2 0x0 B RW 8 1 0x0 B RW 7 1 0x0 B RW 6 1 0x0 B RO 15 1 0x0 A RW 4 1 0x0 B RW 2 2 0x0 B RW 0 2 0x0 B OFD1_EN 00: Off State Diagnosis disabled (Default) 01: Pull-up current enabled, Pull-down current disabled 10: Pull-down current enabled, Pull-up current disabled 11: Off State Diagnosis disabled OND1_DIS 0: ON State diagnosis enabled on HS and LS (Default) 1: ON State diagnosis disabled on HS and LS LS1_STB_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked HS1_STG_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) SLR 1: Fault redirection masked UNUSED_0 STP_VGS_1_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked STP1_VGS_CFG 00: 0.2 μs (Defaults) 01: 0.5 μs 10: 1 μs 11: 1.5 μs STP1_PWM_CFG 00: 0.2 μs (Defaults) 01: 0.5 μs 10: 1 μs 11: 1.5 μs DS13546 - Rev 3 page 121/153 L9908 Serial Peripheral Interface (SPI) Table 125. CH1_CFG2 Register Name Address CH1_CFG2 0x23 Field Name Type Bit Offset Bit Width UNUSED Reset Value Reset RW 11 5 0x0 B RW 9 2 0x0 B RW 8 1 0x0 B RW 5 3 0x0 B RW 2 3 0x5 B RW 0 2 0x3 B CSM1_SYNC_COUNT_CFG 00: 16Tclk (Default) 01: 24Tclk 10: 32Tclk 11: 40Tclk UNUSED_0 CSM1_SAMPLE_CFG 000: Free running – No T&H (Default) 001: T&H 1st data conversion from triggering 010: T&H 2nd data conversion from triggering 011: T&H 3rd data conversion from triggering 100: T&H 4th data conversion from triggering 101: T&H 5th data conversion from triggering 110: T&H 6th data conversion from triggering SLR 111: T&H 7th data conversion from triggering CSM1_IN_RANGE_CFG 000: VIN_MAX = ±7 mV 001: VIN _MAX =±18 mV 010: VIN _MAX =±36 mV 011: VIN_MAX = ±90 mV 100: VIN_MAX = ±160 mV 101: VIN_MAX = ±300 mV (Default) 110: Reserved 111: Reserved CSM1_OFS 00: 0LSB DAC 01: 90LSB DAC 10: 1024LSB DAC 11: 1024LSB DAC (Default) Table 126. CH1_CFG3 Register Name Address CH1_CFG3 0x24 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_3 RW 15 1 0x0 B UNUSED_2 RW 14 1 0x0 B UNUSED_1 RW 13 1 0x0 B UNUSED_0 RW 12 1 0x0 B RW 11 1 0x0 B RW 0 11 0x0 B ACT1_EN 0: ACT Disabled (Default) 1: ACT Enabled TSYNC1_CFG DS13546 - Rev 3 page 122/153 L9908 Serial Peripheral Interface (SPI) Table 127. CH1_SAFETY_RELEVANT Register Name Address CH1_SAFETY_RELEVANT 0x25 Type Bit Offset Bit Width Reset Value Reset UNUSED_4 RW 15 1 0x0 B UNUSED_3 RW 14 1 0x0 B UNUSED_2 RW 13 1 0x0 B RW 11 2 0x0 B UNUSED_1 RW 10 1 0x0 B UNUSED_0 RW 9 1 0x0 B LS1_STB_REACT_CFG RW 7 2 0x0 B HS1_STG_REACT_CFG RW 5 2 0x0 B CRC RW 0 5 0x17 B Field Name STP_VGS_1_REACT_CFG 00: Full SW Off – disable all HB drivers and CPs, device is sent in SAFE-OFF mode (Default) 01: Reduced Operation Mode – disable failing HB only, device is remain in NORMAL mode 10: Flag only – down-rate fault to simple warning, device is remain in NORMAL mode SRR 11: Flag only – down-rate fault to simple warning, device is remain in NORMAL mode Table 128. CH1_ACT Register Name Address CH1_ACT 0x26 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_3 RO 15 1 0x0 A UNUSED_2 RO 14 1 0x0 A UNUSED_1 RO 13 1 0x0 A UNUSED_0 RO 12 1 0x0 A ACT1_OVF RO 11 1 0x0 A ACT1 RO 0 11 0x0 A Table 129. CH2_STATUS1 Register Name Address CH2_STATUS1 0x28 NSR DS13546 - Rev 3 Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_7 RO 15 1 0x0 A UNUSED_6 RO 14 1 0x0 A UNUSED_5 RO 13 1 0x0 A UNUSED_4 RO 12 1 0x0 A UNUSED_3 RO 11 1 0x0 A UNUSED_2 RO 10 1 0x0 A LS2_OFF RO 9 1 0x0 A HS2_OFF RO 8 1 0x0 A LS2_STB CR 7 1 0x0 A page 123/153 L9908 Serial Peripheral Interface (SPI) Register Name Address NSR Field Name Type Bit Offset Bit Width Reset Value Reset HS2_STG CR 6 1 0x0 A LS2_OFD RO 5 1 0x0 A HS2_OFD RO 4 1 0x0 A UNUSED_1 CR 3 1 0x0 A STP_VGS_2 CR 2 1 0x0 A STP_PWM_2 CR 1 1 0x0 A UNUSED_0 RO 0 1 0x0 A Table 130. CH2_STATUS2 Register Name Address CH2_STATUS2 0x29 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_0 RO 15 1 0x0 A CM2_READ RO 0 15 0x0 A Table 131. CH2_CFG1 Register Name Address CH2_CFG1 0x2A Field Name UNUSED_1 Type Bit Offset Bit Width Reset Value Reset RW 11 5 0x0 B RW 9 2 0x0 B RW 8 1 0x0 B RW 7 1 0x0 B RW 6 1 0x0 B RO 15 1 0x0 A RW 4 1 0x0 B RW 2 2 0x0 B RW 0 2 0x0 B OFD2_EN 00: Off State Diagnosis disabled (Default) 01: Pull-up current enabled, Pull-down current disabled 10: Pull-down current enabled, Pull-up current disabled 11: Off State Diagnosis disabled OND2_DIS 0: ON State diagnosis enabled on HS and LS (Default) 1: ON State diagnosis disabled on HS and LS LS2_STB_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked HS2_STG_REDIRECT_CFG SLR 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked UNUSED_0 STP_VGS_2_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked STP2_VGS_CFG 00: 0.2 μs (Defaults) 01: 0.5 μs 10: 1 μs 11: 1.5 μs STP2_PWM_CFG 00: 0.2 μs (Defaults) DS13546 - Rev 3 page 124/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset 01: 0.5 μs SLR 10: 1 μs 11: 1.5 μs Table 132. CH2_CFG2 Register Name Address CH2_CFG2 0x2B Field Name Type Bit Offset Bit Width UNUSED Reset Value Reset RW 11 5 0x0 B RW 9 2 0x0 B RW 8 1 0x0 B RW 5 3 0x0 B RW 2 3 0x5 B RW 0 2 0x3 B CSM2_SYNC_COUNT_CFG 00: 16Tclk (Default) 01: 24Tclk 10: 32Tclk 11: 40Tclk UNUSED_0 CSM2_SAMPLE_CFG 000: Free running – No T&H (Default) 001: T&H 1st data conversion from triggering 010: T&H 2nd data conversion from triggering 011: T&H 3rd data conversion from triggering 100: T&H 4th data conversion from triggering 101: T&H 5th data conversion from triggering 110: T&H 6th data conversion from triggering SLR 111: T&H 7th data conversion from triggering CSM2_IN_RANGE_CFG 000: VIN_MAX = ±7mV 001: VIN _MAX = ±18 mV 010: VIN _MAX = ±36 mV 011: VIN_MAX = ±90 mV 100: VIN_MAX = ±160 mV 101: VIN_MAX = ±300 mV (Default) 110: Reserved 111: Reserved CSM2_OFS 00: 0LSB DAC 01: 90LSB DAC 10: 1024LSB DAC 11: 1024LSB DAC (Default) Table 133. CH2_CFG3 Register Name Address CH2_CFG3 0x2C NSR DS13546 - Rev 3 Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_3 RW 15 1 0x0 B UNUSED_2 RW 14 1 0x0 B page 125/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_1 RW 13 1 0x0 B UNUSED_0 RW 12 1 0x0 B RW 11 1 0x0 B RW 0 11 0x0 B ACT2_EN NSR 0: ACT Disabled (Default) 1: ACT Enabled TSYNC2_CFG Table 134. CH2_SAFETY_RELEVANT Register Name Address CH2_SAFETY_RELEVANT 0x2D Type Bit Offset Bit Width Reset Value Reset UNUSED_4 RW 15 1 0x0 B UNUSED_3 RW 14 1 0x0 B UNUSED_2 RW 13 1 0x0 B RW 11 2 0x0 B UNUSED_1 RW 10 1 0x0 B UNUSED_0 RW 9 1 0x0 B LS2_STB_REACT_CFG RW 7 2 0x0 B HS2_STG_REACT_CFG RW 5 2 0x0 B CRC RW 0 5 0x17 B Field Name STP_VGS_2_REACT_CFG 00: Full SW Off – disable all HB drivers and CPs, device is sent in SAFE-OFF mode (Default) 01: Reduced Operation Mode – disable failing HB only, device remains in NORMAL mode 10: Flag only – down-rate fault to simple warning, device remains in NORMAL mode SRR 11: Flag only – down-rate fault to simple warning, device remains in NORMAL mode Table 135. CH2_ACT Register Name Address CH2_ACT 0x2E NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_3 RO 15 1 0x0 A UNUSED_2 RO 14 1 0x0 A UNUSED_1 RO 13 1 0x0 A UNUSED_0 RO 12 1 0x0 A ACT2_OVF RO 11 1 0x0 A ACT2 RO 0 11 0x0 A Table 136. CH3_STATUS1 DS13546 - Rev 3 Register Name Address CH3_STATUS1 0x30 Field Name UNUSED_7 Type Bit Offset Bit Width Reset Value Reset RO 15 1 0x0 A page 126/153 L9908 Serial Peripheral Interface (SPI) Register Name Address NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_6 RO 14 1 0x0 A UNUSED_5 RO 13 1 0x0 A UNUSED_4 RO 12 1 0x0 A UNUSED_3 RO 11 1 0x0 A UNUSED_2 RO 10 1 0x0 A LS3_OFF RO 9 1 0x0 A HS3_OFF RO 8 1 0x0 A LS3_STB CR 7 1 0x0 A HS3_STG CR 6 1 0x0 A LS3_OFD RO 5 1 0x0 A HS3_OFD RO 4 1 0x0 A UNUSED_1 CR 3 1 0x0 A STP_VGS_3 CR 2 1 0x0 A STP_PWM_3 CR 1 1 0x0 A UNUSED_0 RO 0 1 0x0 A Table 137. CH3_STATUS2 Register Name Address CH3_STATUS2 0x31 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_0 RO 15 1 0x0 A CM3_READ RO 0 15 0x0 A Table 138. CH3_CFG1 Register Name Address CH3_CFG1 0x32 Type Bit Offset Bit Width Reset Value Reset RW 11 5 0x0 B RW 9 2 0x0 B RW 8 1 0x0 B RW 7 1 0x0 B RW 6 1 0x0 B UNUSED_0 RO 15 1 0x0 A STP_VGS_3_REDIRECT_CFG RW 4 1 0x0 B Field Name UNUSED_1 OFD3_EN 00: Off State Diagnosis disabled (Default) 01: Pull-up current enabled, Pull-down current disabled 10: Pull-down current enabled, Pull-up current disabled 11: Off State Diagnosis disabled OND3_DIS 0: ON State diagnosis enabled on HS and LS (Default) 1: ON State diagnosis disabled on HS and LS SLR LS3_STB_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked HS3_STG_REDIRECT_CFG 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked DS13546 - Rev 3 page 127/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset RW 2 2 0x0 B RW 0 2 0x0 B 0: Fault redirected on FS_FLAG/IC ERR (Default) 1: Fault redirection masked STP3_VGS_CFG 00: 0.2 μs (Defaults) 01: 0.5 μs 10: 1 μs SLR 11: 1.5 μs STP3_PWM_CFG 00: 0.2 μs (Defaults) 01: 0.5 μs 10: 1 μs 11: 1.5 μs Table 139. CH3_CFG2 Register Name Address CH3_CFG2 0x33 Field Name UNUSED Type Bit Offset Bit Width Reset Value Reset RW 11 5 0x0 B RW 9 2 0x0 B RW 8 1 0x0 B RW 5 3 0x0 B RW 2 3 0x5 B RW 0 2 0x3 B CSM3_SYNC_COUNT_CFG 00: 16Tclk (Default) 01: 24Tclk 10: 32Tclk 11: 40Tclk UNUSED_0 CSM3_SAMPLE_CFG 000: Free running – No T&H (Default) 001: T&H 1st data conversion from triggering 010: T&H 2nd data conversion from triggering 011: T&H 3rd data conversion from triggering 100: T&H 4th data conversion from triggering SLR 101: T&H 5th data conversion from triggering 110: T&H 6th data conversion from triggering 111: T&H 7th data conversion from triggering CSM3_IN_RANGE_CFG 000: VIN_MAX = ±7 mV 001: VIN _MAX = ±18 mV 010: VIN _MAX = ±36 mV 011: VIN_MAX = ±90 mV 100: VIN_MAX = ±160 mV 101: VIN_MAX = ±300 mV (Default) 110: Reserved 111: Reserved CSM3_OFS 00: 0LSB DAC DS13546 - Rev 3 page 128/153 L9908 Serial Peripheral Interface (SPI) Register Name Address Field Name Type Bit Offset Bit Width Reset Value Reset 0 0 01: 90LSB DAC 10: 1024LSB DAC SLR 11: 1024LSB DAC (Default) 0 0 0 0 Table 140. CH3_CFG3 Register Name Address CH3_CFG3 0x34 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_3 RW 15 1 0x0 B UNUSED_2 RW 14 1 0x0 B UNUSED_1 RW 13 1 0x0 B UNUSED_0 RW 12 1 0x0 B RW 11 1 0x0 B RW 0 11 0x0 B ACT3_EN 0: ACT Disabled (Default) 1: ACT Enabled TSYNC3_CFG Table 141. CH3_SAFETY_RELEVANT Register Name Address CH3_SAFETY_RELEVANT 0x35 Type Bit Offset Bit Width Reset Value Reset UNUSED_4 RW 15 1 0x0 B UNUSED_3 RW 14 1 0x0 B UNUSED_2 RW 13 1 0x0 B RW 11 2 0x0 B UNUSED_1 RW 10 1 0x0 B UNUSED_0 RW 9 1 0x0 B LS3_STB_REACT_CFG RW 7 2 0x0 B HS3_STG_REACT_CFG RW 5 2 0x0 B CRC RW 0 5 0x17 B Field Name STP_VGS_3_REACT_CFG 00: Full SW Off – disable all HB drivers and CPs, device is sent in SAFE-OFF mode (Default) 01: Reduced Operation Mode – disable failing HB only, device remains in NORMAL mode SRR 10: Flag only – down-rate fault to simple warning, device remains in NORMAL mode 11: Flag only – down-rate fault to simple warning, device remains in NORMAL mode DS13546 - Rev 3 page 129/153 L9908 Window Watchdog Timer (WTD) Table 142. CH3_ACT Register Name Address CH3_ACT 0x36 NSR Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_3 RO 15 1 0x0 A UNUSED_2 RO 14 1 0x0 A UNUSED_1 RO 13 1 0x0 A UNUSED_0 RO 12 1 0x0 A ACT3_OVF RO 11 1 0x0 A ACT3 RO 0 11 0x0 A Table 143. SPI_CMM_FAULT Register Name Address SPI_CMM_FAULT 0xFD Field Name Type Bit Offset Bit Width Reset Value Reset UNUSED_11 RO 15 1 0x0 A UNUSED_10 RO 14 1 0x0 A UNUSED_9 RO 13 1 0x0 A CR 12 1 0x0 A CR 11 1 0x0 A CR 10 1 0x0 A CR 9 1 0x0 A UNUSED_8 RO 8 1 0x0 A UNUSED_7 RO 7 1 0x0 A UNUSED_6 RO 6 1 0x0 A UNUSED_5 RO 5 1 0x0 A UNUSED_4 RO 4 1 0x0 A UNUSED_3 RO 3 1 0x0 A UNUSED_2 RO 2 1 0x0 A UNUSED_1 RO 1 1 0x0 A UNUSED_0 RO 0 1 0x0 A FCNTERR Wrong Frame Counter bit CRCERR Wrong CRC check value SHORTERR Previous SPI frame length32 bit Window Watchdog Timer (WTD) L9908 implements a watchdog timer function to ensure a safe SPI communication with μC in case of corrupted or lost SPI communication. DS13546 - Rev 3 page 130/153 L9908 Window Watchdog Timer (WTD) Figure 85. Watchdog Timer simplified block diagram Watchdog timer function can be enabled by the SPI signal WDT_EN in the register GEN_CFG1: Table 144. Watchdog enable bit WDT_EN Description 0 Watchdog disabled (Default) 1 Watchdog enabled Once enabled, WDT_EN can be reset to disable only by INT_RST = 0 or CFG_RST = 0. Activation status of WDT is also stored in the SPI read only register WD_ON_STATUS: WD_ON_STATUS = 0 WDT is not active, WD_ON_STATUS = 1 WDT is active. As soon as the watchdog is enabled the overflow counter is started thus defining the available refresh window Twdt_ovf which length is defined by the SPI register WDT_OVF_CFG. Table 145. Watchdog configuration table for WDT overflow timer WDT_OVF_CFG1 WDT_OVF_CFG0 0 0 11.26 ms 0 1 22.52 ms (Default) 1 0 45.04 ms 1 1 90.11 ms Description The WDT overflow counter status can be accessed through the dedicated SPI read only register WDT_OVF_STATUS. The counter value in seconds can be retrieved by the following reconstruction formula: TWTD_OVF − STATUS = ΔWTD_OVF_LSB × DWTD_OVF_STATUS (27) Where: DWDT_OVF is the digital word stored in WDT_OVF_STATUS and ∆WDT_OVF_LSB is the counter LSB as defined in Table 146. Table 146. WDT overflow timer LSB WDT_OVF_CFG DS13546 - Rev 3 Description 00 0.2048 ms 01 0.4096 ms (Default) 10 0.8192 ms page 131/153 L9908 Window Watchdog Timer (WTD) WDT_OVF_CFG 11 Description 1.6384 ms Reprogramming of WDT_OVF_CFG configuration is possible only while WDT_EN = 0 Table 147. WDT overflow counter accuracy Symbol WDT_ovf_acc Parameter WDT overflow counter accuracy Min Typ Max Unit -10 - 10 % Within this window the watchdog expects a refresh pulse to reset the overflow counter and restart a new window: if refresh is missed before the overflow counter is elapsed the error flag WDT_OVF_Fail is set and L9908 is sent to safe state. The flag remains set until the WDT is reset by the SPI command or re-enabled after a power-on sequence. Figure 86. WDT Operation – Overflow timer failure The refresh of the overflow counter has to be performed by the uC through a dedicated SPI frame including the 4-bit watchdog refresh command. The watchdog circuitry compares the received watchdog refresh command with an internal look-up table and answers with a corresponding 4-bit Gray code in the next SPI MISO frame. Table 148. Watchdog Binary to Gray answer conversion Binary (μC) → Gray (L9908) Binary → (μC) → Gray (L9908) Binary (μC) → Gray (L9908) Binary (μC) → Gray (L9908) 0x0 (0000) → 0x0 (0000) 0x4 (0100) → 0x6 (0110) 0x8 (1000) → 0xC (1100) 0xC (1100) → 0xA (1010) 0x1 (0001) → 0x1 (0001) 0x5 (0101) → 0x7 (0111) 0x9 (1001) → 0xD (1101) 0xD (1101) → 0xB (1011) 0x2 (0010) → 0x3 (0011) 0x6 (0110) → 0x5 (0101) 0xA (1010) → 0xF (1111) 0xE (1110) → 0x9 (1001) 0x3 (0011) → 0x2 (0010) 0x7 (0111) → 0x4 (0100) 0xB (1011) → 0xE (1110) 0xF (1111) → 0x8 (1000) The expected watchdog command order starts with number 0x0 (0000) and is incremented by 1 at each refresh window if the command is correctly interpreted and no failure is detected. Once command number 0xF (1111) is reached the sequence restarts with number 0x0 (0000). DS13546 - Rev 3 page 132/153 L9908 Window Watchdog Timer (WTD) Figure 87. Watchdog command order sequence In case of a wrong WDT data command (command different from the expected sequence order), the watchdog word fail counter is incremented by 1. With the next valid watchdog data command the fail counter is decreased by 1. If the failure counter reaches the failure limit defined in the SPI register WDT_FAIL_COUNT_CFG the watchdog fail flag WDT_DATA_fail is set and L9908 is sent to safe state. The fail counter limit can be programmed by the following SPI bit set: Table 149. Watchdog configuration table for WDT data fail counter WDT_FAIL_COUNT_CFG1 WDT_FAIL_COUNT_CFG0 0 0 1 0 1 1 1 0 2 1 1 3 (Default) Description The information about the number of encountered WDT data failures is stored in the dedicated SPI register WDT_FAIL_COUNT_STATUS. DS13546 - Rev 3 page 133/153 L9908 Window Watchdog Timer (WTD) Figure 88. WDT Operation – Word sequence failure In case of failure (WDT_OVF_fail =1 or WDT_DATA_fail =1) the WDT can be reset by setting to10 the SPI register command WDT_RESET. Table 150. Watchdog RESET bits Note: DS13546 - Rev 3 WDT_RST1 WDT_RST0 0 0 NO Reset 0 1 NO Reset (Default) Description 1 0 Reset 1 1 NO Reset This command is processed by the logic only if a failure is detected (WDT_OVF_fail = 1 or WDT_DATA_fail = 1). The WDT_RESET doesn’t reset the WDT_EN bit but only the error flag: µC needs to refresh the WDT properly afterwards. page 134/153 L9908 Window Watchdog Timer (WTD) Figure 89. WDT Operation – WDT Reset after overflow timer failure DS13546 - Rev 3 page 135/153 L9908 Application circuit 6 Application circuit 6.1 12 V/24 V systems Figure 90. Application circuit, 12 V/24 V systems DS13546 - Rev 3 page 136/153 L9908 48 V systems 6.2 48 V systems Figure 91. Application circuit, 48 V systems 6.3 Bill of materials The following table summarizes the suggested BOM for both systems shown on Figure 90 and Figure 91. Table 151. Application circuit - BOM Component Min Typ Max Unit DS13546 - Rev 3 Minimum requirement 12 V systems 24 V systems 48 V systems 50 V 100 V Comment CBR1 - 390 - nF CBSn - 1 - μF 25 V CCSO1 - 220 - pF 6.3 V CCSO2 - 220 - pF 6.3 V CCSO3 - 220 - pF 6.3 V CDC1 - 10 - nF 6.3 V Max tolerance ±5% to be mounted close to RDC CDC2 - 10 - nF 6.3 V Max tolerance ±5% to be mounted close to RDC CDCd - 220 - nF 6.3 V To be mounted close to pin With RCSO1,2,3, is mandatory for CSO signal stability page 137/153 L9908 Bill of materials Component Min Typ Max Unit DS13546 - Rev 3 Minimum requirement 12 V systems 24 V systems 48 V systems Comment CFLY1 - 1 - μF 50 V 100 V - CFLY2 - 1 - μF 50 V 100 V - CGHSn - - - 16 V Optional CGLSn - - - 16 V Optional CHB1n - 100 - nF 50 V 100 V - CHB2n - 220 - μF 50 V 100 V - CINHn - 10 - pF 6.3 V Optional CINLn - 10 - pF 6.3 V Optional CS1n - 10 - nF 6.3 V Max tolerance ±5% to be mounted close to RSHUNTn CS2n - 10 - nF 6.3 V Max tolerance ±5% to be mounted close to RSHUNTn CSdn - 220 - nF 6.3 V To be mounted close to pin CVBAT1 - 100 - nF 50 V 100 V - CVBAT2 - 10 - μF 50 V 100 V - CVBP1 - 1 - μF 50 V 100 V 16 V - CVBP2 - 100 - nF 50 V 100 V 16 V To be mounted close to pin CVBP3 - 100 - nF 50 V - CVDD1 - 1 - μF 6.3 V - CVDD2 - 100 - nF 6.3 V To be mounted close to pin CVDH1 - 100 - nF 50 V 100 V To be mounted close to pin CVDH2 - 1 - μF 50 V 100 V - CVIO1 - 1 - μF 6.3 V - CVIO2 - 100 - nF 6.3 V To be mounted close to pin CVPRE1 - 4.7 6.8 μF 16 V Max tolerance ±20% CVPRE1 - 4.7 6.8 μF CVPRE2 - 100 - nF D1 - - - SMA6T39AY SMA6T56AY D2 - - - Short SMA6T6V7AY DBR1 - - - - STPS3L60 - DBR2 - - - - STPS0520Z - RVBP1 - 22 - kΩ - - RVBP2 - 22 - kΩ - - RBR1 - 1 - kΩ - - RBR2 - 39 - kΩ - - RBR3 - 22 - kΩ - - RCSO1 - 1 - kΩ - RCSO2 - 1 - kΩ - n.a. n.a. 16 V Max tolerance ±20% 16 V To be mounted close to pin n.a. - With CCSO1,2,3, is mandatory for CSO signal stability page 138/153 L9908 Layout guidelines Component Min Typ Max Unit 6.4 Minimum requirement 12 V systems Comment 24 V systems 48 V systems With CCSO1,2,3, is mandatory for CSO signal stability RCSO3 - 1 - kΩ - RDC - 4 - mΩ WSL10204L000FEA REN_BR - 100 - Ω - Optional RFS_FLAG - 100 - Ω - Optional RGHS1n - 47 - Ω - - RGHS2n - 100 - kΩ - - RGLS1n - 47 - Ω - - RGLS2n - 100 - kΩ - - RINHn - 100 - Ω - Optional RINLn - 100 - Ω - Optional RNCS - 100 - Ω - Optional RNDIS - 100 - Ω - Optional RSCLK - 100 - Ω - Optional RSDI - 100 - Ω - Optional RSDO - 100 - Ω - Optional RSHUNTn - 4 - mΩ WSL10204L000FEA TBR1 - - - - TBR2 - - - - BCP56-16 - TVBP1 - - - - BCP56-16 - THSn - - - - STL225N6F7AG STD105N10F7AG - TLSn - - - - STL225N6F7AG STD105N10F7AG - STL225N6F7AG STH275N8F7 - - Layout guidelines The following layout guidelines apply to any of the above shown application circuits. • Three separated bulk capacitors CHB1 should be used - one per half bridge. • Three separated ceramic capacitors CHB2 should be used - one per half bridge. • Each of the 3 bulk capacitors CHB1 and each of the 3 ceramic capacitors CHB2 should be assigned to one of the half bridges and should be placed very close to it. • The components within one half bridge should be placed close to each other to reduce stray inductance to a minimum: high-side MOSFET, low-side MOSFET, bulk capacitor CHB1, ceramic capacitor CHB2 and the shunt resistor RSHUNT form a loop that should be as small and tight as possible. The traces should be short and wide. • The three half bridges can be separated; however, when there is one common GND referenced shunt resistor (RDC) for the three half bridges the sources of all low-side MOSFETs should be close to each other and close to the common shunt resistor. • Additional R-C snubber circuits can be placed to attenuate/suppress oscillations during switching of the MOSFETs, there may be one or two snubber circuits per half bridge and components must be low inductive in terms of routing and packaging (ceramic capacitors). • The exposed pad on the backside of the package shall be connected to GND. DS13546 - Rev 3 page 139/153 L9908 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 TQFP48 (7x7x1 mm exp. pad down) package information Figure 92. TQFP48 (7x7x1 mm exp. pad down) package outline θ2 θ1 θ θ3 DS13546 - Rev 3 page 140/153 L9908 TQFP48 (7x7x1 mm exp. pad down) package information Table 152. TQFP48 (7x7x1 mm exp. pad down) package mechanical data Symbol Dimensions in mm Min. Typ. Max. ɵ 0° 3.5° 7° ɵ1 0° - - ɵ2 10° 12° 12° ɵ3 10° 12° 12° A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 - 0.20 D 9.00 D1 7.00 D2 - - 5.51 D3 3.70 - - e - 0.50 - E 9.00 E1 7.00 E2 - - 5.51 E3 3.70 - - L 0.45 0.60 0.75 L1 1.00 N 48 R1 0.08 - - R2 0.08 - 0.2 S 0.2 - - Tolerance of form and position DS13546 - Rev 3 aaa - 0.20 - bbb - 0.20 - ccc - 0.08 - ddd - 0.08 - page 141/153 L9908 TQFP48 (7x7x1 mm exp. pad down) PCB landpattern 7.2 TQFP48 (7x7x1 mm exp. pad down) PCB landpattern Figure 93. Suggested PCB landpattern DS13546 - Rev 3 page 142/153 L9908 Revision history Table 153. Document revision history Date Version 16-Nov-2020 1 Changes Initial release. Updated: • 03-Mar-2021 2 Section 5.9 Internal clock; • Section 5.13.1 A/D conversion; • Section 5.13.2.3 Digital format current information • Section 5.13.3.1 Analog format current information; • Section 5.13.4 Current monitor A/D - D/A chain; • Table 12. VDD monitor electrical characteristics; • Table 36. Clock spread spectrum electrical characteristics; • Table 42. Motor battery monitor electrical characteristics; • Table 44. Pre-regulation stage electrical characteristics; • Table 48. VBP monitor electrical characteristics; • Table 51. Charge pump 2 electrical characteristics; • Table 53. Bootstrap Limiter 1 electrical characteristics; • Table 54. VCP Monitor electrical characteristics; • Table 70. Current Monitor Input characteristics; • Table 79. Current monitor`s analog output characteristics • Table 87. OFD electrical characteristics; • Table 91. OND electrical characteristics; • Table 93. PVF electrical characteristics. Removed "Restricted" watermark. Added Section 7.2 TQFP48 (7x7x1 mm exp. pad down) PCB landpattern. Updated: 28-Mar-2022 DS13546 - Rev 3 3 • Section 5.11.4 Supply distribution stage; • Section 5.12 Half bridges gate drivers; • Section 5.12.3 Shoot-Through Protection (STP); • Section 5.13.1 A/D conversion; • Section 6.3 Bill of materials; • Table 9. Quiescent current consumption in reset mode; • Table 10. Mean current consumptions in normal mode; • Table 44. Pre-regulation stage electrical characteristics; • Table 53. Bootstrap Limiter 1 electrical characteristics; • Table 54. VCP Monitor electrical characteristics; • Table 58. Pre-driver timings; • Table 60. VGS monitor electrical characteristics; • Table 76. Current monitors A/D auto-triggering latency; • Table 80. Current monitors A/D - D/A auto-triggering latency; • Table 93. PVF electrical characteristics; • Table 127. CH1_SAFETY_RELEVANT; • Table 152. TQFP48 (7x7x1 mm exp. pad down) package mechanical data; • Figure 7. Damage protected activation simplified structure; • Figure 10. Internal reset logic simplified block diagram; • Figure 23. Power-Up diagram; • Figure 26. Ext. FET gate supply simplified block diagram; • Figure 39. VGS Monitor operative ranges; • Figure 65. OFF State Diagnosis simplified block diagram; • Figure 66. OFD currents in motor phases; page 143/153 L9908 Date Version Changes • Figure 68. OFD Masking and deglitch filtering - LSn_OFD Example; • Figure 69. OFD Masking and deglitch filtering - LSn_OFD Example with multiple glitches; • Figure 77. Ground pins inter-connection; • Figure 79. Junction temperature ranges; • Figure 90. Application circuit, 12 V/24 V systems; • Figure 91. Application circuit, 48 V systems. Minor text changes in: DS13546 - Rev 3 • Section 5.4 Configuration mode; • Section 5.6.4 Gate driver supply enable logic. page 144/153 L9908 Contents Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Maximum Operating Range (MOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Parametrical Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Absolute Maximum Ratings (AMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 ESD resistivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4 Functional safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4.1 4.2 5 Safe states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.1 SAFE-OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.2 SAFE-DIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.3 SAFE-HIZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Safe state activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.1 Internal supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.2 Internal supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.3 VDD monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2 Internal resets (INT_RST, CFG_RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 Device operation state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 Configuration mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4.1 5.5 Self-test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.5.1 5.6 DS13546 - Rev 3 Configuration mode activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Self-test activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Fault Handling Management (FHM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.6.1 FHC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6.2 Fault reaction scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.6.3 Half bridges disable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 page 145/153 L9908 Contents 5.6.4 Gate driver supply enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.7 Power-Up sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.8 Digital I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.9 5.8.1 VIO power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.8.2 Digital Input (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.8.3 Digital Output (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.9.1 Spread Spectrum Modulation (SSM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.9.2 Internal Clock Monitor (ICM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.10 Motor Battery Monitor (MBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.11 Gate driver supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.12 5.13 5.11.1 Pre-regulation stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.11.2 VBP monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.11.3 VPRE monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.11.4 Supply distribution stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.11.5 VCP monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Half bridges gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.12.1 Ext. FET VGS monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.12.2 Dead Time Protection (DTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.12.3 Shoot-Through Protection (STP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Current monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.13.1 A/D conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 5.13.2 Digital signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.13.3 D/A conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.13.4 Current monitor A/D - D/A chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.14 Off State Diagnosis (OFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 5.15 On State Diagnosis (OND). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.16 Phase Voltage Feedback (PVF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.16.1 CSO3 - PVF multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.17 Actuation Timers (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.18 Ground Loss Monitor (GLM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 5.19 Temperature Monitor (OTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 DS13546 - Rev 3 page 146/153 L9908 Contents 5.20 5.21 6 7 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 5.20.1 Protocol description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 5.20.2 Frame description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 5.20.3 Frame monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.20.4 Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 5.20.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Window Watchdog Timer (WTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.1 12 V/24 V systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 6.2 48 V systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.3 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.4 Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.1 TQFP48 (7x7x1 mm exp. pad down) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 140 7.2 TQFP48 (7x7x1 mm exp. pad down) PCB landpattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DS13546 - Rev 3 page 147/153 L9908 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Pin list description . . . . . . . . . . . . . . . . . . . . . . . . . . . Safety related digital input pins functional partitioning . . . NDIS and EN_BR electrical characteristics . . . . . . . . . . Functional operating conditions . . . . . . . . . . . . . . . . . . Parametrical operating conditions . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . ESD resistivity (pin level) . . . . . . . . . . . . . . . . . . . . . . Temperature ranges and thermal data . . . . . . . . . . . . . Quiescent current consumption in reset mode . . . . . . . . Mean current consumptions in normal mode . . . . . . . . . Internal power supply electrical characteristics. . . . . . . . VDD monitor electrical characteristics. . . . . . . . . . . . . . SW reset activation register. . . . . . . . . . . . . . . . . . . . . Internal resets sources and filtering . . . . . . . . . . . . . . . Power up/down timings. . . . . . . . . . . . . . . . . . . . . . . . Operation mode status bits . . . . . . . . . . . . . . . . . . . . . Device operation modes summary . . . . . . . . . . . . . . . . CONFIG mode activation register. . . . . . . . . . . . . . . . . CFG timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-test selection bits. . . . . . . . . . . . . . . . . . . . . . . . . Self-test mode activation register . . . . . . . . . . . . . . . . . Self-test procedure status bits . . . . . . . . . . . . . . . . . . . Self-test timings and timeout . . . . . . . . . . . . . . . . . . . . Fault summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Reaction Configuration bits . . . . . . . . . . . . . . . . . Internal Managed Faults reaction details . . . . . . . . . . . . Fault output redirection configuration bit . . . . . . . . . . . . IC ERR status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault output redirection configuration bit . . . . . . . . . . . . EN_BR minimum t_off time . . . . . . . . . . . . . . . . . . . . . Digital input pins functional partitioning . . . . . . . . . . . . . Digital input electrical characteristics (Control Loop Pins) Digital output pins functional partitioning . . . . . . . . . . . . Digital output electrical characteristics . . . . . . . . . . . . . Internal clock electrical characteristics . . . . . . . . . . . . . Clock spread spectrum electrical characteristics . . . . . . Clock spread spectrum enable bit . . . . . . . . . . . . . . . . Internal clock monitor electrical characteristics. . . . . . . . Motor battery monitor UV threshold configuration bits . . . Motor battery monitor OV threshold configuration bits . . . Motor battery monitor filtering configuration bits . . . . . . . Motor battery monitor electrical characteristics. . . . . . . . Charge pump 1 enable bit . . . . . . . . . . . . . . . . . . . . . . Pre-regulation stage electrical characteristics . . . . . . . . VBP monitor UV threshold configuration bits . . . . . . . . . VBP monitor OV threshold configuration bits . . . . . . . . . VBP monitor filtering configuration bits . . . . . . . . . . . . . VBP monitor electrical characteristics . . . . . . . . . . . . . . VPRE Monitor electrical characteristics. . . . . . . . . . . . . Charge pump 2 enable bit . . . . . . . . . . . . . . . . . . . . . . Charge pump 2 electrical characteristics . . . . . . . . . . . . Bootstrap limiter 1 disable bit. . . . . . . . . . . . . . . . . . . . DS13546 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 6 . 6 . 7 10 10 14 14 16 16 21 22 24 24 27 28 28 29 29 30 30 31 31 32 33 34 34 34 35 36 43 44 44 44 45 45 45 45 46 46 46 47 49 49 51 51 51 52 54 55 55 56 page 148/153 L9908 List of tables Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Bootstrap Limiter 1 electrical characteristics . . . . . . . . . . . . . . . . . . VCP Monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . n-th Half Bridge pre-drivers disable mode bit . . . . . . . . . . . . . . . . . . Pre-drivers HIZ mode enable bit. . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-drivers behavior truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-driver timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-drivers electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . VGS monitor electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . Dead Time Protection configuration bits . . . . . . . . . . . . . . . . . . . . . Dead Time Protection accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . Shoot-Through Protection on PWM inputs enable bit . . . . . . . . . . . . Shoot-Through Protection on Ext. FET VGS enable bit . . . . . . . . . . . Shoot-Through Protection on PWM inputs filtering configuration bits. . Shoot-Through Protection on Ext. FET VGS filtering configuration bits Shoot-Through Protection accuracy . . . . . . . . . . . . . . . . . . . . . . . . n-th Current Monitor Channel enable bit . . . . . . . . . . . . . . . . . . . . . Current Monitor input range configuration bit . . . . . . . . . . . . . . . . . . Current Monitor Input characteristics . . . . . . . . . . . . . . . . . . . . . . . Command edge triggering configuration bits . . . . . . . . . . . . . . . . . . Synchronization counter configuration bits. . . . . . . . . . . . . . . . . . . . Current monitors LP filtering configuration bits . . . . . . . . . . . . . . . . . Current monitors sampling configuration bits . . . . . . . . . . . . . . . . . . Digital format current information LSB. . . . . . . . . . . . . . . . . . . . . . . Current monitors A/D auto-triggering latency . . . . . . . . . . . . . . . . . . Current monitors output offset configuration bits. . . . . . . . . . . . . . . . Current monitors output gain configuration . . . . . . . . . . . . . . . . . . . Current monitor`s analog output characteristics . . . . . . . . . . . . . . . . Current monitors A/D - D/A auto-triggering latency . . . . . . . . . . . . . . CSM gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current monitor A/D - D/A total error. . . . . . . . . . . . . . . . . . . . . . . . Current monitor chain noise performance . . . . . . . . . . . . . . . . . . . . OFD enable bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD fault detection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD blanking time configuration bits . . . . . . . . . . . . . . . . . . . . . . . OFD electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . OND enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OND blanking time configuration bits . . . . . . . . . . . . . . . . . . . . . . . OND filtering time configuration bits . . . . . . . . . . . . . . . . . . . . . . . . OND electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . PVF threshold selection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PVF electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . PVF output redirection selection bit . . . . . . . . . . . . . . . . . . . . . . . . CSO3-PVFn output multiplexing selection bits . . . . . . . . . . . . . . . . . Actuation Timers configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . Actuation Timers enable bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Actuation Timers electrical characteristics . . . . . . . . . . . . . . . . . . . . GLM electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal warning configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . OTM electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MOSI - SPI frame description . . . . . . . . . . . . . . . . . . . . . . . . . . . . MISO - SPI frame description . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHIPID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GEN_CFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS13546 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 . 58 . 60 . 60 . 61 . 61 . 63 . 66 . 67 . 68 . 69 . 70 . 70 . 70 . 70 . 71 . 72 . 73 . 76 . 78 . 79 . 82 . 85 . 86 . 86 . 87 . 87 . 88 . 89 . 89 . 89 . 91 . 91 . 93 . 94 . 94 . 95 . 96 . 97 . 98 . 99 100 100 100 101 101 102 103 104 105 107 107 .110 .111 page 149/153 L9908 List of tables Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. GEN_CFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GE_CFG3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GEN_CFG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GEN_STATUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GEN_STATUS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GEN_STATUS3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GEN_TEMP_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SW_RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT_CFG_CMD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT_STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIST_KEY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CFG_EN_UNLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAFETY_RELEVANT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAFETY_RELEVANT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAFETY_RELEVANT3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH1_STATUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH1_STATUS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH1_CFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH1_CFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH1_CFG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH1_SAFETY_RELEVANT. . . . . . . . . . . . . . . . . . . . . . . . . . CH1_ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH2_STATUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH2_STATUS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH2_CFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH2_CFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH2_CFG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH2_SAFETY_RELEVANT. . . . . . . . . . . . . . . . . . . . . . . . . . CH2_ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH3_STATUS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH3_STATUS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH3_CFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH3_CFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH3_CFG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CH3_SAFETY_RELEVANT. . . . . . . . . . . . . . . . . . . . . . . . . . CH3_ACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI_CMM_FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog enable bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog configuration table for WDT overflow timer . . . . . . . . WDT overflow timer LSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT overflow counter accuracy. . . . . . . . . . . . . . . . . . . . . . . Watchdog Binary to Gray answer conversion. . . . . . . . . . . . . . Watchdog configuration table for WDT data fail counter . . . . . . Watchdog RESET bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit - BOM. . . . . . . . . . . . . . . . . . . . . . . . . . . . TQFP48 (7x7x1 mm exp. pad down) package mechanical data . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . DS13546 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 .112 .113 .115 .115 .115 .116 .116 .117 .117 .117 .118 .118 .119 120 120 121 121 122 122 123 123 123 124 124 125 125 126 126 126 127 127 128 129 129 130 130 131 131 131 132 132 133 134 137 141 143 page 150/153 L9908 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. DS13546 - Rev 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connection diagram (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 V pulse scenario - applicative condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2s2p PCB with thermal vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Safe states activation paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Damage protected activation simplified structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal supply operative range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD functional ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal reset logic simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device operational state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CONFIG mode state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self-test mode state machine (NORMAL MODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault output redirection logic simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . Shutdown fault - Transient fault timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shutdown fault - Permanent fault timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-retry faults - Transient fault timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-retry faults - Permanent fault timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . Reduced operation fault - Transient fault timing diagram . . . . . . . . . . . . . . . . . . . . . . Reduced operation fault - Permanent fault timing diagram . . . . . . . . . . . . . . . . . . . . . Warning - Transient fault timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Warning - Permanent fault timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power-Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDH operative range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ext. FET gate supply simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBP functional ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPRE monitor boot masking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPRE operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BT1 behavior timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP UV boot masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCP operative range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-drivers Disable mode behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-drivers HIZ mode behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-drivers delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-drivers rise/fall time characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ext. FET Turn-on/off simplified behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pre-driver peak output current limitation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Monitor operative ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dead Time Protection functional operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interlocking protection on PWM inputs: functional operation . . . . . . . . . . . . . . . . . . . . Shoot-Through diagnosis on PWM inputs: functional operation . . . . . . . . . . . . . . . . . . Shoot-through protection on Ext. FET Vgs functional operation . . . . . . . . . . . . . . . . . . n-th Current Monitor Channel simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . External Shunts Configurations a) DC-Link, b) 2xSingle Leg + DC-Link, c) 3xSingle Leg A/D Conversion simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Monitor input dynamic timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current monitor input CMRR - Positive Common Mode input voltage . . . . . . . . . . . . . . Current monitor input CMRR - Negative Common Mode input voltage . . . . . . . . . . . . . Command edge triggering timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-triggering timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital signal processing simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 4 . 7 . 9 15 19 20 22 23 25 26 29 31 35 36 36 37 37 38 39 39 40 42 43 48 48 53 54 55 57 58 59 60 61 62 63 65 66 67 67 68 69 69 71 71 72 74 75 75 77 78 78 page 151/153 L9908 List of figures Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. DS13546 - Rev 3 Digital LP filtering simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Free running sampling timing diagram - non-zero current + auto-triggering . . . . . . . . . . . . . . . . . Free running sampling timing diagram - non-zero current + auto-triggering, latency to CSOn . . . . Free running sampling timing diagram - non-zero current + command edge-triggering . . . . . . . . . Free running sampling timing diagram - zero current (offset) + auto-triggering. . . . . . . . . . . . . . . Free running sampling timing diagram - zero current (offset) + command edge-triggering . . . . . . . T&H sampling timing diagram - non-zero current + auto-triggering. . . . . . . . . . . . . . . . . . . . . . . T&H sampling timing diagram - zero current (offset) + auto-triggering . . . . . . . . . . . . . . . . . . . . T&H sampling timing diagram - non-zero current + command edge-triggering . . . . . . . . . . . . . . . T&H sampling timing diagram - zero current (offset) + command edge-triggering. . . . . . . . . . . . . D/A conversion simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A/D-D/A chain accuracy block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFF State Diagnosis simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD currents in motor phases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD enabling and masking time start - IPU example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD Masking and deglitch filtering - LSn_OFD Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OFD Masking and deglitch filtering - LSn_OFD Example with multiple glitches . . . . . . . . . . . . . . ON State Diagnosis simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OND blanking and filtering (VDS_LSn example), multiple fault . . . . . . . . . . . . . . . . . . . . . . . . . OND blanking and filtering (VDS_LSn example), single fault. . . . . . . . . . . . . . . . . . . . . . . . . . . Off State Diagnosis block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase voltage feedback behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Actuation Timer simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Actuation Timers timing diagram on ACT (positive & negative polarity). . . . . . . . . . . . . . . . . . . . Ground pins inter-connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature monitor ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Junction temperature ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI connection modes "a" star connection (supported) "b" daisy-chain connection (not supported) SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Write-Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Read-Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI Clear on Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Operation – Overflow timer failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog command order sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Operation – Word sequence failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WDT Operation – WDT Reset after overflow timer failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit, 12 V/24 V systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application circuit, 48 V systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TQFP48 (7x7x1 mm exp. pad down) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suggested PCB landpattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 . 80 . 80 . 81 . 81 . 82 . 83 . 84 . 84 . 85 . 86 . 88 . 90 . 92 . 92 . 93 . 93 . 95 . 96 . 97 . 98 . 99 100 101 102 103 104 105 105 108 108 109 131 132 133 134 135 136 137 140 142 page 152/153 L9908 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS13546 - Rev 3 page 153/153