L9945TR

L9945 Datasheet Automotive fully configurable 8-channel High/Low side MOSFET pre-driver suitable for 12 V and 24 V systems Features TQFP64 exposed pad down GADG1606171506PS • • • • • • • • • • Product status link L9945 Product summary Order code Package Packing L9945 TQFP64 (exposed pad down) Tray L9945TR • • Tape and reel • • • • • AEC-Q100 qualified 12 V and 24 V battery systems compliance 3.3 V and 5 V logic compatible I/O 8-channel configurable MOSFET pre-driver – High-side (N-channel and P-channel MOS) – Low-side (N-channel MOS) – H-bridge (up to 2 H-bridge) – Peak & Hold (2 loads) Operating battery supply voltage 3.8 V to 36 V Operating VDD supply voltage 4.5 V to 5.5 V All device pins, except the ground pins, withstand at least 40 V Programmable gate charge/discharge currents for improving EMI behavior Individual diagnosis for: – Short circuit to battery – Open load – Short circuit to ground Highly flexible overcurrent sensing implementation – Possibility of monitoring external MOS drain to source voltage – Possibility of monitoring voltage on external shunt resistor – 64 programmable overcurrent thresholds independent for each channel – Ultra-fast output shutdown in case of overcurrent Current limitation for H-Bridge configuration 32-bit SPI protocol available for configuration and diagnostics – Failures latched even if they occur during diagnostics reading – Daisy chain operation – SDO protected against overvoltage Safety features – Fast switch off redundant output disable through two external pins – Built In Self Test (BIST) for logic operation – Hardware Self Check (HWSC) for VDD5 overvoltage comparator – Configurable Communication Check (CC) watchdog timer available – Disable feedback through bi-directional pin – Highly redundant output monitoring through dedicated SPI registers 10-bit ADC for battery and die temperature measurements available through SPI VDD5 monitoring for over/under voltage VPS (battery) monitoring for under voltage ISO26262 systems compatible DS12275 - Rev 8 - December 2019 For further information contact your local STMicroelectronics sales office. www.st.com L9945 Description The L9945 is an 8-channel MOSFET pre-driver configurable for low-side, high-side, peak and hold and H-Bridge load control. It is designed to comply with the requirements of 12 V (passenger vehicle) and 24 V (commercial vehicle) battery systems. All outputs can be PWM controlled. Six outputs are capable of driving safety relevant loads. One output can be dedicated to the actuation of safety relevant loads requiring a dedicated enable pin (EN6). The device offers the possibility of controlling two independent H-Bridges. The device can also drive up to two loads requiring "peak & hold" control strategy. The driver outputs are protected against short circuit condition. The device protects the external MOS in case of an overcurrent event. Each output provides full diagnostic information such as short to battery, short to ground and open-load. Each output status can be constantly monitored through dedicated SPI registers. The voltage slew rate of the external transistors 1-8 is controlled during turn ON and turn OFF in order to improve EMI behavior. A double, redundant, external disable source is available through DIS and NDIS pins in order to improve safety. The device is configurable via SPI through a 32-bit protocol. DS12275 - Rev 8 page 2/151 L9945 Block diagram 1 Block diagram Figure 1. Block diagram L9945 GNDCP CH4 VIO CH3 SDI SDO SCK SPI Watchdog Charge Pump CH1 VGBHI BATT12 NCS DRN1/2 GNDIO Power Supply BIST & HWSC GND Battery & Temperature Monitor NRES DIS NDIS OUT3 OUT4 OUT5 OUT6 NON1 GNSP1/2 SNGP1/2 BATT34 DRN3/4 GNSP3/4 SNGP3/4 DRN5/6 GNSP5/6 SNGP5/6 BATT56 OUT7 OUT8 LOGIC EN6 NON8 OUT1 OUT2 Output Channels VDD5 VPS CH2 DRN7/8 GNSP7/8 SNGP7/8 BATT78 Channel Diagnostics PGND78 PGND56 PGND34 PGND12 GADG2302170914PS DS12275 - Rev 8 page 3/151 L9945 Applications 2 Applications The device offers three different configuration options for the output channels: High-Side/Low-Side, Peak & Hold and H-Bridge. P&H configuration requires 2 or 4 channels, while H-Bridge requires 4 or 8 channels. Channels not used in P&H or H-Bridge are available for HS/LS usage. All the configurations involving channel 6 require the output driver 6 to be enabled through the EN6 input. 2.1 High-Side / Low-Side, with configurable FET type (N channel or P channel) Each channel features a dedicated SPI register where the user can specify: • MOS side: High-Side or Low-Side, through the LS_HS_config_xx bit; • MOS type: NMOS or PMOS, through the N_P_config_xx bit; – PMOS type is available only for High-Side. The picture below shows an example of High-Side configuration with NMOS transistor on channel 1. Refer to this schematic in order to understand how the external FET must be mounted with respect to the DRNx/GNSPx/ SNGPx/BATTx pins. Figure 2. Example of High-Side configuration with NMOS on channel 1 VBATT BATT12 HS NMOS RSH DRN1 CM RM CBATT GNSP1 RG GND RPD PGND12 DFW GND CESD GND LOAD OUT1 SNGP1 GND Note: the freewheeling diode is needed only in case of inductive load. GADG2302171549PS The following picture shows an example of High-Side configuration with PMOS transistor on channel 5. Refer to this schematic in order to understand how the external FET must be mounted with respect to the DRNx/GNSPx/ SNGPx/BATTx pins. DS12275 - Rev 8 page 4/151 L9945 High-Side / Low-Side, with configurable FET type (N channel or P channel) Figure 3. Example of High-Side configuration with PMOS on channel 5 VBATT BATT56 RSH GNSP5 HS PMOS RPU SNGP5 CBATT RG GND RM CM OUT5 DRN5 LOAD DFW CESD PGND56 GND GND GND Note: the freewheeling diode is needed only in case of inductive load. GADG2302171301PS The picture below shows an example of Low-Side configuration with NMOS transistor on channel 3. Refer to this schematic in order to understand how the external FET must be mounted with respect to the DRNx/GNSPx/ SNGPx/PGNDx pins. Figure 4. Example of Low-Side configuration with NMOS on channel 3 VBATT DFW DRN3 CM GNSP3 RM LOAD BATT34 CESD GND RG LS NMOS RPD SNGP3 RSH PGND34 Note: the freewheeling diode is needed only in case of inductive load. DS12275 - Rev 8 GND GADG2302170929PS page 5/151 L9945 Peak & Hold Note: When using channel 6, the EN6 input must be set high to enable the output driver. The LS/HS configuration is suitable for driving whatever high-side/low-side loads as: • Lamps (any channel); • ON/OFF electrovalves (any channel); • Any safety relevant load (channel 6 has dedicated EN6 enable input); • Lambda probe heater (any channel); • Limp home functionalities or not safety related loads (channels 7 and 8 not affected by external disable input). 2.2 Peak & Hold The device can handle up to two peak & hold loads. There are two possible configurations which can co-exist: • P&H1: it involves channels 1 (HS) and 4 (LS) and can be selected through the PH1_config bit • P&H2: it involves channels 2 (HS) and 3 (LS) and can be selected through the PH2_config bit Once a peak & hold configuration is selected through its config bit, the corresponding output channels are automatically configured according to the pre-determined transistor side. The FET type for the High-Side can be selected through its N_P_config_xx bit. Figure 5. Example of peak & hold configuration with NMOS (HS) on channel 1 and NMOS (LS) on channel 4 VBATT BATT12 RSH DRN1 HS NMOS RM CM GNSP1 RG CBATT M1 RPD GND SNGP1 OUT1 BATT34 LOAD CESD DFW VBATT GND GND DRN4 OUT4 RFB DFB DZFB CESD LS NMOS CM GNSP4 RM GND RG M4 RPD SNGP4 RSH PGND34 DS12275 - Rev 8 GADG2402171042PS page 6/151 L9945 H-Bridge Figure 5 shows an example of P&H1 configuration with NMOS transistor on the High-Side. Refer to this schematic in order to understand how the external FETs must be mounted with respect to the DRNx/GNSPx/ SNGPx/PGNDx/BATTx pins. In case of PMOS on the High-Side, refer to Figure 3 in order to understand the DRNx/GNSPx/SNGPx/BATTx pin connection. The peak and hold configuration is suitable for driving several types of loads as: • Injectors; • Fuel pump; • Other type of electrovalves and coils that may benefit from peak and hold control. 2.3 H-Bridge The device can handle up to two H-Bridges. There are two possible configurations which can co-exist: • H-Bridge 1: it involves channels 1 (HS), 2 (HS), 3 (LS) and 4 (LS) and can be selected through the HB1_config bit • H-Bridge 2: it involves channels 5 (HS), 6 (HS), 7 (LS) and 8 (LS) and can be selected through the HB2_config bit Once an H-Bridge configuration is selected through its config bit, the corresponding output channels are automatically configured as reported above. The FET type for the High-Side transistors can be selected through their N_P_config_xx bit. In case of H-bridge with PMOS on the High-Side, refer to Figure 3 in order to understand how DRNx/GNSPx/ SNGPx/BATTx are mounted with respect to NMOS pin connection. The H-Bridge configuration is suitable for driving the following types of loads: • Brushed DC motors Note: DS12275 - Rev 8 When configuring H-Bridge 2, the EN6 input must be set high to enable the output driver. page 7/151 L9945 H-Bridge Figure 6. Example of H-Bridge configuration with NMOS as HS and LS transistors (channels 1-4 used) VBATT BATT12 BATT12 RSH DRN2 DRN1 CM RM RG CBATT HS NMOS GNSP1 CBATT GND GND RM CM RG HS NMOS GNSP2 RPD RPD SNGP2 SNGP1 OUT1/ OUT3 OUT2/ OUT4 M CESD DRN3 CM RM GND GND LS NMOS RG GNSP3 DRN4 CESD RM CM LS NMOS RPD RG GNSP4 RPD SNGP4 SNGP3 RSH PGND34 PGND34 GND GADG2402171049PS DS12275 - Rev 8 page 8/151 L9945 Device pins 3 Device pins This section contains the device pinout, the pin description and configuration and the electrical characteristics. 3.1 Pinout The picture below shows the device pinout. Each pin features also the absolute maximum ratings. All pins, except the ground ones, can withstand at least 40 V to GND. Maximum differential voltage allowed across the following pins is 20 V: • GNSPx and SNGPx; • CH2 and VPS; • CH4 and CH2; • VGBHI and VPS; • VGBHI and CH4. -14V -20V GNSP4 DRN4 80V -14V SNGP4 60V -1V BATT34 60V -14V SNGP3 60V -14V GNSP3 60V -20V DRN3 80V -0.3V PGND34 60V -0.3V PGND12 0.3V -20V DRN2 60V -14V GNSP2 0.3V -14V SNGP2 80V -1V 60V 60V -14V SNGP1 BATT12 60V -14V 60V 80V -20V DRN1 GNSP1 pin name negative positive Figure 7. L9945 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 positive negative pin name 40V -0.3V NON1 1 48 RESERVED -0.3V 60V 40V -0.3V NON2 2 47 -0.3V 40V 40V -0.3V NON3 3 46 RESERVED -0.3V 60V 40V -0.3V NON4 4 45 -0.3V 40V 40V -0.3V NON5 5 44 RESERVED -0.3V 60V 40V -0.3V NON6 6 43 CH1 -0.3V 60V 40V -0.3V NON7 7 42 VPS -1V 60V 40V -0.3V NON8 8 L9945 41 CH3 -0.3V 60V 40V -0.3V VIO 9 TQFP64 Exposed Pad 40 CH2 -0.3V 80V 40V -0.3V SDO 10 39 CH4 -0.3V 80V 0.3V -0.3V GNDIO 11 38 VGBHI -0.3V 80V 40V -0.3V NRES 12 37 GNDCP -0.3V 0.3V 40V -0.3V NCS 13 36 GND -0.3V 0.3V 40V -0.3V SDI 14 35 VDD5 -0.3V 40V 40V -0.3V SCK 15 34 RESERVED -0.3V 60V 40V -0.3V DIS 16 33 RESERVED -0.3V 60V 10x10mm with 0.5mm pitch pin name EN6 NDIS negative positive DS12275 - Rev 8 DRN5 -20V 60V GNSP5 -14V SNGP5 -14V 60V 80V BATT56 -1V 60V SNGP6 -14V 60V GNSP6 -14V 80V DRN6 -20V 60V PGND56 -0.3V 0.3V PGND78 -0.3V 0.3V DRN7 -20V 60V GNSP7 -14V 80V SNGP7 -14V 60V SNGP8 -1V 60V BATT78 -14V 60V DRN8 -14V GNSP8 -20V 60V 80V positive negative pin name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GAPG0802160930CFT page 9/151 L9945 Pin names and functions 3.2 Pin names and functions The table below lists all the information about device pins. Note: The package exposed pad must be soldered on the PCB and connected to ground. Pins GNDIO and GNDCP must be shorted and ground connected. Syntax: P = Power, G = Ground, D = Digital, A = Analog, I = Input, O = Output, NA = Not Available, L = Low, H = High, PU = Pull Up, PD = Pull Down. Table 1. Pin list Pin # Pin Name Pin type PU/PD Active State HBM ESD (1) Description Power Supply And Ground 42 VPS P NA NA NA 4 kV Battery Input, used to supply charge pump 36 GND G NA NA NA 2 kV Ground 35 VDD5 P NA NA NA 2 kV 5 V Input (usually output of external regulator) Digital inputs (connected to external microcontroller) Output 1 ON-OFF signal 1 NON1 D I PU L 2 kV 2 NON2 D I PU L 2 kV 3 NON3 D I PU L 2 kV 4 NON4 D I PU L 2 kV 5 NON5 D I PU L 2 kV 6 NON6 D I PU L 2 kV 7 NON7 D I PU L 2 kV 8 NON8 D I PU L 2 kV Output 8 ON-OFF signal NPWM signal for H-Bridge 1 Output 2 ON-OFF signal DIR signal for H-Bridge 1 Output 3 ON-OFF signal HIZ signal for H-Bridge 1 Output 4 ON-OFF signal Output 5 ON-OFF signal NPWM signal for H-Bridge 2 Output 6 ON-OFF signal DIR signal for H-Bridge 2 Output 7 ON-OFF signal HIZ signal for H-Bridge 2 Output pre-driver 64 DRN1 A I NA NA 4 kV FET drain on channel 1 63 GNSP1 A O NA NA 4 kV NFET gate / PFET source on channel 1 62 SNGP1 A O NA NA 4 kV NFET source / PFET gate on channel 1 61 BATT12 P I NA NA 4 kV Battery for channels 1 and 2 57 PGND12 G I NA NA 4 kV Power ground for channels 1 and 2 58 DRN2 A I NA NA 4 kV FET drain on channel 2 59 GNSP2 A O NA NA 4 kV NFET gate / PFET source on channel 2 60 SNGP2 A O NA NA 4 kV NFET source / PFET gate on channel 2 55 DRN3 A I NA NA 4 kV FET drain on channel 3 54 GNSP3 A O NA NA 4 kV NFET gate / PFET source on channel 3 53 SNGP3 A O NA NA 4 kV NFET source / PFET gate on channel 3 52 BATT34 P I NA NA 4 kV Battery for channels 3 and 4 56 PGND34 G I NA NA 4 kV Power ground for channels 3 and 4 DS12275 - Rev 8 page 10/151 L9945 Pin names and functions Pin type PU/PD Active State HBM ESD (1) Pin # Pin Name Description 49 DRN4 A I NA NA 4 kV FET drain on channel 4 50 GNSP4 A O NA NA 4 kV NFET gate / PFET source on channel 4 51 SNGP4 A O NA NA 4 kV NFET source / PFET gate on channel 4 32 DRN5 A I NA NA 4 kV FET drain on channel 5 31 GNSP5 A O NA NA 4 kV NFET gate / PFET source on channel 5 30 SNGP5 A O NA NA 4 kV NFET source / PFET gate on channel 5 29 BATT56 P I NA NA 4 kV Battery for channels 5 and 6 25 PGND56 G I NA NA 4 kV Power ground for channels 5 and 6 26 DRN6 A I NA NA 4 kV FET drain on channel 6 27 GNSP6 A O NA NA 4 kV NFET gate / PFET source on channel 6 28 SNGP6 A O NA NA 4 kV NFET source / PFET gate on channel 6 23 DRN7 A I NA NA 4 kV FET drain on channel 7 22 GNSP7 A O NA NA 4 kV NFET gate / PFET source on channel 7 21 SNGP7 A O NA NA 4 kV NFET source / PFET gate on channel 7 20 BATT78 P I NA NA 4 kV Battery for channels 7 and 8 24 PGND78 G I NA NA 4 kV Power ground for channels 7 and 8 17 DRN8 A I NA NA 4 kV FET drain on channel 8 18 GNSP8 A O NA NA 4 kV NFET gate / PFET source on channel 8 19 SNGP8 A O NA NA 4 kV NFET source / PFET gate on channel 8 SPI block (used for communication with external microcontroller) 15 SCK D I PU NA 2 kV SPI clock 14 SDI D I PU NA 2 kV SPI data in 10 SDO D O NA NA 2 kV SPI data out. An external pull-down resistor in the [10k - 47k] range must be mounted vs GNDIO. 13 NCS D I PU L 2 kV SPI chip select 9 VIO P NA NA NA 2 kV Supply voltage for SDO. Must be connected to the same power supply as the SPI of the master device (usually the external microcontroller) 11 GNDIO G NA NA NA 2 kV Ground for SPI. Must be shorted to GNDCP Reset / Disable 12 NRES D I PU L 2 kV Reset input. Must be connected to ECU reset 16 DIS D I PU H 2 kV Disable input. Must be connected to the external microcontroller to allow the disabling of the outputs 1-6. 45 NDIS D I/O PD L 2 kV Negated disable input/output. Can be used as a negated disable input. Can also be used as output to generate an interrupt in the external microcontroller whenever the NDIS node is pulled down (internal disable event) 47 EN6 D I PD H 2 kV Output 6 Enable. Can be used to enable output driver for safety relevant load control. Charge Pump 38 VGBHI P NA NA NA 2 kV Charge pump output (battery + 12 V). Connected to VPS pin through a “tank” capacitor 43 CH1 A I/O NA NA 2 kV 1st node for flying capacitor 1 40 CH2 A I/O NA NA 2 kV 2nd node for flying capacitor 1 DS12275 - Rev 8 page 11/151 L9945 Pin names and functions Pin type PU/PD Active State HBM ESD (1) Pin # Pin Name Description 41 CH3 A I/O NA NA 2 kV 1st node for flying capacitor 2 39 CH4 A I/O NA NA 2 kV 2nd node for flying capacitor 2 37 GNDCP G NA NA NA 2 kV Ground for charge pump. Must be shorted to GNDIO D I NA NA 2 kV Tie low Other pins 44 RESERVED 48 RESERVED NA NA NA NA 2 kV Leave floating 34 RESERVED NA NA NA NA 2 kV Leave floating 46 RESERVED NA NA NA NA 2 kV Leave floating 33 RESERVED NA NA NA NA 2 kV Leave floating 1. See Table 4and Figure 8. DS12275 - Rev 8 page 12/151 L9945 Product electrical and thermal characteristics 4 Product electrical and thermal characteristics This section contains the Absolute Maximum Ratings (AMR), the latch-up trials, the ESD classification and the range of functionality of the device. The information provided here refers to the global behavior of the device. For specific information about the electrical characteristics of each interface/component, refer to the related section of the datasheet. 4.1 Absolute maximum ratings Within the maximum ratings, no damage to the component or latch-up occurs and the defined leakage currents won't be exceeded. However, the full functionality of the device is guaranteed only in the functional range. This part may be irreparably damaged if taken outside the specified absolute maximum ratings. Operation above the absolute maximum ratings may also cause a decrease in reliability. Note: A negative current is flowing out of the L9945, a positive current into the L9945. Table 2. Absolute maximum ratings capability Symbol Parameter description Comment Min. Max. Unit Supply Pins VDD5 VDD5 voltage range -0.3 40 V -1 60 V Ext. HS, Static VVPS_sta Static VPS voltage range Max voltage: VGBHI – VPS = 20 V VVPS_dyn Dynamic VPS voltage range Dynamic; 2 ms test pulse 1 -2 60 V IPS_leak Leakage on pin VPS POR or NRES active; VPS = [0 – 36] V 0 20 µA VGBHI VGBHI voltage range (Ch. Pump) -0.3 80 V -0.3 40 V -14 60 V -14 80 V -20 60 V -1 60 V - -0.3 0.3 V - -0.3 60 V VVIO VIO voltage range Max voltage: VGBHI – VPS = 20 V Supply for SDO Output Pre-Driver Max voltage: VSNGPx SNGPx voltage range GNSPx - SNGPx = 20 V (in all conditions) BATTxx – SNGPx ≥ 0 V (When DSM is used for OC detection) VGNSPx GNSPx voltage range VDRNx DRNx voltage range Max voltage: GNSPx - SNGPx = 20 V Max voltage: VBATTxx BATTxx voltage range BATTxx – SNGPx ≥ 0 V When DSM is used for OC detection Ground pins: GND, GNDIO, GNDCP, PGNDxx VGND_PINS Ground voltage range Charge Pump VCH1&3 CH1 & CH3 DS12275 - Rev 8 page 13/151 L9945 Latch-up trials Symbol Parameter description Comment Min. Max. Unit Max voltage: VCH2&4 CH2 & CH4 CH2 - VPS = 20 V CH4 - CH2 = 20 V -0.3 80 V -0.3 40 V VGBHI - CH4 = 20 V Digital HV pins: NONx, NRES, NDIS, DIS, EN6, NCS, SCK, SDI, SDO VDIG_IO Input voltage range SDO and NDIS have to withstand this voltage also in ON-condition Refer to Figure 7 for the device pinout with AMR indicated for each pin. 4.2 Latch-up trials The table below lists the information about the Latch-up trials. Note: A negative current is flowing out of the L9945, a positive current into the L9945. Table 3. Latch-up trials Symbol LU Parameter description Latch-up Test 4.3 Comment Min. Max. Unit 100 - mA Min. Max. Unit -4 4 kV -2 2 kV For corner pins DRN1, DRN4, DRN5 according to Q100-011 -600 750 V For corner pin T1 according to Q100-011 -750 600 V For corner pin NON1 according to Q100-011 -600 600 V For corner pin DIS according to Q100-011 -600 500 V For corner pins T4, T8 according to Q100-011 -750 750 V For all other pins -500 500 V For all pins according to JEDEC78 class II level A ESD performance The table below contains all the information about the ESD characterization of the device. Note: A negative current is flowing out of the L9945, a positive current into the L9945. Table 4. ESD performance Symbol Parameter description Comment ESD Classification (refer to Figure 8) Human Body Model (HBM) (100 pF/ 1.5 kΩ) VESD Charged Device Model (CDM) For pins: DRNx, SNGPx, GNSPx, BATTxx, PGNDxx, VPS According to Q100-002 For all other pins according to Q100-002 Protection diodes current IESD_SUP ESD protection diode current For pins VPS, VDD5, VGBHI, VIO -1 1 mA IESD_DRNx ESD protection diode current For DRNx pins -1 1 mA IESD_DIG ESD protection diode current For pins NONx, NRES, NDIS, DIS, SDI, SCK, EN6, NCS, SDO -1 1 mA DS12275 - Rev 8 page 14/151 L9945 ESD performance ± 4kV DRN4 +750V / -600V ± 4kV GNSP4 +500V / -500V ± 4kV SNGP4 +500V / -500V ± 4kV BATT34 +500V / -500V ± 4kV SNGP3 +500V / -500V ± 4kV GNSP3 +500V / -500V ± 4kV DRN3 +500V / -500V ± 4kV PGND34 +500V / -500V ± 4kV PGND12 +500V / -500V ± 4kV DRN2 +500V / -500V ± 4kV GNSP2 +500V / -500V ± 4kV SNGP2 +500V / -500V ± 4kV BATT12 +500V / -500V ± 4kV SNGP1 +500V / -500V ± 4kV GNSP1 +500V / -500V ± 4kV DRN1 +750V / -600V HBM pin name CDM Figure 8. ESD ratings on pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 CDM HBM pin name pin name +600V / -600V ± 2kV NON1 1 48 RESERVED ± 2kV +600V / -750V +500V / -500V ± 2kV NON2 2 47 EN6 ± 2kV +500V / -500V +500V / -500V ± 2kV NON3 3 46 RESERVED ± 2kV +500V / -500V +500V / -500V ± 2kV NON4 4 45 NDIS ± 2kV +500V / -500V +500V / -500V ± 2kV NON5 5 44 RESERVED ± 2kV +500V / -500V +500V / -500V ± 2kV NON6 6 43 CH1 ± 2kV +500V / -500V +500V / -500V ± 2kV NON7 7 42 VPS ± 2kV +500V / -500V +500V / -500V ± 2kV NON8 8 L9945 41 CH3 ± 2kV +500V / -500V +500V / -500V ± 2kV VIO 9 TQFP64 Exposed Pad 40 CH2 ± 2kV +500V / -500V +500V / -500V ± 2kV SDO 10 39 CH4 ± 2kV +500V / -500V +500V / -500V ± 2kV GNDIO 11 38 VGBHI ± 2kV +500V / -500V +500V / -500V ± 2kV NRES 12 37 GNDCP ± 2kV +500V / -500V +500V / -500V ± 2kV NCS 13 36 GND ± 2kV +500V / -500V +500V / -500V ± 2kV SDI 14 35 VDD5 ± 2kV +500V / -500V +500V / -500V ± 2kV SCK 15 34 RESERVED ± 2kV +500V / -500V +500V / -600V ± 2kV DIS 16 33 RESERVED ± 2kV +750V / -750V 10x10mm with 0.5mm pitch HBM CDM DRN5 ± 4kV +750V / -600V GNSP5 ± 4kV +500V / -500V SNGP5 ± 4kV +500V / -500V BATT56 ± 4kV +500V / -500V SNGP6 ± 4kV +500V / -500V GNSP6 ± 4kV +500V / -500V DRN6 ± 4kV +500V / -500V PGND56 ± 4kV +500V / -500V PGND78 ± 4kV +500V / -500V DRN7 ± 4kV +500V / -500V GNSP7 ± 4kV +500V / -500V SNGP7 ± 4kV +500V / -500V BATT78 ± 4kV +500V / -500V SNGP8 ± 4kV +500V / -500V GNSP8 ± 4kV +500V / -500V DRN8 ± 4kV +750V / -750V CDM HBM pin name 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GADG2402171310PS Figure 8 summarizes the ESD ratings for each pin according to both CDM and HBM models. DS12275 - Rev 8 page 15/151 L9945 Thermal behavior 4.4 Thermal behavior The table below contains the temperature ranges and the thermal resistance information. The device functionality is lifetime guaranteed up to 150 °C (junction temperature). If the junction temperature crosses TOT_OFF, overtemperature is detected. Status of the overtemperature comparator can be monitored reading OT_STATE bit via SPI. The external microcontroller can either read the temperature measured by the Temperature ADC or monitor OT_STATE bit: in case of overtemperature, L9945 must be disabled via external input. Note: VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 5. Thermal behavior Symbol Parameter description Comment Min. Max. Unit Temperature ranges Tj_op Operating / Lifetime (junction) Lifetime guaranteed -40 150 °C Tstg Storage temperature -55 °C is allowed for a maximum of 15h -40 +150 °C Tj_fct Functional (junction) Transient condition 150 TOT_OFF - 165 190 °C - 100 900 ns - 2.4 °C/W - 30 °C/W TOT_OFF Over temperature comparator threshold tOff_prot Comparator reaction time including analogue deglitching filter Thermal resistance Rth_j_c Thermal resistance (junction to case) Rth_j_a Thermal resistance (junction to ambient) Values are according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board (see Figure 9) Figure 9. Sketch of a 2s2p PCB with thermal vias 2s2p PCB + vias ΘJ-A (2s2p) GADG2702170724PS Note: DS12275 - Rev 8 In "2s2p", the "s" suffix stands for "Signal" and the number before indicates how many PCB layers are dedicated to signal wires. The "p" suffix stands for "Power" and the number before indicates how many PCB layers are dedicated to power planes. The graph below shows the thermal impedance of the package. page 16/151 L9945 Thermal behavior Figure 10. Thermal impedance diagram 25 ZTH (°C/W) 20 15 10 5 1.0E-05 1.0E-03 1.0E-01 1.0E+01 1.0E+03 Time (s) GADG2702170740PS 4.4.1 Temperature ADC An internal ADC monitors the junction temperature. Measure is available reading Temp_ADC[x] bit and applying the following conversion law: Eq. (1): Junction temperature conversion law T j = 0.28 × CODE − 65 (1) The table below reports the electrical characteristics for the temperature ADC. Note: VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 6. Temperature ADC electrical characteristics Symbol ADC_res fADC Tj_ADC_in T_ACC DS12275 - Rev 8 Parameter Test condition Min. Typ. Max. Unit Resolution - - 10 - bit Conversion rate - - 62.5 - kHz Temperature range - -40 - 190 °C Temp accuracy From -40 °C to 190 °C -10 - 10 °C page 17/151 L9945 Range of functionality 4.5 Range of functionality The table below lists the range of functionality for the electrical parameters. Note: Junction temperature is assumed Tj = Tj_fct unless otherwise noted. Table 7. Range of functionality Symbol Parameter description Comment Min. Max. Unit 3.8 36 V - 48 V - 60 V Supply pins Operational For 15 min VVPS External load and charge pump supply at 45 °C Load dump (< 500 ms) VVDD5 VVIO DS12275 - Rev 8 Supply for internal digital, analog and SPI (except SDO) Tj = Tj_op 4.5 5.5 V Supply for SPI pin SDO Tj = Tj_op 3.0 5.5 V page 18/151 L9945 Functional description 5 Functional description This section contains the functional description of the L9945. A general description of the device functionality is provided along with the detailed operation of each sub-block. Relations and interconnections between various sub-blocks are explained. For a detailed diagnostic analysis, refer to Section 6.2 Diagnostics overview. 5.1 General description The device contains eight pre-drivers for external FETs. Each pre-driver can be configured to drive a high-side or low-side external driver (LS_HS_config_xx bit). The external FET can be either N-channel (low-side and highside) or P-channel (high-side). FET type is selectable through N_P_config_xx bit. Complex configurations for P&H and H-Bridge are automatically applied programming the corresponding bit via SPI (HBx_config or PHx_config). The outputs are controlled either directly by pins NONx or via SPI commands (programming SPI_ON_OUTxx bit). For each channel, control strategy is selected by programming the SPI_input_sel_xx bit. Output channels must be enabled prior to use by programming the en_OUT_xx bit in the corresponding output register. Channel 6 requires also the EN6 input to be set high in order to be enabled (suitable for safety relevant load control). IC provides charge pump for driving external low-side and high-side NMOS. Gate charge/discharge currents can be either constant, with value selectable via SPI, or limited by external resistor. GCC_config_xx bit defines the charge/discharge strategy. An external capacitor connected between transistor gate and drain is recommended to improve EMI performances. External FET is protected against overcurrent (OC) during the ON phase by rapidly switching OFF the transistor with a high gate current in case of OC detection. The value of such shutdown current can be programmed via the GCC_OVERRIDE_CONFIG bit. Two detection strategies are available: either monitoring the voltage between transistor drain and source (DSM) or monitoring the drop on an external shunt resistor. Detection strategy is selectable via OC_DS_Shunt_xx bit. OC threshold is programmable via SPI (OC_config_xx bit). The device offers the possibility of compensating the OC threshold with respect to temperature (OC_Temp_comp_xx bit) and battery variations (OC_Batt_comp_xx bit). In case of an OC event, output re-engagement strategy is selectable through prot_config_xx bit. Detection of Open Load (OL) and STB/STG failures is performed during the OFF phase. The diagnostic phase durations and currents can be selected through tdiag_config_xx and diag_i_config_xx bit. In peak and hold configuration, the OFF diagnostic strategy can be programmed through PHx_diag_strategy bit. In H-Bridge mode, the dead time to avoid cross conduction on the same branch of the bridge can be programmed through the HBx_dead_time bit. An extended set of OFF diagnostic times is available for the H-Bridge mode by programming the HBx_tdiag_ext_config bit. A current limitation feature is available for H-Bridge configuration. The diagnostic status of each channel is reported in the next received frame after having sent the following SPI command: 0x9AAA0001. Note: The "x" in the bit names symbolize the generic channel number or the configuration index (e.g. NONx refers to NON1, NON2, … , NON8. PHx_diag_strategy refers to PH1_diag_strategy and PH2_diag_strategy). 5.2 Supply concept The device has 4 supply pins: VDD5, VPS, VGBHI, and VIO. • VDD5 has to be provided by the ECU power supply and feeds most of the internal sub-blocks. Two internal regulators are used to generate separate 3.3 V supplies for analog and digital domains. • VPS has to be provided by the battery and is used to feed the internal charge pump. • VGBHI is the output voltage of the charge pump and it is used for driving the gate of the external FETs. • VIO is a separate power supply dedicated for the SDO pin of the Serial Peripheral Interface. It must be connected to the same voltage level of the SPI master. The VIO pin is implemented in order to be compliant with both 3.3 V and 5 V systems. DS12275 - Rev 8 page 19/151 L9945 Supply concept 5.2.1 VDD5 supply block The VDD5 pin is internally split between analog and digital domain to reduce interference between the different parts of the component. Two regulators are implemented in order to provide separate 3.3 V domains: • VDD_int_a is generated out of VDD5. It is the overvoltage protected internal supply of the low voltage analog part, such as diagnostic comparators, gate drives for integrated low-side, bias currents, bandgap etc.; • VDD_int_d is generated out of VDD5. It is the overvoltage protected internal supply for the digital part. The component starts operation when VDD5 is higher than the power-on reset threshold (VPOR). Details about the reset block are given in the Section 5.3 Reset. The VDD5 is monitored to generate over (OV) and under voltage (UV) disable in case of fault. The disable signal acts both internally and externally: in case of output disable due to failure on VDD5, the NDIS bidirectional pin is internally pulled down. The purpose is providing a feedback to the external microcontroller monitoring the device status. Detailed information about disable sources is given in the Section 6.1 Disable sources paragraph. Range of characteristic is defined for VDD5 from 4.5 V to 5.5 V. In this range, the component works according to the specification without any restrictions and all parameters are in the specified range. The table below lists the electrical characteristics of the VDD5 supply block. Note: Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 8. VDD5 supply block electrical characteristics Symbol Parameter IVDD5_opm Test condition Min. Typ. Max. Unit VDD5 operating mode current All outputs controlled ON 7 - 35 mA VDD5 current in case of overvoltage 5.5 V < VDD5 ≤ 36 V 8 - 40 mA VVDD5_UV VDD5 UV threshold Undervoltage 4.5 - 4.7 V VVDD5_UV_HYS VDD5 UV hysteresis VVDD5_UV 10 - 50 mV VDD5 undervoltage filter time - 2 2.6 3.25 ms VDD5_UV Comparator output reaction time - 100 - 700 ns tVDD5_UV2 VDD5 under voltage filter time for NDIS activation - 415 500 625 ms VVDD5_OV VDD5 overvoltage disable threshold Self-checked by HWSC 5.3 - 5.5 V VVDD5_OV_HYS VDD5 OV disable hysteresis - 10 - 50 mV tVDD5_OV VDD5 overvoltage filter time - 2.0 2.6 3.25 ms VDD5_OV Comparator output reaction time - 100 - 700 ns POR release threshold Related to VDD5 4.15 - 4.45 V POR hysteresis - 0.15 - 0.25 V POR RESET delay time POR delay at startup of VDD5 10 - 50 µs IVDD5OV tVDD5_UV1 tVDD5_UV_react tVDD5_OV_react VPOR VPOR_HYS tPOR_D 5.2.2 VPS supply block The VPS pin is a battery supply. It is used for the internal charge pump to drive the N-channel external MOSFETs. The VPS line is monitored to detect low voltage on VPS. In case the voltage on VPS is lower than VVPS_UV the pre-drivers are actively turned off. Such event is latched in VPS_LATCH, cleared on SPI readout. The undervoltage comparator output can be monitored reading VPS_STATE bit via SPI. The table below lists the electrical characteristics for the VPS supply block: Note: DS12275 - Rev 8 Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. page 20/151 L9945 Supply concept Table 9. VPS supply block electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit IVPS_OPM IVPS operating mode current - 3 - 50 mA VVPS_UV VPS low battery detection threshold - 3.5 - 3.8 V tVPS_react VPS Comparator output reaction time - 100 - 700 ns Filter time for VPS low battery detection - 0.5 - 5 µs tLBD_FIL 5.2.3 VPS ADC L9945 has an internal ADC monitoring VPS. Measure is obtained reading VPS_ADC[x] bit and applying the following conversion law: Eq. (2): Battery monitor conversion law VPS = 0.048 × CODE (2) The table below reports the electrical characteristics of the VPS ADC. Note: Tj = Tj_op; all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 10. VPS ADC electrical characteristics Symbol ADC_res fADC VPS_ADC_in VPS_ACC 5.2.4 Parameter Test Condition Min. Typ. Max. Unit Resolution - - 10 - bit Conversion rate - - 62.5 - kHz Input range VVPS - 0 - 48 V 3.5 V < VVPS < 12 V -400 - 400 mV 12 V < VVPS < 48 V -3.3 - 3.3 % VVPS accuracy Charge pump (VGBHI) To effectively bias the high side drivers and fail safe switch, a charge pump is used to drive the gate voltage above VPS. The charge pump switching frequency is nominally 200 KHz. A built-in monitoring circuit checks if the charge pump output voltage is sufficient to control the high side valve driver. In case of undervoltage (VGBHI < VCP_UV), the outputs are actively turned off and VCP_UV_LATCH is set (readable via SPI, cleared on readout). The output of the undervoltage comparator can be monitored reading VCP_UV_STATE via SPI. At power ON, the charge pump is enabled when VDD5 is above VPOR and NRES is not asserted. Refer to the AN: "Charge Pump Stress Estimation In Switching Applications" in order to understand how the switching frequency of the outputs affects the charge pump behavior. DS12275 - Rev 8 page 21/151 L9945 Supply concept Figure 11. Charge pump connections CTANK Battery CFLY1 VPS CH1 X CFLY2 CH2 X X CH3 X CH4 X VGBHI X Charge Pump Ratings: CTANK: 16 V CFLY1, CFLY2: 50 V for 12 V systems, 100 V for 24 V systems. GADG2702170853PS The table below lists the electrical characteristics of the charge pump: Note: Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 11. Charge pump electrical characteristics Symbol VVGBHI fCP CTANK CFLY Parameter Charge pump voltage versus charge pump load current Test Condition Min. Typ. Max. VVPS+12 VVPS+16 Unit VVPS ≥ 8 V; IVGBHI = 15 mA (DC) VVPS+9 V VVPS_UV ≤ VVPS < 8 V; IVGBHI = 6 mA (DC) VVPS+5 - VVPS+16 V Charge pump frequency Dependent on tSYS 184 200 216 kHz Charge pump tank capacitor Connected to VPS IVGBHI = 15 mA 420 470 520 nF 198 220 242 nF VVPS+5.1 V Charge pump flying capacitors Connected between CH1-CH2, CH3-CH4; IVGBHI = 15 mA VCP_UV Under voltage threshold Referenced to VVPS VVPS+3.9 - VhCP_UV Under voltage hysteresis Referenced to VVPS 250 - tCP_UV Under voltage filter time - 10 - 30 µs Referenced to GND - - 80 V VVGBHI_MAX Charge pump max voltage mV tCPstartup Startup time - - - 2 ms IBIAS_ON Internal absorption in when VGNSPx = ON Design info. Not tested in ATE - - 530 µA IBIAS_OFF Internal absorption in when VGNSPx = OFF Design info. Not tested in ATE - - 480 µA 5.2.5 VIO supply pin & SDO pin characteristics The VIO supply pin is used to feed SDO output driver. It can be connected either to 5 V or 3.3 V supply, in order to be compatible with different external I/O logic. In case of an overvoltage condition at the SDO output, the SDO driver is switched off and eventual back feeding current towards VIO is blocked. Once the over-voltage is removed from SDO-pin, the output is re-activated at NCS low-to-high transition. SDO overvoltage event is latched in SDO_OV_LATCH, cleared via SPI readout. Table below lists the electrical characteristics for the SDO output pin. DS12275 - Rev 8 page 22/151 L9945 Reset Note: Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 12. SDO pin electrical characteristics Symbol Parameter tsdo_trans Test condition Min. Max. Unit SDO Rise and Fall time CLOAD = 20 to 150 pF 5 35 ns tpcld Propagation delay – incl. Rise/Fall time (SCLK to data at SDO active) CLOAD = 150 pF - 50 ns tcsdv NCS = LOW to output SDO active CLOAD = 150 pF - 90 ns tpchdz NCS L/H to SDO @ high impedance - - 75 ns CIN_SPI Input capacitance at SDI; SDO; SCLK; NCS - - 10 pF VSDOH High output level ISDO = -2 mA VIO - 0.4 V - V VSDOL Low output level ISDO = 3.2 mA 0.4 V -5 5 µA -5 15 µA 2 30 µA NCS = HIGH; 0 < VSDO < VIO – 0.3 V ISDO_Leak Tri state leakage current NCS = HIGH; VSDO = VIO – 0.3 V NCS = HIGH; VSDO = VIO Over voltage detection threshold at SDO output (for reverse supply protection) Prevent output from damage; avoid back supply to VIO; no hysteresis required tOV_SDO_fil Overvoltage detection analog filter time - 100 700 ns tOFF_PROT_OV Overvoltage detection HS turn OFF/ON time at SDO. Includes analog filter time and comparator reaction time until 50% IOVpeak_SDO_HS 0.5 5 μs IOVpeak_SDO_HS Maximum possible peak reverse current at SDO HS before protection Turn Off VSDO = 36 V; VIO = 3 V; limited by RDSON only; HS channel On 90 250 mA VOV_SDO VIO + 0.05 VIO + 0.2 Note: The SDO pin electrical characteristics are also reported in the SPI table. SDO PCB trace must be routed carefully in order avoid spikes on SDO pin, which may generate an overvoltage failure. A pull-down resistor in the [10 - 47] kΩ range on SDO pin is also recommended. 5.3 Reset V The device is reset by the following two events: Power On Reset (POR) • DS12275 - Rev 8 0 ≤ VDD5 ≤ VPOR: – Logic is reset; – Outputs are in three-state, diagnostics regulators for open load detection are OFF; – No violation of leakage current requirements; – Charge pump is disabled. page 23/151 L9945 Output pre-drivers • VPOR ≤ VDD5 ≤ 4.5 V: – SPI functional (if VIO is stable); – Internal oscillator is functional and the logic is working correctly; – The outputs can switch according to the control; – Regulators for open load detection may provide wrong diagnostic; – Overcurrent shutdown is active but thresholds may be inaccurate. NRES assertion: • • • • • NRES input is active low; It is typically connected to the VDD5 reset of the ECU power supply; NRES is internally pulled up: in case of NRES pin left unconnected, NRES is inactive; Open load failure detection is inactive during NRES assertion; Charge pump is disabled while NRES is asserted. Both POR and NRES events are latched and readable via SPI: • After POR, the n_POR_LATCH is set and can be cleared via SPI readout; • When NRES is active, NRES_LATCH is set and can be cleared via SPI readout. The two reset events are ORed, so that full functionality is achieved only when both POR and NRES are released. The default configuration for the outputs after reset is Low-Side with NFET. Channels are three-stated until the output is enabled through the en_OUT_xx bit. After configuration and enable, all outputs follow the control signal as long as reset (NRES, POR) is not active. In case of a reset all outputs will be immediately disabled and all diagnostic and protection information will be lost. 5.4 Output pre-drivers This paragraph contains the available configurations for the output pre-drivers. Enable and control strategies are explained. Output diagnostic is also explained, along with other useful application information. 5.4.1 Available configurations There are eight pre-driver channels. Each channel can be independently configured in three different ways, via SPI configuration commands: • Low-Side with NFET; • High-Side with NFET; • High-Side with PFET. Channel side is programmed through LS_HS_config_xx bit, while FET type is selected through N_P_config_xx bit. Refer to Section 2 Applications in order to understand how the external FET must be mounted with respect to device pins. Complex configurations for H-Bridge and Peak & Hold are presented in their respective section. 5.4.2 Default configuration and output enable After reset channels are configured as Low-Side with NFET by default. Outputs are in three-state until they are configured and enabled through the en_OUT_xx bit. Channel 6 has an additional enable control via the EN6 input: EN6 is in logical AND with en_OUT_06 bit, meaning that both signals have to be set high in order to enable the output driver. This feature makes it suitable for safety relevant load control. EN6 status can be monitored reading EN6_STATE bit via SPI. If channel 6 has been disabled setting EN6 low, the event is latched in EN6_LATCH, cleared on SPI readout. 5.4.3 Output control The outputs can be controlled ON and OFF via SPI bit SPI_ON_OUTxx or input pins NONx. The selection of the control signal is independent for each channel and is programmed via the SPI_input_sel_xx bit: • SPI_input_sel_xx = 0: control via NONx input – The NONx inputs are active low, meaning that the output is ON when the input is low and vice-versa DS12275 - Rev 8 page 24/151 L9945 Output pre-drivers • SPI_input_sel_xx = 1: control via SPI_ON_OUTxx bit – The SPI_ON_OUTxx bit are positive asserted, meaning that the output is ON when the input is high and vice-versa The table below summarizes output behavior depending on control strategy and control input. Table 13. Output status depending on control strategy and control input SPI_input_sel_xx NONx SPI_ON_OUTxx External FET status 0 0 X(1) ON 0 1 X OFF 1 X 0 OFF 1 X 1 ON 1. All “X” = don't care. 5.4.4 Gate charge/discharge currents During normal operation external FET is actively switched ON/OFF by means of a pull up/pull down current source, as shown in Figure 12. Figure 12. Output pre-driver control Ratings: CM = 50 V for 12 V systems, 100 V for 24 V systems. VGBHI NONx = 0 or SPI_ON_OUTxx = 1 CM IPU RG IPD VPS NONx = 1 or SPI_ON_OUTxx = 0 NONx = 0 or SPI_ON_OUTxx = 1 RPD NONx = 1 or SPI_ON_OUTxx = 0 To load or battery IPU RG IPD CM To load or ground To load NFET output control GADG2702171056PS RPU PFET output control The pull up/pull down currents can be programmed via SPI through the GCC_config_xx bit, as shown in the table below: Table 14. Selection of gate charge/discharge currents GCC_config_xx 00 DS12275 - Rev 8 IPU / IPD [mA] Limited by external resistor (RG) Internally clamped to ICh0Gx/IDCh0Gx 01 20 10 5 11 1 page 25/151 L9945 Output pre-drivers In case GCC_config_xx is programmed "0b00", an external resistor RG is required for protecting the transistor gate against excessive current: the resistor must be mounted in series on the IPU / IPD path, as shown in Figure 12. However, to prevent charge pump stress, L9945 internally limits the maximum charge/discharge current to ICh0Gx/IDCh0Gx (refer to Table 15). External measures have to be taken to keep the external MOS reliably OFF in case of output three-state. For external NMOS a gate pull down resistor RPD is needed and for external PMOS a gate pull up resistor RPU is necessary (refer to Figure 12). In order to improve EMI behavior, an external Miller capacitor CM can be mounted between transistor gate and drain. Value of this capacitor depends on: • The switching frequency required by the application; • The programmed charge/discharge current. The AN "How To Improve EMI Behavior In Switching Applications" provides a guideline for CM selection. It also helps choosing the right value for IPU/IPD in order to reduce EMI. 5.4.5 Internal and external clamping The device guarantees a maximum gate to source voltage of 20 V by means of an internal clamping circuitry which limits the overdrive. However, such a clamp is not intended as a protection against external spikes or failures (STB/STG). Figure 13. Clamping for HS configuration Device side Board side Device side VPS Board side VPS VGBHI DRNxx Control signal CM IPU GNSPxx Control I PD signal SNGPxx Internal clamping Control signal IPU SNGPxx RG External clamping R PU RG Control I PD signal RPD Internal clamping GNSPxx CM DRNxx To load HS NFET External clamping To load HS PFET Ratings: NMOS ==> VGS = 20 V , PMOS ==> VSG = 20 V GADG2702171244PS Figure 13 shows the recommended clamping for the external FETs used in HS configuration. The internal clamping is meant to protect against overdrive but is not intended to be a recirculation path for the current. An external freewheeling diode is needed for inductive switching loads. DS12275 - Rev 8 page 26/151 L9945 Output pre-drivers Figure 14. Clamping for LS configuration VBATT Device side Board side To load External clamping VGBHI DRNxx Control signal IPU CM GNSPxx RG Control I PD signal RPD Internal clamping SNGPxx To PGND LS NFET GADG2702171519PS Figure 14 shows the recommended clamping solutions for the LS configuration. Voltage on the DRNx pin has to be limited to prevent component damage. A suppressor circuit can be used to clamp the voltage on DRNx pin (AMR is 60 V). For the freewheeling of inductive loads: • A Zener feedback to the gate can be a solution to allow active freewheeling; • A diode on DRNx pin can be used to allow passive freewheeling towards battery. 5.4.6 Electrical characteristics The table below lists the electrical characteristics for the output pre-drivers. Note: Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. A current flowing out of L9945 has minus (-) sign; a current flowing into L9945 has plus (+) sign. Charge currents turn ON the NMOS and OFF the PMOS. Discharge currents turn OFF the NMOS and ON the PMOS. Table 15. Output pre-driver stages electrical characteristics Symbol Parameter VGNSP -VSNGP Gate Output voltage (Reversed for PMOS) ICh3Gx Gate charge current NMOS Gate charge current PMOS Test condition GCC[1:0] = [1, 1] Min. Typ. Max. Unit 10 - 14 V -1.88 - -1.1 mA -1.85 - -0.55 mA ICh2Gx Gate charge current NMOS and PMOS GCC[1:0] = [1, 0] -8.6 - -4 mA ICh1Gx Gate charge current NMOS and PMOS GCC[1:0] = [0, 1] -32.4 - -19.6 mA -100 - -40 mA -77 - -43.5 mA ICh0Gx Gate charge current NMOS Gate charge current PMOS GCC[1:0] = [0, 0] IDCh3Gx Gate discharge current NMOS and PMOS GCC[1:0] = [1, 1] 0.75 - 1.9 mA IDCh2Gx Gate discharge current NMOS and PMOS GCC[1:0] = [1, 0] 3.8 - 7.4 mA IDCh1Gx Gate discharge current NMOS and PMOS GCC[1:0] = [0, 1] 16.8 - 27.4 mA IDCh0Gx Gate discharge current NMOS and PMOS GCC[1:0] = [0, 0] 55 - 101 mA Tsw_GC Delay to switch from GCC[a,b] to GCC[c,d] - - - 0.1 µs DS12275 - Rev 8 page 27/151 L9945 H-Bridge Symbol Parameter Test condition Min. Typ. Max. Unit Minimum peak current capability VPS > 7.5V Tested at VPS > 7.5 V and output shorted to GND 40 - - mA Equivalent capacitive load to be driven - 0.1 - - nF Turn ON/OFF delay test condition: 0.1 nF 50% NONx to 50% OFF gate current checked for LS/HS config (switch) - - 1.5 μs Turn OFF/ON delay 50% NONx to 50% ON gate current test condition: 0.1 nF checked for LS/HS config (switch) - - 1.5 μs ICR_CON Pre-driver Cross conduction current guaranteed by design - - 2 mA ILEAK_Gx GNSPx leakage current in tristate GNSP-SNGP voltage requirements < 20 V in case of external P-channel (Gate to SNGPx) -10 - 10 µA DRNx input leakage current POR or NRES active; V_DRNx = 0 V to 28 V -10 - 10 µA SNGPx input leakage current POR or NRES active or Normal mode; V_SNGPx = 0 V to 28 V -10 - 10 µA GNSP to SNGP voltage when OFF gate current is on - - - 100 mV Ipeak CLOAD td_OFF td_ON IDRNx ILEAK_S VGNSP-VSNGP 5.5 H-Bridge The pre-drivers can be configured into two independent H-Bridges. In this configuration Channels 1-4 are used for H-Bridge 1, while Channels 5-8 are used for H-bridge 2. The AN5311 "L9945 in H-Bridge configuration" covers all the main aspects of H-Bridge configuration. The device can handle up to two H-bridge. There are two possible configurations which can co-exist: • H-Bridge 1: it involves channels 1 (HS), 2 (HS), 3 (LS) and 4 (LS) and can be activated by setting HB1_config = 1 • H-Bridge 2: it involves channels 5 (HS), 6 (HS), 7 (LS) and 8 (LS) and can be activated by setting HB2_config = 1 Configurations above are automatically applied once the HBx_config bit is set. The N_P_config_xx bit set the MOSFET type (NMOS, PMOS) used in the H-bridge high-side. For H-bridge 2, EN6 must be set high to enable channel 6. 5.5.1 H-Bridge driving modes The H-Bridge must be controlled via the external NONx pins. Such inputs have different meanings while in HBridge mode: Table 16. NONx signals in H-bridge configuration HB1 HB2 Signal description NON1 NON5 NPWM – Negative asserted Pulse Width Modulation signal NON2 NON6 DIR – Direction signal NON3 NON7 HiZ – High Impedance (all FETs actively switched off, load floating) NON4 NON8 Not used Any attempt to control channels via SPI is ignored while H-Bridge mode is active. In driving mode the H-bridge work according to the following table: DS12275 - Rev 8 page 28/151 L9945 H-Bridge Table 17. Truth table HiZ DIR NPWM HBx_AFW Q1 Q2 Q3 Q4 Load’s driving direction 0 0 0 X (1) OFF ON ON OFF Reverse 0 0 1 0 OFF OFF ON OFF Freewheeling (reverse) 0 0 1 1 OFF OFF ON ON Active freewheeling (reverse) 0 1 0 X ON OFF OFF ON Forward 0 1 1 0 OFF OFF OFF ON Freewheeling (forward) 0 1 1 1 OFF OFF ON ON Active freewheeling (forward) 1 X X X OFF OFF OFF OFF High Impedance 1. X = don't care. The freewheeling is performed on low side, as shown in Figure 15. Software brake mode can be performed by setting the active freewheeling bit (HBx_AFW). DS12275 - Rev 8 page 29/151 L9945 H-Bridge Figure 15. H-bridge driving configurations VBR VBR Rshunt CH1_OC CH1 Q1 Q2 M Out1(HB+) CH3 Rshunt CH2_OC CH2 Out2(HB-) Q3 Q4 CH3_OC CH4 CH4_OC CH1 Q1 M Out1(HB+) CH3 Q2 Q4 CH3_OC CH4_OC GND NPWM = ‘0’; DIR = ‘1’; HBx_AFW=’x’; HiZ=’0' (Active) Freewheeling low-side (forward) NPWM = ‘0’; DIR = ‘0’; HBx_AFW=’x’; HiZ=’0' (Active) Freewheeling low-side (reverse) VBR Rshunt Q2 M Q3 CH2 Out2(HB-) Q4 CH3_OC VBR Rshunt CH2_OC Q1 High impedance VBR CH1_OC CH3 CH4 Rshunt GND Out1(HB+) Out2(HB-) Q3 Rshunt CH1 CH2 CH4 CH4_OC CH1_OC CH1 Q1 Q3 NPWM = ‘1’; DIR = ‘1’; HiZ=’0' HBx_AFW=’1' -> Freewheel through Q3 MOSFET HBx_AFW=’0' -> Freewheel through Q3 diode CH2 Out2(HB-) Q4 CH3_OC CH4 CH4_OC Rshunt GND Q2 M Out1(HB+) CH3 Rshunt CH2_OC CH1_OC CH1 CH2_OC Q1 OFF M Out1(HB+) CH3 Q3 OFF NPWM = ‘1’; DIR = ‘0’; HiZ=’0' HBx_AFW=’1' -> Freewheel through Q3 MOSFET HBx_AFW=’0' -> Freewheel through Q3 diode CH2 Out2(HB-) Q4 OFF CH3_OC CH4 CH4_OC Rshunt GND Q2 OFF Rshunt GND NPWM = ‘x’; DIR = ‘x’; HBx_AFW=’x’; HiZ=’1' GAPG0102161245CFT 5.5.2 H-Bridge diagnostics H-bridge status can be monitored by reading each channel diagnostic as if they operated independently (refer to Section 6.2 Diagnostics overview). However, different OC sensing strategies can be implemented, as discussed in Overcurrent detection. While in H-Bridge configuration, an extended set of values is available for OFF state diagnostic timer (tDIAG), as shown in H-Bridge OFF state diagnostic timings. 5.5.3 H-bridge dead time To prevent shoot-through (e.g. Q1 and Q3 ON) it's possible to choose different dead time values for both Hbridges independently. Such parameters are selectable via SPI through the HBx_dead_time bit according to the following table. DS12275 - Rev 8 page 30/151 L9945 H-Bridge Table 18. Dead time values HBx_dead_time [1] HBx_dead_time [0] Dead time (min) Dead time (typ) Dead time (max) Unit 0 0 0.5 1 1.5 µs 0 1 1 2 3 µs 1 0 3 4 5 µs 1 1 7 8 (default) 9 µs Note: x = H-bridge number The dead time intervenes in case of H-Bridge direction change, that is upon DIR transitions. The following table describes the output behavior in case of DIR transition. Table 19. Output response in case of DIR transition DIR Transition Q1/Q5 Q2/Q6 Q3/Q7 Q4/Q8 0→1 Turns ON after HBx_dead_time, if NPWM was ‘0’ before DIR switch and did not toggle during dead time Turns OFF immediately Turns OFF immediately Turns ON after HBx_dead_time 1→0 Turns OFF immediately Turns ON after HBx_dead_time, if NPWM was ‘0’ before DIR switch and did not toggle during dead time Turns ON after HBx_dead_time Turns OFF immediately Note: NPWM should be stable before applying the DIR transition, and it should not be switched during the dead-time due to DIR switch. Otherwise, once dead-time for DIR switch event has expired, the dead-time for NPWM transition will start, resulting in twice the dead-time applied. Once NPWM has been toggled at tNPWM_SWITCH time instant, DIR input shall not be switched within a defined grey-zone in respect to tNPWM_SWITCH . Grey zone is defined by: 5 tGREY = tNPWM_SWITCH  + HBx_dead_time ± fMAIN_CLK1 For further information refer to the AN "L9945_DIR_switching_recommendations". The dead timers also operate during NPWM switching activity. Transitions are described in the following table. Table 20. Output response in case of NPWM transition NPWM Transitio n DIR = 1 DIR = 0 DIR = 1 DIR = 0 Q1/Q5 Q2/Q6 Q3/Q7 Q4/Q8 HBx_AFW = 0 HBx_AFW = 1 HBx_AFW = 0 HBx_AFW = 1 0→1 Turns OFF after HBx_dead_time if NPWM is still ‘1’ Turns OFF immediately Kept OFF Turns ON after 2*HBx_dead_time if NPWM is still ‘1’ Kept OFF Turns ON after 2*HBx_dead_time if NPWM is still ‘1’ 1→0 Turned OFF immediately. Then, it turns ON after HBx_dead_time if NPWM is still ‘0’ Turns ON after HBx_dead_time if NPWM is still ‘0’ Kept OFF Turned OFF immediately Kept OFF Turned OFF immediately Note: DS12275 - Rev 8 in case NPWM is switched with a very high frequency, which is incompatible with HBx_dead_time, the HS will be kept OFF. This happens because every time NPWM toggles 1 → 0, the HS output is reset to its default value of ‘0’. However, this condition should be avoided by choosing switching frequency and duty-cycle in order to allow dead-timer to expire after both transitions. page 31/151 L9945 H-Bridge 5.5.4 H-bridge disabling When DIS/NDIS is asserted the H-bridge is disabled and all the pre-drivers are actively turned off. The same behavior is observed when HiZ or NRES is asserted. Table 21. H-bridge state for different DIS/NDIS and NRES NRES HiZ HBx_config DIS NDIS H-bridge state 0 0 1 0 1 All 4 MOSFET actively OFF 1 1 1 0 1 All 4 MOSFET actively OFF 1 0 1 0 0 All 4 MOSFET actively OFF 1 0 1 0 1 Normal operation 1 0 1 1 0 All 4 MOSFET actively OFF 1 0 1 1 1 All 4 MOSFET actively OFF HBx_config must not be changed while H-Bridge is operating. 5.5.5 Overcurrent detection strategies for H-Bridge The over current detection can be performed either by measuring the voltage drop on external shunt resistors or through the Drain to Source Measurement of each transistor (DSM). Each transistor of the H-Bridge can detect overcurrent independently. If an OC event occurs on a channel, the four devices will be actively shut-off and HBridge outputs will be three-stated. Diagnostic latches have always to be cleared before re-engaging the H-Bridge after an overcurrent detection. Different scenarios for OC detection are possible: • OC detection through one shunt resistor mounted on the low-side between SNGPx and PGNDxx pins, as shown in Figure 16. DSM used for OC detection on the HS transistors. – To avoid inhomogeneous OC protection over the H-Bridge, OC threshold programmed for HS via DSM must be adapted to the ones programmed on the LS via shunt sensing. OC threshold adaption must account for the RDSon of the HS devices. • OC detection through two shunt resistors. The first mounted on the low-side between SNGPx and PGNDxx pins, the second mounted on the high-side between GNSPx (PMOS)/DRNx (NMOS) and BATTxx pins (see Figure 16). – To avoid inhomogeneous OC threshold for the H-Bridge, the two shunt resistors must be equal and the four OC thresholds must hold the same value. • OC detection through DSM (see Figure 16) – In case the 4 MOSFETs are equal, the 4 OC thresholds must be equal; – In case the 2 FETs used on high-side are different from the ones on low-side, a different value for OC threshold must be specified for the HS pair. OC threshold adaption must account for the RDSon of the HS devices. DS12275 - Rev 8 page 32/151 L9945 H-Bridge Figure 16. OC detection strategies for H-Bridge: (left) one shunt resistor for LS, DSM for HS; (center) two shunt resistors; (right) DSM VBR VBR CH2_OC CH1_OC CH1 Q1 Q2 M Out1(HB+) CH3 Q3 CH2 Out2(HB-) Q4 CH3_OC Rshunt CH4 CH4_OC Rshunt CH1_OC CH1 Q1 M Out1(HB+) CH3 Q2 Q3 Q4 Rshunt GND CH2 Out2(HB-) CH3_OC GND VBR CH2_OC CH4 CH4_OC CH2_OC CH1_OC CH1 Q1 M Out1(HB+) CH3 Q2 Q3 CH3_OC CH2 Out2(HB-) Q4 CH4 CH4_OC GND GADG2802170759PS When shunt measurement is selected, current limitation feature is available. • In case current limitation feature is enabled (HBx_ILIM_en = 1), the comparator on CH3/CH7 is used for current limitation while the one on CH4/CH8 detects OC. In order to guarantee full protection of the load and the FETs, CH4/CH8 overcurrent comparator is enabled even if transistor is OFF phase. Therefore, in case Rshunt is shorted to battery, the OC event will be immediately detected; • In case current limitation feature is disabled (HBx_ILIM_en = 0), both LS channels are used for OC detection. OC comparators are active only in the ON phase of the transistors. OC detection timings depend on the selected sensing strategy, as explained in Section 6.3.3 OC sensing strategy. Once an actual OC event has been recognized, behavior depends on the current limitation feature: • If HBx_ILIM_en = 0, the current limitation feature is disabled and the H-Bridge is three-stated (all FETs actively OFF, load floating); • If HBx_ILIM_en = 1, the current limitation feature is enabled. The device will limit the current one more time after OC threshold crossing and, in case of failure still persisting, the H-Bridge is three-stated (all FETs actively OFF, load floating) after tOC + tOFF (refer to Figure 18). 5.5.6 Current limitation for H-Bridge Current limitation feature is able to limit the maximum current in the load modulating the NPWM signal, as shown in Figure 17. This allows keeping the current of the load below the current limitation threshold (ILIM_th). Current limitation function is available only when shunt measurement is selected and can be activated setting HBx_ILIM_en = 1. Current limitation threshold (I LIM_th) is set by OC_config_03 [5-0] bit for H-bridge 1 and OC_config_07 [5-0] bit for H-Bridge 2. Hence, channel 3 is no longer used for OC detection in H-Bridge 1, but it activates the current limitation. The same function is implemented on channel 7 in H-Bridge 2. DS12275 - Rev 8 page 33/151 L9945 H-Bridge Figure 17. Current limitation timing diagram NON1/5 (NPWM) Internal NPWM toff tBLANK_HB toc Ch3/7 toc Ch4/8 OC Failure Running Timers HBx_ILIM CH4/8 CH3/7 tBLANK_HB tBLANK_HB toff OC_th (CH4/8) tOC Current RShunt ILIM_th (CH3/7) 0A 0s tBLANK_HB toff Running Timers Current through Load and Rshunt Current through Load only t Current through Rshunt only toc GAPG0102161535CFT If the current stays above the programmed threshold (ILIM_th) longer than tOC, the H-bridge is driven into freewheeling phase (active freewheeling or not, depending on HBx_AFW bit) for a programmable OFF time (tOFF). During tOFF, high-side outputs are actively OFF but low-side outputs remain controlled according to DIR and HBx_AFW values, performing a freewheeling action on the low-side. Once tOFF expires, load current is compared against ILIM_th threshold: DS12275 - Rev 8 • In case load current is below ILIM_th, normal operation can continue (refer to Figure 17). • In case current is not below ILIM_th, the high-side channel is turned on for a tFIL_ON + tOC period and then turned off for another tOFF time. Such operation continues until either the current decreases below ILIM_th or the current reaches the overcurrent threshold and H-Bridge is three-stated (all FETs actively OFF, load floating) (refer to Figure 18). page 34/151 L9945 H-Bridge Note: since current limitation makes use of shunt sensing, the blanking time programmed for CH3/CH7 has no effect in detection timings. The blanking time has only effect on FETs using DSM. Figure 18. Current limitation iterations (until OC failure) NON1/5 (NPWM) Internal NPWM toff tBLANK_HB toc Ch3/7 toc Ch4/8 OC Failure Running Timers HBx_ILIM OC Failure CH4/8 CH3/7 tBLANK_HB tOC tBLANK_HB toff OC_th (CH4/8) tOC Current RShunt ILIM_th (CH3/7) freewheeling 0A 0s tBLANK_HB toff Running Timers toc Current through Load and Rshunt Current through Rshunt only t Current through Load only GAPG0102161522CFT When current limitation threshold is reached for the first time, a dedicated HBx_ILIM latch is set, indicating that current limitation function has been activated. This latch is cleared on SPI readout. The OFF time interval for current limitation (tOFF) is selectable via SPI according to HBx_toff bit: DS12275 - Rev 8 page 35/151 L9945 Peak & Hold Table 22. tOFF selection 5.5.7 HBx_toff [1-0] Min tOFF value Typical tOFF value Max tOFF value Unit 00 28 31 34 µs 01 42 48 52 µs 10 56 62.5 70 µs 11 110 125 140 µs H-Bridge OFF state diagnostic timings The device offers the possibility to select the OFF state diagnostic filter times tDIAG among two different strategies, selectable via HBx_tdiag_ext_config bit (refer to Table 23): • When HBx_tdiag_ext_config = 0, the diagnostic filter time tDIAG selected for CH1 (CH5) is automatically extended to all channels member of the bridge; • When HBx_tdiag_ext_config = 1, the diagnostic filter time tDIAG must be set individually for each channel member of the bridge. Regardless of the strategy selected, the tDIAG filter time can be programmed via tdiag_config_xx bit. Table 23. OFF state diagnostic timings for H-Bridge Symbol tdiag_config_xx Parameter Min. Typ. Max. Unit THB_diag_1 00 H-Bridge Diag Time 1 10 11.2 12.4 µs THB_diag_2 01 H-Bridge Diag Time 2 26 28.9 31.8 µs HBx_tdiag_ext_config = 0 THB_diag_3 10 H-Bridge Diag Time 3 36 40 44 µs (all channels set as CH1/CH5) THB_diag_4 11 H-Bridge Diag Time 4 46 51.2 56.4 µs TDIAG_HB_100 00 H-Bridge Diag Time 1 23 25.6 28.2 µs TDIAG_HB_101 01 H-Bridge Diag Time 2 55 61.2 67.4 µs HBx_tdiag_ext_config = 1 TDIAG_HB_110 10 H-Bridge Diag Time 3 95 105.6 116.2 µs (channels to be set individually) TDIAG_HB_111 11 H-Bridge Diag Time 4 135 150 165 µs 5.6 Comment Peak & Hold The pre-drivers can be configured into two independent peak & hold blocks. In this configuration Channels 1,4 are used for Peak & Hold 1, while Channels 2,3 are used for Peak & Hold 2. The device can handle up to two Peak & Hold branches. There are two possible configurations which can coexist: • Peak & Hold 1: it involves channels 1 (HS) and 4 (LS) and can be activated by setting PH1_config = 1; • Peak & Hold 2: it involves channels 2 (HS) and 3 (LS) and can be activated by setting PH2_config = 1. Configurations above are automatically applied once the PHx_config bit is set. The N_P_config_xx bit set the MOSFET type (NMOS, PMOS) used in the Peak & Hold high-side. 5.6.1 Peak & Hold driving mode All channels involved in the peak & hold configuration can be driven independently either via the corresponding NONx pin or via SPI, depending on SPI_INPUT_SEL_xx bit. An external microcontroller shall close the control loop in order to guarantee the desired current profile in the load. The device does not feature any internal current control capability while in peak & hold configuration. DS12275 - Rev 8 page 36/151 L9945 Peak & Hold 5.6.2 Peak & Hold diagnostics When in peak & hold configuration, diagnostic is performed independently on each channel, as if a low-side or high-side configuration was applied. The external microcontroller monitoring the device must properly combine the diagnostic information of the high-side channel to the one read on the low-side channel in order to determine the eventual fault type. Refer to Table 36 for the diagnostic codes. 5.6.3 ON state diagnostics ON state diagnostic latches are updated only when both channels are switched ON, that is, only when the current is supposed to actually flow in the load. In case an OC event occurs on a channel while the other is switched OFF, OC protection is triggered and the external FET is protected, but the diagnostic code of that channel is not updated. OC event will be eventually confirmed once both channels are switched ON (OC or OC pin will be reported). When in peak & hold configuration, L9945 protects the external FET against overcurrent as in the HS/LS configuration. However, an additional diagnostic code is available for this configuration: • If an overcurrent event occurs while the output is switching ON (tblank_oc timer still running), an OC pin failure is stored in the diagnostic latches → code "000" • If an overcurrent event occurs while the output is fully ON (tblank_oc timer expired), an OC failure is stored in the diagnostic latches → code "001" In order to detect a short across the load (SCL) failure, when an OC/OC pin event occurs simultaneously on HS and LS, an OC pin failure is latched for both sides. 5.6.4 OFF state diagnostics When both HS and LS are commanded OFF by the control signal, an intentional open load occurs on both load pins (refer to Internal regulator for open load (OL) detection). In order to avoid false OL detection, OL fault is masked in this condition. The diagnostic code reported in such case can be selected by programming the PHx_diag_strategy bit: • If PHx_diag_strategy = 0, "No OL/STG/STB failure" is reported → code "110"; • If PHx_diag_strategy = 1, "No diagnostic done" is reported → code "111". OL detection is guaranteed in case HS and LS have different states. In normal HS/LS configuration, the OFF diagnostic filter timer tDIAG is started every time a channel is switched OFF. In peak & hold configuration, two additional events generate a start condition for tDIAG: • • HS OFF, LS OFF → ON; LS OFF, HS OFF → ON. Therefore, an eventual OL fault is detected as soon as one of the two transistor is switched ON (after tDIAG) While HS is in the OFF state, if the voltage on the load node rises above VOL, the fast discharge current is activated to prevent false STB detection (refer to OFF state diagnostics and Fast charge/discharge currents). Referring to Figure 19, Table 24 shows the possible faults in peak & hold configuration, along with the diagnostic strategy. Refer to Table 36 for the diagnostic codes. Note: DS12275 - Rev 8 Table 24 has been compiled under the assumption of all channels starting from "No failure" state (100). Such state is reached during normal operation of the circuit when no failure has been detected by both OFF and ON state diagnostics. Therefore, the diagnostic strategy can be applied if at least one ON/OFF switching cycle has been completed without failures. In case the starting state was "No diagnostic done", the "No failure" state can be replaced with "No OL/STG/STB failure" (110) for OFF state diagnostics and with "No OC failure" (101) for ON state diagnostics. Diagnostic codes follow a priority concept. Diagnostic latches are reset in case of NRES/POR assertion or in case of SPI readout. Refer to Diagnostics overview to understand priority and FSM algorithm. page 37/151 L9945 Peak & Hold Table 24. Diagnostic strategy for peak & hold configuration Circuit state Fault type HS OFF HS ON HS OFF HS ON LS OFF LS OFF LS ON LS ON HS LS HS LS HS LS HS OUT1 STB STB No fail No fail No fail STB No fail(1) No fail(2) OUT1 STG No fail STG No fail(1) STG No fail No fail No diag(4) No diag(4) No STB/STG/OL(4) No STB/STG/OL(4) No fail OL OL No fail No fail (2) OUT4 STB STB No fail No fail(2) No fail STB No fail(1) No fail OUT4 STG No fail STG No fail(1) STG No fail No fail(2) No diag(4) No diag(4) No STB/STG/OL(4) No STB/STG/OL(4) No fail OL OL No fail No fail (1) No fail(1) No diag(4) No diag(4) No STB/STG/OL(4) No STB/STG/OL(4) No fail No fail No fail No fail OC pin(3) OC pin(3) OUT1 OL OUT4 OL OUT1-OUT4 short (SCL) OC OC pin(3) No fail(1) OC(1) LS No fail(1) OC(1) No fail (2) No fail (2) OC(3) OC pin(3) No fail(1) 1. Current limited by the load. In case current is greater than the OC threshold, protection is triggered and external FET is shut OFF. However, diagnostic latches are not updated. 2. Current in the shunt resistor is 0 mA. Micro may monitor. 3. Depending on transistor switch ON delay and configured tblank_oc. 4. Depending on PHx_diag_strategy. DS12275 - Rev 8 page 38/151 L9945 Internal oscillator Figure 19. Possible faults in peak & hold configuration VBATT BATT12 RSH DRN1 HS NMOS RM CM GNSP1 RG CBATT M1 RPD GND STB SNGP1 OUT1 VBATT OL CEMI STG LOAD DFW GND GND BATT34 OL SCL STB DRN4 OUT4 RFB DFB DZFB CEMI STG LS NMOS CM GNSP4 RM GND RG M1 RPD SNGP4 RSH PGND34 5.7 GADG2802171105PS Internal oscillator The L9945 has an internal oscillator providing the timing and control for all device operating functions. The nominal clock frequency is 10 MHz. The oscillator is functional when VDD5 > VPOR. 5.7.1 Spread spectrum In order to minimize the noise generated by the internal clock signal, the device offers the spread spectrum functionality. Such feature is disabled by default and can be activated by programming the spread_spectrum bit. 5.7.2 Internal oscillator electrical characteristics The table below reports the detailed electrical characteristics of the internal oscillator. Note: DS12275 - Rev 8 Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. page 39/151 L9945 Digital I/Os Table 25. Internal oscillator electrical characteristics Symbol Parameter Test condition fMAIN_CLK1 Clock Frequency tolMAIN_CLK Tolerance of frequency of internal clock oscillator 5.8 Typ. - 10 - MHz -7.7 fMAIN_CLK1 7.7 % - -4 - 4 % - - 80 - kHz - fMOD_range_MAIN Clock frequency modulation range spread spectrum enabled fMOD_MAIN Min. Spread spectrum modulation frequency Spread spectrum disabled; 4.5 V < VVDD5 ≤ 36 V Max. Unit Digital I/Os Table 1 reports each pin functionality, along with the pull-up/pull-down implementation. Back supply current into any digital pin is not allowed. For detailed information about the functionality of the SPI related pins (SCK, SDI, SDO, NCS), refer to Serial Peripheral Interface (SPI). For the electrical characteristics of the SDO output refer to VIO supply pin & SDO pin characteristics. For detailed information about the functionality of the reset pin (NRES), refer to Reset. For detailed information about the functionality of the channel control pins (NONx and EN6), refer to Output predrivers. For detailed information about the functionality of the device disable pins (DIS and NDIS), refer to Disable sources. 5.8.1 Digital I/Os electrical characteristics The table below lists the electrical characteristics for the digital pins. Note: Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. Table 26. Digital I/Os electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit VIN_L Low input level - - - 0.75 V VIN_H High input level - 1.75 - - V Hysteresis - 0.1 - 0.5 V IPU Input pull-up current source NONx, NRES, DIS, NCS, SDI, SCK -30 - -100 µA IPD Input pull-down current sink NDIS, EN6 30 - 100 µA Filter time Applies to NRES, DIS, NDIS 0.5 - 5.0 μs Low output level for NDIS bidirectional pin VDD5 > VPOR; INDIS = 5 mA - - 0.4 V VIN_HYS tFIL_a VNDISL Note: DS12275 - Rev 8 The NDIS bidirectional pin features internal protection against overvoltage when used as output. Such electrical characteristics are listed in the DIS & NDIS pins paragraph. page 40/151 L9945 Serial Peripheral Interface (SPI) 5.9 Serial Peripheral Interface (SPI) The device is equipped with a Serial Peripheral Interface implementing a 32-bit, synchronous, full duplex, serial protocol. The interface is used to configure the L9945 by programming its internal registers. Device status and diagnostic information can also be read via SPI. 5.9.1 SPI Quick Look Table 27. SPI quick look Parameter Frame length SPI Mode Max Frequency Protocol Chip Select Signal Active State Endianess Value 32 bit or multiple Mode 1 (CPOL = 0 & CPHA = 1) 5 MHz Out of frame Active Low MSB first The SPI can work in two different ways: parallel operation and daisy chain. These two methods can co-exist, as shown in Figure 20, where a parallel communication is implemented between a master device and three subblocks. Two of them are daisy chains while the last one is made of a single device. In the example, three Chip Select (CS) wires are used for communicating with 6 devices. 5.9.2 Parallel operation In parallel operation the communication is performed between a device, named master and one or more devices, named slaves. The master can start/stop the communication and generates the clock signal. Each slave device has a dedicated chip select (CS) signal, used to address the communication between the master and the selected slave. 5.9.3 Daisy chain In daisy chain configuration, master device can communicate with several slaves using only one wire for chip select (CS). All the slaves in the daisy chain are selected when the CS is in the active state. The serial output line of every slave is connected to the serial input line of the following device. This means that data shifted out by a device is shifted in the following one. For instance, after each 32 clock chunk, an entire frame is transferred from a slave to another. Example given, if a three devices chain is implemented, after 96 clock pulses, the master will program the slaves by shifting out three different frames (each one made up of 32 bits). The first frame shifted out of the master will reach the last device of the chain, the second frame will reach the mid device while the third frame will be shifted into the first member of the chain (refer to Figure 21). DS12275 - Rev 8 page 41/151 L9945 Serial Peripheral Interface (SPI) Figure 20. Daisy chain and parallel operation uC shift register SDO CLK reads from IC A-IC C NCS1 NCS1 NCS2 NCS3 NCS1: low for 96 clocks CLK CLK NCS1 IC A: L9945 SDI SDI writes into IC A-IC C CLK NCS1 IC B: L9945 shift register SDO SDI shift register CLK IC C: L9945 SDO shift register SDI SDO three devises in one daisy chain reads from IC D -E NCS2: low for 64 clocks CLK NCS2 CLK NCS2 IC D: L9945 SDI writes into IC D -E shift register CLK IC E: L9945 SDO SDI shift register SDO two devises in one daisy chain reads from IC F NCS3: low for 32 clocks CLK NCS3 writes into IC F CLK IC F: L9945 SDI shift register SDO single chain GAPG0102161614CFT Figure 21. Data transfer in daisy chain operation master SDI SDO device 3 SDO device 2 SDO device 1 master SDO SDI device 3 SDI device 2 SDI device 1 NCS1 CLK GADG2802171135PS 5.9.4 SPI electrical characteristics signal and the timing diagram This section contains the electrical characteristics of the SPI signal and the timing diagram. Note: DS12275 - Rev 8 Tj = Tj_op; VVPS_UV < VVPS < 60 V, all supplies are independent; 4.5 V < VDD5 < 5.5 V; 3.0 V < VIO < 5.5 V, unless otherwise noted. page 42/151 L9945 Serial Peripheral Interface (SPI) Table 28. SPI electrical characteristics Symbol fSCK Parameter Comment Min. Max. Unit Clock frequency (50% duty cycle) SPI works for all frequencies 0 5 MHz SDO Rise and Fall time 20 pF to 150 pF load 5 35 ns tclh Minimum time SCLK=HIGH - 75 - ns tcll Minimum time SCLK=LOW - 75 - ns tpcld Propagation delay – incl. Rise/Fall time (SCLK to data at SDO active) 150 pF load - 50 ns tcsdv NCS = LOW to output SDO active 150 pF load - 90 ns tsclch SCLK low before NCS low (setup time SCLK to NCS change H/L) - 75 - ns SCLK change L/H after NCS = low - 600 - ns tscld SDI input setup time (SCLK change H/L after SDI data valid) - 15 - ns thcld SDI input hold time (SDI data hold after SCLK change H/L) - 15 - ns tsclcl SCLK low before NCS high - 100 - ns thclch SCLK high after NCS high - 100 - ns tpchdz NCS L/H to SDO @ high impedance - - 75 ns tonNCS NCS min. high time Minimum high time between two consecutive commands 400 - ns CIN_SPI Input capacitance at SDI; SDO; SCLK; NCS - - 10 pF NCS Filter time (Pulses ≤ tfNCS will be ignored) - 10 40 ns VSDOH High output level ISDO = -2 mA VIO - 0.4 V - V VSDOL Low output level ISDO = 3.2 mA - 0.4 V -5 15 µA 2 30 µA tsdo_trans SCLK change L/H after NCS = low thclcl_app tfNCS NCS = HIGH; ISDO_Leak Three state leakage current 0 < VSDO ≤ VIO – 0.3 V NCS = HIGH; VSDO = VIO SDO protection; 0 V < VIO < 36 V; 0 < VSDO < 36 V; all voltages are independent VOV_SDO Over voltage detection threshold at SDO output - Overvoltage detection analog filter time - 100 700 ns tOFF_PROT_OV Overvoltage detection HS turn OFF/ON time at SDO - 0.5 5 μs IOVpeak_SDO_HS Maximum possible peak reverse current at SDO HS before protection Turn Off VSDO = 36 V; VIO = 3 V; limited by RDSON only 90 250 mA Communication Timeout DIS/NDIS released after NRES release. 55 85 ms Deadline for the first communication engagement DIS/NDIS released before NRES release. 110 165 ms tOV_SDO_fil VIO + 0.05 VIO + 0.2 V Communication Check tCC tCC_INIT DS12275 - Rev 8 page 43/151 L9945 Serial Peripheral Interface (SPI) Figure 22. SPI timing diagram t hclcl_app t ON_NCS t sclcl Tsclk NCS t clh t cll t scld t hcld SCK SDI t pchdz t pcld t csdv SDO GADG2802171207PS Figure 22 shows that the device has CPOL = 0 and CPHA = 1. During Reset, SDO is forced into a high impedance state and any inputs from SCLK and SDI are ignored. 5.9.5 SPI protocol The SPI protocol features frames structured as follows: Table 29. SPI protocol Command Data MSB LSB MOSI C3 C2 C1 C0 R/W D26 D25 D24 D23 D22 D21 D20 …. D3 D2 D1 P MISO C3 C2 C1 C0 R/W R26 R25 R24 R23 R22 R21 R20 …. R3 R2 R1 P The MSB of each frame will be shifted in/out first. Each frame is equipped with an odd parity bit (LSB). The response is out of frame, so the response to Nth frame will be received when sending the (N+1)th frame. Figure 23. Out of frame response SDI SDO frame A frame B frame C (previous response) response to frame A response to frame B GADG2802171255PS The response frame 0x00000000 will be issued in the following cases: • After a reset event (POR or NRES assertion) • Invalid command received (see Table 30. SPI MOSI list for the list of available commands) • Number of SCK pulses not multiple of 32 • Parity error on the received command Chip select (NCS) assertion without any following SCK pulse is ignored and doesn't generate any error. In order to ignore spurious transitions, NCS input is equipped with a deglitch filter tfNCS. DS12275 - Rev 8 page 44/151 L9945 SPI MOSI/MISO list 5.10 SPI MOSI/MISO list The following paragraph contains the SPI MOSI and MISO list. Each frame consists of 32 bits with odd parity. Protocol is out of frame. The following table contains links to SPI commands that can be sent on MOSI line, along with their description. The corresponding answers issued by L9945 on MISO line are also described and linked on the right columns. Note: All MISO default values have been scanned performing read only requests ("R/W" = 1). Table 30. SPI MOSI list MOSI Request Answer MISO COMMAND 0 Spread spectrum and diagnostic enable,OUT1-8 control, input selection and protection disable Spread spectrum and diagnostic enable, input selection, protection disable and output voltage status RESPONSE 0 COMMAND 1 OUT1 configuration and H-Bridge 1 diagnostic time OUT1 configuration and H-Bridge 1 diagnostic time RESPONSE 1 COMMAND 2 OUT2 configuration, H-Bridge 1 current limitation timing, BCF selection OUT2 configuration, H-Bridge 1 current limitation timing, BCF selection RESPONSE 2 COMMAND 3 OUT3 configuration, H-Bridge 1 current limitation enable and active freewheeling, gate charge/ discharge current override OUT3 configuration, H-Bridge 1 current limitation enable and active freewheeling, gate charge/ discharge current override RESPONSE 3 COMMAND 4 OUT4 configuration, P&H1 configuration, H-Bridge 1 OUT4 configuration, P&H1 configuration, H-Bridge 1 enable enable RESPONSE 4 COMMAND 5 OUT 5 configuration and H-Bridge 2 diagnostic time OUT 5 configuration and H-Bridge 2 diagnostic time RESPONSE 5 COMMAND 6 OUT6 configuration, H-Bridge 2 current limitation timing OUT6 configuration, H-Bridge 2 current limitation timing RESPONSE 6 COMMAND 7 OUT7 configuration, H-Bridge 2 current limitation enable and active freewheeling OUT7 configuration, H-Bridge 2 current limitation enable and active freewheeling RESPONSE 7 COMMAND 8 OUT8 configuration, P&H2 configuration, H-Bridge 2 OUT8 configuration, P&H2 configuration, H-Bridge 2 enable enable COMMAND 9 Diagnostic read and diagnostic pulses RESPONSE 8 H-Bridge1-2 current limitation latches and channels diagnostic status RESPONSE 9 COMMAND 10 BIST request and CC enable BIST & HWSC result and device status RESPONSE 10 COMMAND 11 Channel 1-4 control signal integrity Channel 1-4 control signal integrity RESPONSE 11 COMMAND 12 Channel 5-8 control signal integrity Channel 5-8 control signal integrity RESPONSE 12 COMMAND 13 Device status, battery and temperature monitor Device status, battery and temperature monitor RESPONSE 13 Note: ΔT = TjFET: Tj TjFET = junction temperature of the external FET Tj = junction temperature of L9945. DS12275 - Rev 8 page 45/151 L9945 SPI MOSI/MISO list 5.10.1 COMMAND X frame partitioning COMMAND 0 Description 9 8 7 6 5 4 3 2 1 0 SPI_ON_OUT_08 SPI_ON_OUT_07 SPI_ON_OUT_06 SPI_ON_OUT_05 SPI_ON_OUT_04 SPI_ON_OUT_03 SPI_ON_OUT_02 SPI_ON_OUT_01 PARITY PROT_DISABLE_02 PROT_DISABLE_03 PROT_DISABLE_04 PROT_DISABLE_05 PROT_DISABLE_06 PROT_DISABLE_07 PROT_DISABLE_08 SPI_INPUT_SEL_01 SPI_INPUT_SEL_02 SPI_INPUT_SEL_03 SPI_INPUT_SEL_04 SPI_INPUT_SEL_05 SPI_INPUT_SEL_06 SPI_INPUT_SEL_07 SPI_INPUT_SEL_08 ENABLE_DIAGNOSTIC C SPREAD_SPECTRUM R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_DISABLE_01 Frame partitioning Spread spectrum and diagnostic enable,OUT1-8 control, input selection and protection disable [31:28] C: Command 0 0000 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26] SPREAD_SPECTRUM: Activates or deactivates the spread spectrum functionality 0: Deactivated 1: Activated [25] ENABLE_DIAGNOSTIC: Enables or disables the diagnostics for all outputs. When set to "0" diagnostics for all outputs is "No diagnostic done". 0: Diagnostic disable 1: Diagnostic enable [24] SPI_INPUT_SEL_08: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [23] SPI_INPUT_SEL_07: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [22] SPI_INPUT_SEL_06: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [21] SPI_INPUT_SEL_05: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [20] SPI_INPUT_SEL_04: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI DS12275 - Rev 8 page 46/151 L9945 SPI MOSI/MISO list [19] SPI_INPUT_SEL_03: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [18] SPI_INPUT_SEL_02: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [17] SPI_INPUT_SEL_01: Driving mode selection bit (output driven by SPI or NON) 0: Output controlled via NONx 1: Output controlled via SPI [16] PROT_DISABLE_08: Protection disable for CH8. As long as the bit is set, CH8 is kept actively OFF 0: Output enabled 1: Output OFF [15] PROT_DISABLE_07: Protection disable for CH7. As long as the bit is set, CH7 is kept actively OFF 0: Output enabled 1: Output OFF [14] PROT_DISABLE_06: Protection disable for CH6. As long as the bit is set, CH6is kept actively OFF 0: Output enabled 1: Output OFF [13] PROT_DISABLE_05: Protection disable for CH5. As long as the bit is set, CH5 is kept actively OFF 0: Output enabled 1: Output OFF [12] PROT_DISABLE_04: Protection disable for CH4. As long as the bit is set, CH4 is kept actively OFF 0: Output enabled 1: Output OFF [11] PROT_DISABLE_03: Protection disable for CH3. As long as the bit is set, CH3 is kept actively OFF 0: Output enabled 1: Output OFF [10] PROT_DISABLE_02: Protection disable for CH2. As long as the bit is set, CH2 is kept actively OFF 0: Output enabled 1: Output OFF [9] PROT_DISABLE_01: Protection disable for CH1. As long as the bit is set, CH1 is kept actively OFF 0: Output enabled 1: Output OFF [8] SPI_ON_OUT_08: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [7] SPI_ON_OUT_07: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [6] SPI_ON_OUT_06: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [5] SPI_ON_OUT_05: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON DS12275 - Rev 8 page 47/151 L9945 SPI MOSI/MISO list [4] SPI_ON_OUT_04: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [3] SPI_ON_OUT_03: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [2] SPI_ON_OUT_02: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [1] SPI_ON_OUT_01: SPI output control bit (switches ON/OFF the output) 0: Output OFF 1: Output ON [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 48/151 L9945 SPI MOSI/MISO list COMMAND 1 Description: 3 2 1 0 PARITY 4 EN_OUT_01 5 LS_HS_CONFIG_01 6 N_P_CONFIG_01 7 GCC_CONFIG_01 8 DIAG_I_CONFIG_01 9 OC_DS_SHUNT_01 TBLANK_OC_01 OC_BATT_COMP_01 OC_CONFIG_01 OC_TEMP_COMP_01 OC_READ_01 TDIAG_CONFIG_01 HB1_TDIAG_EXT_CONFIG C HB1_DEAD_TIME R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_01 Frame partitioning OUT1 configuration and H-Bridge 1 diagnostic time [31:28] C: Command 1 0001 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [25:26] HB1_DEAD_TIME: H-bridge1 dead time to avoid cross conduction 00: 1 µs 01: 2 µs 10: 4 µs 11: 8 µs [24] HB1_TDIAG_EXT_CONFIG: Selection of tdiag timers for H-bridge 1. This function only applies when HB1_config = 1 0: H-bridge tdiag timers for HB1. The programmed TDIAG_CONFIG_01 will be extended to CH2. CH3 and CH4. 1: Standard tdiag timers for HB1. The programmed TDIAG_CONFIG_01 is valid only for CH1, while CH2, CH3 and CH4 must be set individually. [23:22] TDIAG_CONFIG_01: H-bridge 1 OFF state diagnostic blanking/filter timer. This values are valid only when HB1_tdiag_ext_config = 0 & HB1_config = 1. 00: 11.2 µs 01: 28.9 µs 10: 40 µs 11: 51.2 µs OFF state diagnostic blanking/filter timer for CH1. It is valid for HB1 only when HB1_tdiag_ext_config = 1 & HB1_config = 1 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_01: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold DS12275 - Rev 8 page 49/151 L9945 SPI MOSI/MISO list [20:15] OC_CONFIG_01: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_01: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C [12] OC_BATT_COMP_01: Over current detection with battery compensation. 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_01: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_01: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_01 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_01: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_01: CH1 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_01: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_01: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_01: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_01: Enable output 01 0: Output disabled 1: Output enabled DS12275 - Rev 8 page 50/151 L9945 SPI MOSI/MISO list [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 51/151 L9945 SPI MOSI/MISO list COMMAND 2 Description: 3 2 1 0 PARITY 4 EN_OUT_02 5 LS_HS_CONFIG_02 6 N_P_CONFIG_02 7 GCC_CONFIG_02 8 DIAG_I_CONFIG_02 9 OC_DS_SHUNT_02 TBLANK_OC_02 OC_BATT_COMP_02 OC_CONFIG_02 OC_TEMP_COMP_02 OC_READ_02 TDIAG_CONFIG_02 BATT_FACT_CONFIG C HB1_TOFF R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_02 Frame partitioning Output configuration OUT2 [31:28] C: Command 2 0010 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26:25] HB1_TOFF: H-bridge1 off timer during current limitation 00: 31 µs 01: 48 µs 10: 62.5 µs 11: 125 µs [24] BATT_FACT_CONFIG: Selection of the factor used in battery compensation 0: Factor for CV 1: Factor for PV [23:22] TDIAG_CONFIG_02: OFF state diagnostic blanking/filter timer for output 02. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_02: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_02: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_02: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C DS12275 - Rev 8 page 52/151 L9945 SPI MOSI/MISO list [12] OC_BATT_COMP_02: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_02: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_02: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_02 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_02: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_02: CH2 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_02: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_02: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_02: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_02: Enable output 02 0: Output disabled 1: Output enabled [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 53/151 L9945 SPI MOSI/MISO list COMMAND 3 Description: 3 2 1 0 PARITY 4 EN_OUT_03 5 LS_HS_CONFIG_03 6 N_P_CONFIG_03 7 GCC_CONFIG_03 8 DIAG_I_CONFIG_03 9 OC_DS_SHUNT_03 TBLANK_OC_03 OC_BATT_COMP_03 OC_CONFIG_03 OC_TEMP_COMP_03 OC_READ_03 TDIAG_CONFIG_03 GCC_OVERRIDE_CONFIG HB1_AFW C HB1_ILIM_EN R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_03 Frame partitioning Output configuration OUT2 [31:28] C: Command 3 0011 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26] HB1_ILIM_EN: H-bridge1 current limit activation. CH3 OC threshold is used for current limitation, it is only valid for Shunt measurement 0: Current limitation not active 1: Current limitation active [25] HB1_AFW: H-bridge1 active freewheel configuration on LS 0: Passive freewheeling 1: Active freewheeling [24] GCC_OVERRIDE_CONFIG: Selection of the GCC override configuration upon OC detection. It has no effect if GCC[1:0] = '00' (current limited by external resistor) 0: Selective override: 1 mA --> 5 mA 5 mA --> 20 mA 1: Global override: 1 mA --> 20 mA 5 mA --> 20 mA [23:22] TDIAG_CONFIG_03: OFF state diagnostic blanking/filter timer for output 03. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_03: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_03: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 DS12275 - Rev 8 page 54/151 L9945 SPI MOSI/MISO list [14:13] OC_TEMP_COMP_03: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C [12] OC_BATT_COMP_03: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_03: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_03: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_03 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_03: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_03: CH3 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_03: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_03: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_03: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_03: Enable output 03 0: Output disabled 1: Output enabled DS12275 - Rev 8 page 55/151 L9945 SPI MOSI/MISO list [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 56/151 L9945 SPI MOSI/MISO list COMMAND 4 Description: 3 2 1 0 PARITY 4 EN_OUT_04 DIAG_I_CONFIG_04 5 LS_HS_CONFIG_04 6 N_P_CONFIG_04 7 GCC_CONFIG_04 8 OC_DS_SHUNT_04 9 TBLANK_OC_04 OC_BATT_COMP_04 OC_CONFIG_04 OC_TEMP_COMP_04 OC_READ_04 TDIAG_CONFIG_04 PH1_CONFIG PH1_diag_strategy C HB1_CONFIG R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_04 Frame partitioning OUT4 configuration, P&H1 configuration, H-Bridge 1 enable [31:28] C: Command 4 0100 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26] HB1_CONFIG: Configures CH1-CH2-CH3-CH4 for H-bridge1 operation 0: H-bridge not configured 1: CH1-CH4 configured as H-bridge [25] PH1_DIAG_STRATEGY: OL masking strategy to prevent false OL assertion in P&H1 configuration 0: "No OL/STG /STB" failure reported 1: "No diagnostic done" reported [24] PH1_CONFIG: Configures CH1-CH4 for Peak and Hold1 operation 0: Peak and Hold1 not configured 1: Peak and Hold1 configured [23:22] TDIAG_CONFIG_04: OFF state diagnostic blanking/filter timer for output 04. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_04: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_04: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_04: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C DS12275 - Rev 8 page 57/151 L9945 SPI MOSI/MISO list [12] OC_BATT_COMP_04: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_04: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_04: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_04 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_04: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_04: CH4 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_04: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_04: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_04: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_04: Enable output 04 0: Output disabled 1: Output enabled [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 58/151 L9945 SPI MOSI/MISO list COMMAND 5 Description 3 2 1 0 PARITY 4 EN_OUT_05 5 LS_HS_CONFIG_05 6 N_P_CONFIG_05 7 GCC_CONFIG_05 8 DIAG_I_CONFIG_05 9 OC_DS_SHUNT_05 TBLANK_OC_05 OC_BATT_COMP_05 OC_CONFIG_05 OC_TEMP_COMP_05 OC_READ_05 TDIAG_CONFIG_05 HB2_TDIAG_EXT_CONFIG C HB2_DEAD_TIME R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_05 Frame partitioning OUT 5 configuration and H-Bridge 2 diagnostic time [31:28] C: Command 5 0100 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26:25] HB2_DEAD_TIME: CH-bridge2 dead time to avoid cross conduction 00: 1 µs 01: 2 µs 10: 4 µs 11: 8 µs [24] HB2_TDIAG_EXT_CONFIG: Selection of tdiag timers for H-bridge 2. This function only applies when HB2_config = 1 (command 8) 0: H-bridge tdiag timers for HB2. The programmed TDIAG_CONFIG_05 will be extended to CH6, CH7 and CH8. 1: Standard tdiag timers for HB2. The programmed TDIAG_CONFIG_05 is valid only for CH5, while CH6, CH7 and CH8 must be set individually. [23:22] TDIAG_CONFIG_05: H-bridge 2 OFF state diagnostic blanking/filter timer. This values are valid only when HB2_tdiag_ext_config = 0 & HB2_config =1 00: 11.2 µs 01: 28.9 µs 10: 40 µs 11: 51.2 µs OFF state diagnostic blanking/filter timer for output 05. It has no effect if HB2_config = 1 & HB2_tdiag_ext_config = 1 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs DS12275 - Rev 8 page 59/151 L9945 SPI MOSI/MISO list [21] OC_READ_05: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_05: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_05: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C [12] OC_BATT_COMP_05: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_05: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_05: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_05 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_05: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_05: CH5 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_05: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_05: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_05: Configures the channel as LS or HS 0: LS configuration 1: HS configuration DS12275 - Rev 8 page 60/151 L9945 SPI MOSI/MISO list [1] EN_OUT_05: Enable output 05 0: Output disabled 1: Output enabled [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 61/151 L9945 SPI MOSI/MISO list COMMAND 6 Description 3 2 1 0 PARITY 4 EN_OUT_06 5 LS_HS_CONFIG_06 6 N_P_CONFIG_06 7 GCC_CONFIG_06 8 DIAG_I_CONFIG_06 9 OC_DS_SHUNT_06 TBLANK_OC_06 OC_BATT_COMP_06 OC_CONFIG_06 OC_TEMP_COMP_06 OC_READ_06 TDIAG_CONFIG_06 NOT_USED_FIXED_PATTERN C HB2_TOFF R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_06 Frame partitioning OUT2 configuration, H-Bridge 2 current limitation timing [31:28] C: Command 6 0110 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26:25] HB2_TOFF: H-bridge2 off timer during current limitation 00: 31 µs 01: 48 µs 10: 62.5 µs 11: 125 µs [24] FIXED_PATTERN 0 [23:22] TDIAG_CONFIG_06: OFF state diagnostic blanking/filter timer for output 06. It has no effect if HB2_config =1 & HB2_tdiag_ext_config = 0. 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_06: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_06: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_06: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C DS12275 - Rev 8 page 62/151 L9945 SPI MOSI/MISO list [12] OC_BATT_COMP_06: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_06: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_06: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_06 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_06: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_06: CH6 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_06: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_06: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_06: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_06: Enable output 06 0: Output disabled 1: Output enabled [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 63/151 L9945 SPI MOSI/MISO list COMMAND 7 Description 3 2 1 0 PARITY 4 EN_OUT_07 5 LS_HS_CONFIG_07 6 N_P_CONFIG_07 7 GCC_CONFIG_07 8 DIAG_I_CONFIG_07 9 OC_DS_SHUNT_07 TBLANK_OC_07 OC_BATT_COMP_07 OC_CONFIG_07 OC_TEMP_COMP_07 OC_READ_07 TDIAG_CONFIG_07 FIXED_PATTERN HB2_AFW C HB2_ILIM_EN R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_07 Frame partitioning OUT7 configuration, H-Bridge 2 current limitation enable and active freewheeling [31:28] C: Command 7 0111 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26] HB2_ILIM_EN: H-bridge2 current limit activation. CH7 OC threshold is used for current limitation, only valid with Shunt measurement 0: Current limitation not active 1: Current limitation active [25] HB2_AFW: H-bridge2 active freewheel configuration on LS 0: Passive freewheeling 1: Active freewheeling [24] FIXED_PATTERN 0 [23:22] TDIAG_CONFIG_07: OFF state diagnostic blanking/filter timer for output 07. It has no effect if HB2_config =1 & HB2_tdiag_ext_config = 0. 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_07: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_07: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_07: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C DS12275 - Rev 8 page 64/151 L9945 SPI MOSI/MISO list [12] OC_BATT_COMP_07: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_07: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_07: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_07 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_07: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_07: CH7 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_07: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_07: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_07: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_07: Enable output 07 0: Output disabled 1: Output enabled [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 65/151 L9945 SPI MOSI/MISO list COMMAND 8 Description: 3 2 1 0 PARITY 4 EN_OUT_08 DIAG_I_CONFIG_08 5 LS_HS_CONFIG_08 6 N_P_CONFIG_08 7 GCC_CONFIG_08 8 OC_DS_SHUNT_08 9 TBLANK_OC_08 OC_BATT_COMP_08 OC_CONFIG_08 OC_TEMP_COMP_08 OC_READ_08 TDIAG_CONFIG_08 PH2_CONFIG PH2_diag_strategy C HB2_CONFIG R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_08 Frame partitioning OUT8 configuration, P&H2 configuration, H-Bridge 2 enable [31:28] C: Command 8 1000 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26] HB2_CONFIG: Configures CH5-CH6-CH7-CH8 for H-bridge2 operation 0: Not H-bridge configured 1: CH5-CH8 configured as H-bridge [25] PH2_DIAG_STRATEGY: OL masking strategy to prevent false OL assertion in P&H2 configuration 0: "No OL/STG /STB" failure reported 1: "No diagnostic done" reported [24] PH2_CONFIG: Configures CH2-CH3 for Peak and Hold2 operation 0: Peak and Hold2 not configured 1: Peak and Hold2 configured [23:22] TDIAG_CONFIG_08: OFF state diagnostic blanking/filter timer for output 08. It has no effect if HB2_config =1 & HB2_tdiag_ext_config = 0. 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs [21] OC_READ_08: Selection of the OC threshold to read. Fixed threshold or actual threshold. 0: Read fixed OC threshold 1: Read actual OC threshold [20:15] OC_CONFIG_08: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 [14:13] OC_TEMP_COMP_08: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C DS12275 - Rev 8 page 66/151 L9945 SPI MOSI/MISO list [12] OC_BATT_COMP_08: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated [11:9] TBLANK_OC_08: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs [8] PROT_CONFIG_08: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event. This bit has no effect for H-Bridge configuration. Behavior in case of HB is always as PROT_CONFIG_08 = '1'. Diagnostics latches have to be cleared in case of OC in order to re-activate the bridge. 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event [7] OC_DS_SHUNT_08: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt [6] DIAG_I_CONFIG_08: CH8 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability [5:4] GCC_CONFIG_08: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA [3] N_P_CONFIG_08: NMOS or PMOS option for HS configuration 0: Output configured for NMOS 1: Output configured for PMOS [2] LS_HS_CONFIG_08: Configures the channel as LS or HS 0: LS configuration 1: HS configuration [1] EN_OUT_08: Enable output 08 0: Output disabled 1: Output enabled [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 67/151 L9945 SPI MOSI/MISO list COMMAND 9 Description: 9 8 7 6 5 4 3 2 1 0 DIAG_ON_PULSE_08 DIAG_ON_PULSE_07 DIAG_ON_PULSE_06 DIAG_ON_PULSE_05 DIAG_ON_PULSE_04 DIAG_ON_PULSE_03 DIAG_ON_PULSE_02 DIAG_ON_PULSE_01 PARITY DIAG_OFF_PULSE_02 DIAG_OFF_PULSE_03 DIAG_OFF_PULSE_04 DIAG_OFF_PULSE_05 DIAG_OFF_PULSE_06 FIXED_PATTERN DIAG_OFF_PULSE_07 C DIAG_OFF_PULSE_08 R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DIAG_OFF_PULSE_01 Frame partitioning Diagnostic pulses [31:28] C: Command 9 1001 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26:17] FIXED_PATTERN 0101010101 [16] DIAG_OFF_PULSE_08: Diagnostic OFF pulse request on CH8 0: no pulse 1: OFF pulse [15] DIAG_OFF_PULSE_07: Diagnostic OFF pulse request on CH7 0: no pulse 1: OFF pulse [14] DIAG_OFF_PULSE_06: Diagnostic OFF pulse request on CH6 0: no pulse 1: OFF pulse [13] DIAG_OFF_PULSE_05: Diagnostic OFF pulse request on CH5 0: no pulse 1: OFF pulse [12] DIAG_OFF_PULSE_04: Diagnostic OFF pulse request on CH4 0: no pulse 1: OFF pulse [11] DIAG_OFF_PULSE_03: Diagnostic OFF pulse request on CH3 0: no pulse 1: OFF pulse [10] DIAG_OFF_PULSE_02: Diagnostic OFF pulse request on CH2 0: no pulse 1: OFF pulse DS12275 - Rev 8 page 68/151 L9945 SPI MOSI/MISO list [9] DIAG_OFF_PULSE_01: Diagnostic OFF pulse request on CH1 0: no pulse 1: OFF pulse [8] DIAG_ON_PULSE_08: Diagnostic ON pulse request on CH8 0: no pulse 1: ON pulse [7] DIAG_ON_PULSE_07: Diagnostic ON pulse request on CH7 0: no pulse 1: ON pulse [6] DIAG_ON_PULSE_06: Diagnostic ON pulse request on CH6 0: no pulse 1: ON pulse [5] DIAG_ON_PULSE_05: Diagnostic ON pulse request on CH5 0: no pulse 1: ON pulse [4] DIAG_ON_PULSE_04: Diagnostic ON pulse request on CH4 0: no pulse 1: ON pulse [3] DIAG_ON_PULSE_03: Diagnostic ON pulse request on CH3 0: no pulse 1: ON pulse [2] DIAG_ON_PULSE_02: Diagnostic ON pulse request on CH2 0: no pulse 1: ON pulse [1] DIAG_ON_PULSE_01: Diagnostic ON pulse request on CH1 0: no pulse 1: ON pulse [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 69/151 L9945 SPI MOSI/MISO list COMMAND 10 Frame partitioning Description: 6 5 4 3 2 1 0 PARITY 7 FIXED_PATTERN FIXED_PATTERN 8 CONFIG_CC C 9 BIST_RQ R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 BIST request and CC enable [31:28] C: Command 10 1010 [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only [26:7] FIXED_PATTERN: Not used 01010101010101010101 [6:5] BIST_RQ: Request for BIST and HWSC sequence 00: not allowed => behavior as for "no request" 01: request 10: no request 11: not allowed => behavior as for "no request" [4:3] CONFIG_CC: Activation or deactivation of communication check 00: not allowed => previous configuration will be maintained 01: CC active 10: CC inactive 11: not allowed => previous configuration will be maintained [2:1] FIXED_PATTERN 10 [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 70/151 L9945 SPI MOSI/MISO list COMMAND 11 Fixed frame 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xBAAAAAAA Description: Channel 1-4 control signal integrity COMMAND 12 Fixed frame 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xCAAAAAAB Description: Channel 5-8 control signal integrity COMMAND 13 Fixed frame 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0xDAAAAAAA Description: DS12275 - Rev 8 Device status, battery and temperature monitor page 71/151 L9945 SPI MOSI/MISO list RESPONSE X frame partitioning RESPONSE 0 Frame partitioning Description 9 PROT_DISABLE_01 PROT_DISABLE_02 PROT_DISABLE_03 PROT_DISABLE_04 PROT_DISABLE_05 PROT_DISABLE_06 PROT_DISABLE_07 PROT_DISABLE_08 SPI_INPUT_SEL_01 SPI_INPUT_SEL_02 SPI_INPUT_SEL_03 SPI_INPUT_SEL_04 SPI_INPUT_SEL_05 SPI_INPUT_SEL_06 SPI_INPUT_SEL_07 SPI_INPUT_SEL_08 ENABLE_DIAGNOSTIC C SPREAD_SPECTRUM R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8 7 6 5 4 3 2 1 OUTPUT_VOLTAGE[8:1] 0 PARITY 5.10.2 Spread spectrum and diagnostic enable, input selection, protection disable and output voltage status. Initial OUTPUT_VOLTAGE field value depends on load. [31:28] C: Response to command 0 Reset: 0000 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] SPREAD_SPECTRUM: Active or deactive the spread spectrum functionality 0: Inactive 1: Active Reset: 0 Reset Condition: POR, NRES [25] ENABLE_DIAGNOSTIC: Enable or disable the diagnostics for all outputs. When i to "0" diagnostics for all outputs is "Not Diag Done" 0: Diagnostic disable 1: Diagnostic enable Reset: 0 Reset Condition: POR, NRES [24] SPI_INPUT_SEL_08: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 72/151 L9945 SPI MOSI/MISO list [23] SPI_INPUT_SEL_07: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [22] SPI_INPUT_SEL_06: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [21] SPI_INPUT_SEL_05: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [20] SPI_INPUT_SEL_04: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [19] SPI_INPUT_SEL_03: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [18] SPI_INPUT_SEL_02: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [17] SPI_INPUT_SEL_01: Driving mode selection bit (output driven by SPI or NON) 0: Output control by NONx 1: Output control by SPI Reset: 0 Reset Condition: POR, NRES [16] PROT_DISABLE_08: Protection disable for CH8. As long as the bit is set, CH8 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [15] PROT_DISABLE_07: Protection disable for CH7. As long as the bit is set, CH7 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 73/151 L9945 SPI MOSI/MISO list [14] PROT_DISABLE_06: Protection disable for CH6. As long as the bit is set, CH6 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [13] PROT_DISABLE_05: Protection disable for CH5. As long as the bit is set, CH5 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [12] PROT_DISABLE_04: Protection disable for CH4. As long as the bit is set, CH4 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [11] PROT_DISABLE_03: Protection disable for CH3. As long as the bit is set, CH3 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [10] PROT_DISABLE_02: Protection disable for CH2. As long as the bit is set, CH2 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [9] PROT_DISABLE_01: Protection disable for CH1. As long as the bit is set, CH1 is kept actively OFF 0: Output enabled 1: Output OFF Reset: 0 Reset Condition: POR, NRES [8:1] OUTPUT_VOLTAGE: Output voltage compared to LVT threshold (Low-Side) 0: VOUT < VLVT output ON 1: VOUT > VLVT output OFF Reset: Initial OUTPUT_VOLTAGE field value depends on load Reset Condition: POR, NRES Output voltage compared to VOL threshold (High-Side) 0: VOUT < VOL output OFF 1: VOUT > VOL output ON Reset: Initial OUTPUT_VOLTAGE field value depends on load Reset Condition: POR, NRES Note: DS12275 - Rev 8 The OUTPUT_VOLTAGE[8:1] field value depends on external HW configuration. By default, all channels are configured as LS NMOS. Hence, the default value of this field follows such interpretation. page 74/151 L9945 SPI MOSI/MISO list [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even DS12275 - Rev 8 page 75/151 L9945 SPI MOSI/MISO list RESPONSE 1 Description: OUT1 configuration and H-Bridge 1 diagnostic time Reset: 0x1EC00001 3 2 1 0 PARITY 4 EN_OUT_01 5 LS_HS_CONFIG_01 6 N_P_CONFIG_01 7 GCC_CONFIG_01 8 DIAG_I_CONFIG_01 9 OC_DS_SHUNT_01 T_BLANK_OC_01 OC_BATT_COMP_01 OC_CONFIG_01 OC_TEMP_COMP_01 OC_READ_01 TDIAG_CONFIG_01 HB1_TDIAG_EXT_CONFIG C HB1_DEAD_TIME R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_01 Frame partitioning [31:28] C: Response to command 1 Reset: 0001 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:25] HB1_DEAD_TIME: H-bridge 1 dead time to avoid cross conduction 00: 1 µs 01: 2 µs 10: 4 µs 11: 8 µs Reset: 11 Reset Condition: POR, NRES [24] HB1_TDIAG_EXT_CONFIG: Selection of tdiag timers for H-bridge 1. This function only applies when HB1_config = 1 0: H-bridge tdiag timers for HB1. The programmed TDIAG_CONFIG_01 will be extended to CH2, CH3 and CH4 1: Standard tdiag timers for HB1. The programmed TDIAG_CONFIG_01 is valid only for CH1, while CH2, CH3 and CH4 must be set individually. Reset: 0 Reset Condition: POR, NRES [23:22] TDIAG_CONFIG_01: DS12275 - Rev 8 page 76/151 L9945 SPI MOSI/MISO list H-bridge 1 OFF state diagnostic blanking/filter timer. This values are valid only when HB1_tdiag_ext_config = 0 & HB1_config =1 00: 11.2 µs 01: 28.9 µs 10: 40 µs 11: 51.2 µs OFF state diagnostic blanking/filter timer for CH1. It is valid for HB1 only when HB1_tdiag_ext_config = 1 & HB1_config = 1 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES [21] OC_READ_01: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_01: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_01: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_01: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 77/151 L9945 SPI MOSI/MISO list [11:9] TBLANK_OC_01: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES [8] PROT_CONFIG_01: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_01: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES [6] DIAG_I_CONFIG_01: CH1 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_01: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_01: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_01: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 78/151 L9945 SPI MOSI/MISO list [1] EN_OUT_01: Enable output 01 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 1 Reset Condition: - DS12275 - Rev 8 page 79/151 L9945 SPI MOSI/MISO list RESPONSE 2 Description: OUT2 configuration, H-Bridge 1 current limitation timing, BCF selection Reset: 0x2EC00001 3 2 1 0 PARITY 4 EN_OUT_02 5 LS_HS_CONFIG_02 6 N_P_CONFIG_02 7 GCC_CONFIG_02 8 DIAG_I_CONFIG_02 9 OC_DS_SHUNT_02 T_BLANK_OC_02 OC_BATT_COMP_02 OC_CONFIG_02 OC_TEMP_COMP_02 OC_READ_02 TDIAG_CONFIG_02 BATT_FACT_CONFIG C HB1_TOFF R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_02 Frame partitioning [31:28] C: Response to command 2 Reset: 0010 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:25] HB1_TOFF: H-bridge1 off timer during current limitation 00: 31 µs 01: 48 µs 10: 62.5 µs 11: 125 µs Reset: 11 Reset Condition: POR, NRES [24] BATT_FACT_CONFIG: Selection of the factor used in battery compensation 0: Factor for CV 1: Factor for PV Reset: 0 Reset Condition: POR, NRES [23:22] TDIAG_CONFIG_02: OFF state diagnostic blanking/filter timer for output 02. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES DS12275 - Rev 8 page 80/151 L9945 SPI MOSI/MISO list [21] OC_READ_02: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_02: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_02: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_02: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES [11:9] TBLANK_OC_02: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES [8] PROT_CONFIG_02: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_02: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 81/151 L9945 SPI MOSI/MISO list [6] DIAG_I_CONFIG_02: CH2 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_02: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_02: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_02: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [1] EN_OUT_02: Enable output 02 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 1 Reset Condition: - DS12275 - Rev 8 page 82/151 L9945 SPI MOSI/MISO list RESPONSE 3 3 2 1 0 PARITY 4 EN_OUT_03 5 LS_HS_CONFIG_03 6 N_P_CONFIG_03 7 GCC_CONFIG_03 8 DIAG_I_CONFIG_03 9 OC_DS_SHUNT_03 T_BLANK_OC_03 OC_BATT_COMP_03 OC_CONFIG_03 OC_TEMP_COMP_03 OC_READ_03 TDIAG_CONFIG_03 GCC_OVERRIDE_CONFIG HB1_AFW C HB1_ILIM_EN R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_03 Frame partitioning Description: OUT3 configuration, H-Bridge 1 current limitation enable and active freewheeling, gate charge/ discharge current override Reset 0x3BC00000 [31:28] C: Reponse to command 3 Reset: 0011 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] HB1_ILIM_EN: H-bridge1 current limit activation. CH3 OC threshold is used for current limitation, it is only valid for Shunt measurement 0: Current limitation not active 1: Current limitation active Reset: 0 Reset Condition: POR, NRES [25] HB1_AFW: H-bridge1 active freewheel configuration on LS 0: Freewheel low 1: Active freewheeling Reset: 1 Reset Condition: POR, NRES DS12275 - Rev 8 page 83/151 L9945 SPI MOSI/MISO list [24] GCC_OVERRIDE_CONFIG: GCC configuration of the channel, regardless of its channels configuration (LS.HS,H-bridge) must be override to a higher GCC configuration upon OC detection. GCC configuration will remain active until next (NON+SPI) internal turn off transition, in which case the override will be cleared 0: GCC override function upon OC detection: 1 mA → 5 mA 5 mA → 20 mA 1: GCC override function upon OC detection: 1 mA → 20 mA 5 mA → 20 mA Reset: 1 Reset Condition: POR, NRES [23:22] TDIAG_CONFIG_03: OFF state diagnostic blanking/filter timer for output 03. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES [21] OC_READ_03: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_03: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_03: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_03: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 84/151 L9945 SPI MOSI/MISO list [11:9] TBLANK_OC_03: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES [8] PROT_CONFIG_03: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_03: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES [6] DIAG_I_CONFIG_03: CH3 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_03: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_03: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_03: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 85/151 L9945 SPI MOSI/MISO list [1] EN_OUT_03: Enable output 03 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 86/151 L9945 SPI MOSI/MISO list RESPONSE 4 Description: OUT4 configuration, P&H1 configuration, H-Bridge 1 enable Reset: 0x48C00001 3 2 1 0 PARITY 4 EN_OUT_04 DIAG_I_CONFIG_04 5 LS_HS_CONFIG_04 6 N_P_CONFIG_04 7 GCC_CONFIG_04 8 OC_DS_SHUNT_04 9 T_BLANK_OC_04 OC_BATT_COMP_04 OC_CONFIG_04 OC_TEMP_COMP_04 OC_READ_04 TDIAG_CONFIG_04 PH1_CONFIG PH1_DIAG_STRATEGY C HB1_CONFIG R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_04 Frame partitioning [31:28] C: Response to command 4 Reset: 0100 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] HB1_CONFIG: Configures CH1-CH2-CH3-CH4 for H-bridge1 operation 0: Not H-bridge configured 1: CH1-CH4 configured as H-bridge Reset: 0 Reset Condition: POR, NRES [25] PH1_DIAG_STRATEGY: OL masking strategy to prevent false OL assertion in P&H1 configuration 0: "No OL/STG /STB" failure reported 1: "No diagnostic done" reported Reset: 0 Reset Condition: POR, NRES [24] PH1_CONFIG: Configures CH1-CH4 for Peak and Hold1 configuration 0: Peak and Hold1 not configured 1: Peak and Hold1 configured Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 87/151 L9945 SPI MOSI/MISO list [23:22] TDIAG_CONFIG_04: OFF state diagnostic blanking/filter timer for output 04. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES [21] OC_READ_04: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_04: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_04: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_04: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES [11:9] TBLANK_OC_04: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES DS12275 - Rev 8 page 88/151 L9945 SPI MOSI/MISO list [8] PROT_CONFIG_04: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_04: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES [6] DIAG_I_CONFIG_04: CH4 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_04: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_04: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_04: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [1] EN_OUT_04: Enable output 04 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 89/151 L9945 SPI MOSI/MISO list RESPONSE 5 Description OUT 5 configuration and H-Bridge 2 diagnostic time Reset: 0x5EC00000 3 2 1 0 PARITY 4 EN_OUT_05 5 LS_HS_CONFIG_05 6 N_P_CONFIG_05 7 GCC_CONFIG_05 8 DIAG_I_CONFIG_05 9 OC_DS_SHUNT_05 T_BLANK_OC_05 OC_BATT_COMP_05 OC_CONFIG_05 OC_TEMP_COMP_05 OC_READ_05 TDIAG_CONFIG_05 HB2_TDIAG_EXT_CONFIG C HB2_DEAD_TIME R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_05 Frame partitioning [31:28] C: Response to command 5 Reset: 0101 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:25] HB2_DEAD_TIME: H-bridge2 dead time to avoid cross conduction 00: 1 µs 01: 2 µs 10: 4 µs 11: 8 µs Reset: 11 Reset Condition: POR, NRES [24] HB2_TDIAG_EXT_CONFIG: Selection of tdiag timers for H-bridge 2. This function only applies when HB2_config = 1 (command 8) 0: H-bridge tdiag timers for HB2. The programmed TDIAG_CONFIG_05 will be extended to CH6, CH7 and CH8. 1: Standard tdiag timers for HB2. The programmed TDIAG_CONFIG_05 is valid only for CH5, while CH6, CH7 and CH8 must be set individually Reset: 0 Reset Condition: POR, NRES [23:22] TDIAG_CONFIG_05: DS12275 - Rev 8 page 90/151 L9945 SPI MOSI/MISO list H-bridge 2 OFF state diagnostic blanking/filter timer. This values are valid only when HB2_tdiag_ext_config = 0 & HB2_config =1 00: 11.2 µs 01: 28.9 µs 10: 40 µs 11: 51.2 µs OFF state diagnostic blanking/filter timer for CH5. It is valid for HB1 only when HB2_tdiag_ext_config = 1 & HB2_config = 1 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES [21] OC_READ_05: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_05: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_05: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_05: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 91/151 L9945 SPI MOSI/MISO list [11:9] TBLANK_OC_05: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES [8] PROT_CONFIG_05: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_05: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES [6] DIAG_I_CONFIG_05: CH5 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_05: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_05: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_05: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 92/151 L9945 SPI MOSI/MISO list [1] EN_OUT_05: Enable output 05 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 93/151 L9945 SPI MOSI/MISO list RESPONSE 6 Description: OUT6 configuration, H-Bridge 2 current limitation timing Reset: 0x6EC00000 3 2 1 0 PARITY 4 EN_OUT_06 5 LS_HS_CONFIG_06 6 N_P_CONFIG_06 7 GCC_CONFIG_06 8 DIAG_I_CONFIG_06 9 OC_DS_SHUNT_06 T_BLANK_OC_06 OC_BATT_COMP_06 OC_CONFIG_06 OC_TEMP_COMP_06 OC_READ_06 TDIAG_CONFIG_06 FIXED_PATTERN C HB2_TOFF R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_06 Frame partitioning [31:28] C: Response to command 6 Reset: 0101 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:25] HB2_TOFF: H-bridge2 off timer during current limitation 00: 31 µs 01: 48 µs 10: 62.5 µs 11: 125 µs Reset: 11 Reset Condition: POR, NRES [24] FIXED_PATTERN Reset: 0 Reset Condition: POR, NRES [23:22] TDIAG_CONFIG_06: OFF state diagnostic blanking/filter timer for CH6. It is valid for HB1 only when HB2_tdiag_ext_config = 1 & HB2_config = 1 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES DS12275 - Rev 8 page 94/151 L9945 SPI MOSI/MISO list [21] OC_READ_06: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_06: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_06: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_06: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES [11:9] TBLANK_OC_06: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES [8] PROT_CONFIG_06: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_06: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 95/151 L9945 SPI MOSI/MISO list [6] DIAG_I_CONFIG_06: CH6 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_06: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_06: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_06: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [1] EN_OUT_06: Enable output 06 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 96/151 L9945 SPI MOSI/MISO list RESPONSE 7 Description: OUT7 configuration, H-Bridge 2 current limitation enable and active freewheeling Reset: 0x7AC00000 3 2 1 0 PARITY 4 EN_OUT_07 5 LS_HS_CONFIG_07 6 N_P_CONFIG_07 7 GCC_CONFIG_07 8 DIAG_I_CONFIG_07 9 OC_DS_SHUNT_07 T_BLANK_OC_07 OC_BATT_COMP_07 OC_CONFIG_07 OC_TEMP_COMP_07 OC_READ_07 TDIAG_CONFIG_07 FIXED_PATTERN HB2_AFW C HB2_ILIM_EN R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_07 Frame partitioning [31:28] C: Response to command 7 Reset: 0111 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] HB1_ILIM_EN: H-bridge2 current limit activation. CH7 OC threshold is used for current limitation, it is only valid for Shunt measurement 0: Current limitation not active 1: Current limitation active Reset: 0 Reset Condition: POR, NRES [25] HB2_AFW: H-bridge2 active freewheel configuration on LS 0: Freewheel low 1: Active freewheeling Reset: 1 Reset Condition: POR, NRES [24] FIXED_PATTERN Reset: 0 Reset Condition: POR, NRES [23:22] TDIAG_CONFIG_07: OFF state diagnostic blanking/filter timer for output 07. It has no effect if HB2_config =1 & HB2_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES DS12275 - Rev 8 page 97/151 L9945 SPI MOSI/MISO list [21] OC_READ_07: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_07: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_07: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_07: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES [11:9] TBLANK_OC_07: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES [8] PROT_CONFIG_07: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_07: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 98/151 L9945 SPI MOSI/MISO list [6] DIAG_I_CONFIG_07: CH7 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_07: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_07: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_07: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [1] EN_OUT_07: Enable output 07 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 99/151 L9945 SPI MOSI/MISO list RESPONSE 8 Description OUT8 configuration, P&H2 configuration, H-Bridge 2 enable Reset: 0x88C00001 3 2 1 0 PARITY 4 EN_OUT_08 DIAG_I_CONFIG_08 5 LS_HS_CONFIG_08 6 N_P_CONFIG_08 7 GCC_CONFIG_08 8 OC_DS_SHUNT_08 9 T_BLANK_OC_08 OC_BATT_COMP_08 OC_CONFIG_08 OC_TEMP_COMP_08 OC_READ_08 TDIAG_CONFIG_08 PH2_CONFIG PH2_DIAG_STRATEGY C HB2_CONFIG R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 PROT_CONFIG_08 Frame partitioning [31:28] C: Response to command 8 Reset: 1000 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] HB2_CONFIG: Configures CH5-CH6-CH7-CH8 for H-bridge2 operation 0: Not H-bridge configured 1: CH5-CH8 configured as H-bridge Reset: 0 Reset Condition: POR, NRES [25] PH2_DIAG_STRATEGY: OL masking strategy to prevent false OL assertion in P&H2 configuration 0: "No OL/STG /STB" failure reported 1: "No diagnostic done" reported Reset: 0 Reset Condition: POR, NRES [24] PH2_CONFIG: Configures CH5-CH8 for Peak and Hold2 configuration 0: Peak and Hold2 not configured 1: Peak and Hold2 configured Reset: 0 Reset Condition: POR, NRES DS12275 - Rev 8 page 100/151 L9945 SPI MOSI/MISO list [23:22] TDIAG_CONFIG_08: OFF state diagnostic blanking/filter timer for output 02. It has no effect if HB1_config =1 & HB1_tdiag_ext_config = 0 00: 25.6 µs 01: 61.2 µs 10: 105.6 µs 11: 150 µs Reset: 11 Reset Condition: POR, NRES [21] OC_READ_08: Selection of the OC threshold to read. Fixed threshold or actual threshold 0: Read fixed OC threshold 1: Read actual OC threshold Reset: 0 Reset Condition: POR, NRES [20:15] OC_CONFIG_08: Selection of over current detection threshold. 6 bit to code for the OC detection threshold See Table 40 Reset: 000000 Reset Condition: POR, NRES [14:13] OC_TEMP_COMP_08: Over current detection with temperature compensation (see note of Table 30. SPI MOSI list) 00: No OC compensation 01: ΔT < 60 °C 10: ΔT < 40 °C 11: ΔT < 25 °C Reset: 00 Reset Condition: POR, NRES [12] OC_BATT_COMP_08: Over current detection with battery compensation 0: Battery compensation de-activated 1: Battery compensation activated Reset: 0 Reset Condition: POR, NRES [11:9] TBLANK_OC_08: When DSM is selected, it specifies the OC blanking time to allow VDS settling. When Rshunt is selected, it only determines the assertion of the 'No OC failure' diagnostic code (once expired). 000: 11.1 µs 001: 15.6 µs 010: 20 µs 011: 31.1 µs 100: 42.2 µs 101: 53.3 µs 110: 97.8 µs 111: 142.2 µs Reset: 000 Reset Condition: POR, NRES DS12275 - Rev 8 page 101/151 L9945 SPI MOSI/MISO list [8] PROT_CONFIG_08: Output re-engagement strategy. Specifies how channel reactivation must be performed following an OC event 0: output re-engagement with control signal switching event 1: output re-engagement after diagnostic readout and control signal switching event Reset: 0 Reset Condition: POR, NRES [7] OC_DS_SHUNT_08: Configures the output measure OC with shunt or by DSM 0: OC with DSM 1: OC with Shunt Reset: 0 Reset Condition: POR, NRES [6] DIAG_I_CONFIG_08: CH8 OL regulator output current capability 0: 100 µA capability 1: 1 mA capability Reset: 0 Reset Condition: POR, NRES [5:4] GCC_CONFIG_08: Selection of gate charge/discharge currents 00: Lim by ext resistor 01: 20 mA 10: 5 mA 11: 1 mA Reset: 00 Reset Condition: POR, NRES [3] N_P_CONFIG_08: NMOS or PMOS option for HS configuration 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [2] LS_HS_CONFIG_08: Configures the channel as LS or HS 0: LS configuration 1: HS configuration Reset: 0 Reset Condition: POR, NRES [1] EN_OUT_08: Enable output 08 0: Output disabled 1: Output enabled Reset: 0 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 102/151 L9945 SPI MOSI/MISO list RESPONSE 9 9 8 7 6 5 4 3 2 1 0 DIAG_08_0 DIAG_07_0 DIAG_06_0 DIAG_05_0 DIAG_04_0 DIAG_03_0 DIAG_02_0 DIAG_01_0 PARITY DIAG_02_1 DIAG_03_1 DIAG_04_1 DIAG_05_1 DIAG_06_1 DIAG_07_1 DIAG_08_1 DIAG_01_2 DIAG_02_2 DIAG_03_2 DIAG_04_2 DIAG_05_2 DIAG_06_2 DIAG_07_2 DIAG_08_2 HB1_ILIM C HB2_ILIM R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DIAG_01_1 Frame partitioning Description: OUT8 configuration, P&H2 configuration, H-Bridge 2 enable Reset: 0x99FFFFFE [31:28] C: Response to command 9 Reset: 1001 Reset Condition: POR, NRES [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] HB2_ILIM: H-bridge 2 Current limitation latch 0: No current limitation active 1: Current limitation active Reset: 0 Reset Condition: Read out POR, NRES [25] HB1_ILIM: H-bridge 1 Current limitation latch 0: No current limitation active 1: Current limitation active Reset: 0 Reset Condition: Read out POR, NRES [24, 16, 8] DIAG_08: Diagnostic information for CH8 diag_8[2] diag_8[1] diag_8[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES DS12275 - Rev 8 page 103/151 L9945 SPI MOSI/MISO list [23, 15, 7] DIAG_07: Diagnostic information for CH7 diag_7[2] diag_7[1] diag_7[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES [22, 14, 6] DIAG_06: Diagnostic information for CH6 diag_6[2] diag_6[1] diag_6[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES [21, 13, 5] DIAG_05: Diagnostic information for CH5 diag_5[2] diag_5[1] diag_5[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES DS12275 - Rev 8 page 104/151 L9945 SPI MOSI/MISO list [20, 12, 4] DIAG_04: Diagnostic information for CH4 diag_4[2] diag_4[1] diag_4[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES [19, 11, 3] DIAG_03: Diagnostic information for CH3 diag_3[2] diag_3[1] diag_3[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES [18, 10, 2] DIAG_02: Diagnostic information for CH2 diag_2[2] diag_2[1] diag_2[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES DS12275 - Rev 8 page 105/151 L9945 SPI MOSI/MISO list [17, 9, 1] DIAG_01: Diagnostic information for CH1 diag_1[2] diag_1[1] diag_1[0]: 0 0 0: OC pin failure 0 0 1: OC failure 0 1 0: STG/STB failure 0 1 1: OL failure 1 0 0: no failure 1 0 1: No OC failure 1 1 0: No OL/STG/STB failure 1 1 1: no diagnostic done Reset: 111 Reset Condition: Read out POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 106/151 L9945 SPI MOSI/MISO list RESPONSE 10 Description: Note: 9 8 7 6 5 4 3 2 1 0 UV_VDD5_STATE UV_VDD5_LATCH N_POR_LATCH NRES_LATCH VCP_UV_STATE VCP_UV_LATCH VPS_STATE VPS_LATCH PARITY OV_VDD5_STATE HWSC_DIS HWSC_DONE BIST_DIS BIST_DONE CC_LATCH CONFIG_CC_STATE NDIS_OUT_LATCH NDIS_LATCH NDIS_STATE DIS_LATCH DIS_STATE UV_DIS_LATCH UV_DIS_STATE OV_DIS_LATCH EN6_STATE C EN6_LATCH R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 OV_VDD5_LATCH Frame partitioning BIST & HWSC result and device status the value of DIS, NDIS and EN6 related bit depends on how the microcontroller drives such pins. The value of POR and NRES related bit depends on which event caused the logic reset. The value of BIST and HWSC related bit depends on which event caused the logic reset: self test sequence is not performed in case of POR. In addition, the value of BIST_DONE and HWSC_DONE bit depends on the status of self test sequence at the time instant where the read event occurs. The CC_LATCH is set in case the first SPI communication occurs after the watchdog timer expired. The UV_DIS_LATCH and UV_VDD5_LATCH might be set at startup, depending on the VDD5 ramp slope. It is strongly recommended to perform two consecutive SPI read via COMMAND 10 in order to verify that the relevant faults (eventually latched during startup) are cleared. [31:28] C: Response to command 10 Reset: 1010 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26] EN6_LATCH: Shows if a deactivation via EN6 pin was detected since last read out (EN6 = LOW) 0: no disable via EN6 detected 1: disable via EN6 detected Reset: X Reset Condition: Read out POR [25] EN6_STATE: Shows if channel 6 is currently disabled by the EN6 input 0: EN disabled 1: EN enabled Reset: 0 Reset Condition: [24] OV_DIS_LATCH: Bit set to 1 (OV filtering expired) if VDD5 overvoltage disable was triggered since last read out (shows also if OV occurs during Reset) 0: no OV disable condition detected 1: OV disable condition detected Reset: 0 Reset Condition: - DS12275 - Rev 8 page 107/151 L9945 SPI MOSI/MISO list [23] UV_DIS_STATE: Shows if the device is currently in VDD5 under voltage disable 0: Currently no UV condition 1: UV condition active Reset: 0 Reset Condition: Read out POR, NRES [22] UV_DIS_LATCH: Bit set to 1 (UV filter expired) if VDD5 under voltage disable was triggered 0: no UV condition detected 1: UV condition detected Reset: 0 Reset Condition: Read out POR [21] DIS_STATE: Shows if the device is currently disabled by the DIS input signal 0: DIS inactive 1: DIS active Reset: X Reset Condition: [20] DIS_LATCH: Shows if DIS was applied since last read out. Bit set to 1 by DIS input set HIGH 0: No DIS detected 1: DIS detected Reset: X Reset Condition: Read out POR [19] NDIS_STATE: Shows if the device is currently disabled by the NDIS input signal 0: NDIS active 1: NDIS inactive Reset: X Reset Condition: [18] NDIS_LATCH: Shows if NDIS was applied since last read out. Bit set to 1 by NDIS input = LOW 0: No NDIS detected 1: NDIS detected Reset: X Reset Condition: Read out POR [17] NDIS_OUT_LATCH: Shows NDIS was used as output and internally pulled down. 0: No internal NDIS activation 1: Internal NDIS activation Reset: X Reset Condition: Read out POR [16] CONFIG_CC_STATE: Shows if communication check functionality is activated or deactivated 0: CC inactive 1: CC active Reset: X Reset Condition: Read out POR [15] CC_LATCH: Shows if CC failed since last read out. Bit set to 1 if communication check failed 0: no CC failure detected 1: CC failure detected Reset: X Reset Condition: Read out POR DS12275 - Rev 8 page 108/151 L9945 SPI MOSI/MISO list [14] BIST_DONE: BIST status 0: not done/ongoing 1: BIST finished Reset: X Reset Condition: POR, NRES [13] BIST_DIS: BIST disable event latch 0: BIST passed 1: BIST failed Reset: X Reset Condition: POR, NRES [12] HWSC_DONE: HWSC status 0: not done/ongoing 1: HWSC finished Reset: X Reset Condition: POR, NRES [11] HWSC_DIS: HWSC disable event latch 0: HWSC passed 1: HWSC failed Reset: X Reset Condition: POR, NRES [10] OV_VDD5_STATE: Current state of the VDD5 over voltage comparator output, no digital filter 0: currently no OV condition on VDD5 1: OV condition active on VDD5 Reset: 0 Reset Condition: [9] OV_VDD5_LATCH: Bit set to 1 if a VDD5 over voltage was detected by OV VDD5 comparator (even if OV filter not expired) 0: no VDD5 fast transient OV detected 1: fast VDD5 transient OV detected Reset: 0 Reset Condition: Read out POR, NRES [8] UV_VDD5_STATE: Current state of the VDD5 under voltage comparator output, no digital filter 0: currently no UV condition on VDD5 1: UV condition active on VDD5 Reset: 0 Reset Condition: [7] UV_VDD5_LATCH: Bit set to 1 if a VDD5 under voltage was detected by UV VDD5 comparator (even if UV filter not expired) 0: no fast VDD5 UV transient detected 1: fast VDD5 UV transient detected Reset: 0 Reset Condition: Read out POR, NRES DS12275 - Rev 8 page 109/151 L9945 SPI MOSI/MISO list [6] N_POR_LATCH: Shows if a POR_VDD5 on the int. 5V supply for channel occurred since last read out 0: No POR on VDD5 detected (state after readout) Reset: X Reset Condition: Cleared: Read out 1: POR on VDD5 detected (state after event) Reset: X Reset Condition: Set to default: POR [5] NRES_LATCH: Shows if NRES was applied since last readout bit set to 1 by NRES input is LOW 0: No NRES detected 1: NRES detected Reset: X Reset Condition: Read out POR, NRES [4] VCP_UV_STATE: Returns the output status of the VGBHI undervoltage comparator 0: VPS > VVPS_UV outputs enabled 1: VPS < VVPS_UV outputs disabled Reset: 0 Reset Condition: [3] VCP_UV_LATCH: Returns if a VCP_UV was detected since last read out 0: No VCP_UV detected 1: VCP_UV detected Reset: 0 Reset Condition: Read out POR, NRES [2] VPS_STATE: Feedback of the voltage at the VPS pin: if VPS pin smaller VVPS_UV the external MOSFETs are disabled 0: VPS > VVPS_UV outputs enabled 1: VPS < VVPS_UV outputs disabled Reset: 0 Reset Condition: [1] VPS_LATCH: Returns if a low VPS voltage was detected since last read out 0: No VPS low detected 1: VPS low detected Reset: 0 Reset Condition: Read out POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 110/151 L9945 SPI MOSI/MISO list RESPONSE 11 Frame partitioning Description: Channel 1-4 control signal integrity Reset: 0xBABE0000 PUPD4 9 8 PUPD3 7 6 5 PUPD2 4 3 2 PUPD1 1 0 PARITY C1 C2 C3 C4 V1 V2 FIXED_PATTERN V3 C V4 R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:28] C: Response to command 11 Reset: 1011 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:21] FIXED_PATTERN: Fixed pattern Reset: 010101 Reset Condition: POR, NRES [20:17] V4…1: This bit monitors the external FET drain voltage by exploiting the internal diagnostic comparators. It is useful for obtaining the status of the output during normal operation The value of this bit depends on the channel configuration: 0: Drain voltage low (VDRAIN < VLVT) -> transistor ON 1: Drain voltage high (VDRAIN > VLVT) -> transistor OFF (Low-Side with NFET) 0: Drain voltage low (VDRAIN < VOL) -> transistor OFF 1: Drain voltage high (VDRAIN > VOL) -> transistor ON (High-Side with NFET/PFET) Reset: 1111 Reset Condition: POR, NRES [16:13] C4…1: This bit combines the control signals SPI_ON_OUTxx, NONx and SPI_input_sel_xx to determine if the x-th channel is commanded ON or OFF 0: output commanded OFF 1: output commanded ON Reset: 0000 Reset Condition: POR, NRES DS12275 - Rev 8 page 111/151 L9945 SPI MOSI/MISO list [12:10] PUPD4...1: Pull up / Pull down status of CHx [9:7] This field consists of 3 bit encoding the current status of the gate charge / discharge current sources for the x-th channel. The code depends on the output configuration: [6:4] High-Side with PFET: [3-1] • 100: IPD ON and IPU OFF -> transistor ON • 010: IPD OFF and IPU ON -> transistor OFF • 000: IPD OFF and IPU OFF -> output in three-state • Others: integrity of the output control is compromised High-Side/Low-Side with NFET: • 010: IPD ON and IPU OFF -> transistor OFF • 001: IPD OFF and IPU ON -> transistor ON • 000: IPD OFF and IPU OFF -> output in three-state • Others: integrity of the output control is compromised Reset: 0000 Reset Condition: [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 112/151 L9945 SPI MOSI/MISO list RESPONSE 12 Frame partitioning Description: Channel 5-8 control signal integrity Reset 0xCABE0001 PUPD8 9 8 PUPD7 7 6 5 PUPD6 4 3 2 PUPD5 1 0 PARITY C5 C6 C7 C8 V5 V6 FIXED_PATTERN V7 C V8 R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 [31:28] C: Response to command 12 Reset: 1100 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:21] FIXED_PATTERN: Fixed pattern Reset: 010101 Reset Condition: POR, NRES [20:17] V8…5: This bit monitors the external FET drain voltage by exploiting the internal diagnostic comparators. It is useful for obtaining the status of the output during normal operation The value of this bit depends on the channel configuration: 0: Drain voltage low (VDRAIN < VLVT) -> transistor ON 1: Drain voltage high (VDRAIN > VLVT) -> transistor OFF (Low-Side with NFET) 0: Drain voltage low (VDRAIN < VOL) -> transistor OFF 1: Drain voltage high (VDRAIN > VOL) -> transistor ON (High-Side with NFET/PFET) Reset: 1111 Reset Condition: POR, NRES [16:13] C8…5: This bit combines the control signals SPI_ON_OUTxx, NONx and SPI_input_sel_xx to determine if the x-th channel is commanded ON or OFF 0: output commanded OFF 1: output commanded ON Reset: 0000 Reset Condition: POR, NRES DS12275 - Rev 8 page 113/151 L9945 SPI MOSI/MISO list [10:12] PUPD8...5: Pull up / Pull down status of CHx [9:7] This field consists of 3 bit encoding the current status of the gate charge / discharge current sources for the x-th channel. The code depends on the output configuration: [6:4] High-Side with PFET: [3-1] • 100: IPD ON and IPU OFF -> transistor ON • 010: IPD OFF and IPU ON -> transistor OFF • 000: IPD OFF and IPU OFF -> output in three-state • Others: integrity of the output control is compromised High-Side/Low-Side with NFET: • 010: IPD ON and IPU OFF -> transistor OFF • 001: IPD OFF and IPU ON -> transistor ON • 000: IPD OFF and IPU OFF -> output in three-state • Others: integrity of the output control is compromised Reset: 0000 Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: 0 Reset Condition: - DS12275 - Rev 8 page 114/151 L9945 SPI MOSI/MISO list RESPONSE 13 Frame partitioning TEMP_ADC Description Device status, battery and temperature monitor Reset X 9 8 7 6 5 4 3 2 1 0 PARITY OT_STATE SDO_OV_LATCH NDIS_PROT_LATCH C FIXED_PATTERN R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VPS_ADC [31:28] C: Response to command 12 Reset: 1101 Reset Condition: [27] R/W: Bit to read/write configuration 0: Write & request read 1: Request read only Reset: 1 Reset Condition: POR, NRES [26:24] FIXED_PATTERN: Fixed pattern Reset: 010 Reset Condition: [23] NDIS_PROT_LATCH: Bit set to 1 if the protection on NDIS pin was activated while NDIS was being internally pulled down, reactivation with control change 0: no OV condition on NDIS 1: OV condition on NDIS detected Reset: 0 Reset Condition: Read out POR [22] OT_STATE: Current state of OT comparator output 0: no OV condition on SDO detected 1: OV condition on SDO detected Reset: 0 Reset Condition: [21] SDO_OV_LATCH: Shows if an OV in SDO pin was detected since last read out 0: no OV condition on SDO detected 1: OV condition on SDO detected Reset: 0 Reset Condition: Read out POR DS12275 - Rev 8 page 115/151 L9945 SPI MOSI/MISO list [20:11] TEMP_ADC: Returns the actual temperature measured by the internal temperature sensor of the device. 10 bit to code for the actual temperature of the device See Temperature ADC. Reset: X Reset Condition: POR, NRES [10:1] VPS_ADC: Returns the actual VPS voltage measured by the internal voltage sensor of the device. 10 bit to code for the actual VPS voltage See VPS ADC Reset: X Reset Condition: POR, NRES [0] PARITY: Parity bit, based on even parity calculation 0: If the number of 1 is odd 1: If the number of 1 is even Reset: X Reset Condition: - DS12275 - Rev 8 page 116/151 L9945 Safety & diagnostics 6 Safety & diagnostics This chapter contains all the information regarding safety and diagnostic features. All the external and internal disable sources are described. The Built-In Self-Test (BIST), HardWare Self-Check (HWSC) and the Communication Check (CC) watchdog are also explained. The diagnostics implemented for monitoring the output status and protecting the external FETs are described. All the information regarding the effects of disable sources and diagnostics on the output pre-drivers is summarized in Section 6.6 . 6.1 Disable sources There are several disable sources implemented in order to guarantee safety and correct functionality of the output pre-drivers. 6.1.1 DIS & NDIS pins For safety purposes, L9945 features two disable pins that can be driven by an external microcontroller: • DIS: is a positive asserted disable input with internal pull up. When DIS is asserted, all channels except 7 and 8 are actively turned off. DIS status can be monitored reading DIS_STATE bit via SPI. If DIS has been asserted, the event is latched in the DIS_LATCH, cleared on SPI readout. Outputs are automatically reengaged when DIS is released. • NDIS: is a negative asserted disable input/output with internal pull down. Refer to Figure 24. – When used as input, a negative assertion implies an active shut off of all the outputs except channels 7 and 8. NDIS status can be monitored reading NDIS_STATE bit via SPI. If NDIS has been asserted, the event is latched in the NDIS_LATCH, cleared on SPI readout. Outputs are automatically reengaged when NDIS is released. – L9945 uses this pin as output every time an over/under voltage is detected on VDD5 supply. The purpose is to provide a feedback on the VDD5 status to the external microcontroller. This functionality is enabled only if NRES is set high. If NDIS is internally pulled down, the event is latched in NDIS_out_LATCH, cleared on SPI readout. In case of overvoltage (VDD5 > VVDD5_OV for t > tVDD5_OV) NDIS is pulled-down immediately. In case of undervoltage (VDD5 < VVDD5_UV for t > tVDD5_UV1) NDIS is pulled-down after tVDD5_UV2. Note: DS12275 - Rev 8 For timings and electrical characteristics related to VDD5 refer to Table 8. When configured as H-Bridge, channels 7 and 8 are handled like other channels and are disabled in case of DIS/NDIS assetion. When used as output, NDIS is protected against overvoltage. In case NDIS is internally activated low and the voltage at NDIS pin exceeds VNDIS_OV, for a time longer than tNDIS_OV + tNDIS_OV_react, the protection is activated by switching OFF the pull down structure on NDIS pin. Once the protection is activated it will stay active until the next NDIS internal activation event. NDIS overvoltage event is latched into NDIS_PROT_LATCH, cleared via SPI readout. page 117/151 L9945 Disable sources Figure 24. NDIS structure Input structure Output structure 3.3 V NDIS To logic IPD NMOS 3.3 V VDD5 UV/OV EN GND GND GND GADG1003170815PS Table 31. NDIS OV protection electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit VNDIS_OV NDIS OV disable threshold Low Side ON 0.8 - 1.0 V tNDIS_OV NDIS OV deglitch filter time - 2.2 2.5 2.7 µs NDIS OV Comparator reaction time - 100 - 700 ns tNDIS_OV_react 6.1.2 VDD5 Overvoltage/Undervoltage VDD5 is internally monitored to detect overvoltage/undervoltage conditions: • In case VDD5 ≥ VVDD5_OV, an internal OV disable is generated after the filter time tVDD5_OV. Such an event is latched in OV_DIS_LATCH, cleared on SPI readout. In case of overvoltage all outputs except channel 7 and 8 are actively turned off until the next SPI diagnostic readout. Overvoltage comparator status can be monitored reading OV_VDD5_STATE bit via SPI. If the comparator output goes high due to a transient overvoltage, the OV_VDD5_LATCH is set, even if the filter time tVDD5_OV hasn't expired. This latch is cleared on SPI readout and doesn't imply an output disable. • In case VPOR ≤ VDD5 ≤ VVDD5_UV, an internal UV disable is generated after the filter time tVDD5_UV1. Such an event is latched in UV_DIS_LATCH, cleared on SPI readout. Once UV disable is activated it will stay active at least for tVDD5_UV1 after UV condition disappears. In case of undervoltage all outputs except channel 7 and 8 are actively turned off. If UV condition disappears, outputs are automatically re-engaged. Undervoltage comparator output can be monitored by reading UV_DIS_STATE via SPI. In case VDD5 ≤ VPOR an internal POR is generated and the device is reset. Such an event is latched in n_POR_LATCH and can be cleared via SPI readout. Note: DS12275 - Rev 8 Refer to Table 8 for the electrical characteristics and the parameters regarding VDD5 overvoltage and undervoltage detection. When configured as H-Bridge, channels 7 and 8 are handled like other channels and are disabled in case of VDD5 UV/OV. page 118/151 L9945 Disable sources 6.1.3 BIST & HWSC The device features a Built-In Self-Test (BIST) and a HardWare Self-Check (HWSC). For functional safety considerations, internal disable structures must operate always correctly and reliably. To accomplish this, the disable sources paths and the VDD5 overvoltage detection block are self-checked by L9945: • BIST covers the digital domain of disable-related functions; • HWSC covers the analog domain of the VDD5 overvoltage comparator. In case of BIST or HWSC failure, all channels except 7 and 8 are disabled. BIST is always followed by HWSC to ensure full coverage of digital and analog domains. The sequence is performed in less than 3 ms, and is run: • After each NRES release (POR assertion does not imply BIST & HWSC sequence execution); • On demand, programming the BIST_RQ bit via SPI. Note: Due to device configuration reset during BIST, the procedure must be executed prior to channel configuration applied. The procedure starts with BIST. During BIST execution: • The BIST_DONE latch is set low; • All output drivers (including 7 and 8) are three-stated; • All the device registers are reset, except SPI latches (UV/OV events, disable events, etc.). BIST checks the correct function of the disable logic to the gate drive of the outputs: • Switch OFF paths from DIS, NDIS, EN6, including the bidirectional NDIS output; • Switch OFF path from Communication Check; • Switch OFF path from HWSC/BIST; • Switch OFF path from OV/UV detection block. BIST also checks that the implemented timers can be stopped (e.g. communication check timeout). The BIST_DONE latch is set high once BIST has terminated. • In case the procedure detects an error, the BIST_DIS latch is set and all outputs, except 7 and 8, are kept actively turned off. Channels 7 and 8 are kept in three-state. • In case BIST detected no error, the outputs are kept in three-state HWSC follows BIST and checks the functionality of VDD5 overvoltage detection mechanism. HWSC lasts tHWSC_DUR. During such interval, the outputs 1-6 are kept OFF actively by asserting the HWSC_DIS internal signal; channels 7-8 are still in three-state, since the BIST executed previously. After tHWSC_DUR has expired, the HWSC_DONE latch is set high and the self check result will be available via SPI reading the HWSC_DIS signal status. Two cases can occur: • HWSC failed: the signal HWSC_DIS is kept high and disables (actively) all the outputs except 7 and 8; • HWSC passed: the signal HWSC_DIS is set low and the disable is released. If both BIST and HWSC are successful, BIST_DIS and HWSC_DIS disable signals are released and the outputs can be configured and enabled normally. If one among BIST and HWSC failed, channels 1-6 are kept disabled, regardless of the configuration applied; channels 7-8 can still be enabled. BIST and HWSC sequence is stopped in case of a reset condition: • NRES set low; • POR. Note: DS12275 - Rev 8 When configured as H-Bridge, channels 7 and 8 are handled like other channels and are disabled in case of BIST/HWSC failure. page 119/151 L9945 Disable sources Figure 25. BIST & HWSC sequence POR N N _P R O ES R 1 1  0 0 || 1 1  =0 0 Q ES R R _ N IST B •HWSC_DONE = 0 •HWSC_DIS = 1 •BIST_DONE = 0 •BIST_DIS = 1 END BIST •HWSC_DONE = 1 •HWSC_DIS = X •BIST_DONE = 1 •BIST_DIS = X BIST_RQ = 01 •HWSC_DONE = 0 •HWSC_DIS = 1 •BIST_DONE = 0 •BIST_DIS = 1 H 0  _D O ST E N 1 BI O _D HWSC •HWSC_DONE = 0 •HWSC_DIS = 1 •BIST_DONE = 1 •BIST_DIS = X N E 0 SC  W 1 N_POR 1  0 NRES 1  0 N_POR 1  0 NRES 1  0 GADG2011171331PS Table 32. HWSC timing characteristics Symbol tHWSC_DUR 6.1.4 Parameter HWSC duration time Min. Max. Unit 100 160 µs VPS undervoltage In case VPS is lower than VVPS_UV for tVPS_react + tLBD_FIL, a battery undervoltage is detected, all outputs are actively turned off and the VPS_LATCH is set high (cleared on SPI readout). The undervoltage comparator output can be monitored by reading VPS_STATE bit via SPI. Outputs are re-engaged when undervoltage condition disappears. Table 33. VPS UV detection electrical characteristics Symbol Min. Max. Unit VVPS_UV VPS low battery detection threshold 3.5 3.8 V tVPS_react VPS Comparator output reaction time for L->H and H->L transition 100 700 ns Filter time for VPS low battery detection 0.5 5 µs tLBD_FIL 6.1.5 Parameter Charge pump undervoltage In case VGBHI is lower than VCP_UV for tCP_UV, a charge pump undervoltage is detected, all outputs are actively turned off and the VCP_UV_LATCH is set high (cleared on SPI readout). The undervoltage comparator output can be monitored by reading VCP_UV_STATE bit via SPI. Outputs are re-engaged when undervoltage condition disappears. DS12275 - Rev 8 page 120/151 L9945 Disable sources Table 34. Charge pump undervoltage detection electrical characteristics Symbol Parameter Test condition Min. Max. Unit VCP_UV Under voltage threshold Referenced to VVPS VVPS + 3.9 VVPS + 5.1 V VhCP_UV Under voltage hysteresis Referenced to VVPS 250 - mV Digital filter of UV shutdown - 10 30 µs tCP_UV 6.1.6 SPI enable bit Each channel can be enabled/disabled independently by programming the en_OUT_xx SPI bit. If such bit is set low, the corresponding channel is three-stated. By default, all channels are three-stated and must be enabled setting en_OUT_xx high after having properly configured them in the same SPI register. Output control signal is ignored as long as en_OUT_xx is low. 6.1.7 Protection disable bit L9945 offers additional SPI bit for disabling channels via SPI: prot_disable_xx. Although such bit can disable each channel separately, the main purpose of prot_disable_xx is to allow a fast disabling of all channels through a single SPI frame. In fact, all prot_disable_xx bit are part of the same SPI command. In case prot_disable_xx is set high, the corresponding channel is actively turned off. Output control signal is ignored as long as prot_disable_xx is low. 6.1.8 EN6 input Channel 6 is designed for being used in safety relevant applications. For such reason, an additional enable input, EN6, has been provided. If EN6 is set low, channel 6 is actively turned off and the EN6_LATCH is set high (cleared on SPI readout). Channel 6 control signal is ignored as long as EN6 is low. 6.1.9 NRES assertion In case of NRES assertion, all outputs are actively turned off and the NRES_LATCH is set (cleared on SPI readout). Since channel configuration is reset, output re-engagement must be executed manually. 6.1.10 Communication Check (CC) Communication Check (CC) starts to work as soon as the disable inputs NDIS/DIS are released. With this condition the CC timer is started. Depending on the status of NDIS/DIS at the release of NRES, two possible scenarios can occur: • NDIS/DIS are released after NRES release, once the external microcontroller power-up routine is completed. In this case, CC starts with tCC time frame (see Figure 26) • NDIS/DIS are released before NRES release. In this case, once NRES is deasserted, CC starts with tCC_INIT time frame, in order to allow the external microcontroller completing the power-up routine. Then, it switches to tCC (see Figure 27) Figure 26. NDIS/DIS release after NRES release: tCC is selected as watchdog starting timer value NRES DIS NDIS CC function CC timing disabled enabled 55...80ms typ 66ms 55...80ms 55...80ms GAPG0102161044CFT DS12275 - Rev 8 page 121/151 L9945 Diagnostics overview Figure 27. NDIS/DIS release before NRES release: tCC is selected as watchdog starting timer value. Then, CC timer switches to tCC. NRES DIS NDIS CC function disabled CC timing enabled 110...165ms typ 132ms 55...80ms 55...80ms GAPG0102161058CFT The distinction between tCC and tCC_INIT applies only at the beginning of CC. After the first valid SPI frame, CC always operates with tCC deadline. In case of no valid communication the CC timer will expire and disable all related outputs. With the next valid communication the outputs are enabled. Each correct communication restarts the CC timer. If a CC failure is detected, all channels except 7 and 8 are actively turned off and the CC_LATCH is set high (cleared on SPI readout). The CC can be deactivated by programming the CONFIG_CC field via SPI. By default CC is active. CC status can be monitored by reading the config_CC_STATE SPI bit. Note: When configured as H-Bridge, channels 7 and 8 are handled like other channels and are disabled in case of CC failure. Table 35. CC timings Symbol tCC tCC_INIT 6.2 Parameter Min. Max. Unit Communication Timeout 55 85 ms Deadline for the first communication engagement in case DIS/NDIS are released before NRES release. 110 165 ms Diagnostics overview The device performs two types of diagnostics for each output channel: • ON state diagnostics: overcurrent (OC) detection; • OFF state diagnostics: open load (OL), short to ground (STG), and short to battery (STB) detection. Diagnostic can be enabled/disabled by programming the ENABLE_DIAGNOSTIC bit. The AN "L9945_Diagnostics_Explained" covers all the main aspects of diagnostics and helps choosing the correct values for the tblank_oc and tdiag filter times. Diagnostic report for all channels is readable via SPI, after having issued the 0x9AAA0001 frame. The diagnostic status of each channel is encoded in 3 bit (diag_xx[2-0]), as shown in the table below. DS12275 - Rev 8 page 122/151 L9945 Diagnostics overview Table 36. Diagnostic codes Note: Channel Status diag_xx[2-0] Priority OC pin failure (see note below) 000 1 OC failure 001 2 STG/STB failure 010 3 OL failure 011 4 No failure 100 5 No OC failure 101 6 No OL/STG/STB failure 110 7 No diagnostic done 111 8 The OC pin failure, corresponding to the code "000" is available only for channels operating in Peak & Hold. This code is unused in other configurations. Refer to Section 5.6.2 in order to understand how this diagnostic is performed. Figure 28. Diagnostic codes quick look GADG0806171512PS For an immediate fault detection, the MSB of the diagnostic code can be evaluated, as shown in Figure 28. An MSB equal to zero indicates that a failure occurred. By default, all channels will report the "No diagnostic done" message. Such message is also reported in case diagnostic has been disabled. The diagnostic status follows a priority concept: if more than one event occurs on a channel, only the one with the highest priority will be encoded in the diag_xx[2-0] bit. Priority codes are related to the severity of the fault. OC failures have the highest priority. The diagnostic latches are reset in case of SPI readout, POR or NRES. After a reset event, diagnostic filters are reset to prevent false detection. Figure 29 shows an equivalent Finite State Machine (FSM) that helps understanding diagnostic priority. DS12275 - Rev 8 page 123/151 L9945 ON state diagnostics Figure 29. FSM describing diagnostic priority EN 0 NON X SPI READOUT EN1 NON 1 STB/STG FAIL EN 1 NON 1 VOL FAIL EN 0 OL FAILURE NO OC NON0 NO STG/STB NON 1 VOL FAIL NO FAILURE EN0 NON 0 NON0 LVT FAIL EN 1 NON 1 EN 0 EN 0 NON 1 VOL FAIL NON1 EN1 EN = 0 NO DIAG EN 1 NON 0 Legenda:  Transition with fault  Transition without fault  Default state STG/STB FAILURE NON1 LVT FAIL NON 0 EN  0 Notes:  OC failure leads to output active turn OFF  POR, NRES and NON 0 SPI readout events lead to default state  EN refers to the NON0 en_OUT_xx bit OC  NON refers to FAILURE the generic channel control input (applies also to control via SPI) GADG1003170942PS Note: In case a diagnostic event occurs during SPI readout, such event is latched and provided with the next diagnostic request. 6.3 ON state diagnostics The following diagnostic codes can be set during the output ON state: • The diagnostic code corresponding to normal operation while in ON state is "No OC failure" (101); • The "No failure" (100) code will be reported only once, after an OFF->ON transition, assuming that "No OL/STG/STB failure" latch was set while in OFF state and "No OC failure" is detected; • The "OC failure" (001) or "OC pin failure" (000) codes will be reported in case of overcurrent detection. L9945 protects the external FET against overcurrent (OC) during the ON phase. The device features an analog comparator with a programmable overcurrent threshold. Sensing is performed measuring the voltage drop on an external element and comparing it to the programmed threshold. Such threshold can be compensated against battery and temperature variations for specific applications. 6.3.1 Behavior in case of OC detection If an OC event is detected, the output is actively shut off and the "OC failure" message is encoded in the diag_xx[2-0] bit. To prevent FET damage, in case the normal operation gate charge/discharge currents are low (1 mA or 5 mA), the device selects a higher shut off current among the ones available through GCC_config_xx. By programming the GCC_override_config, it is possible to select the entity of current increase in case of OC, as shown in the table below. These settings are in common between all channels. Table 37. Selection of fast shutdown currents in case of OC detection GCC_override_config 0 DS12275 - Rev 8 IPU or IPD [mA] 1→5 5 → 20 page 124/151 L9945 ON state diagnostics IPU or IPD [mA] GCC_override_config 1 → 20 1 Note: 5 → 20 IPU is used to shut down PMOS, while IPD shuts down NMOS. The GCC override configuration is applied as soon as an OC event is detected. The original GCC configuration is restored once diagnostics have been read. 6.3.2 Output re-engagement strategy after an OC event After an OC event, the affected output must be manually re-engaged. There are two reactivation strategies, configurable via SPI bit prot_config_xx: • Output re-engagement with control signal switching event (default); • Output re-engagement after diagnostic readout and control signal switching event. In case of H-Bridge configuration, the prot_config_xx has no effect. Re-engagement is always performed after diagnostic readout. Note: Control signal can be either NONx or SPI_ON_OUTxx, depending on SPI_INPUT_SEL_xx bit 6.3.3 OC sensing strategy OC detection is performed by sensing the voltage either on an external shunt resistor or between the drain and the source of the external FET. Detection strategy can be selected on each channel independently by programming the OC_DS_Shunt_xx bit as follows: Table 38. OC sensing strategy OC_DS_Shunt_xx OC sensing strategy 0 Drain To Source Measurement (DSM) 1 Shunt Measurement Figure 30. Overcurrent sensing method (example on a LS NMOS) VBATT DFW DRN3 CM OC_DS_SHUNT = 0 → VDS GNSP3 LOAD BATT34 RM CESD GND RG LS NMOS RPD SNGP3 OC_DS_SHUNT = 1 → VSH RSH PGND34 GADG0806171536PS DS12275 - Rev 8 page 125/151 L9945 ON state diagnostics The following behaviors correspond to the different sensing methods (refer to Figure 31): • In case Rshunt is selected, the Vsense behavior during the OFF==>ON transition corresponds to an ascending transient. In case the FET current crosses the OC threshold with a positive slope, tBLANK_OC is stopped and tOC is started. The OC detection will be mainly based on tFIL_ON and tOC parameters. The former is a deglitch filter to avoid small overshoots on the shunt resistor due to inductive effects, while the latter represents the actual OC blanking time. An OC event lasting tFIL_ON+tOC will be detected and the output switched OFF: the programmed tBLANK_OC will have no effect on the OC reaction time. Only in case Peak & Hold configuration is selected and the OC event occurs while tBLANK_OC is still running, an ‘OC pin failure’ (000) will be reported instead of simple ‘OC failure’ (001). However, reaction time won’t be affected. • In case DSM is selected, the Vsense behavior during the OFF==>ON transition corresponds to a falling transient. Once tBLANK_OC has expired, the VDS will be compared to the OC threshold and, if greater, the output will be shut OFF. Hence, tBLANK_OC must be sized to allow VDS settling. In order to ensure maximum FET protection against critical OC events during blanking time, an OC threshold crossing with a positive slope will stop the tblank_oc and engage the tOC filter. Figure 31. Rshunt and DSM method diagram VSH VDS SHUT OFF OC EVENT OC EVENT OC THRESHOLD SWITCH ON NORMAL VALUE SWITCH ON OC THRESHOLD NORMAL VALUE SHUT OFF RSH method, tblank running t DMS method, tblank running t GADG3108170806PS 6.3.4 OC threshold selection The voltage corresponding to the OC threshold can be selected independently for each channel programming the OC_config_xx bit. Such threshold is highly flexible: it is encoded on 6 bits (64 available values) and falls in the [50 - 1000] mV range. Table 39. Overcurrent threshold selection electrical parameters Symbol VOC_RANGE Parameter Range Min. Typ. Max. Unit 50 - 1000 mV OC_RES Resolution - 6 - Bit tSETTLING Threshold settling Time 5 - 18 µs Refer to Table 40 for the encoding tables for LS and HS configurations. Overcurrent threshold must be programmed according to the Eq. (3): Eq. (3): Overcurrent threshold VOC = ROC × IOC (3) where VOC is the value programmed in the OC_config_xx bit, IOC is the maximum current for the given application and ROC can be either RSH (shunt resistor) or RDSon (DSM). Note: DS12275 - Rev 8 For H-Bridge configuration, refer to Overcurrent detection strategies for H-Bridge and Current limitation for HBridge to understand how OC thresholds can be programmed and exploited also for current limitation feature. page 126/151 L9945 ON state diagnostics Table 40. OC threshold selection OC_config_xx[5-0] DS12275 - Rev 8 LS HS Unit Min. Max. Min. Max. 0 53 67 53 69 mV 1 68 82 68 85 mV 2 83 97 83 101 mV 3 97 113 99 117 mV 4 113 128 113 133 mV 5 128 143 129 150 mV 6 142 158 144 166 mV 7 157 173 159 182 mV 8 172 188 172 198 mV 9 186 204 189 214 mV 10 201 220 204 231 mV 11 216 235 219 247 mV 12 231 250 234 263 mV 13 246 266 248 279 mV 14 261 281 264 295 mV 15 275 296 278 311 mV 16 290 311 290 326 mV 17 305 327 305 341 mV 18 320 343 320 356 mV 19 334 358 338 375 mV 20 349 374 351 391 mV 21 364 389 367 407 mV 22 379 405 382 423 mV 23 393 420 397 439 mV 24 408 436 412 455 mV 25 423 451 427 471 mV 26 438 467 442 488 mV 27 453 482 456 504 mV 28 467 498 472 520 mV 29 482 513 486 536 mV 30 497 529 501 552 mV 31 512 544 515 568 mV 32 526 559 525 579 mV 33 541 575 545 595 mV 34 556 590 560 612 mV 35 570 606 575 628 mV 36 585 621 590 644 mV 37 600 637 604 660 mV page 127/151 L9945 ON state diagnostics LS OC_config_xx[5-0] 6.3.5 HS Unit Min. Max. Min. Max. 38 614 653 619 676 mV 39 629 668 634 693 mV 40 644 684 649 708 mV 41 658 699 663 724 mV 42 673 715 679 740 mV 43 688 730 693 756 mV 44 702 746 708 772 mV 45 717 761 723 788 mV 46 732 777 738 804 mV 47 746 792 753 821 mV 48 761 808 767 836 mV 49 776 823 782 852 mV 50 791 839 797 868 mV 51 806 854 812 885 mV 52 820 870 827 900 mV 53 835 885 842 916 mV 54 849 900 856 933 mV 55 864 916 871 949 mV 56 878 931 886 964 mV 57 893 947 900 981 mV 58 908 962 916 997 mV 59 922 977 930 1013 mV 60 937 992 946 1029 mV 61 951 1008 960 1045 mV 62 967 1023 975 1061 mV 63 982 1038 987 1078 mV OC detection timings ON state diagnostics timings are listed in the following table. Table 41. OC detection timings Symbol Parameter OC blanking filter: tBLANK_OC It doesn't mask the OC failure. It only determines the assertion of the "No OC failure" diagnostic code. DS12275 - Rev 8 Condition Min. Typ. Max. Unit tblank_oc = 000 10 11.1 12.2 µs tblank_oc = 001 14 15.6 17.1 µs tblank_oc = 010 18 20 22 µs tblank_oc = 011 28 31.1 34.2 µs tblank_oc = 100 39 42.2 46.5 µs tblank_oc = 101 48 53.3 58.7 µs tblank_oc = 110 88 97.8 107.6 µs tblank_oc = 111 128 142.2 156.5 µs page 128/151 L9945 ON state diagnostics Symbol tFIL_ON tOC 6.3.6 Parameter Condition Min. Typ. Max. Unit OC deglitch filter time - 0.6 - 1 µs OC Detection filter time - 2 - 3 µs Temperature compensation for OC threshold L9945 offers the possibility to compensate the OC threshold against temperature variations. Such feature can be enabled independently on each channel. The device is able to monitor the internal junction temperature Tj through on board Temperature ADC. Given the estimated temperature variation between L9945 junction and the external FET junction Eq. (4): Estimated temperature variation for the compensation algorithm ΔT = T jFET − T j (4) An internal algorithm measures Tj and is able to compensate VOC against RDSon variations induced by TjFET. The latter can be estimated according to the given application and operating scenario. Temperature compensation can be enabled by programming the OC_Temp_comp_xx bit according to the following table: Table 42. Temperature compensation OC_Temp_comp_xx Function 00 Temperature compensation deactivated 01 Temperature compensation active for estimated ∆T < 60 °C. TCF is saturated at '1' for Tj ≥ Tj_SAT = 83 °C. 10 Temperature compensation active for estimated ∆T < 40 °C. TCF is saturated at '1' for Tj ≥ Tj_SAT = 96 °C. 11 Temperature compensation active for estimated ∆T < 25 °C. TCF is saturated at '1' for Tj ≥ Tj_SAT = 108 °C. In case temperature compensation is enabled, the overcurrent threshold must be programmed according to Eq. (3), where ROC is the RDSon of the external FET evaluated for TjFET = 150 °C. The internal algorithm compensates the OC threshold based on a multiplicative factor: Eq. (5): Temperature Compensation Factor (TCF) VOC_comp = TCF × VOC (5) TCF = 1 when Tj ≥ Tj_SAT, and it's decremented with a constant slope of 0.38 %/°C for Tj < Tj_SAT. DS12275 - Rev 8 page 129/151 L9945 ON state diagnostics Figure 32. TCF vs. Tj 1.1 1 0.9 0.8 TCF 0.7 0.6 0.5 0.4 0.3 0.2 0 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 0.1 Tj [°C] TCF (Δ = 25°C) TCF (Δ = 40°C) TCF (Δ = 60°C) GADG2212171232PS Note: This feature is recommended only in case of DSM, because the compensation algorithm is based on RDSon variations. The external FET must have a characteristic RDSon vs. TjFET that matches the 0.38 %/°C slope. In case of shunt measurement, the algorithm may show performances worse than the uncompensated strategy. 6.3.7 Battery compensation for OC threshold L9945 offers the possibility to compensate the OC threshold against battery variations. This feature can be enabled when driving a resistive output load RL, and helps preventing the load resistance from dropping below a minimum threshold RLmin. Given Eq. (3), the IOC can be evaluated as the current flowing when the battery is at its maximum operating value (18 V for passenger vehicles or 36 V for commercial vehicles) and the load resistance assumes its minimum allowed value RLmin: Eq. (6): Overcurrent detection in case of resistive load IOC ≅ VBATTmax RLmin VOC = ROC × VBATTmax RLmin (6) Eq. (6) assumes that RL >> ROC. The sensing resistance ROC can be either the shunt resistor or the RDSon. Referring to Figure 34 and Figure 35, the device measures: Eq. (7): Overcurrent sensing in case of resistive load VSENSE = ROC × ILOAD = ROC × VBATT RL (7) The device is able to monitor the battery voltage on the VPS pin through the on board VPS ADC. This information can be used to compensate the VOC with respect to VBATT variations. Therefore, the OC detection occurs only when VSENSE = VOC due to a RL variation. The internal algorithm compensates the OC threshold based on a multiplicative factor: Eq. (8): Battery Compensation Factor (BCF) VOCcomp = BCF × VOC (8) The battery compensation feature can be activated independently on each channel by programming the OC_Batt_comp_xx bit. Two different BCF have been implemented for Passenger Vehicle (PV) and Commercial Vehicle (CV) applications. The BCF can be selected by programming the Batt_fact_config bit (refer to Figure 33). DS12275 - Rev 8 page 130/151 L9945 ON state diagnostics Figure 33. BCF vs.VPS 1.6 1.5 1.4 1.3 1.2 1.1 BCF 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 VPS [V] BCF (CV) BCF (PV) GADG2212171251PS Note: Because the algorithm is based on the assumption made for Eq. (6), the battery compensation feature is recommended only in case of resistive load. Usage either in case of different load types or in case of small resistive loads may lead to performances worse than the uncompensated strategy. 6.3.8 Reading the compensated OC threshold In general, the overcurrent threshold can be evaluated as follows: Eq. (9): Overcurrent threshold compensation formula VOCcomp = BCF × TCF × VOC (9) Where VOC is the value programmed in the OC_config_xx bit, BCF is the battery compensation factor and TCF is the temperature compensation factor. When a compensation feature is disabled, its compensation factor is set to 1 (no effect on VOC). Note: 6.3.9 It is recommended to enable battery and temperature compensation simultaneously only in case of resistive load with DSM. Different usage may lead to performances worse than the uncompensated strategy. When configuring the device, the OC_read_xx can be used to select whether reading the programmed threshold VOC or the compensated one VOCcomp. OC detection schematics Figure 34 shows the OC detection implementation in case of LS configuration. It can also be applied to the HS scenario with NFET (see description). In case DSM is selected RSH must not be mounted and the pins SNGPx and PGNDxx must be shorted. Figure 35 shows the OC detection implementation in case of HS configuration with PMOS. In case DSM is selected RSH must not be mounted and the pins GNSPx and BATTxx must be shorted. DS12275 - Rev 8 page 131/151 L9945 ON state diagnostics Figure 34. OC detection through DSM or Shunt Measurement in Low Side configuration L9945 BOARD VBATT BATT34 Batt_fact _config BCF LOAD VPS ADC DRN3 1 1 0 0 1 OC_Batt_comp_xx OC_config_xx OC_Tem p_comp ΔT = TjFET - Tj Others TCF DAC 00 CM 1 LS NMOS V OC Tj ADC GNSP3 0 OC V SENSE RM 1 RG T jFET RPD SNGP3 RSH OC_DS_Shunt_xx PGND34 GADG1003171213PS Note: DS12275 - Rev 8 VOC compensation against temperature and battery variations is shown in Figure 34. In case of High Side configuration with NMOS, RSH and the LOAD must be swapped, and the OC_DS_Shunt_xx signal is negated. page 132/151 L9945 OFF state diagnostics Figure 35. OC detection through DSM or Shunt Measurement in High Side configuration with PMOS L9945 BOARD VBATT BATT34 VPS ADC Batt_fact _config BCF RSH GNSP3 1 1 0 0 1 OC_Batt_comp_xx OC_config_xx OC_Tem p_comp Others TCF ΔT = TjFET - Tj DAC 00 1 HS PMOS RPU V OC Tj ADC SNGP3 RG RM 0 OC 1 DRN3 CM LOAD V SENSE TjFET OC_DS_Shunt_xx PGND34 GADG1003171245PS Note: VOC compensation against temperature and battery variations is shown in Figure 35. 6.4 OFF state diagnostics The following diagnostic codes can be set during the output OFF state: • The diagnostic code corresponding to normal operation while in OFF state is "No OL/STG/STB failure" (110); • The "No failure" (100) code will be reported only once, after an ON->OFF transition, assuming that "No OC failure" latch was set while in ON state; • The "OL failure" (011) or "STG/STB failure" (010) codes will be reported respectively in case of open load and short to ground/battery failures. Short To Battery (STB), Open Load (OL) and Short To Ground (STG) are part of the OFF state diagnostics. L9945 measures the voltage on the output node Vout to determine if the output is shorted to battery/ground (respectively for HS/LS configurations) or if the output node is floating (open load). Depending on channel configuration, different faults can be detected: • LS diagnostics – Vout < VLVT indicates a STG (see Figure 36) DS12275 - Rev 8 – VLVT < Vout < VOL indicates an OL – Vout > VOL is a normal condition for LS configuration page 133/151 L9945 OFF state diagnostics • HS diagnostics – Vout > VOL indicates a STB (see Figure 36) – VLVT < Vout < VOL indicates an OL – Vout < VLVT is a normal condition for HS configuration Refer to Table 36 for the diagnostic codes corresponding to the STB/STG and OL faults. Refer to Section 6.4.2 for the VOL and VLVT thresholds value. When an OL or STB/STG fault is detected, the corresponding diagnostic code is latched, but no action is taken on the outputs. Note: Vout corresponds to DRNx pin for LS NMOS and HS PMOS configurations, while it's SNGPx pin for HS NMOS configuration. 6.4.1 Settling and deglitch filter times A filter time tDIAG has been implemented to allow settling of the output node voltage (Vout) before the comparison to the diagnostic thresholds. When an output is switched OFF, the tDIAG filter time is started. When the filter expires, Vout is compared to the VLVT and VOL thresholds to determine the output diagnostic status (see Figure 36). The filter time tDIAG can be programmed as follows: Table 43. Diagnostic filter time selection for OFF state tdiag_config_xx Value Unit Values available for all configurations 00 25.6 µs 01 61.2 µs 10 105.6 µs 11 150 µs Additional values available for H-Bridge configuration (refer to H-Bridge OFF state diagnostic timings) 00 11.2 µs 01 28.9 µs 10 40 µs 11 51.2 µs While in the OFF state, the tDIAG filter is reset and restarts if one of the following condition occurs: • LS configuration – VLVT crossed with a negative slope (possible STG), – • VOL crossed with a negative slope (possible OL), HS configuration – VLVT crossed with a positive slope (possible OL), – VOL crossed with a positive slope (possible STB). To avoid glitches on threshold crossing, a deglitch filter with tFIL_OFF timeout has been implemented. The deglitch filter time tFIL_OFF is fixed (see Figure 36): DS12275 - Rev 8 page 134/151 L9945 OFF state diagnostics Table 44. Deglitch filter time for OFF state diagnostics Symbol Parameter Min. Max. Unit tFIL_OFF Deglitch filter time for OFF state diagnostics 0.3 0.5 µs Figure 36. Deglitch and settling filter times for OFF state diagnostics: (left) STG detection on LS; (right) STB detection on HS HS OFF Diagnostics LS OFF Diagnostics Vout No OL/STG Transient fault ON → OFF transition Vout ON → OFF transition Permanent fault Transient fault Permanent fault STB VOL VOL VLVT VLVT STG t Deglitch filter t FIL_OFF No OL/STB Deglitch filter t Settling counter t t FIL_OFF t Settling counter t DIAG t DIAG t Fast charge t Fast discharge t t GADG1303170949PS Note: 6.4.2 Vout corresponds to DRNx pin for LS NMOS and HS PMOS configurations, while it's SNGPx pin for HS NMOS configuration. Diagnostic thresholds The diagnostic thresholds are fixed, as shown in the table below. They have been designed in tracking, thus both spreading in the same direction. Table 45. OFF state diagnostic thresholds Symbol Parameter Min. Max. Unit 1.9 2.3 V 2.8 3.4 V Threshold for: VLVT • STG detection in LS config (Vout < VLVT) • OL detection in HS/LS config (VLVT < Vout < VOL) Threshold for: VOL Note: DS12275 - Rev 8 • STB detection in HS config (Vout > VOL) • OL detection in HS/LS config (VLVT < Vout < VOL) Vout corresponds to DRNx pin for LS NMOS and HS PMOS configurations, while it's SNGPx pin for HS NMOS configuration. page 135/151 L9945 OFF state diagnostics 6.4.3 Internal regulator for open load (OL) detection Each channel features an internal regulator with limited current capability that regulates the output node voltage Vout around VOUT_OL, which falls in the middle of the [VLVT; VOL] range. OL regulators are always ON, independently on the ENABLE_DIAGNOSTIC bit value. Table 46. Open Load output voltage Note: Symbol Parameter Min. Typ. Max. Unit VOUT_OL Vout node voltage in case of open load 2.25 2.5 2.75 V Vout corresponds to DRNx pin for LS NMOS and HS PMOS configurations, while it's SNGPx pin for HS NMOS configuration. Regulator current capability IDIAG can be programmed via diag_i_config_xx bit as follows: Table 47. Vout regulator current capability IDIAG diag_i_config_xx Min. Max. Unit 0 60 100 µA 1 0.6 1 mA A higher current capability allows compensating the leakage of external devices (FET, recirculation diodes, etc.) The current limitation feature allows distinguishing between OL and STB/STG faults: • In case of open load, the regulator is able to drive Vout around VOUT_OL and the OL fault is flagged; • In case of STB/STG fault, due to the limited current capability, the regulator has no effect on Vout. Therefore, output node voltage stays below VLVT (STG on LS) or above VOL (STB on HS). Refer to Figure 37 and Figure 39 for OL regulator operation in HS configuration. Refer to Figure 38 and Figure 39 for OL regulator operation in LS configuration. 6.4.4 Fast charge/discharge currents In order to reliably detect a fault, the Vout voltage must be stable before the settling time tDIAG expires. In case of STB/STG faults, high current capability of battery and ground supplies guarantee fast Vout settling. In case of open load, Vout must be brought in the [VLVT; VOL] range before tDIAG expires in order to guarantee fault detection. L9945 implements internal fast charge/discharge currents in order to allow settling of Vout in a time suitable for detection: • When HS transistor is switched OFF, a fast discharge current IFAST_DIS rapidly decreases Vout down to VOL to help the OL regulator detect an eventual open load fault (see Figure 37 and Figure 39). IFAST_DIS is enabled in case: – The HS channel has been just switched OFF; – The settling time tDIAG is still running; – • – DS12275 - Rev 8 Vout is above VOL. When LS transistor is switched OFF, a fast charge current IFAST_CHG rapidly increases Vout up to VLVT to help the OL regulator detect an eventual open load fault (see Figure 38 and Figure 39). IFAST_CHG is enabled in case: – The LS channel has been just switched OFF; – The settling time tDIAG is still running; Vout is below VLVT. page 136/151 L9945 OFF state diagnostics Figure 37. OFF state output regulator for OL detection. Example of operation on HS Device side Board side VBATT BATT12 DRN1 HS NMOS RM CM RG CBATT RPD GND VOUT_OL GND Vout ≈ VOUT_OL OUT1 SNGP1 EN V3V3A IDIAG CEMI DFW GND LOAD GNSP1 ON OFF 1 0 IFAST_DIS GND GND VOL GND V3V3A 1 IN t CK RES Vout deglitch IFAST_DIS