L9950TR

L9950 L9950XP Door actuator driver Features ■ One full bridge for 6A load (Ron=150 m ) ■ Two half bridges for 3A load (Ron=300 m ) ■ Two half bridges for 1.5A load (Ron=800 m ) ■ One highside driver for 6A load (Ron=100 m ) ■ Four highside drivers for 1.5 A load (Ron=800 m ) ■ Programmable softstart function to drive loads with higher inrush currents (i.e. current >6 A,>3 A,>1.5 A) PowerSO-36 PowerSSO-36 Applications ■ Very low current consumption in standby mode (IS < 6 A typ; ICC 0.7 VCC, CL = 100 pF DO delay time Table 17. CSN timing Symbol Parameter Test condition Min. Typ. Max. Unit tCSN_HI,stb Minimum CSN HI time, Transfer of SPI command switching from standby mode to Input Register - 20 50 µs tCSN_HI,min Maximum CSN HI time, active mode - 2 4 µs Figure 3. Transfer of SPI command to input register SPI - transfer timing diagram CSN high to low: DO enabled CSN time CLK 0 1 2 3 4 5 6 7 X 18 19 X 0 20 21 22 23 time DI: data will be accepted on the rising edge of CLK signal DI 0 1 2 3 4 5 6 7 X X 18 19 0 20 21 22 23 DO: data will change on the falling edge of CLK signal DO 0 1 2 3 fault bit Input Data Register 16/39 4 5 6 7 X X 18 19 20 21 22 23 1 time 0 1 time CSN low to high: actual data is transfered to output power switches old data 1 new data time Doc ID 10311 Rev 11 L9950 - L9950XP Electrical specifications Figure 4. SPI - input timing 0.8 VCC CSN 0.2 VCC t t set CSN t CLKH se t CLK 0.8 VCC CLK 0.2 VCC t t set DI hold DI t CLKL 0.8 VCC Valid DI Valid 0.2 VCC Figure 5. SPI - DO valid data delay time and valid time t f in t r in 0.8 VCC 0.5 VCC 0.2 VCC CLK t r DO DO (low to high) 0.8 VCC 0.2 VCC t d DO t f DO 0.8 VCC DO (high to low) 0.2 VCC Doc ID 10311 Rev 11 17/39 Electrical specifications Figure 6. L9950 - L9950XP SPI - DO enable and disable time tf in tr in 0.8 VCC 50% 0.2 VCC CSN 50% DO pull-up load to VCC C L = 100 pF ten DO tri L t dis DO L tri 50% DO pull-down load to GND C L = 100 pF ten DO tri H Figure 7. t dis DO H tri SPI - driver turn-on/off timing, minimum csn hi time CSN low to high: data from shift register is transferred to output power switches t r in t f in tCSN_HI,min 80% 50% 20% CSN tdOFF output current of a driver ON state OFF state 80% 50% 20% t OFF tdON t ON output current of a driver 18/39 OFF state Doc ID 10311 Rev 11 ON state 80% 50% 20% L9950 - L9950XP Figure 8. Electrical specifications SPI - timing of status bit 0 (fault condition) CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO CSN time CLK time DI time DI: data is not accepted DO 0time DO: status information of data bit 0 (fault condition) will stay as long as CSN is low Doc ID 10311 Rev 11 19/39 Application information L9950 - L9950XP 3 Application information 3.1 Dual power supply: VS and VCC The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (VCC increases from under voltage to VPOR OFF = 4.2 V) the circuit is initialized by an internally generated power on reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to tristate (high impedance) and the status registers are cleared. 3.2 Standby mode The standby mode of the L9950 is activated by clearing the bit 23 of the Input Data Register 0. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 6 µA (50 µA) for CSN = high (DO in tristate). By switching the VCC voltage a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode. 3.3 Inductive loads Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT6 without external free wheeling diodes. The highside drivers OUT7 to OUT11 are intended to drive resistive loads. Hence only a limited energy (E100 µH) an external free wheeling diode connected to GND and the corresponding output is needed. 3.4 Diagnostic functions All diagnostic functions (over/open load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open load: 1 ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the overload and thermal shutdown condition will disable the corresponding driver (overload) or all drivers (thermal shutdown), respectively. Without setting the over-current recovery bits in the Input Data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers. 20/39 Doc ID 10311 Rev 11 L9950 - L9950XP 3.5 Application information Overvoltage and under voltage detection If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical 21 V), the outputs OUT1 to OUT11 are switched to high impedance state to protect the load. When the voltage VS drops below the under voltage threshold VSUV OFF (UV switch OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS recovers to normal operating voltage the outputs stages return to the programmed state (input register 0: bit 20=0). If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage. 3.6 Temperature warning and thermal shutdown If junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. In order to reactivate the output stages the junction temperature must decrease below Tj SD - Tj SD HYS and the thermal shutdown bit has to be cleared by the microcontroller. 3.7 Open-load detection The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 3.8 Over load detection In case of an over-current condition a flag is set in the status register in the same way as open load detection. If the over-current signal is valid for at least tISC = 32 µs, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver. Doc ID 10311 Rev 11 21/39 Application information 3.9 L9950 - L9950XP Current monitor The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits 18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5, OUT6 and OUT11 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open or overload condition. For example this can be used to detect the motor state (starting, free running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs). 3.10 PWM inputs Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit is set, the output is controlled by the logically AND combination of the PWM signal and the output control bit in Input Data Register. The outputs OUT1-OUT8 and OUT11 are controlled by the PWM1 input and the outputs OUT9/10 are controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals. 3.11 Cross current protection The six half brides of the device are cross current protected by an internal delay time. If one driver (LS or HS) is turned off the activation of the other driver of the same half bridge will be automatically delayed by the cross current protection time. After the cross current protection time is expired the slew rate limited switch off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned on with slew rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned off before the opposite driver will start to conduct. 3.12 Programmable soft start function to drive loads with higher inrush current Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits. 22/39 Doc ID 10311 Rev 11 L9950 - L9950XP Figure 9. Application information Example of programmable soft start function for inductive loads Doc ID 10311 Rev 11 23/39 Functional description of the SPI L9950 - L9950XP 4 Functional description of the SPI 4.1 Serial Peripheral Interface (SPI) This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin will reflect the status bit 0 (fault condition) of the device which is a logical or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI communication cycle. Note: In contrast to the SPI standard the least significant bit (LSB) will be transferred first (see Figure 3). 4.2 Chip Select Not (CSN) The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN input pin is driven above 7.5V, the L9950 will go into a test mode. In the test mode the DO will go from tri state to active mode. 4.3 Serial Data In (DI) The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Note: 24/39 Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. Doc ID 10311 Rev 11 L9950 - L9950XP 4.4 Functional description of the SPI Serial Data Out (DO) The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. 4.5 Serial clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. 4.6 Input data register The device has two input registers. The first bit (bit 0) at the DI input is used to select one of the two Input Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver. If bit 23 is zero, the device will go into the standby mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN). 4.7 Status register This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI communication cycle. If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers. Doc ID 10311 Rev 11 25/39 Functional description of the SPI 4.8 L9950 - L9950XP Test mode The test mode can be entered by rising the CSN input to a voltage higher than 7.0 V. In the test mode the inputs CLK, DI, PWM1/2 and the internal 2 MHz CLK can be multiplexed to data output DO for testing purpose. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. For EWS testing a special test pad is available to measure the internal bandgap voltage, the TW and TSD thresholds. The internal logic prevents that the Hi-Side and Lo-Side driver of the same half-bridge can be switched on at the same time. In the test mode this combination is used to multiplex the desired signals according to following table: Table 18. Test mode LS1 HS1 LS2 HS2 LS3 HS3 26/39 DO LS3 HS3 LS4 HS4 LS5 HS5 Test pad ! (both HI) ! (both HI) ! (both HI) No error ! (both HI) ! (both HI) ! (both HI) 5µA Iref both HI ! (both HI) ! (both HI) DI both HI ! (both HI) ! (both HI) Tsens1 ! (both HI) both HI ! (both HI) CLK ! (both HI) both HI ! (both HI) Tsens2 both HI both HI ! (both HI) INT_CLK both HI both HI ! (both HI) Tsens3 ! (both HI) ! (both HI) both HI PWM1 ! (both HI) ! (both HI) both HI Tsens4 both HI ! (both HI) both HI PWM2 both HI ! (both HI) both HI Tsens5 ! (both HI) both HI both HI Tsens6 both HI both HI both HI Vbandgap Doc ID 10311 Rev 11 L9950 - L9950XP Functional description of the SPI Table 19. SPI - input data and status registers 0 Input register 0 (write) Status register 0 (read) Bit 23 22 Name Comment Enable bit If Enable Bit is set the device will be switched in active mode. If Enable Bit is cleared device go into standby mode and all bits are cleared. After poweron reset device starts in standby mode. Reset bit If Reset Bit is set both status registers will be cleared after rising edge of CSN input. OC recovery duty cycle 21 0: 12% 1: 25% 20 19 Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS output will be multiplexed to the CM output: Current monitor select bits Comment Always 1 A broken VCC or SPI connection of the L9950 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. In case of an overvoltage or VS overvoltage undervoltage event the corresponding bit is set and the outputs are deactivated. If This bit defines in VS voltage recovers to normal combination with the overoperating conditions outputs current recovery bit (Input VS undervoltage are reactivated automatically Register 1) the duty cycle (if Bit 20 of status register 0 is in over-current condition not set). of an activated driver. If this bit is set the microcontroller has to Overvoltage/Un clear the status register dervoltage after recovery disable undervoltage/overvoltage event to enable the outputs. 18 Name Bit 19 Bit 18 Output 0 0 OUT11 1 0 OUT1/OUT 6 0 1 OUT5 1 1 OUT4 Thermal shutdown In case of an thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. Temperature warning This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown. Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times). HS driver of OUT1 is only selected if HS driver OUT1 is switched on and HS driver OUT6 is not activated. Doc ID 10311 Rev 11 27/39 Functional description of the SPI Table 19. L9950 - L9950XP SPI - input data and status registers 0 (continued) Input register 0 (write) Status register 0 (read) Bit Name Name 17 OUT11 – HS on/off OUT11 – HS over-current 16 OUT10 – HS on/off OUT10 – HS over-current 15 OUT9 – HS on/off OUT9 – HS over-current 14 OUT8 – HS on/off OUT8 – HS over-current 13 OUT7 – HS on/off 12 OUT6 – HS on/off 11 OUT6 – LS on/off 10 OUT5 – HS on/off 9 OUT5 – LS on/off 8 OUT4 – HS on/off 7 OUT4 – LS on/off 6 OUT3 – HS on/off 5 OUT3 – LS on/off 4 OUT2 – HS on/off OUT2 – HS over-current 3 OUT2 – LS on/off OUT2 – LS over-current 2 OUT1 – HS on/off OUT1 – HS over-current 1 OUT1 – LS on/off OUT1 – LS over-current 0 28/39 Comment If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (Input Register 1) the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT6 are half bridges. If the bits of HSand LS driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND. In test mode (CSN>7.5 V) this bit combinations are used to multiplex internal signals to the DO output. Comment OUT7 – HS over-current OUT6 – HS over-current OUT6 – LS over-current OUT5 – HS over-current OUT5 – LS over-current OUT4 – HS over-current OUT4 – LS over-current OUT3 – HS over-current In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the overcurrent Recovery Enable bit is set (Input Register 1) the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21). If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (Reset Bit) to reactivate the output driver. OUT3 – LS over-current 0 No error bit Doc ID 10311 Rev 11 A logical NOR combination of all bits 1 to 22 in both status registers. L9950 - L9950XP Functional description of the SPI Table 20. SPI - input data and status registers 1 Input register 1 (write) Status register 1 (read) Bit Name Comment 23 Enable bit If Enable bit is set the device will be switched in active mode. If Enable Bit is cleared device go into standby mode and all bits are cleared. After poweron reset device starts in standby mode. 22 OUT11 OC Recovery Enable VS overvoltage 21 OUT10 OC Recovery Enable VS undervoltage 20 19 18 OUT9 OC Recovery Enable OUT8 OC Recovery Enable In case of an over-current event the over-current status bit (Status Register 0) is set and the output is switched off. If the over-current Recovery Enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21 of Input Data Register 0). Depending on occurrence of Overcurrent Event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero. OUT7 OC Recovery enable Doc ID 10311 Rev 11 Name Comment Always 1 A broken VCC or SPI connection of the L9950 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If VS voltage recovers to normal operating conditions outputs are reactivated automatically. In case of an thermal shutdown all outputs are switched off. The Thermal shutdown microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. Temperature warning This bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown. Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times). 29/39 Functional description of the SPI Table 20. L9950 - L9950XP SPI - input data and status registers 1 (continued) Input register 1 (write) Status register 1 (read) Bit Name Name 17 OUT6 OC Recovery Enable OUT11 – HS open load 16 OUT5 OC Recovery Enable OUT10 – HS open load 15 OUT4 OC Recovery Enable 14 OUT3 OC Recovery Enable 13 OUT2 OC Recovery Enable OUT7 – HS open load 12 OUT1 OC Recovery Enable OUT6 – HS open load 11 OUT11 PWM1 Enable OUT6 – LS open load 10 OUT10 PWM2 Enable OUT5 – HS open load 9 OUT9 PWM2 Enable OUT5 – LS open load 8 OUT8 PWM1 Enable OUT4 – HS open load 7 OUT7 PWM1 Enable 6 OUT6 PWM1 Enable 5 OUT4 PWM1 Enable 4 OUT4 PWM1 Enable 3 OUT3 PWM1 Enable OUT2– LS open load 2 OUT4 PWM1 Enable OUT1 – HS open load 1 OUT4 PWM1 Enable OUT1 – LS open load 0 30/39 Comment After 50 ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed. If the PWM1/2 Enable Bit is set and the output is enabled (Input Register 0) the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input is low. OUT9 and OUT10 is controlled by PWM2 input all other outputs are controlled by PWM1 input. 1 OUT9 – HS open load OUT8 – HS open load OUT4 – LS open load OUT3 – HS open load OUT3 – LS open load OUT2 –HS open load No Error bit Doc ID 10311 Rev 11 Comment The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. A logical NOR combination of all bits 1 to 22 in both status registers. L9950 - L9950XP 5 Packages thermal data Packages thermal data Figure 10. Packages thermal data Doc ID 10311 Rev 11 31/39 Package and packing information L9950 - L9950XP 6 Package and packing information 6.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.2 PowerSO-36 package information Figure 11. PowerSO-36 package dimensions 32/39 Doc ID 10311 Rev 11 L9950 - L9950XP Package and packing information PowerSO-36 mechanical data Table 21. Millimeters Symbol Min. Typ. Max. A - - 3.60 a1 0.10 - 0.30 a2 - - 3.30 a3 0 - 0.10 b 0.22 - 0.38 c 0.23 - 0.32 D* 15.80 - 16.00 D1 9.40 - 9.80 E 13.90 - 14.5 E1 * 10.90 - 11.10 E2 - - 2.90 E3 5.80 - 6.20 e - 0.65 - e3 - 11.05 - G 0 - 0.10 H 15.50 - 15.90 h - - 1.10 L 0.8 - 1.10 M - - - N - - 10 deg R - - - s - - 8 deg Doc ID 10311 Rev 11 33/39 Package and packing information 6.3 L9950 - L9950XP PowerSSO-36 package information Figure 12. PowerSSO-36 package dimensions PowerSSO-36 mechanical data Table 22. Millimeters Symbol 34/39 Min. Typ. Max. A 2.15 - 2.45 A2 2.15 - 2.35 a1 0 - 0.10 b 0.18 - 0.36 c 0.23 - 0.32 D(1) 10.10 - 10.50 E 7.4 - 7.6 e - 0.5 - e3 - 8.5 - F - 2.3 - G - - 0.1 G1 - - 0.06 H 10.1 - 10.5 h - - 0.4 k 0° - 8° Doc ID 10311 Rev 11 L9950 - L9950XP Package and packing information PowerSSO-36 mechanical data (continued) Table 22. Millimeters Symbol Min. Typ. Max. L 0.55 - 0.85 M - 4.3 - N - - 10° O - 1.2 - Q - 0.8 - S - 2.9 - T - 3.65 - U - 1 - X 4.3 - 5.2 Y 6.9 - 7.5 1. “D” and “E” do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.15 mm per side (0.006”). 6.4 PowerSO-36 packing information Figure 13. PowerSO-36 tube shipment (no suffix) Doc ID 10311 Rev 11 35/39 Package and packing information L9950 - L9950XP Figure 14. PowerSO-36 tape and reel shipment (suffix “TR”) TAPE DIMENSIONS A0 B0 K0 K1 F P1 W 15.20 ± 0.1 16.60 ± 0.1 3.90 ± 0.1 3.50 ± 0.1 11.50 ± 0.1 24.00 ± 0.1 24.00 ± 0.3 All dimensions are in mm. 36/39 Doc ID 10311 Rev 11 REEL DIMENSIONS Base qty Bulk qty A (max) B (min) C (±0.2) D (min) G (+2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 L9950 - L9950XP 6.5 Package and packing information PowerSSO-36 packing information Figure 15. PowerSSO-36 tube shipment (no suffix) C Base qty Bulk qty Tube length (±0.5) A B C (±0.1) B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 16. PowerSSO-36 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base qty Bulk qty A (max) B (min) C (±0.2) F G (+2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape hole spacing Component spacing Hole diameter Hole diameter Hole position Compartment depth Hole spacing W P0 (±0.1) P D (±0.05) D1 (min) F (±0.1) K (max) P1 (±0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets sealed with cover tape. User direction of feed Doc ID 10311 Rev 11 37/39 Revision history 7 L9950 - L9950XP Revision history Table 23. 38/39 Document revision history Date Revision Description of changes Apr-2004 1 First Issue Jun-2004 2 Changed maturity from product preview to final; Changed values in the Table 4: ESD protection Jul-2004 3 Minor changes Jun-2005 4 PowerSSO-36 package insertion Jul-2005 5 Figure 1 modification Sep-2005 6 Features modification; Table 7 modification (ICC; IS + ICC); Figure 10 modification; IQLL modification. 14-Nov-2007 7 Document restructured and reformatted. Added PowerSO-36 packing information and PowerSSO-36 packing information. 05-Nov-2008 8 Updated Table 22: PowerSSO-36 mechanical data. 30-Mar-2009 9 Changed Section : Application on cover page Changed Section 6.1: ECOPACK® 09-Jun-2009 10 Table 22: PowerSSO-36 mechanical data: – Changed A (max) value from 2.50 to 2.45 – Changed A2 (max) value from 2.40 to 2.35 – Changed L (max) value from 0.90 to 0.85 19-Sep-2013 11 Updated Disclaimer. Doc ID 10311 Rev 11 L9950 - L9950XP Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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