L9952GXP
Power management system IC
Features
■
Two 5V low-drop voltage regulators (250mA,
100mA continuous mode
■
Low stand-by current: VBAT stby, 7µA; ,V1 stby,
45µA, (75µA in cycl. sense)
■
Window watchdog and fail-safe output
■
Interrupt output
■
Wake-up logic with cyclic contact monitoring
■
LIN 2.1 compliant (SAEJ2602 compatible)
transceiver
■
24 bit SPI interface for mode control and
diagnostic
Applications
■
■
Output drivers
■
4 High side drivers for e.g. LED or HALL
(RDSon,typ = 7 Ω )
■
1 High side driver Out_HS ( RDSon,typ = 1 Ω )
■
2 Relay drivers ( RDSon,typ = 2 Ω )
■
Outputs are short circuit protected
■
2 Op amp's for current sensing in GND return
lines
■
Temperature warning and thermal shutdown
Table 1.
Po w e r S SO -3 6
Automotive ECU’ s such as door zone and
body control modules.
Description
The L9952GXP is a power management system
IC containing two low drop regulators with
advanced contact monitoring and additional
peripheral functions.
The integrated standard serial peripheral interface
(SPI) controls all L9952GXP operation modes
and provides driver diagnostic functions.
Device summary
Order codes
Package
PowerSSO-36
September 2013
Tube
Tape and reel
L9952GXP
L9952GXPTR
Doc ID 13518 Rev 6
1/68
www.st.com
1
Contents
L9952GXP
Contents
1
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
2.2
2.1.1
Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.2
Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power control in operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.1
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2
Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3
V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.4
VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Wake up events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5
Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6
Hall sensor ports: WU3,4, Dig_Out 3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.7
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.8
Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9
Window – watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.10
Fail safe output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.11
Reset – generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.12
V1, V2 fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.13
Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.14
PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.15
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.16
LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.17
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18
2/68
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.17.1
Dominant TxD time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.17.2
Short to battery time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.17.3
Short to ground mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18.1
Normal wake up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.18.2
Wake up from short to GND condition . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Doc ID 13518 Rev 6
L9952GXP
Contents
2.18.3
3
RxD pin in V1 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.19
LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20.1
Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20.2
Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.20.3
Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.20.4
Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.20.5
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1
Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.1
Over voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.2
Under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.2
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 25
3.3
SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4
High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5
Low side driver outputs Rel1, Rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
6.1
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 30
6.3
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3
Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.4
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.5
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.6
Reset generator (V1 supervision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.7
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 13518 Rev 6
3/68
Contents
L9952GXP
7.8
8
10
4/68
7.8.1
Output (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.8.2
Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.9
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
7.10
Wake up inputs ( WU1..WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.11
Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.12
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.13
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.14
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14.1
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14.2
Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.14.3
Input PWM 2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.14.4
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.14.5
DO, FSO, Dig_Out3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.14.6
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.14.7
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1
9
High side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.1.1
Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.1.2
Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.1.3
Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8.1.4
Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
8.1.5
Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2
PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3
PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Doc ID 13518 Rev 6
L9952GXP
List of tables
List of tables
Table 1.
Table 2.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power-on Reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Reset generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
High side outputs (Out_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
High side outputs (OUT 1..4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wake up inputs(WU1...WU4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Wake up input (INH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LIN receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LIN DC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LIN transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
LIN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
LIN DC values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI (Input CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Inputs: CLK, DI, PWM 1, PWM 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Input PWM2 Vth for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DO, FSO, Digout3,4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Control register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Configuration bit HSxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Configuration bit OUT_HSx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Configuration bit RELx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Configuration bit On_V2x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Configuration bit TRIG, GO_VBAT, GO_V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Configuration bit Wx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Configuration bit Ux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Configuration bit Lx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Configuration bit Txx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Configuration bit INT_enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Configuration bit OLT_HSx, VSLOCK Out, O_HS_REC, LINPU and TXD_TOUT. . . . . . . 59
Doc ID 13518 Rev 6
5/68
List of tables
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
6/68
L9952GXP
Configuration bit LEVx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Configuration bit ICxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Configuration bit LIN slope, LS_ovuv and ICMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Configuration bit HSx_OL, HSx_OC and Relx_OC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Configuration bit SHT5V2, WUx, INH, LIN and Cold Start . . . . . . . . . . . . . . . . . . . . . . . . . 61
Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Configuration bit OV, UV, TW, TSDx and Vx Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Configuration bit STx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Configuration bit Rx, WDx, TRIG, SHT_GND, SHT_BAT and DOM_TXD . . . . . . . . . . . . . 63
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Doc ID 13518 Rev 6
L9952GXP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating modes, main states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
NReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Lin master pull up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area (V1 ON) . . . . . 32
PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON) . . . . . . . . . . . . 32
PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Watchdog, closed and open window tolerances and save trigger area . . . . . . . . . . . . . . . 39
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI - Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
SPI - Edges timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
SPI - CSN low to high transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
SPI - High to low transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
PowerSSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Doc ID 13518 Rev 6
7/68
Pin definitions and functions
1
L9952GXP
Pin definitions and functions
Figure 1.
Block diagram
VBat
Vs
VS
Vs
V2
220nF
CAN
VBat
Temp Prewarning
& Shutdown
Voltage
Regulator 2
Undervoltage Overvoltage Shutdown
CAN
INH
V1
220nF
Wake Up IN
Vs
M
Output Clamp
Voltage
Regulator 1
R
Rel1
Low Side
C
R
Rel2
Low Side
Output Clamp
C
Voltage
Monitor
PWM1
+
PWM2
-
NReset
Window
Watchdog
SPI
-
CSN
CLK
DI
DO
+
Microcontroller
LOGIC
High Side
Dig_Out3
Dig_Out4 /
Interrupt
High Side
TxD
RxD
LINPU
High Side
LIN 2.1 1)
SAEJ2602
High Side
OP2+
OP2OP2out
OUT_HS
µC (ADC)
e. g. Bulb,
LED, Hall
Sensor
Out1
Out2
e. g. LED,
Hall Sensor
Out3
LIN
LIN
1)
For detailed information
see
EMC test report from
IBEE Zwickau
OP1+
OP1OP1out
WU3
ESDLIN1524BJ
WU4
LIN 2.1 certified
High Side
Wake Up IN
WU1
Wake Up IN
WU2
Cyclic Contact
Monitoring
Wake Up IN
FSO
Fail-safe Logic
Out4
Wake Up IN
GND
Table 2.
Pin
name
8/68
Pins definitions and functions
PowerSS0-36
Function
GND
1
Ground
V2
2
Voltage regulator 2 output : 5 V supply for external loads e.g. IR
receiver, potentiometer
V1
3
Voltage regulator 1 output : 5 V supply e.g. micro controller, Can
transceiver
NReset
4
NReset output to micro controller - Internal pull-up of typ. 100KΩ
( reset state = low )
INH
5
Wake-up input e.g. from CAN transceiver
RxD
6
Receiver output of the LIN 2.1 transceiver
Doc ID 13518 Rev 6
L9952GXP
Pin definitions and functions
Table 2.
Pins definitions and functions (continued)
Pin
name
PowerSS0-36
Function
TxD
7
Transmitter input of the LIN 2.1 transceiver
OP2+
8
Non inverting input of operational sense amplifier
OP2-
9
Inverting input of operational sense amplifier
OP2OUT
10
Output of operational sense amplifier
DI
11
SPI : serial data input
DO
12
SPI : serial data output
CLK
13
SPI : serial clock input
CSN
14
SPI : chip select not input
PWM1
15
Pulse width modulation input
PWM2
16
Pulse width modulation input
Dig_Out3
17
Digital output
Dig_Out4/INT
18
Digital output (configurable as Interrupt Output)
Wu4..1
19 to 22
OP1OUT
23
Output of operational sense amplifier
OP1-
24
Inverting input of operational sense amplifier
OP1+
25
Non inverting input of operational sense amplifier
Out4..1
26 to 29
Out_HS
30
High side drivers (1 Ω, typ.) - to supply e.g. LED’ s, Bulbs, HALL
sensors or external contacts
Vs
31
Power supply voltage
LINPU
32
LIN master pull up
LIN
33
LIN bus line
Rel1
34
Low side driver (2 Ω, typ.) - e.g. relay
Rel2
35
Low side driver (2 Ω, typ.) - e.g. relay
FSO
36
Fail safe output - used to supervise or control applications in case of
watchdog and/or V1 under-voltage failure (e.g. to activate
emergency lights)
Wake-up input: input pins for static or cyclic monitoring of external
contacts
High side driver (7 Ω, typ.) - to supply e.g. LED’ s, HALL sensors or
external contacts
Doc ID 13518 Rev 6
9/68
Pin definitions and functions
Figure 2.
L9952GXP
Pins configuration
GND 1
V2 2
V1 3
36 FSO
PowerSSO - 36
31 Vs
RxD 6
30 OUT_HS
TxD 7
OP2+ 8
29 OUT 1
L9952GXP
28 OUT 2
OPOUT2 10
27 OUT 3
DI 11
26 OUT 4
DO 12
CLK 13
CSN 14
25 OP1+
24 OP123 OPOUT1
PWM1 15
22 WU1
PWM2 16
Dig_Out 3 17
21 WU2
TAB = GND
Dig_Out 4/ INT 18
10/68
34 REL1
33 LIN
32 LINPU
NRESET 4
INH 5
OP2 - 9
35 REL2
Doc ID 13518 Rev 6
20 WU3
19 WU4
L9952GXP
Description
2
Description
2.1
Voltage regulator
The L9952GXP contains 2 independent and fully protected low drop voltage regulators,
which are designed for very fast transient response.
The output voltage is stable with loads capacitors > 220nF.
2.1.1
Voltage regulator: V1
The voltage regulator V1 provides 5V supply voltage and up to 250mA continuous load
current for the external digital logic (micro controller, CAN transceiver ...). In addition the
regulator V1 drives the L9952GXP internal 5V loads. The voltage regulator is protected
against overload and over-temperature. An external reverse current protection has to be
provided by the application circuitry to prevent the output capacitor from being discharged
by negative transients or low input voltage. The output voltage precision is better than +/-2%
(incl. temperature drift and line-/load regulation) for operating mode; respectively +/-3%
during low current mode. Current limitation of the regulator ensures fast charge of external
bypass capacitors. The output voltage is stable for ceramic load capacitors > 220nF.
If device Temperature exceeds TSD1 threshold, all outputs (Hsx, Lsx, V2, LIN) will be
deactivated except V1. Hence the micro controller has the possibility for interaction or error
logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 will be deactivated
(see state chart Fig. 3.1: “Protection and diagnosis”). A timer is started and the voltage
regulator is deactivated for tTSD = 1sec. During this time, all other wakeup sources (CAN,
LIN, and WU1...4) are disabled. After 1 sec, the voltage regulator will try to restart
automatically. If TSD2 occurs within one minute and for 8 consecutive times, the L9952GXP
enters the VBAT - standby mode.
In case of short to GND at “V1” after initial turn on (V1 < 2V for at least 4ms) the L9952GXP
enters the VBAT - standby mode. Reactivation (wake-up) of the device can be achieved
with signals from CAN, LIN, WU1..4, SPI.
2.1.2
Voltage regulator: V2
The voltage regulator V2 supplies additional 5V loads (e.g. Logic components, external
sensors, external potentiometers). The continuous load current is 50mA. The regulator
provides accuracy better than + 3% @ 50mA (4% @ 100mA) load current.
In case of short to GND at “V2” after initial turn on (V2 < 2V for at least 4ms) the V2 regulator
is switched off. Micro processor has to send a clear command to reactivate the V2 regulator.
V2 is protected against:
●
Overload
●
Over temperature
●
Short circuit (short to ground and battery supply voltage)
●
Reverse biasing
Doc ID 13518 Rev 6
11/68
Description
2.2
L9952GXP
Power control in operating modes
The L9952GXP can be operated in 4 different operating modes:
●
Active
●
Flash
●
V1- standby
●
VBAT - standby
A cyclic monitoring of wake-up inputs is available in stand-by modes.
2.2.1
Active mode
All functions are available.
2.2.2
Flash mode
To disable the watchdog feature a FLASH program mode is available.
The mode can be entered by VPWM2 ≥ 9V
In this case all other functions are the same as in active mode
Watchdog can be disabled as well as soon as L9952GXP enters the V1 standby mode (see
section 2.9 for details)
Note:
“High” level for flash mode selection is VPWM2 ≥ 9V. For all other operation modes, standard
5V logic signals are required. For proper operation PWM1 must not be set to a voltage level
above standard 5V logic.
2.2.3
V1 standby mode
Outputs and internal loads are switched off. To supply the micro controller in a low power
mode, the voltage regulator1 (V1) remains active. The intention of the V1 standby mode is
to preserve the RAM contents. A cyclic contact supply and wake-up input sense feature (for
cyclic monitoring of external contacts) can be activated by SPI.
2.2.4
VBAT standby mode
To achieve minimum current consumption during VBAT standby mode, all L9952GXP
functions (except the ones for wake up functionality) are switched off.
In VBAT - standby mode the current consumption of the L9952GXP is reduced to 7µA, typical
(without cyclic sense feature selected).
The transitions from active mode to either V1-standby or VBAT - standby are controlled by
SPI.
VBAT - standby mode is dominant; i.e. if both bits, V1 - standby and VBAT - standby are set to
“1”, the L9952GXP will enter VBAT - standby mode.
12/68
Doc ID 13518 Rev 6
L9952GXP
2.3
Description
Wake up events
A wake-up from standby mode will switch the device to active mode. This can be initiated by
one or more of the following sources:
●
Change of the LIN state at LIN bus interfaces
●
A current at the INH pin (I ≥200uA) controlled by the CAN-transceiver (the CAN
transceiver is not a part of the IC).
●
Positive/negative edge at wake up pins WU1...WU4 -> change of level after going into
stand-by
●
Change of open-load state at OUT1 to 4
●
SPI access in V1-standby mode (CSN is low and first rising edge on CLK)
Table 3.
Wake up events
Wake up source
Description
LIN
Always active
INH
Always active
WU1...4
Can be individually disabled via SPI
Open Load at HS outputs
Can be individually disabled via SPI
SPI Access
High level at PWM2 input
Always active
(except in VBAT - standby mode)
VPWM2 > 9V (1)
1. Only if internal oscillator is running (e. g. in cyclic sense configuration or after wake-up request).
All wake-up events (except wake-up by LIN, INH or SPI from V1standby mode) generate a
Reset pulse (NReset low for 2ms).
Wake-up events from V1standby by LIN, INH or SPI do not cause a Reset and the Reset
generation is blocked for 2ms, i. e. a watchdog failure during this timeframe will not cause a
reset.
Doc ID 13518 Rev 6
13/68
Description
2.4
L9952GXP
Functional overview (truth table)
Table 4.
Functional overview (truth table)
Operating modes
Function
2.3.1
Voltage-regulator, V1
2.3.2
Voltage-regulator, V2
2.3.3
Reset-generator
Active mode
V1-standby
static mode
(cyclic sense)
On
On (1)
Comments
VOUT= 5V
VOUT= 5V
On / Off
(2)
On
(2)
/ Off
VBAT-standby
static mode
(cyclic sense)
Off
On
(2)
/ Off
On
On
Off
On
Off if
(I_V1 < ICMP
and ICMP=0)
or ICMP = 1
Off
Off (3)
Active (4)
Active (4)
On / Off
On (2) / Off
On (2) / Off
V1 monitor
2.3.4
Window watchdog
2.3.5
Wake up
2.3.6
HS-cyclic supply
2.3.7
Relay driver
On
Off
Off
2.3.8
Operational amplifiers
On
Off
Off
2.3.9
LIN line driver
On
Off
Off
2.3.10
LIN line receiver
On
On
On
2.3.11
FSO
Hi – no error
Lo – WD or V1
fail
Hi – no error
Lo – WD or V1
fail (5)
Lo -> because
V1= off
2.3.12
Oscillator
On
(6)
(6)
2.3.13
Vs-Monitor
On
(7)
(7)
Oscillator
timebase
LIN 2.1
Fail-safe
output
1. Supply the processor in low current mode
2. Only active when selected via SPI
3. Input Status can be read by SPI (Status Register 0); Inputs should be configured for static sense (Control
Register 2)
4. Unless disabled by SPI
5. Watchdog is active in V1 standby mode, until I(V1) is below ICMP current threshold
6. Activation = ON if cyclic sense is selected
7. Cyclic activation = pulsed ON during cyclic sense
14/68
Doc ID 13518 Rev 6
L9952GXP
Description
Figure 3.
Operating modes, main states
Vs > Vpor
Vbat startup
All registers
cleared to ‚0',
Cold start bit (D19, SR0)
set to ‚1'
Vpwm2>9V
Flash Mode
Watchdog: OFF
Vpwm2 short to GND
Or
15 x WD Failure
Vpwm2>9V
Note 1
V1: on
Reset Generator: active
Watchdog: active
Fail Safe Out: active
Wake-up
Event
Wake-up
Event
Vpwm2>9V
Note 1
V1 Standby
Mode
Vbat Standby
Mode
V1: off
V2: according to SPI settings
Reset Generator: off (Nreset=low)
Watchdog: off
Fail Safe Out: low
HSD, LSD: Off
SPI command: ‚Go Vcc’
(D21 CR0)
Thermal Shutdown TSD2
OR IV1 > 1mA AND ICMP = 0 AND 15 x WD fail
V1: on
Reset Generator: active
Watchdog:
OFF (if Iv1 1V and Vin < (Vs –
2V), a Wake-up request is processed. During Wake-up request, the internal oscillator and
other circuit blocks are activated in order to allow more accurate monitoring of the inputs.
In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a
cyclic wake up feature is implemented. This feature allows periodical activation of the wakeup inputs to read the status of the external contacts. The periodical activation can be linked
to Timer 1 (0.5sec to 4.0sec in 0.5sec steps) or Timer 2 (50ms). The input signal is filtered
with a filter time of 16us after a programmable delay (80us or 800us). A Wake-up will be
processed if the status has changed versus the previous cycle.
The Outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the
timing according to the cyclic monitoring of the wake-up inputs.
If the wake-up inputs are configured for cyclic sense mode (Icxx in control register 2), the
same input filter timing (Timer1 or Timer2) and the corresponding input filter delay (control
register 2) must be used for the HS Outputs (Hsxx in control register 0) which supply the
external contact switches.
In Standby mode, the inputs WU1-4 are SPI configurable for pull-up or pull-down current
source configuration according to the setup of the external contacts (pull-up for active low
contacts, pull-down for active high contacts). In active mode the inputs have a pull down
resistor of 100 kOhm (typ).
In Active mode, the input status can be read by SPI (Status Register 0). Static sense should
be configured (Control Register 2) before the read operation is started (In cyclic sense
configuration, the input status is updated according to the cyclic sense timing; Therefore,
reading the input status in this mode may not reflect the actual status).
2.6
Hall sensor ports: WU3,4, Dig_Out 3,4
Applications like Hall sensor outputs need high processing speed. The 12V signals
connected to the wakeup inputs WU3 and WU4 can be looped through to the digital outputs
Dig_Out 3 and Dig_Out 4 (5V) in order to avoid read out of the input state by SPI.
The setup is programmable by SPI.
The open load states of the High Side Drivers OUT1 and OUT2 can be looped through the
digital outputs Dig_Out3 and Dig_Out4 without delay. In addition, the status of OUT1 and
OUT2 can be accessed through the SPI interface. This feature is intended for 2-pin HALL
sensors. Open Load information is only valid during ON state.
The Open Load threshold at pins OUT1...4 can be switched from IOLD1 = 2mA to
IOLD2 = 8 mA via SPI .
16/68
Doc ID 13518 Rev 6
L9952GXP
2.7
Description
Interrupt
Dig_Out4 can be configured via SPI as Interrupt output (INT) by setting Bit 20 /
CR1:INT_enable=’1’.
This configuration will enable the following behaviour:
2.8
●
INT pin is pulled high for 2ms in case of any wake-up from V1 standby mode (WU
inputs, LIN, INH, SPI, open load HS, Iv1 > ICMP_ris)
●
Wake-up events from V1 standby do not generate a reset (i.e. NRESET is not pulled
low)
●
The Dig_Out4 settings in CR1 (Bits 12..14) will be ignored
Cyclic contact supply
In V1 and VBAT - standby mode, any high side driver output (OUT1..4, OUTHS) can be used
to periodically supply external contacts.
The timing is selectable by SPI
Timer 1: period is X sec, the on-time is 10ms resp. 20ms
With X ∈ {0.5, 1.0, 1.5, ... 4 }
Timer 2: period is 50ms, the on- time is 100us resp. 1ms:
Note:
Cyclic sense setup: if cyclic sense feature is used for wake-up inputs (Icxx in control register
2), same input filter timing (Timer1 or Timer2) must be used for HS Outputs (Hsxx in control
register 0).
2.9
Window – watchdog
During normal operation the watchdog monitors the micro controller within a nominal trigger
cycle of 10ms.
In VBAT -standby , V1-standby and Flash program modes, the watchdog circuit is
automatically disabled. However, the watchdog will remain enabled in V1-standby mode
until the current at V1 decreases below ICMP_fall. The V1 current monitoring can be
disabled, if the ICMP bit (CR2, D20) is set to '1'.
After ‘power-on’, ‘standby mode’ or reset, the window watchdog starts with a long open
window (65ms). The long open window allows the micro controller to run its own setup and
then to trigger the watchdog via the SPI. The trigger is finally accepted when the CSN input
becomes HIGH after the transmission of the SPI word.
A correct watchdog trigger will start the window watchdog with a closed window (< 6ms)
followed by an open window (< 10ms), see timing diagrams. Subsequently, the micro
controller has to serve the watchdog by alternating the watchdog trigger bit (CR0, D19). The
“negative” or “positive” edge has to meet the open window time. A correct watchdog trigger
signal will immediately start the next closed window.
After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. In case of
7 further watchdog failures, the V1 regulator is completely turned off and the device goes
into VBAT -standby mode until a wakeup occurs. (e.g. via LIN, CAN/INH).
Doc ID 13518 Rev 6
17/68
Description
L9952GXP
The watchdog is triggered by toggling the trigger bit (CR0, D19).
Note:
The active trigger window will be reset after each correct trigger write operation.
In case of reset (NReset low for 2ms) the trigger bit is set to “0”.
In case of a WD failure, the outputs (Lsx, Hsx, V2) are switched off and NReset is pulled low
for 2ms.
Writing to control register 0 without inverting the WD trigger bit is possible at any time.
Figure 4.
Watchdog
Watchdog Failure
Wake up event
Vbatstdby
Mode
8+7
WD Failures
V1 off
for 200 ms
t=200ms
8x WD Failure
Watchdog active
With
Normal window
(10ms)
HSD, LSD : according to
CR0
Reset
(Nreset =low for 2ms)
LSD: Off (control bits set to ‚0')
HSD: Off (control bits remain
unchanged)
Watchdog Failure (‚long
open window’ passed
without TRIG=1
Set WD Trigger Bit = ‚1' or
toggle trigger bit if wake-up
from V1standby
2ms
Wake-up event
or exit Flash Mode
Power-on
Reset
Watchdog active
with
‚long open window’
(65ms nom)
HS and LS outputs are
off
Go to standby mode or
Flash Mode (PWM2>9V)
INH, LIN, SPI
I(V1)>1mA and ICMP=0
Watchdog
Inactive
(standby modes,
Flash Mode)
18/68
Toggle WD Trigger Bit
Within nominal window
Doc ID 13518 Rev 6
Go to standby mode
or Flash Mode (PWM2>9V)
Set
WD Trigger Bit = ‚0' or write
non-inverting value to trigger
bit after wake-up from
V1standby mode
L9952GXP
2.10
Description
Fail safe output
After power-on (Vs > VPOR) or wakeup from VBAT -standby mode, the output FSO is set to
“HIGH”, if V1 is above the V1 threshold. FSO is set to “LOW” in case of V1 under voltage or
watchdog failure.
During V1-standby mode, FSO is HIGH unless a V1 under-voltage or watchdog reset
occurs. WD remains enabled in V1 standby mode until IV1 drops below 150uA. In VBAT standby mode, FSO is low. At exit from VBAT - standby mode, it goes to high as soon as V1
is stable.
At wakeup FSO remains high, provided that the watchdog is triggered successfully. It is set
low if the watchdog is not served during the long open window of if a V1 under-voltage
occurs.
Figure 5.
FSO
V1 undervoltage
Watchdog Failure
TSD2
Vbatstdby Mode
FSO = 0
2.11
Reset – generator
IF V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is switched to “HIGH” after a 2ms reset delay time. This is necessary for a
defined start of the micro controller when the application is switched on.
As soon as an under voltage condition of the output voltage (V1 < VRT) for more than 8us
appears, the reset output is switched low again.
Figure 6.
NReset
Wake-up Event 1)
V1 Undervoltage
Vpwm2 < 9V
(Exit Flash Mode)
Watchdog
Failure
NReset = 0
1) Only if
(INT_en = 0) and (wake-up by WU-input or High Side Open Load)
Doc ID 13518 Rev 6
19/68
Description
2.12
L9952GXP
V1, V2 fail
The V1, and V2 regulator output voltages are monitored.
In case of a drop below the V1, V2 – fail thresholds (V1,2 < 2V,typ for t > 2us), the V1,2 - fail
bits are latched. The fail bits are cleared by a dedicated SPI command.
If 4ms after turn on of the regulator the V1,2 voltage is below the V1,2 fail thresholds,
(independent for V1,2 ), the L9952GXP will identify a short circuit condition at the related
regulator output and the regulator will be switched off.
In case of a V1 failure the device enters VBAT - standby mode automatically.
In case of a V2 failure the SHT5V2 bit (SR0 Bit12) is set.
2.13
Low side driver outputs Rel1, Rel2
The outputs Rel1, Rel2 (RDSon = 2 Ω typ. @25 °C) are specially designed to drive relay
loads.
Typical relays used have the following characteristics:
Relay type 1:
–
closed armature: R = 160 Ω +10%, L= 300mH
–
open armature: R = 160 Ω +10%, L= 240mH
Relay type 2:
–
closed armature: R= 220 Ω +10%, L= 420mH
–
open armature: R= 220 Ω +10%, L= 330mH
The outputs provide an active output zener clamping (40V) feature for the demagnetisation
of the relay coil, even though a load dump condition exists. In case of watchdog failure the
relay drivers will be switched off and the low side driver control bits are cleared.
Note:
2.14
1
Due to relays bouncing, high dV/dt and/or dI/dt transients may occur on the low side driver
outputs. In case high currents are switched (for example window lift motor), due to parasitic
capacitive inductive coupling from load side of relays to the relays coils, the Absolute
Maximum Ratings of the Low Side driver outputs may be exceeded. In order to avoid this, it
is recommended to place a 10nF capacitor at the Rel1, Rel2 outputs to GND.
2
If a hard short circuit to VBAT is possible at the "Low Side Driver" outputs, an RC network is
required with TRC > 1µs, R ≥ 1 Ω (see block diagram, the value is given for an output short
circuit of given di/dt = 5A/µs).
PWM inputs
The inputs PWM 1,2 can be used to control the output drivers Out1..4 and OUT_HS with a
PWM signal. Each PWM input can be mapped individually to each of the above listed
outputs according to the SPI settings.
20/68
Doc ID 13518 Rev 6
L9952GXP
2.15
Description
Operational amplifiers
The operational amplifiers are especially designed to be used for sensing and amplifying the
voltage drop across ground connected shunt resistors. Therefore the input common mode
range includes - 0.2 ... 3V.
The operational amplifiers are designed for GND + 3V... GND – 0.2V input voltage swing
and rail-to-rail output voltage range. All Pins (positive, negative and outputs ) are available
to be able to operate in non-inverting and inverting mode. Both operational amplifiers are
on-chip compensated for stability over the whole operating range within the defined load
impedance.
Figure 7.
Lin master pull up
Vs
LIN
c on t r ol
TS W
con t r ol
LIN PU
30k
LIN
1k
M a s t e r n od e
p u ll u p
Gn d
A dedicated built-in switch “Tsw” enables the LIN to act as a master. (see chapter 2.18)
2.16
LIN bus interface
General requirements:
●
Speed communication up to 20kbit/s
●
LIN 2.0 compliant (SAEJ2602 compatible) transceiver
●
Function range from +40V to -18V DC at LIN Pin
●
GND disconnection fail safe at module level
●
Off mode: does not disturb network
●
GND shift operation at system level
●
Microcontroller Interface with CMOS compatible I/O pins.
●
Pull up resistor internal.
●
ESD: immunity against automotive transients per ISO7637 specification (see
application note)
●
Matched output slopes and propagation delay
In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
Doc ID 13518 Rev 6
21/68
Description
2.17
L9952GXP
Error handling
The L9952GXP provides the following 3 error handling features which are not described in
the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers / micro
controllers to switch the application back to normal operation mode.
2.17.1
Dominant TxD time out
If TXI is in dominant state (low) for more than 12ms (typ) the transmitter will be disabled until
TXI becomes recessive (high). This feature can be disabled via SPI.
2.17.2
Short to battery time out
If TXI changes to dominant (low) state but RXI signal does not follow within 40µs, the
transmitter will be disabled until TXI becomes recessive (high).
2.17.3
Short to ground mode
A wake up caused by a message on the bus will start the voltage regulator and the micro
controller to switch the application back to normal operation mode.
2.18
Wake up (from LIN)
In standby mode the L9952GXP can receive a wake up from LIN bus. For the wake up
feature the L9952GXP logic differentiates two different conditions.
2.18.1
Normal wake up
Normal wake up can occur when the LIN transceiver was set in standby mode while LIN
was in recessive (high) state. A dominant level at LIN for at least 40µs, will switch the
L9952GXP to active mode.
2.18.2
Wake up from short to GND condition
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for at least 40us, will switch the L9952GXP to active mode.
2.18.3
RxD pin in V1 standby
In V1 standby condition the RxD is a tristate pin.
22/68
Doc ID 13518 Rev 6
L9952GXP
2.19
Description
LINPU
The LINPU (LIN pull up) signal is set by L9952GXP logic in order to drive the LIN
transceiver in master mode. The master mode is realized by an internal high side switch and
an external diode in series with an external 1k resistor. In master mode the high side switch
is closed causing an external pull up path in parallel to the internal one (diode & 30k
resistor).
HS (high side) characteristics:
●
HS does not have an over current protection.
●
The HS remains active in standby mode.
●
Switch off only in case of over temperature (TSD2 = thermal shutdown #2).
●
Typical RDSon, 10 Ω.
The Linpu is activated by default (LIN master mode) and can be switched off with a SPI
command (see register 2) to reduce current in case of LIN shorted to ground.
2.20
Serial Peripheral Interface (SPI)
A 24 bit SPI command (2 adresses + 22 data bits) is used for bi-directional communication
with the micro controller.
During active mode, the SPI:
1) triggers the watchdog
2) controls the modes and status of all L9952GXP modules (incl. input and output drivers)
3) provides driver output diagnostic
4) provide L9952 diagnostic (incl. over temperature warning, L9952GXP operation status)
Note:
During stand-by modes, the SPI is generally deactivated.
The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL=0 and CPHA=0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to micro controller with a build-in SPI. Only three CMOScompatible output pins and one input pin will be needed to communicate with the device. A
fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the
global error flag (fault condition) of the device which is a logical -”OR” of all over current, Vsover / under voltage, temperature warning/shutdown and V1 Fail bits. The micro controller
can poll the status of the device without the need of a full SPI-communication cycle.
2.20.1
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) will be in high impedance state. A low signal activates the output driver and
a serial communication can be started. The state during CSN = 0 is called a communication
frame.
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23/68
Description
2.20.2
L9952GXP
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI will be
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register will be transferred to
Data Input Register. The writing to the selected Data Input Register is only enabled if exactly
24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame will be ignored. This safety
function is implemented to avoid an activation of the output stages by a wrong
communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
2.20.3
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go from
high impedance to a low or high level depending on the global error flag (fault condition).
The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer
the content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK will shift the next bit out.
2.20.4
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the
falling edge of the CLK signal. The SPI can be driven with a CLK frequency up to 1MHz.
2.20.5
Data registers
The device has 3 Control registers and 2 Status registers. The first two bits (D22+D23) at
the DI-Input are used to select one of the Control registers. All bits are first shifted into an
input shift register. After the rising edge of CSN the contents of the input shift register will be
written to the selected Control register only if a frame of exact 24 bits is detected. If the
Control register 1 is selected for data transfer, the Status register 1 will be transferred to the
DO during the current communication frame. For the selection of Control register 0 or
Control register 2, the Status register 0 is transferred to DO.
24/68
Doc ID 13518 Rev 6
L9952GXP
Protection and diagnosis
3
Protection and diagnosis
3.1
Power supply fail
Over and under-voltage detection on Vs.
3.1.1
Over voltage
If the supply voltage Vs reaches the over voltage threshold (VSOV)
3.1.2
●
The outputs HS1..4, OUT_HS, Rel1,2, and LIN are switched to high impedance state
(load protection)
●
The over voltage bit is set and can be cleared with the clear bit (CR1,CLR)
●
Automatic recovery after Vs over-voltage; selectable via SPI (CR2, bit4)
Under voltage
If the supply voltage Vs drops below the under voltage threshold voltage(VSUV)
3.2
●
The outputs HS1..4, OUTHS, Rel1,2, and LIN are switched to high impedance state
(load protection)
●
The under voltage bit is set
●
Automatic recovery after Vs under-voltage; selectable via SPI (CR2, bit4)
Temperature warning and thermal shutdown
See state chart: “ Protection and diagnosis”.
3.3
SPI diagnosis
Digital diagnosis features are provided by SPI:
●
V1 reset threshold programmable
●
Over temperature including pre warning
●
Open load separately for each output stage
●
Overload status
●
Vs-supply over/under voltage
●
V1 and V2 fail bit
●
Status of the WU1...4, LIN and INH pin
●
Cold start bit
●
Number of unsuccessful V1 restarts after thermal shutdown
●
Number of sequential watchdog failures
●
Status of watchdog trigger bit TRIG: (SR1, Bit 16)
●
LIN status (short to ground, short to VBAT, dominant TxD)
See the following state chart: “Protection and diagnosis”.
Doc ID 13518 Rev 6
25/68
Protection and diagnosis
Figure 8.
L9952GXP
Protection and diagnosis
Tj > 155°C
TSD2
TSD1
All outputs: off
V1: off for 1 sec
‚TSD2-bit is set (D4 SR1)
T > 1sec
All outputs except V 1: off
‚TSD 1'-Bit is set(D3 SR1)
8x TSD2
(each TSD2
within 1 min)
Tj > 140°C
SPI command: ‚CLR’
(D21 CR1)
OR
Power-on reset
Temperature
Warning
Vbatstdby
‚Temperature Warning'Bit set
(D2 SR1)
All outputs incl V 2: off
SPI command: ‚CLR’
(D21 CR1)
OR
Power-on reset
Wake-up event
Power-on reset
Tj > 130°C
A ctive
Mode
Standby Modes
(during cyclic sense )
Vs Undervoltage
Vs Overvoltage
SPI command: ‚CLR’
(D21 CR1)
OR
Autorestart activated
(D4 CR2)
SPI command: ‚CLR’
(D21 CR1)
OR
Autorestart activated
(D4 CR2)
Vs Lockout
Vs Lockout
All outputs: high Impedance
OV Bit set (D0 SR1)
Auto-restart if selected by SPI
8 successive watchdog
failures
26/68
Doc ID 13518 Rev 6
All outputs: off
UV bit set (D1 SR1)
Auto-restart if selected by SPI
V1 off for
200ms
7 additional watchdog failures
in sequence
Vbatstdby
mode
L9952GXP
3.4
Protection and diagnosis
High side driver outputs
The component provides a total of 4 high side outputs Out1...4, (7 Ω typ. @ 25C) to drive
e.g. LED' s or hall sensors and 1 high side output OUT_HS with 1 Ω typ. @ 25 C).
The high side outputs are protected against
●
Over- and under voltage
●
Overload (short circuit)
●
Over temperature with pre warning
If the output current exceeds the current shutdown threshold the output transistor is turned
off and the corresponding diagnosis bit of the output is set.
The switches are automatically disabled in case of reset condition, Vs-under, Vs-over
voltage or thermal shutdown (TSD1&2).
For OUT_HS an auto recovery feature is available in active mode.
If the OUT_HS output current exceeds the current shutdown threshold, the output transistor
is turned off and the corresponding diagnosis bit of the output is set.
Via SPI command the auto recovery feature can be enabled in order to restart the driver in
case of over current shutdown. This over current recovery feature is intended for loads
which have an initial current higher than the over current limit of the output (e.g. Inrush
current of cold light bulbs).
The device itself can not distinguish between a real overload and a non linear load like a
light bulb. A real overload condition can only be qualified by time. As an example, the micro
controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.
After clearing the recovery bit, the output will be automatically disabled if the overload
condition still exists.
The status of all high side outputs (over-current, open load) can be monitored by SPI
interface.
In case of a watchdog failure, the high side drivers are switched off. The control bits are not
cleared, i.e. the drivers will go to the previous state once the watchdog failure condition
disappears.
ESD structures are configured for nominal currents only. If external loads are connected to
different grounds, the current load must be limited to this nominal current.
Note:
Loss of ground or ground shift with externally grounded loads.
3.5
Low side driver outputs Rel1, Rel2
The outputs provide an active output zener clamping feature for the demagnetisation of the
relay coil, even though a load dump condition exists. For safety reasons the relay drivers
are linked with the Watchdog: in case of failure, or missing trigger signal the relay drivers will
switch off.
Doc ID 13518 Rev 6
27/68
Absolute maximum ratings
4
Absolute maximum ratings
Table 5.
Absolute maximum ratings
Symbol
VS
Value
Unit
DC supply voltage / “jump start”
-0.3 to +28
V
Single pulse / tmax < 400 ms
“transient load dump”
-0.3 to +40
V
-0.3 to +5.25
V
-0.3 to +28
V
-0.3 to V1+0.3
V
Stabilized supply voltage, logic
supply
V2
Stabilized supply voltage
VDI VCLK
VTXD VCSN
VDO VRXD
VNRESET VFSO
VDIGOUT3,4
Logic input / output voltage range
VINH
VPWM1, VPWM2,
VREL1, VREL2,
Wake up input voltage range
PWM input voltage range
Low side output voltage range
-0.3 to +40
V
VOUT1..4,, VOUTH
High side output voltage range
-0.3 to VS + 0.3
V
VWU1...4,
Wake up input voltage range
-0.3 to VS + 0.3
V
VOP1+,VOP1-,
VOP2+, VOP2-,
Opamp1 input voltage range
Opamp2 input voltage range
-0.3 to V1 + 0.3
V
VOPOUT1,
VOPOUT2
Analog Output voltage range
-0.3 to VS + 0.3
V
-20 to +40
V
5
mA
IInput
28/68
Parameter
V1
VLIN, VLINPU
Note:
L9952GXP
LIN bus I/O voltage range
Current injection into Vs related
input pins
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit !
Doc ID 13518 Rev 6
L9952GXP
5
ESD protection
ESD protection
Table 6.
ESD protection
Parameter
Value
Unit
All pins, except LIN(1)
+/- 2
kV
All output
pins(2)
+/- 4
kV
LIN(3)
+/- 1.5
kV
LIN(4)
+/- 8
kV
All pins (charge device model)
+/- 500
V
Corner pins (charge device model)
+/- 750
V
+/- 200
V
All
pins(5)
1. HBM (human body model, 100pF, 1.5 kΩ ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A
2. HBM with all none zapped pins grounded
3. Without external components
4. Acc. DIN EN61000-4-2 (330Ω, 150pF), with external components:
- Diode, type ESDLIN1524BJ
- SMD Ferrite bead, type TDKMMZ2012Y202B
- Capacitor C=220pF
For detailed information please see EMC report from IBEE Zwickau (available on request)
5. Acc. Machine Model: C=220pF; L=0.75µH; R=10Ω
Doc ID 13518 Rev 6
29/68
Thermal data
L9952GXP
6
Thermal data
6.1
Operating junction temperature
Table 7.
6.2
Operating junction temperature
Item
Symbol
6.1.1
Tj
6.1.2
RthjA
Parameter
Operating junction temperature
Thermal resistance junction- ambient
Unit
- 40 to 150
°C
See Figure 10.
°C/W
Temperature warning and thermal shutdown
Table 8.
Temperature warning and thermal shutdown
Item
Symbol
6.2.1
TW ON
6.2.2
TSD1 OFF
6.2.3
TSD2OFF
6.2.4
TSD2 ON
6.2.5
TSD12hys
Parameter
Min.
Typ. Max. Unit
Thermal over temperature
warning threshold
Tj (1)
120
130
140
°C
Thermal shutdown
junction temperature 1
Tj (1)
130
140
150
°C
Tj (1)
140
155
170
°C
Thermal shutdown
junction temperature 2
1. Non-overlapping
30/68
Value
Doc ID 13518 Rev 6
Hysteresis
5
°C
L9952GXP
6.3
Thermal data
Package and PCB thermal data
Figure 9.
Note:
PowerSSO-36 PC board
Layout condition of Rth and Zth measurements ( board finish thickness 1.6 mm +/- 10%
board double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070mm
(front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08
mm, Cu thickness on vias 0.025 mm ).
Doc ID 13518 Rev 6
31/68
Thermal data
L9952GXP
Figure 10. PowerSSO-36 thermal resistance junction ambient Vs. PCB copper area
(V1 ON)
RTHj _amb( ° C/ W)
110
90
70
50
30
0
2
4
6
8
10
PCB Cu heat sink area ( cm^ 2)
Figure 11. PowerSSO-36 thermal impedance junction ambient single pulse (V1 ON)
ZTH (° C/ W)
1000
Footprint
100
2 cm2
8 cm2
10
1
0,1
0,01
0,1
1
10
Time ( s)
32/68
Doc ID 13518 Rev 6
100
1000
L9952GXP
Thermal data
Equation 1: pulse calculation formula
Z
THδ
= R
TH
⋅δ+Z
THtp
(1 – δ)
where δ = tP/T
Figure 12. PowerSSO-36 thermal fitting model (V1 ON)
Table 9.
Thermal parameters
Area/island (cm2)
Footprint
R1 (°C/W)
5
R2 (°C/W)
2
8
18
10
10
R3 (°C/W)
29
22
7,8
R4 (°C/W)
51
29
21
C1 (W.s/°C)
0,0003
C2 (W.s/°C)
0,35
1
1
C3 (W.s/°C)
1,5
1,3
1,3
C4 (W.s/°C)
5
15
15
Doc ID 13518 Rev 6
33/68
Electrical characteristics
L9952GXP
7
Electrical characteristics
7.1
Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 18V; 4.8V < V1 < 5.2V; all outputs open; Tj = -40°C...130°C,
unless otherwise specified.
Table 10.
Item
Symbol
7.1.1
VS
7.1.2
VSUV
VS UV-threshold voltage
7.1.3
Vhyst_UV
Undervoltage hysteresis
7.1.4
VSOV
VS OV-threshold voltage
VS increasing /
decreasing
18
7.1.5
Vhyst_OV
Overvoltage hysteresis
Hysteresis
0.5
IV(act)
Current concumption in
active mode
Vs=12V, TxD LIN
high, V2 on,
Outputs off
Iv1=Iv2=0A
IV(BAT)
Current consumption in
VBAT - standby mode
VS=12V, both
voltage regulators
deactivated, no
wake-up request
IV(BAT)CS
Current consumption in
VBAT - standby mode
Current consumption in
V1-standby mode
7.1.6
7.1.7
7.1.8
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Supply and supply monitoring
Parameter
Test condition
Min.
Typ.
Max.
Unit
6
13.5
18
V
5.81
V
0.15
V
22
V
1
1.5
V
2.7
20
mA
1
7
10
µA
VS=12V, both
voltage regulators
deactivated, (cyclic
sense)
40
75
100
µA
V1=5V, VS=12V,
Voltage regulator
V1 active, without
cyclic sense, no
wake-up request
10
45
70
µA
Supply voltage range
VS increasing /
decreasing
5.11
0.04
0.1
7.1.9
IV(V1)
7.1.10
IV(BATWU)
Current consumption in
VBAT-standby mode with a 1.5V
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