L9953

L9953 L9953XP Door actuator driver Features ■ One full bridge for 6A load (Ron=150mΩ) ■ Three half bridges for 1.5A load (Ron=800mΩ) ■ One highside driver for 6A load (Ron=100mΩ) ■ Two highside drivers for 1.5A load (Ron=800mΩ) ■ Programmable softstart function to drive loads with higher inrush currents (i.e. current >6A, >1.5A) ■ Very low current consumption in stand-by mode (IS < 6µA typ; Tj ≤ 85 °C) Applications ■ All outputs short circuit protected ■ ■ Current monitor output for highside OUT1, OUT4, OUT5 and OUT8 ■ All outputs over temperature protected ■ Open load diagnostic for all outputs ■ Overload diagnostic for all outputs ■ Separated half bridges for door lock motor ■ PWM control of all outputs ■ Charge pump output for reverse polarity protection Table 1. PowerSO-36 PowerSSO-36 Door actuator driver with bridges for door lock , mirror axis control, mirror fold and highside driver for mirror defroster and two 10W-light bulbs. Description The L9953 and L9953XP are microcontroller driven multifunctional door actuator driver for automotive applications. Up to three DC motors and three grounded resistive loads can be driven with five half bridges and three highside drivers. The integrated standard serial peripheral interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic informations are available via SPI. Device summary Order codes Package Tube Tape and reel PowerSO-36 L9953 L9953TR PowerSSO-36 L9953XP L9953XPTR September 2013 Doc ID 14278 Rev 4 1/38 www.st.com 1 Contents L9953 / L9953XP Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 2/38 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20 3.8 Open load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 Over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 Programmable softstart function to drive loads with higher inrush current 21 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 Serial clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.6 Input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Doc ID 14278 Rev 4 L9953 / L9953XP Contents 4.8 Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.9 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.10 SPI - input data and Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 6.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 PowerSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 PowerSSO-36™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.4 PowerSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.5 PowerSSO-36™ packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 14278 Rev 4 3/38 List of tables L9953 / L9953XP List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/38 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 OUT1 - OUT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI - input data and Status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Doc ID 14278 Rev 4 L9953 / L9953XP List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - driver turn-on/off timing, minimum CSN hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 22 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSO-36™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSO-36™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PowerSSO-36™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PowerSSO-36™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 14278 Rev 4 5/38 Block diagram and pin description 1 L9953 / L9953XP Block diagram and pin description Figure 1. Block diagram V B AT R ev e rs e P olarity P rotec tion * N o te : V a lu e o f ca p a cito r h a s to b e ch o o s e n ca re fu lly to lim it th e V S vo lta g e b e lo w a b s o lu te m a xim u m ra tin g s in ca se o f a n u n e xp e cte d fre e w h e e lin g co n d itio n (e .g . TS D , P O R ) 100k * VS 10k 100µ F OU T1 C h a rg e P ump VCC M irro r C o m m o n OU T2 1k 1k 1k 1k Driver Interface & Diagnostic DI DO C LK CSN Interface ** ** ** ** SPI VCC PW M1 ** 1k OU T4 OU T5 MU X M M irro r H o riz o n ta l M L o c k / F o ld e r OUT6 OUT7 OUT8 PW M2 / CM M irro r V e rtic a l OU T3 µC **1k M D e fro s te r 4 GN D ** N o te : R e sisto rs b e tw e e n µ C a n d L 9 9 5 3 a re re co m m e n d e d to lim it c u rre n ts fo r n e g a tive vo lta g e tra n si e n ts a t V B A T (e .g . IS O typ e 1 p u lse ) Table 2. Pin definitions and functions Pin 1, 18, 19, 36 2, 35 3 4 5 6/38 Symbol Function GND Ground: Reference potential Important: for the capability of driving the full current at the outputs all pins of GND must be externally connected. OUT8 Highside driver output 8 The output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The highside driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and open load protected. Important: for the capability of driving the full current at the outputs both pins of OUT8 must be externally connected. OUT1 OUT2 OUT3 Half-bridge-output 1,2,3 The output is built by a highside and a lowside switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: highside driver from output to VS, lowside driver from GND to output). This output is over-current and open load protected. Doc ID 14278 Rev 4 L9953 / L9953XP Block diagram and pin description Table 2. Pin definitions and functions (continued) Pin 6, 7, 14, 15, 23, 25, 28, 32 8 9 Symbol Function VS Power supply voltage (external reverse protection required) For this input a ceramic capacitor as close as possible to GND is recommended. Important: for the capability of driving the full current at the outputs all pins of VS must be externally connected. DI Serial data input The input requires CMOS logic levels and receives serial data from the microcontroller. The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred first. Current monitor output/PWM2 input Depending on the selected multiplexer bits of Input Data Register this CM/PWM2 output sources an image of the instant current through the corresponding highside driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the output OUT7. CSN Chip select not input / test mode This input is low active and requires CMOS logic levels. The serial data transfer between L9953 and micro controller is enabled by pulling the input CSN to low level. If an input voltage of more than 7.5V is applied to CSN pin the L9953 will be switched into a test mode. 11 DO Serial data output The diagnosis data is available via the SPI and this tristate-output. The output will remain in tristate, if the chip is not selected by the input CSN (CSN = high) 12 VCC Logic supply voltage For this input a ceramic capacitor as close as possible to GND is recommended. 13 CLK Serial clock input This input controls the internal shift register of the SPI and requires CMOS logic levels. 16,17, 20,21, OUT4 OUT5 Half-bridge-output 4,5: see OUT1 (pin 3). Important: for the capability of driving the full current at the outputs both pins of OUT4 (OUT5, respectively) must be externally connected. 26 CP Charge pump output This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection 27 PWM1 10 PWM1 input: This input signal can be used to control the drivers OUT1-OUT6 and OUT8 by an external PWM signal. Doc ID 14278 Rev 4 7/38 Block diagram and pin description Table 2. Pin definitions and functions (continued) Pin Symbol 31 33 OUT6, OUT7 22, 24, 29, 30, 34 NC Figure 2. L9953 / L9953XP Function Highside driver output 6,7: Each output is built by a highside switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. Each highside driver is a power DMOS transistor with an internal parasitic reverse diode from each output to VS (bulk-drain-diode). Each output is over-current and open load protected. Not connected pins. Configuration diagram (top view) GND 1 36 GND OUT8 2 35 OUT8 OUT1 3 34 NC OUT2 4 OUT3 5 33 OUT7 32 Vs Vs 6 31 OUT6 Vs 7 DI 8 CM / PWM2 9 CSN 10 PowerSO-36 PowerSSO-36 29 NC 28 Vs 27 PWM1 DO 11 26 CP Vcc 12 CLK 13 25 Vs Vs 14 23 Vs Vs 15 22 NC 24 NC 21 OUT5 OUT4 16 OUT4 17 GND 18 8/38 30 NC 20 OUT5 19 GND Doc ID 14278 Rev 4 L9953 / L9953XP Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 3. Absolute maximum ratings Symbol Parameter Value Unit -0.3 to28 V 40 V -0.3 to 5.5 V Digital input / output voltage -0.3 to VCC + 0.3 V VCM Current monitor output -0.3 to VCC + 0.3 V VCP Charge pump output -25 to VS + 11 V DC supply voltage VS VCC VDI, VDO, VCLK, VCSN, Vpwm1 2.2 Single pulse tmax < 400ms Stabilized supply voltage, logic supply IOUT1,2,3,6,7 Output current ±5 A IOUT4,5,8 Output current ±10 A ESD protection Table 4. ESD protection Parameter All pins Value Unit ± 2(1) kV 8(2) kV ± Output pins: OUT1 - OUT8 1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A. 2. HBM with all unzapped pins grounded. 2.3 Thermal data Table 5. Symbol Tj Operating junction temperature Parameter Operating junction temperature Doc ID 14278 Rev 4 Value Unit -40 to 150 °C 9/38 Electrical specifications Table 6. L9953 / L9953XP Temperature warning and thermal shutdown Symbol Parameter Min. TjTW ON Temperature warning threshold junction temperature TjSD ON Thermal shutdown threshold junction temperature Tj increasing TjSD OFF Thermal shutdown threshold junction temperature Tj decreasing Tj 130 Max. Unit 150 °C 170 °C 150 TjSD HYS Thermal shutdown hysteresis 2.4 Typ. °C 5 °K Electrical characteristics VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 7. Symbol VS Supply Parameter Test condition Operating supply voltage range 7 Unit 28 V 20 mA VS = 16V, VCC = 0V standby mode OUT1 - OUT8 floating Ttest = -40°C, 25°C 4 12 µA Ttest = 85°C(1) 6 25 µA VCC DC supply current VS = 16V, VCC = 5.3V CSN = VCC , active mode 1 3 mA VCC quiescent supply current VS = 16V, VCC = 5.3V CSN = VCC standby mode OUT1 - OUT8 floating 25 50 µA Sum quiescent supply current VS = 16V, VCC = 5.3V CSN = VCC standby mode OUT1 - OUT8 floating Ttest = 130°C 50 100 µA VS quiescent supply current 1. Guaranteed by design. 10/38 Max. 7 IS IS + ICC Typ. VS = 16V, VCC = 5.3V active mode OUT1 - OUT8 floating VS DC supply current ICC Min. Doc ID 14278 Rev 4 L9953 / L9953XP Table 8. Symbol Electrical specifications Overvoltage and under voltage detection Parameter Test condition Min. Typ. Max Unit VSUV ON VS UV-threshold voltage VS increasing 5.7 7.2 V VSUV OFF VS UV-threshold voltage VS decreasing 5.5 6.9 V VSUV hyst VS UV-hysteresis VSUV ON - VSUV OFF VSOV OFF VS OV-threshold voltage VS increasing 18 24.5 V VSOV ON VS OV-threshold voltage VS decreasing 17.5 23.5 V VSOV hyst VS OV-hysteresis VSOV OFF - VSOV ON VPOR OFF Power-On-reset threshold VCC increasing VPOR ON Power-On-reset threshold VCC decreasing VPOR hyst Power-On-reset hysteresis VPOR OFF - VPOR ON Table 9. Symbol 0.5 V 1 V 4.4 3.1 V V 0.3 V Current monitor output Parameter Test condition Min. Typ. Unit 4 V VCM Functional voltage range VCC = 5V ICM,r Current monitor output ratio: ICM / IOUT1,4,5,8 0V ≤ VCM ≤ 4V, VCC=5V 1 -----------------10.000 Current monitor accuracy 0 V ≤ VCM ≤ 3.8V, VCC = 5V, IOut,min=500mA, IOut max = 6A (FS = full scale= 600μA) 4% + 1%FS 8% + 2%FS - Typ. Max Unit ICM acc Table 10. Symbol VCP ICP 0 Max - Charge pump output Parameter Charge pump output voltage Charge pump output current Test condition Min. VS = 8V, ICP = -60µA VS+6 VS+13 V VS = 10V, ICP = -80µA VS+8 VS+13 V VS ≥ 12V, ICP = -100µA VS+10 VS+13 V VCP = VS+10V, VS =13.5V 95 300 µA Doc ID 14278 Rev 4 150 11/38 Electrical specifications Table 11. Symbol L9953 / L9953XP OUT1 - OUT8 Parameter Test condition rON OUT1, rON OUT2 On-resistance to supply or GND rON OUT3 rON OUT4, On-resistance to supply rON OUT5 or GND rON OUT6, On-resistance to supply rON OUT7 rON OUT8 On-resistance to supply 12/38 Min. Typ. Max Unit VS = 13.5 V, Tj = 25 °C, IOUT1,2,3 = ± 0.8A 800 1100 mΩ VS = 13.5 V, Tj = 125 °C, IOUT1,2,3 = ± 0.8 A 1250 1700 mΩ VS = 13.5 V, Tj = 25 °C, IOUT4,5 = ± 3 A 150 200 mΩ VS = 13.5 V, Tj = 125 °C, IOUT4,5 = ± 3 A 225 300 mΩ VS = 13.5 V, Tj = 25 °C, IOUT6,7 = − 0.8A 500 700 mΩ VS = 13.5 V, Tj = 125 °C, IOUT6,7 = −0.8 A 700 950 mΩ VS = 13.5 V, Tj = 25 °C, IOUT8 = -3 A 100 150 mΩ VS = 13.5 V, Tj = 125 °C, IOUT8 = -3 A 150 200 mΩ IOUT1 IOUT2 IOUT3 Output current limitation to GND Source, VS=13.5 V -3.0 -1.5 A IOUT1 IOUT2 IOUT3 Output current limitation to supply Sink, VS=13.5 V 1.5 3.0 A IOUT4 IOUT5 Output current limitation to GND Source, VS=13.5 V -10.5 -6 A IOUT4 IOUT5 Output current limitation to supply Sink, VS=13.5 V 6 10.5 A IOUT6 IOUT7 Output current limitation to GND Source, VS=13.5 V -3.0 -1.5 A IOUT8 Output current limitation to GND Source, VS=13.5 V -10.5 -6 A td ON H Output delay time, highside driver on VS=13.5 V, corresponding lowside driver is not active 20 40 80 µs td OFF H Output delay time, highside driver off VS=13.5 V 50 150 300 µs td ON L Output delay time, lowside driver on VS=13.5 V, corresponding highside driver is not active 15 30 70 µs td OFF L Output delay time, lowside driver off VS=13.5 V 60 100 200 µs Doc ID 14278 Rev 4 L9953 / L9953XP Table 11. Symbol Electrical specifications OUT1 - OUT8 (continued) Parameter Test condition Min. Typ. Max Unit td HL Cross current protection time, source to sink tCC ONLS_OFFHS - td OFF H(1) 200 400 µs td LH Cross current protection time, sink to source tCC ONHS_OFFLS - td OFF L(1) 200 400 µs 0 -2 -5 µA IQLH VOUT1-8=0V, standby Switched-off output current highside drivers of mode OUT1-8 VOUT1-8=0V, active mode -40 -15 0 µA 0 80 120 µA -40 -15 0 µA IQLL VOUT1-5= VS, standby Switched-off output current lowside drivers of mode OUT1-5 VOUT1-5= VS, active mode IOLD123 Open load detection current of OUT1, OUT2 and OUT3 Source and sink 15 40 60 mA IOLD45 Open load detection current of OUT4 and OUT5 Source and sink 60 150 300 mA IOLD67 Open load detection current of OUT6 and OUT7 Source 15 40 60 mA IOLD8 Open load detection current of OUT8 Source 30 150 300 mA td OL Minimum duration of open load condition to set the status bit 500 3000 µs tISC Minimum duration of over-current condition to switch off the driver 10 100 µs frec0 Recovery frequency for OC recovery duty cycle bit=0 2 8 kHz frec1 Recovery frequency for OC recovery duty cycle bit=1 3 16 kHz dVOUT123/dt Slew rate of OUT123 and dVOUT67/dt OUT 67 dVOUT45/dt Slew rate of OUT4 and OUT5 dVOUT8/dt Slew rate of OUT8 VS =13.5 V Rload = 16.8 Ω 0.08 0.2 0.4 V/µs VS =13.5 V Rload = 4.5 Ω 0.08 0.2 0.4 V/µs VS =13.5 V Rload = 4.5 Ω 0.08 0.2 0.4 V/µs 1. tCC ON is the switch on delay time td ON if complement in half bridge has to switch Off. Doc ID 14278 Rev 4 13/38 Electrical specifications 2.5 L9953 / L9953XP SPI - electrical characteristics (VS = 8 to 16V, VCC = 4.5 to 5.3V, Tj = - 40 to 150°C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin). Table 12. Delay time from standby to active mode Symbol Parameter tset Delay time Table 13. Test condition Min. Switching from standby to active mode. Time until output drivers are enabled Parameter 160 300 µs Max. Unit Min. Typ. 1.5 2.0 VinL Input low level VCC = 5V Input high level VCC = 5V VinHyst Input hysteresis VCC = 5V 0.5 ICSN in Pull up current at input CSN VCSN = 3.5V VCC = 5V -40 ICLK in Pull down current at input CLK Cin(1) Unit Test condition VinH IPWM1 in Max. Inputs: CSN, CLK, PWM1/2 and DI Symbol IDI in Typ. Pull down current at input DI Pull down current at input PWM1 Input capacitance at input CSN, CLK, DI and PWM1/2 3.0 V 3.5 V V -20 -5 µA VCLK = 1.5V 10 25 50 µA VDI = 1.5V 10 25 50 µA VPWM = 1.5V 10 25 50 µA 10 15 pF Max. Unit 0 V < VCC < 5.3V 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 14. DI timing(1) Symbol Parameter Test condition Min. tCLK Clock period VCC = 5V 1000 ns tCLKH Clock high time VCC = 5V 400 ns tCLKL Clock low time VCC = 5V 400 ns tset CSN CSN setup time, CSN low before rising edge of CLK VCC = 5V 400 ns tset CLK CLK setup time, CLK high before rising edge of CSN VCC = 5V 400 ns tset DI DI setup time VCC = 5V 200 ns thold time DI hold time VCC = 5V 200 ns tr in Rise time of input signal DI, CLK, CSN VCC = 5V 100 ns tf in Fall time of input signal DI, CLK, CSN VCC = 5V 100 ns 1. DI timing parameters tested in production by a passed / failed test: 14/38 Typ. Tj= -40°C / +25°C: SPI communication @ 2MHz. Tj= +125°C SPI communication @ 1.25 MHz. Doc ID 14278 Rev 4 L9953 / L9953XP Table 15. Symbol Electrical specifications DO Parameter Test condition VDOL Output low level VCC = 5 V, ID = -2mA VDOH Output high level VCC = 5 V, ID = 2 mA IDOLK Tristate leakage current VCSN = VCC, 0V < VDO < VCC Tristate input capacitance VCSN = VCC, 0V < VCC < 5.3V CDO (1) Min. Typ. Max. Unit 0.2 0.4 V VCC -0.4 VCC-0.2 -10 V 10 µA 15 pF Typ. Max. Unit 10 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 16. Symbol DO timing Parameter Test condition Min. tr DO DO rise time CL = 100 pF, Iload = -1mA 80 140 ns tf DO DO fall time CL = 100 pF, Iload = 1mA 50 100 ns ten DO tri L DO enable time from tristate to low level CL = 100 pF, Iload = 1mA pull-up load to VCC 100 250 ns tdis DO L tri DO disable time from low level to tristate CL = 100 pF, Iload = 4 mA pull-up load to VCC 380 450 ns ten DO tri H DO enable time CL =100 pF, Iload = -1mA from tristate to high level pull-down load to GND 100 250 ns tdis DO H tri DO disable time CL = 100 pF, Iload = -4mA from high level to tristate pull-down load to GND 380 450 ns 50 250 ns Typ. Max. Unit td DO Table 17. VDO < 0.3 VCC, VDO > 0.7VCC, CL = 100pF DO delay time CSN timing Symbol Parameter Test condition Min. tCSN_HI,stb CSN HI time, switching from standby mode Transfer of SPI-command to Input Register 20 µs Transfer of SPI-command to input register 4 µs tCSN_HI,min CSN HI time, active mode Doc ID 14278 Rev 4 15/38 Electrical specifications Figure 3. L9953 / L9953XP SPI - transfer timing diagram CSN high to low: DO enabled CSN time CLK 0 1 2 3 4 5 6 X 7 X 18 19 0 20 21 22 23 time DI: data will be accepted on the rising edge of CLK signal DI 0 1 2 3 4 5 6 7 X X 18 19 0 20 21 22 23 DO: data will change on the falling edge of CLK signal DO 0 1 2 3 4 5 6 7 X 18 19 20 21 22 23 Input Data Register old data 1 time 0 1 time CSN low to high: actual data is transfered to output power switches fault bit Figure 4. X 1 new data time SPI - input timing 0.8 VCC CSN 0.2 VCC t t set CSN t CLKH se t CLK 0.8 VCC CLK 0.2 VCC t set DI t hold DI t CLKL 0.8 VCC DI Valid Valid 0.2 VCC 16/38 Doc ID 14278 Rev 4 L9953 / L9953XP Electrical specifications Figure 5. SPI - DO valid data delay time and valid time t f in t r in 0.8 VCC 0.5 VCC 0.2 VCC CLK t r DO DO (low to high) 0.8 VCC 0.2 VCC t d DO t f DO 0.8 VCC DO (high to low) 0.2 VCC Figure 6. SPI - DO enable and disable time tf in tr in 0.8 VCC 50% 0.2 VCC CSN DO pull-up load to VCC C L = 100 pF 50% ten DO tri L t dis DO L tri 50% DO pull-down load to GND C L = 100 pF ten DO tri H Doc ID 14278 Rev 4 t dis DO H tri 17/38 Electrical specifications Figure 7. L9953 / L9953XP SPI - driver turn-on/off timing, minimum CSN hi time CSN low to high: data from shift register is transferred to output power switches t r in t f in tCSN_HI,min 80% 50% 20% CSN tdOFF output current of a driver ON state OFF state 80% 50% 20% t OFF tdON t ON output current of a driver Figure 8. OFF state ON state 80% 50% 20% SPI - timing of status bit 0 (fault condition) CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO CSN time CLK time DI time DI: data is not accepted DO 0time DO: status information of data bit 0 (fault condition) will stay as long as CSN is low 18/38 Doc ID 14278 Rev 4 L9953 / L9953XP Application information 3 Application information 3.1 Dual power supply: VS and VCC The power supply voltage VS supplies the half bridges and the highside drivers. An internal charge-pump is used to drive the highside switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. In case of poweron (VCC increases from under voltage to VPOR OFF = 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to tristate (high impedance) and the status registers are cleared. 3.2 Standby mode The standby mode of the L9953 is activated by clearing the bit 23 of the Input Data Register 0. All latched data will be cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 6 µA (50µA) for CSN = high (DO in tristate). By switching the VCC voltage a very low quiescent current can be achieved. If bit 23 is set, the device will be switched to active mode. 3.3 Inductive loads Each half bridge is built by an internally connected highside and a lowside power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT5 without external free-wheeling diodes. The highside drivers OUT6 to OUT8 are intended to drive resistive loads. Hence only a limited energy (E100μH) an external free-wheeling diode connected to GND and the corresponding output is needed. 3.4 Diagnostic functions All diagnostic functions (over/open load, power supply over-/under voltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open load: 1ms, respectively) before the corresponding status bit in the status registers will be set. The filters are used to improve the noise immunity of the device. Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers. On contrary, the overload condition will disable the corresponding driver (over-current) and over temperature will switch off all drivers (thermal shutdown). Without setting the over-current recovery bits in the Input Data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers. Doc ID 14278 Rev 4 19/38 Application information 3.5 L9953 / L9953XP Overvoltage and under voltage detection If the power supply voltage VS rises above the overvoltage threshold VSOV OFF (typical 21 V), the outputs OUT1 to OUT8 are switched to high impedance state to protect the load. When the voltage VS drops below the under voltage threshold VSUV OFF (UV-switch-OFF voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS recovers to normal operating voltage the outputs stages return to the programmed state (input register 0: bit 20=0). If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage. 3.6 Charge pump The charge pump runs under all conditions in normal mode. In standby the charge pump is disabled. 3.7 Temperature warning and thermal shutdown If junction temperature rises above Tj TW a temperature warning flag is set and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit will be set and power DMOS transistors of all output stages are switched off to protect the device. Temperature warning flag and thermal shutdown bit are latched and must be cleared by the microcontroller. The related bit is only cleared if the temperature decreases below the trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated. 3.8 Open load detection The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. 3.9 Over load detection In case of an over-current condition a flag is set in the status register in the same way as open load detection. If the over-current signal is valid for at least tISC = 32 µs, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver. 20/38 Doc ID 14278 Rev 4 L9953 / L9953XP 3.10 Application information Current monitor The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected highside driver. The bits 18 and 19 of the Input Data Register 0 control which of the outputs OUT1, OUT4, OUT5, and OUT8 will be multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs). 3.11 PWM inputs Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit in Input Data Register 1 is set, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in Input Data Register 0. The outputs OUT1-OUT6 and OUT8 are controlled by the PWM1 input and the output OUT7 is controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals. 3.12 Cross-current protection The six half-bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct. 3.13 Programmable softstart function to drive loads with higher inrush current Loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device will automatically switchon the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 12% or 25%. The PWM modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at 3kHz or 6kHz. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current Recovery bit for the first 50ms. After clearing the recovery bit the output will be automatically disabled if the overload condition still exits. Doc ID 14278 Rev 4 21/38 Application information Figure 9. 22/38 L9953 / L9953XP Example of programmable softstart function for inductive loads Doc ID 14278 Rev 4 L9953 / L9953XP Functional description of the SPI 4 Functional description of the SPI 4.1 Serial Peripheral Interface (SPI) This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS-compatible output pins and one input pin will be needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPIcommunication cycle. Note: In contrast to the SPI-standard the least significant bit (LSB) will be transferred first (see Figure 3). 4.2 Chip Select Not (CSN) The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) will be in high impedance state. A low signal will activate the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN will be called a communication frame. If the CSN-input pin is driven above 7.5V, the L9953 will go into a test mode. In the test mode the DO will go from tri-state to active mode. 4.3 Serial Data In (DI) The input pin is used to transfer data serial into the device. The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register. The writing to the selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame will be ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. Doc ID 14278 Rev 4 23/38 Functional description of the SPI 4.4 L9953 / L9953XP Serial Data Out (DO) The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. 4.5 Serial clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. 4.6 Input data register The device has two input registers. The first bit (bit 0) at the DI-input is used to select one of the two Input Registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver. If bit 23 is zero, the device will go into the standby-mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers will be cleared after the current communication frame (rising edge of CSN). 4.7 Status register This devices uses two status registers to store and to monitor the state of the device. Bit 0 is used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPIcommunication cycle. If one of the over-current bits is set, the corresponding driver will be disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers will go into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers. 4.8 Scan mode The Scan Mode can be entered by rising the PWM1 input to a voltage higher than 9.5V. 24/38 Doc ID 14278 Rev 4 L9953 / L9953XP 4.9 Functional description of the SPI Test mode The Test Mode can be entered by rising the CSN input to a voltage higher than 9.5V. In the test mode the inputs CLK, DI, PWM1/2, the internal 2MHz CLK, OL and OC can be multiplexed to output DO and Iref, Tsens1-4 and Vbgp can be multiplexed to input CM/PWM2. Furthermore the over-current thresholds are reduced by a factor of 4 to allow EWS testing at lower current. The internal logic prevents that the High-Side and Low-Side driver of the same half-bridge can be switched-on at the same time. In the test mode this combination is used to multiplex the desired signals according to following table: Table 18. Test mode OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 PWM PWM PWM PWM PWM PWM 1 EN 1 EN 1 EN 1 EN 1 EN 1 EN DO LS3 HS3 LS4 HS4 LS5 HS5 Test Pad ! (both HI) ! (both HI) ! (both HI) NoError ! (both HI) ! (both HI) ! (both HI) 5µA Iref both HI ! (both HI) ! (both HI) DI both HI ! (both HI) ! (both HI) Tsens1 ! (both HI) both HI ! (both HI) CLK ! (both HI) both HI ! (both HI) Tsens2 both HI both HI ! (both HI) INT_CLK both HI both HI ! (both HI) Tsens3 ! (both HI) ! (both HI) both HI PWM1 ! (both HI) ! (both HI) both HI Tsens4 both HI ! (both HI) both HI PWM2 both HI ! (both HI) both HI x ! (both HI) both HI both HI OL ! (both HI) both HI both HI x both HI both HI both HI OC both HI both HI both HI Vbandgap Doc ID 14278 Rev 4 25/38 Functional description of the SPI 4.10 L9953 / L9953XP SPI - input data and Status registers Table 19. SPI - input data and Status registers 0 Input register 0 (write) Status register 0 (read) Bit 23 22 21 Name Comment Enable bit Comment If Enable Bit is set the device will be switched in active mode. If Enable Bit is cleared the device go into standby mode and all bits are cleared. After power-on reset device starts in standby mode. Always 1 A broken VCC-or SPIconnection of the L9953 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. If Reset Bit is set both status registers will be cleared after rising edge of CSN input. VS overvoltage In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If OC recovery This bit defines in VS voltage recovers to normal duty cycle combination with the overoperating conditions outputs current recovery bit (Input VS undervoltage are reactivated automatically Register 1) the duty cycle (if Bit 20 of status register 0 is 0: 12% 1: 25% in over-current condition of not set). an activated driver. Reset bit 20 If this bit is set the microcontroller has to Overvoltage/Un clear the status register dervoltage after recovery undervoltage/overvoltage disable event to enable the outputs. 19 Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS-output will be multiplexed to the CM output: Current monitor select bits 18 26/38 Name Bit 19 Bit 18 Output 0 0 OUT8 1 0 OUT1 0 1 OUT5 1 1 OUT4 Thermal shutdown In case of a thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. Temperature warning This TW bit is for information purpose only. It can be used for a thermal management by the microcontroller to avoid a thermal shutdown. Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times). Doc ID 14278 Rev 4 L9953 / L9953XP Functional description of the SPI Table 19. SPI - input data and Status registers 0 (continued) Input register 0 (write) Status register 0 (read) Bit Name Comment Name 17 OUT8 – HS on/off OUT8 – HS over-current 16 x (don’t care) 0 15 OUT7 – HS on/off 14 OUT6 – HS on/off 13 x (don’t care) 12 x (don’t care) 11 x (don’t care) 10 OUT5 – HS on/off 9 OUT5 – LS on/off 8 OUT4 – HS on/off 7 OUT4 – LS on/off 6 OUT3 – HS on/off 5 OUT3 – LS on/off 4 OUT2 – HS on/off 3 OUT2 – LS on/off 2 OUT1 – HS on/off OUT1 – HS over-current 1 OUT1 – LS on/off OUT1 – LS over-current 0 If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (Input Register 1) the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT5 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND. In test mode (CSN>9.5V) this bit combinations are used to multiplex internal signals to the DO-output. LS3 HS3 LS4 HS4 LS5 HS5 CM/PWM2 0 0 0 0 0 0 5µA Iref 1 1 0 0 0 0 Tsens1 0 0 1 1 0 0 Tsens2 1 1 1 1 0 0 Tsens3 0 0 0 0 1 1 Tsens4 1 1 1 1 1 1 Vbgp 0 OUT7 – HS over-current OUT6 – HS over-current 0 0 OUT5 – HS over-current OUT5 – LS over-current OUT4 – HS over-current OUT4 – LS over-current OUT3 – HS over-current OUT3 – LS over-current In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current Recovery Enable bit is set (Input Register 1) the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21). If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (Reset Bit) to reactivate the output driver. OUT2 – HS over-current OUT2 – LS over-current No error bit Doc ID 14278 Rev 4 Comment A logical NOR-combination of all bits 1 to 22 in both status registers. 27/38 Functional description of the SPI Table 20. L9953 / L9953XP SPI - input data and status registers 1 Input register 1 (write) Status register 1 (read) Bit Name Comment 23 Enable bit If Enable bit is set the device will be switched in active mode. If Enable Bit is cleared device goes into standby mode and all bits are cleared. After poweron reset device starts in standby mode. 22 OUT8 OC Recovery Enable VS overvoltage 21 0/1 VS undervoltage 20 19 18 28/38 OUT7 OC Recovery Enable OUT6 OC Recovery Enable In case of an over-current event the over-current status bit (Status Register 0) is set and the output is switched off. If the over-current Recovery Enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (Bit 21 of Input Data Register 0). Depending on occurrence of Overturned Event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero. 0/1 Doc ID 14278 Rev 4 Name Comment Always 1 A broken VCC-or SPIconnection of the L9953 can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. In case of an overvoltage or under voltage event the corresponding bit is set and the outputs are deactivated. If Vs voltage recovers to normal operating conditions outputs are reactivated automatically. In case of a thermal shutdown all outputs are switched off. The Thermal shutdown microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. Temperature warning The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit. Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is only present during start up time Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times). L9953 / L9953XP Functional description of the SPI Table 20. SPI - input data and status registers 1 (continued) Input register 1 (write) Status register 1 (read) Bit Name Comment Name OUT8 – HS open load 17 16 OUT5 OC Recovery Enable 0 15 OUT4 OC Recovery Enable OUT7 – HS open load 14 OUT3 OC Recovery Enable 13 OUT2 OC Recovery Enable 0 12 OUT1 OC Recovery Enable 0 11 OUT8 PWM1 Enable 0 10 0/1 OUT5 – HS open load 9 8 7 6 After 50ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed. If the PWM1/2 Enable Bit is set and the output is enabled OUT7 PWM2 (Input Register 0) the output is Enable switched on if PWM1/2 input is OUT6 PWM1 high and switched off if PWM1/2 input is low. OUT7 is Enable controlled by PWM2 input. All other outputs are controlled by 0/1 PWM1 input. For test mode rise CSN>9.5 V. 0/1 5 OUT5 PWM1 Enable 4 OUT4 PWM1 Enable 3 OUT3 PWM1 Enable OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 DO 0 0 0 0 0 0 No error 1 1 0 0 0 0 Di 0 0 1 1 0 0 CLK 1 1 1 1 0 0 CLK 2MHz 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 PWM1 PWM2 OL OUT6 – HS open load OUT5 – LS open load OUT4 – HS open load OUT4 – LS open load OUT3 – HS open load The open load detection monitors the load current in each activated output stage. If the load current is below the open load detection threshold for at least 1 ms (tdOL) the corresponding open load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open load status without changing the mechanical/electrical state of the loads. OUT3 – LS open load OUT2 –HS open load OUT2– LS open load OC 2 OUT2 PWM1 Enable OUT1 – HS open load 1 OUT1 PWM1 Enable OUT1 – LS open load 0 Comment 1 No Error bit Doc ID 14278 Rev 4 A logical NORcombination of all bits 1 to 22 in both status registers. 29/38 Packages thermal data 5 L9953 / L9953XP Packages thermal data Figure 10. Packages thermal data 30/38 Doc ID 14278 Rev 4 L9953 / L9953XP Package and packing information 6 Package and packing information 6.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.2 PowerSO-36™ package information Figure 11. PowerSO-36™ package dimensions Doc ID 14278 Rev 4 31/38 Package and packing information Table 21. L9953 / L9953XP PowerSO-36™ mechanical data Millimeters Symbol Min. Typ. A a1 Max. 3.60 0.10 0.30 a2 3.30 a3 0 0.10 b 0.22 0.38 c 0.23 0.32 D* 15.80 16.00 D1 9.40 9.80 E 13.90 14.5 E1 * 10.90 11.10 E2 E3 2.90 5.80 6.20 e 0.65 e3 11.05 G 0 0.10 H 15.50 15.90 h L 1.10 0.8 1.10 M N 10 deg R s 32/38 8 deg Doc ID 14278 Rev 4 L9953 / L9953XP 6.3 Package and packing information PowerSSO-36™ package information Figure 12. PowerSSO-36™ package dimensions Table 22. PowerSSO-36™ mechanical data Millimeters Symbol Min. Typ. Max. A - - 2.45 A2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 D* 10.10 - 10.50 E* 7.4 - 7.6 e - 0.5 - e3 - 8.5 - F - 2.3 - G - - 0.1 G1 - - 0.06 H 10.1 - 10.5 h - - 0.4 k 0° - 8° L 0.55 - 0.85 N - - 10 deg Doc ID 14278 Rev 4 33/38 Package and packing information Table 22. L9953 / L9953XP PowerSSO-36™ mechanical data (continued) Millimeters Symbol 6.4 Min. Typ. Max. X 4.3 - 5.2 Y 6.9 - 7.5 PowerSO-36™ packing information Figure 13. PowerSO-36™ tube shipment (no suffix) 34/38 Doc ID 14278 Rev 4 L9953 / L9953XP Package and packing information Figure 14. PowerSO-36™ tape and reel shipment (suffix “TR”) TAPE DIMENSIONS A0 B0 K0 K1 F P1 W 15.20 ± 0.1 16.60 ± 0.1 3.90 ± 0.1 3.50 ± 0.1 11.50 ± 0.1 24.00 ± 0.1 24.00 ± 0.3 All dimensions are in mm. Doc ID 14278 Rev 4 REEL DIMENSIONS Base Qty Bulk Qty A (max) B (min) C (±0.2) D (min) G (+2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 35/38 Package and packing information 6.5 L9953 / L9953XP PowerSSO-36™ packing information Figure 15. PowerSSO-36™ tube shipment (no suffix) Base Qty Bulk Qty Tube length (±0.5) A B C (±0.1) C B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 16. PowerSSO-36™ tape and reel shipment (suffix “TR”) Reel dimensions Base Qty Bulk Qty A (max) B (min) C (±0.2) F G (+2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (±0.1) P D (±0.05) D1 (min) F (±0.1) K (max) P1 (±0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min 500mm min Empty components pockets sealed with cover tape. User direction of feed 36/38 Doc ID 14278 Rev 4 No components L9953 / L9953XP 7 Revision history Revision history Table 23. Document revision history Date Revision 23-Jan-2008 1 Initial release. 2 Table 22: PowerSSO-36™ mechanical data: – Deleted A (min) value – Changed A (max) value from 2.47 to 2.45 – Changed A2 (max) value from 2.40 to 2.35 – Changed a1 (max) value from 0.075 to 0.1 – Added F and k rows 14-May-2010 3 Table 22: PowerSSO-36™ mechanical data: – Changed X: minimum value from 4.1 to 4.3 and maximum value from 4.7 to 5.2 – Changed Y: minimum value from 6.5 to 6.9 and maximum value from 7.1 to 7.5 22-Sep-2013 4 Updated Disclaimer. 24-Jun-2009 Description of changes Doc ID 14278 Rev 4 37/38 L9953 / L9953XP Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2013 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 38/38 Doc ID 14278 Rev 4