L9954LXPTR

L9954LXP Door actuator driver Features ■ Three half bridges for 0.75 A loads (RDSon = 1600 mΩ) ■ Two configurable high-side driver for up to 1.5A load (RDSon = 500 mΩ) or 0.35 A load (Ron = 1800 mΩ) ■ One high-side driver for 6 A load (RDSon = 100 mΩ) ■ Programmable soft start function to drive loads with higher inrush currents (i.e. current > 6 A, current > 1.5 A) PowerSSO-36 ■ Very low current consumption in standby mode (IS < 6 µA typ; Tj ≤ 85 °C) ■ All outputs short circuit protected ■ Current monitor output for high-side OUT1, OUT4, OUT5 and OUT6 ■ All outputs over temperature protected ■ Open-load diagnostic for all outputs ■ Overload diagnostic for all outputs ■ PWM control of all outputs ■ Charge pump output for reverse polarity protection Table 1. Applications ■ Door actuator driver with bridges for mirror axis control and high-side driver for mirror defroster and two 10 W light bulbs and/or LEDs. Description The L9954LXP is a microcontroller driven multifunctional door actuator driver for automotive applications. Up to two DC motors and three grounded resistive loads can be driven with three half bridges and three high-side drivers. The integrated standard Serial Peripheral Interface (SPI) controls all operation modes (forward, reverse, brake and high impedance). All diagnostic information is available via SPI. Device summary Order codes Package PowerSSO-36 September 2013 Tube Tape and reel L9954LXP L9954LXPTR Doc ID 16186 Rev 3 1/35 www.st.com 1 Contents L9954LXP Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 2/35 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 SPI - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.1 Dual power supply: VS and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3 Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 21 3.8 Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.9 Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.10 Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 PWM inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12 Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 Programmable soft start function to drive loads with higher inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Chip Select Not (CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 Serial Data In (DI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.4 Serial Data Out (DO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5 Serial Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.6 Input Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 16186 Rev 3 L9954LXP Contents 4.7 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 SPI - input data and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 6.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 PowerSSO-36 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 16186 Rev 3 3/35 List of tables L9954LXP List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. 4/35 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Overvoltage and under voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 OUT1 - OUT6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Inputs: CSN, CLK, PWM1/2 and DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SPI - input data and status registers 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI - input data and status registers 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Doc ID 16186 Rev 3 L9954LXP List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI - DO valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - DO enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI - driver turn-on / off timing, minimum CSN HI time . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Programmable soft start function for inductive loads and incandescent bulbs . . . . . . . . . . 23 Packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-36 tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Doc ID 16186 Rev 3 5/35 Block diagram and pin description 1 L9954LXP Block diagram and pin description Figure 1. VBAT Block diagram Reverse Polarity Protection * Note: Value of capacitor has to be choosen carefully to limit the VS voltage below absolute maximum ratings in case of an unexpected freewheeling condition (e.g. TSD, POR) 100k * VS 10k 100µF OUT1 Charge Pump VCC ** 1k ** 1k ** 1k ** 1k DI DO CLK CSN **1k PWM1 SPI Interface VCC Driver Interface & Diagnostic OUT2 OUT3 Mirror Common M Mirror Vertical M Mirror Horizontal Lock / Folder OUT4 Programmable Bulb (10W) or LED Mode OUT5 µC OUT6 PWM2 / CM **1k MUX Defroster 4 GND ** Note: Resistors between µC and L9954LXP are recommended to limit currents for negative voltage transients at VBAT (e.g. ISO type 1 pulse) Figure 2. Configuration diagram (top view) GND 1 36 GND OUT6 2 35 OUT6 OUT1 3 34 NC OUT2 4 OUT3 5 33 OUT5 32 Vs Vs 6 31 OUT4 Vs 7 DI 8 30 NC CM / PWM2 9 PowerSSO-36 CSN 10 6/35 29 NC 28 Vs 27 PWM1 DO 11 26 CP Vcc 12 CLK 13 25 Vs Vs 14 23 NC NC 15 22 NC NC 16 NC 17 GND 18 21 NC 24 NC 20 NC 19 GND Doc ID 16186 Rev 3 L9954LXP Block diagram and pin description Table 2. Pin definitions and functions Pin 1, 18, 19, 36 2, 35 3 4 5 6, 7, 14, 25, 28, 32 8 9 10 11 Symbol Function GND Ground: reference potential. Important: for the capability of driving the full current at the outputs all pins of GND must be externally connected. OUT6 High-side driver output 6 The output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. The high-side driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS (bulk-drain-diode). The output is over-current and openload protected. Important: for the capability of driving the full current at the outputs both pins of OUT6 must be externally connected. OUT1 OUT2 OUT3 Half-bridge output 1,2,3 The output is built by a high-side and a low-side switch, which are internally connected. The output stage of both switches is a power DMOS transistor. Each driver has an internal parasitic reverse diode (bulk-drain-diode: high-side driver from output to VS, switchs driver from GND to output). This output is over-current and open-load protected. VS Power supply voltage (external reverse protection required) For this input a ceramic capacitor as close as possible to GND is recommended. Important: for the capability of driving the full current at the outputs all pins of VS must be externally connected. DI Serial data input The input requires CMOS logic levels and receives serial data from the microcontroller. The data is an 24bit control word and the least significant bit (LSB, bit 0) is transferred first. Current monitor output/PWM2 input Depending on the selected multiplexer bits of input data register this CM/PWM2 output sources an image of the instant current through the corresponding high-side driver with a ratio of 1/10.000. This pin is bidirectional. The microcontroller can overdrive the current monitor signal to provide a second PWM input for the output OUT5. CSN Chip select not input This input is low active and requires CMOS logic levels. The serial data transfer between L9954LXP and micro controller is enabled by pulling the input CSN to low-level. DO Serial data output The diagnosis data is available via the SPI and this 3-state output. The output remains in 3-state, if the chip is not selected by the input CSN (CSN = high) Doc ID 16186 Rev 3 7/35 Block diagram and pin description Table 2. 8/35 L9954LXP Pin definitions and functions (continued) Pin Symbol Function 12 VCC Logic supply voltage For this input a ceramic capacitor as close as possible to GND is recommended. 13 CLK Serial clock input This input controls the internal shift register of the SPI and requires CMOS logic levels. 26 CP Charge pump output This output is provided to drive the gate of an external n-channel power MOS used for reverse polarity protection. 27 PWM1 PWM1 input This input signal can be used to control the drivers OUT1-OUT4 and OUT6 by an external PWM signal. 31 33 OUT4, OUT5 High-side driver output 4 and 5 Each output is built by a high-side switch and is intended for resistive loads, hence the internal reverse diode from GND to the output is missing. For ESD reason a diode to GND is present but the energy which can be dissipated is limited. Each high-side driver is a power DMOS transistor with an internal parasitic reverse diode from each output to VS (bulk-drain-diode). Each output is over-current and openload protected. 15, 16, 17, 20, 21, 22, 23, 24, 29, 30, 34 NC Not connected pins. Doc ID 16186 Rev 3 L9954LXP Electrical specifications 2 Electrical specifications 2.1 Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 3. Absolute maximum ratings Symbol Parameter Value Unit -0.3 to 28 V 40 V -0.3 to 5.5 V Digital input / output voltage -0.3 to VCC + 0.3 V VCM Current monitor output -0.3 to VCC + 0.3 V VCP Charge pump output -25 to VS + 11 V DC supply voltage VS VCC VDI, VDO, VCLK, VCSN, Vpwm1 2.2 Single pulse tmax < 400 ms Stabilized supply voltage, logic supply IOUT1,2,3,4,5 Output current ±5 A IOUT6 Output current ±10 A ESD protection Table 4. ESD protection Parameter All pins Value Unit ± 2 (1) kV (2) kV ±8 Output pins: OUT1 - OUT6 1. HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114-A. 2. HBM with all unzapped pins grounded. 2.3 Thermal data Table 5. Symbol Tj Operating junction temperature Parameter Operating junction temperature Doc ID 16186 Rev 3 Value Unit -40 to 150 °C 9/35 Electrical specifications Table 6. L9954LXP Temperature warning and thermal shutdown Symbol Parameter Min. TjTW On Temperature warning threshold junction temperature TjSD On Thermal shutdown threshold junction temperature Tj increasing TjSD Off Thermal shutdown threshold junction temperature Tj decreasing Tj 130 Max. Unit 150 °C 170 °C 150 TjSD HYS Thermal shutdown hysteresis 2.4 Typ. °C 5 °K Electrical characteristics Values specified in this section are for VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 7. Symbol VS Supply Parameter Test condition Operating supply voltage range 7 Unit 28 V 20 mA VS = 16 V, VCC = 0 V standby mode OUT1 - OUT6 floating Ttest = -40 °C, 25 °C 4 12 µA Ttest = 85 °C (1) 6 25 µA VCC DC supply current VS = 16 V, VCC = 5.3 V CSN = VCC , active mode 1 3 mA VCC quiescent supply current VS = 16 V, VCC = 5.3 V CSN = VCC standby mode OUT1 - OUT6 floating 25 50 µA Sum quiescent supply current VS = 16 V, VCC = 5.3 V CSN = VCC standby mode OUT1 - OUT6 floating Ttest = 130 °C 50 200 µA VS quiescent supply current 1. Guaranteed by design. 10/35 Max. 7 IS IS + ICC Typ. VS = 16 V, VCC = 5.3 V active mode OUT1 - OUT6 floating VS DC supply current ICC Min. Doc ID 16186 Rev 3 L9954LXP Electrical specifications Table 8. Symbol Overvoltage and under voltage detection Parameter Test condition Min. Typ. Max. Unit VSUV On VS UV-threshold voltage VS increasing 5.7 7.2 V VSUV Off VS UV-threshold voltage VS decreasing 5.5 6.9 V VSUV hyst VS UV-hysteresis VSUV On - VSUV Off VSOV Off VS OV-threshold voltage VS increasing 18 24.5 V VSOV On VS OV-threshold voltage VS decreasing 17.5 23.5 V VSOV hyst VS OV-hysteresis VSOV Off - VSOV On VPOR Off Power-on reset threshold VCC increasing VPOR On Power-on reset threshold VCC decreasing VPOR hyst Power-on reset hysteresis VPOR Off - VPOR On Table 9. Symbol VCM ICM,r 0.5 V 1 V 4.4 3.1 V V 0.3 V Current monitor output Parameter Test condition Functional voltage range VCC = 5 V Min. Typ. 0 Current monitor output ratio: ICM / IOUT6 1 ---------------10000 Current monitor output ratio: ICM / IOUT1 1 ------------3800 Current monitor output ratio: 0 V ≤ VCM ≤ 4 V, VCC = 5 V ICM / IOUT4,5 low RDSon mode 1 ---------------10200 Current monitor output ratio: ICM / IOUT4,5 high RDSon mode --1 ------------2400 Doc ID 16186 Rev 3 Max. Unit 4 V - 11/35 Electrical specifications Table 9. L9954LXP Current monitor output (continued) Symbol Parameter Test condition Current monitor accuracy Acc ICM / IOUT 8 0 V ≤ VCM ≤ 3.8 V, VCC = 5 V, IOut,min 8 = 0.5 A, IOut max 8 = 5.9 A Current monitor accuracy Acc ICM / IOUT 1 0 V ≤ VCM ≤ 3.8 V, VCC = 5V, IOut,min 1= 60mA, IOut max 1= 0.6A Current monitor accuracy Acc ICM / IOUT 4,5 high RDSon mode 0 V ≤ VCM ≤ 3.8 V, VCC = 5 V, IOut,min 4,5 = 30 mA, IOut max 4,5 = 300 mA Current monitor accuracy Acc ICM / IOUT 4,5 low RDSon mode 0 V ≤ VCM ≤ 3.8 V, VCC = 5 V, IOut,min 4,5 = 150 mA, IOut max 4,5 = 1 A ICM acc Table 10. Parameter Test condition Charge pump output voltage ICP Charge pump output current Table 11. OUT1 - OUT6 Symbol Min. Max. Unit 4% + 1%FS 8% + 2%FS - Typ. Max. Unit VS = 8 V, ICP = -60 µA VS+6 VS+13 V VS = 10 V, ICP = -80 µA VS+8 VS+13 V VS ≥ 12 V, ICP = -100 µA VS+10 VS+13 V 300 µA Typ. Max. Unit 1600 2200 mΩ 2500 3400 mΩ 500 700 mΩ 700 950 mΩ Tj = 25 °C, IOUT4,5 = - 0.2 A 2000 2700 mΩ Tj = 125 °C, IOUT4,5 = - 0.2 A 3200 4300 mΩ VCP = VS + 10 V, VS = 13.5 V Parameter Test condition VS = 13.5 V, Tj = 25 °C, RDSon OUT1, On resistance to supply or IOUT1,2,3 = ± 0.4 A RDSon OUT2 GND VS = 13.5 V, Tj = 125 °C, RDSon OUT3 IOUT1,2,3 = ± 0.4 A RDSon OUT4, RDSon OUT5 VS = 13.5 V, Tj = 25 °C, On resistance to supply in IOUT4,5 = -0.8 A low RDSon mode V = 13.5 V, T = 125 °C, S j IOUT4,5 = -0.8 A On resistance in high RDSon mode 12/35 Typ. Charge pump output Symbol VCP Min. Doc ID 16186 Rev 3 95 Min. 150 L9954LXP Electrical specifications Table 11. Symbol OUT1 - OUT6 (continued) Parameter Test condition RDSon OUT6 On resistance to supply Min. Typ. Max. Unit VS = 13.5 V, Tj = 25 °C, IOUT6 = −3 A 100 150 mΩ VS = 13.5 V, Tj = 125 °C, IOUT6 = −3 A 150 200 mΩ IOUT1 IOUT2 IOUT3 Output current limitation to GND Source, VS = 13.5 V -1.25 -0.75 A IOUT1 IOUT2 IOUT3 Output current limitation to supply Sink, VS = 13.5 V 0.75 1.25 A -3.0 -1.5 A -0.65 -0.35 A -10.5 -6 A IOUT4 IOUT5 Output current limitation to GND in low RDSon mode Output current limitation to GND in high RDSon mode Source, VS = 13.5 V IOUT6 Output current limitation to GND Source, VS = 13.5 V td On H Output delay time, highside driver on VS = 13.5 V, Rload = (1) corresponding low-side driver is not active 10 40 80 µs td Off H Output delay time, highside driver off VS = 13.5 V, Rload = (2) 15 150 300 µs td On L Output delay time, lowside driver on VS = 13.5 V, Rload = (2) corresponding high-side driver is not active 15 30 70 µs td Off L Output delay time, lowside driver off VS = 13.5 V, Rload = (2) 20 150 300 µs td HL Cross current protection time, source to sink tCC ONLS_OFFHS - td Off H(2) 200 400 µs td LH Cross current protection time, sink to source tCC ONHS_OFFLS - td OFF L(2) 200 400 µs IQLH Switched-off output current high-side drivers of OUT1-6 IQLL IOLD123 VOUT1-6 = 0 V, standby mode -3 0 -3 µA VOUT1-2-3-6 = 0 V, active mode -40 -15 0 µA VOUT4-5 = 0 V, active mode -10 -8 0 µA 0 80 120 µA -40 -15 0 µA 10 20 30 mA Switched-off output VOUT1-3 = VS, standby mode current low-side drivers of VOUT1-3 = VS, active mode OUT1-3 Open-load detection current of OUT1, OUT2 and OUT3 Source and sink Doc ID 16186 Rev 3 13/35 Electrical specifications Table 11. Symbol L9954LXP OUT1 - OUT6 (continued) Parameter Test condition Open-load detection current of OUT4 and OUT5 IOLD45 Min. Typ. Max. Unit 15 40 60 mA 5 10 15 mA 30 150 300 mA Source Open-load detection current of OUT4 and OUT5 in high RDSon mode IOLD6 Open-load detection current of OUT6 td OL Minimum duration of open-load condition to set the status bit 500 3000 µs tISC Minimum duration of overcurrent condition to switch off the driver 10 100 µs frec0 Recovery frequency for OC recovery duty cycle bit=0 1 4 kHz frec1 Recovery frequency for OC recovery duty cycle bit=1 2 6 kHz Source dVOUT123/dt dVOUT45/dt Slew rate of OUT123 and OUT45 VS = 13.5 V, Rload = (2) 0.1 0.4 0.9 V/µs dVOUT6/dt Slew rate of OUT6 VS = 13.5 V, Rload = (2) 0.08 0.2 0.4 V/µs 1. OUT1,2,3 32OHM OUT4,5 16OHM OUT4,5 high RDSon mode 63OHM OUT6 4OHM 2. tCC ON is the switch On delay time td ON if complement in half bridge has to switch off. 2.5 SPI - electrical characteristics Values specified in this section are VS = 8 to 16 V, VCC = 4.5 to 5.3 V, Tj = - 40 to 150 °C, unless otherwise specified. The voltages are referred to GND and currents are assumed positive, when the current flows into the pin. Table 12. 14/35 Delay time from standby to active mode Symbol Parameter tset Delay time Test condition Switching from standby to active mode. Time until output drivers are enabled after CSN going to high. Doc ID 16186 Rev 3 Min. Typ. Max. Unit 160 300 µs L9954LXP Electrical specifications Table 13. Inputs: CSN, CLK, PWM1/2 and DI Symbol Parameter Test condition Min. Typ. 1.5 2.0 Max. Unit VinL Input low-level VCC = 5 V VinH Input high-level VCC = 5 V VinHyst Input hysteresis VCC = 5 V 0.5 ICSN in Pull up current at input CSN VCSN = 3.5 V, VCC = 5 V -40 -20 -5 µA ICLK in Pull down current at input CLK VCLK = 1.5 V 10 25 50 µA Pull down current at input DI VDI = 1.5 V 10 25 50 µA Pull down current at input PWM1 VPWM = 1.5 V 10 25 50 µA Input capacitance at input CSN, CLK, DI and PWM1/2 0 V < VCC < 5.3 V 10 15 pF Max. Unit IDI in IPWM1 in Cin(1) 3.0 V 3.5 V V 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 14. DI timing (1) Symbol Parameter Test condition Min. Typ. tCLK Clock period VCC = 5 V 1000 - ns tCLKH Clock high time VCC = 5 V 400 - ns tCLKL Clock low time VCC = 5 V 400 - ns tset CSN CSN setup time, CSN low before rising edge of CLK VCC = 5 V 400 - ns tset CLK CLK setup time, CLK high before rising edge of CSN VCC = 5 V 400 - ns tset DI DI setup time VCC = 5 V 200 - ns thold DI DI hold time VCC = 5 V 200 - ns tr in Rise time of input signal DI, CLK, VCC = 5 V CSN - 100 ns tf in Fall time of input signal DI, CLK, CSN - 100 ns VCC = 5 V 1. DI timing parameters tested in production by a passed / failed test: Tj = -40 °C / +25 °C: SPI communication @ 2 MHz. Tj = +125 °C SPI communication @ 1.25 MHz. Table 15. Symbol DO Parameter Test condition VDOL Output low-level VCC = 5 V, ID = -2 mA VDOH Output high-level VCC = 5 V, ID = 2 mA Doc ID 16186 Rev 3 Min. Typ. Max. Unit 0.2 0.4 V VCC - 0.4 VCC - 0.2 V 15/35 Electrical specifications Table 15. L9954LXP DO (continued) Symbol Parameter IDOLK 3-state leakage current VCSN = VCC, 0V < VDO < VCC 3-state input capacitance VCSN = VCC, 0 V < VCC < 5.3 V CDO (1) Test condition Min. Typ. -10 10 Max. Unit 10 µA 15 pF 1. Value of input capacity is not measured in production test. Parameter guaranteed by design. Table 16. Symbol DO timing Parameter Test condition Typ. Max. Unit tr DO DO rise time CL = 100 pF, Iload = -1 mA - 80 140 ns tf DO DO fall time CL = 100 pF, Iload = 1 mA - 50 100 ns ten DO tri L DO enable time CL = 100 pF, Iload = 1 mA from 3-state to low-level pull up load to VCC - 100 250 ns tdis DO L tri DO disable time CL = 100 pF, Iload = 4 mA from low-level to 3-state pull up load to VCC - 380 450 ns ten DO tri H DO enable time from 3-state to highlevel CL =100 pF, Iload = -1 mA pull down load to GND - 100 250 ns tdis DO H tri DO disable time from high-level to 3state CL = 100 pF, Iload = -4 mA pull down load to GND - 380 450 ns DO delay time VDO < 0.3 VCC, VDO > 0.7 VCC, CL = 100pF - 50 250 ns td DO Table 17. CSN timing Symbol Parameter Test condition Min. Typ. Max. Unit tCSN_HI,stb CSN HI time, switching from standby mode Transfer of SPI command to Input Register 20 - - µs Transfer of SPI command to input register 4 - - µs tCSN_HI,min CSN HI time, active mode 16/35 Min. Doc ID 16186 Rev 3 L9954LXP Electrical specifications Figure 3. SPI - transfer timing diagram CSN high to low: DO enabled CSN time CLK 0 1 2 3 4 5 6 X 7 X 18 19 0 20 21 22 23 time DI: data will be accepted on the rising edge of CLK signal DI 0 1 2 3 4 5 6 7 X X 18 19 0 20 21 22 23 DO: data will change on the falling edge of CLK signal DO 0 1 2 3 4 5 6 7 X 18 19 20 21 22 23 Input Data Register old data 1 time 0 1 time CSN low to high: actual data is transfered to output power switches fault bit Figure 4. X 1 new data time SPI - input timing 0.8 VCC CSN 0.2 VCC t t set CSN t CLKH se t CLK 0.8 VCC CLK 0.2 VCC t set DI t hold DI t CLKL 0.8 VCC DI Valid Valid 0.2 VCC Doc ID 16186 Rev 3 17/35 Electrical specifications Figure 5. L9954LXP SPI - DO valid data delay time and valid time t f in t r in 0.8 VCC 0.5 VCC 0.2 VCC CLK t r DO DO (low to high) 0.8 VCC 0.2 VCC t d DO t f DO 0.8 VCC DO (high to low) 0.2 VCC Figure 6. SPI - DO enable and disable time tf in tr in 0.8 VCC 50% 0.2 VCC CSN DO pull-up load to VCC C L = 100 pF 50% ten DO tri L t dis DO L tri 50% DO pull-down load to GND C L = 100 pF ten DO tri H 18/35 Doc ID 16186 Rev 3 t dis DO H tri L9954LXP Electrical specifications Figure 7. SPI - driver turn-on / off timing, minimum CSN HI time CSN low to high: data from shi ft register is transferred to output power switches t t r in tCSN_HI,min f in 80% 50% 20% CSN tdOFF output voltage current output of aa driver driver of ON state OFF state t 80% 50% 20% OFF t dON t output voltage current output ofaa driver driver of Figure 8. ON OFF state 80% ON state 50% 20% SPI - timing of status bit 0 (fault condition) CSN high to low and CLK stays low: status information of data bit 0 (fault condition) is transfered to DO CSN time CLK time DI time DI: data is not accepted DO 0time DO: status information of data bit 0 (fault condition) will stay as long as CSN is low Doc ID 16186 Rev 3 19/35 Application information L9954LXP 3 Application information 3.1 Dual power supply: VS and VCC The power supply voltage VS supplies the half bridges and the high-side drivers. An internal charge-pump is used to drive the high-side switches. The logic supply voltage VCC (stabilized 5 V) is used for the logic part and the SPI of the device. Due to the independent logic supply voltage the control and status information not are lost, if there are temporary spikes or glitches on the power supply voltage. In case of power-on (VCC increases from under voltage to VPOR Off = 4.2 V) the circuit is initialized by an internally generated power-on-reset (POR). If the voltage VCC decreases under the minimum threshold (VPOR ON = 3.4 V), the outputs are switched to 3-state (high impedance) and the status registers are cleared. 3.2 Standby mode The standby mode of the L9954LXP is activated by clearing the bit 23 of the input data register 0. All latched data is cleared and the inputs and outputs are switched to high impedance. In the standby mode the current at VS (VCC) is less than 6 µA (50µA) for CSN = high (DO in 3-state). By switching the VCC voltage a very low quiescent current can be achieved. If bit 23 is set, the device is switched to active mode. 3.3 Inductive loads Each half bridge is built by an internally connected high-side and a low-side power DMOS transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs OUT1 to OUT3 without external free-wheeling diodes. The high-side drivers OUT4 to OUT6 are intended to drive resistive loads. Hence only a limited energy (E100μH) an external free-wheeling diode connected to GND and the corresponding output is needed. 3.4 Diagnostic functions All diagnostic functions (over/open-load, power supply over-/under voltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32 µs (open-load: 1ms, respectively) before the corresponding status bit in the status registers is set. The filters are used to improve the noise immunity of the device. Open-load and temperature warning function are intended for information purpose and not changes the state of the output drivers. On contrary, the overload condition disables the corresponding driver (over-current) and overtemperature switchs off all drivers (thermal shutdown). Without setting the over-current recovery bits in the input data register, the microcontroller has to clear the over-current status bits to reactivate the corresponding drivers. 20/35 Doc ID 16186 Rev 3 L9954LXP 3.5 Application information Overvoltage and under voltage detection If the power supply voltage VS rises above the overvoltage threshold VSOV Off (typical 21 V), the outputs OUT1 to OUT6 are switched to high impedance state to protect the load. When the voltage VS drops below the under voltage threshold VSUV Off (UV-switch-off voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). If the supply voltage VS recovers (register 0: bit 20=0) to normal operating voltage the outputs stages return to the programmed state after at least 32 µs. If the under voltage/overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. The microcontroller needs to clear the status bits to reactivate the drivers. It is strongly recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage. 3.6 Charge pump The charge pump runs under all conditions in normal mode. In standby the charge pump is out of action. 3.7 Temperature warning and thermal shutdown If junction temperature rises above Tj TW a temperature warning flag is set after at least 32 µs and is detectable via the SPI. If junction temperature increases above the second threshold Tj SD, the thermal shutdown bit is set and power DMOS transistors of all output stages are switched off to protect the device after at least 32 µs. Temperature warning flag and thermal shutdown bit are latched and must be cleared by the microcontroller. The related bit is only cleared if the temperature decreases below the trigger temperature. If the thermal shutdown bit has been cleared the output stages are reactivated. 3.8 Open-load detection The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (tdOL) the corresponding open-load bit is set in the status register. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads. 3.9 Overload detection In case of an over-current condition a flag is set in the status register in the same way as open-load detection. If the over-current signal is valid for at least tISC = 32 µs, the overcurrent flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. If the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver. Doc ID 16186 Rev 3 21/35 Application information 3.10 L9954LXP Current monitor The current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high-side driver. Signal at output CM is blanked after switching on of driver until correct settlement of circuitry (at least for 32 µs). The bits 18 and 19 of the input data register 0 control which of the outputs OUT1, OUT4, OUT5 and OUT6 is multiplexed to the current monitor output. The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. For example this can be used to detect the motor state (starting, free-running, stalled). Moreover, it is possible to regulate the power of the defroster more precise by measuring the load current. The current monitor output is bidirectional (c.f. PWM inputs). 3.11 PWM inputs Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface. If the PWM enable bit in Input data register 1 is set, the output is controlled by the logically AND-combination of the PWM signal and the output control bit in input data register 0. The outputs OUT1-OUT4 and OUT6 are controlled by the PWM1 input and the output OUT5 is controlled by the bidirectional input CM/PMW2. For example, the two PWM inputs can be used to dim two lamps independently by external PWM signals. 3.12 Cross-current protection The three half-bridges of the device are cross-current protected by an internal delay time. If one driver (LS or HS) is turned-off the activation of the other driver of the same half bridge is automatically delayed by the cross-current protection time. After the cross-current protection time is expired the slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver starts to conduct. 22/35 Doc ID 16186 Rev 3 L9954LXP 3.13 Application information Programmable soft start function to drive loads with higher inrush current Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable soft start function (i.e. overcurrent recovery mode). Each driver has a corresponding over-current recovery bit. If this bit is set, the device switchs automatically on the outputs again after a programmable recovery time. The duty cycle in over-current condition can be programmed by the SPI interface to be about 15 %...25 %. The PWM modulated current provides sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. The PWM frequency settles at 1.5 kHz or 3 kHz. The device itself cannot distinguish between a real overload and a non linear load like a light bulb. A real overload condition can only be qualified by time. As an example the microcontroller can switch on light bulbs by setting the over-current recovery bit for the first 50ms. After clearing the recovery bit the output is automatically disabled if the overload condition still exits. Figure 9. Programmable soft start function for inductive loads and incandescent bulbs Load Current Load Current Unlimited Inrush Current Unlimited Inrush Current Limited Inrush Current in overcurrent recovery mode with incandescent bulb Limited Inrush Current in overcurrent recovery mode with inductive load Overcurrent detection Overcurrent detection t Doc ID 16186 Rev 3 t 23/35 Functional description of the SPI L9954LXP 4 Functional description of the SPI 4.1 Serial Peripheral Interface (SPI) This device uses a standard SPI to communicate with a microcontroller. The SPI can be driven by a microcontroller with its SPI peripheral running in following mode: CPOL = 0 and CPHA = 0. For this mode, input data is sampled by the low to high transition of the clock CLK, and output data is changed from the high to low transition of CLK. This device is not limited to microcontroller with a build-in SPI. Only three CMOS compatible output pins and one input pin are needed to communicate with the device. A fault condition can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. The microcontroller can poll the status of the device without the need of a full SPI communication cycle. Note: In contrast to the SPI standard the least significant bit (LSB) is transferred first (see Figure 3). 4.2 Chip Select Not (CSN) The input pin is used to select the serial interface of this device. When CSN is high, the output pin (DO) is in high impedance state. A low signal activates the output driver and a serial communication can be started. The state when CSN is going low until the rising edge of CSN is called a communication frame. 4.3 Serial Data In (DI) The input pin is used to transfer data serial into the device. The data applied to the DI is sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register. At the rising edge of the CSN signal the contents of the shift register is transferred to data input register. The writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are counted within one frame the complete frame is ignored. This safety function is implemented to avoid an activation of the output stages by a wrong communication frame. Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. 4.4 Serial Data Out (DO) The data output driver is activated by a logical low-level at the CSN input and goes from high impedance to a low or high-level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin transfers the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK shifts the next bit out. 24/35 Doc ID 16186 Rev 3 L9954LXP 4.5 Functional description of the SPI Serial Clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the falling edge of the CLK signal. 4.6 Input Data Register The device has two input registers. The first bit (bit 0) at the DI input is used to select one of the two input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register is written to the selected input data register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of the selected status register is transferred to DO during the current communication frame. Bit 1-17 controls the behavior of the corresponding driver. If bit 23 is zero, the device goes into the standby mode. The bits 18 and 19 are used to control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status registers. The bits in the status registers is cleared after the current communication frame (rising edge of CSN). 4.7 Status register This devices uses two status registers to store and to monitor the state of the device. No error bit (bit 0) is used as a fault bit and is a logical-NOR combination of bits 1-22 in both status registers. The state of this bit can be polled by the microcontroller without the need of a full SPI communication cycle. If one of the over-current bits is set, the corresponding driver is disabled. If the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers goes into a high impedance state. Again the microcontroller has to clear the bit to enable the drivers. Doc ID 16186 Rev 3 25/35 Functional description of the SPI 4.8 L9954LXP SPI - input data and status registers Table 18. SPI - input data and status registers 0 Input register 0 (write) Status register 0 (read) Bit 23 22 21 20 Name Comment Enable bit Overvoltage/ undervoltage recovery disable If enable bit is set the device switches in active mode. If enable bit is cleared the device goes into standby mode and all bits are cleared. After power-on reset device starts in standby mode. Always 1 A broken VCC-or SPI connection of the L9954LXP can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. If reset bit is set both status registers are cleared after rising edge of CSN input. VS overvoltage If this bit is set the microcontroller has to clear the status register after under voltage / overvoltage event to enable the outputs. Depending on combination of bit 18 and 19 the current image (1/10.000) of the selected HS-output is multiplexed to the CM output: Current monitor select bits 26/35 Comment In case of an overvoltage or undervoltage event the corresponding bit is set and the outputs are deactivated. If OC recovery This bit defines in VS voltage recovers to normal duty cycle combination with the overoperating conditions outputs current recovery bit (input VS undervoltage are reactivated automatically register 1) the duty cycle (if bit 20 of status register 0 is 0: 12% 1: 25% in overcurrent condition of not set). an activated driver. Reset bit 19 18 Name Bit 19 Bit 18 Output 0 0 OUT6 1 0 OUT1 0 1 OUT4 1 1 OUT5 Doc ID 16186 Rev 3 Thermal shutdown In case of a thermal shutdown all outputs are switched off. The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs. Temperature warning The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit. Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is cleared automatically after start up time has finished. Since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times). L9954LXP Functional description of the SPI Table 18. SPI - input data and status registers 0 (continued) Input register 0 (write) Status register 0 (read) Bit Name Comment Name 17 OUT6 – HS on/off OUT6 – HS over-current 16 x (don’t care) 0 15 OUT5 – HS on/off OUT5 – HS over-current 14 OUT4 – HS on/off OUT4 – HS over-current 13 x (don’t care) 12 x (don’t care) 11 x (don’t care) 10 x (don’t care) 9 x (don’t care) 8 x (don’t care) 7 x (don’t care) 6 OUT3 – HS on/off 5 OUT3 – LS on/off 4 OUT2 – HS on/off 3 OUT2 – LS on/off OUT2 – LS over-current 2 OUT1 – HS on/off OUT1 – HS over-current 1 OUT1 – LS on/off OUT1 – LS over-current 0 If a bit is set the selected output driver is switched on. If the corresponding PWM enable bit is set (input register 1) the driver is only activated if PWM1 (PWM2) input signal is high. The outputs of OUT1-OUT3 are half bridges. If the bits of HSand LS-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from VS to GND. 0 0 0 0 0 0 0 0 OUT3 – HS over-current OUT3 – LS over-current OUT2 – HS over-current No error bit Doc ID 16186 Rev 3 Comment In case of an over-current event the corresponding status bit is set and the output driver is disabled. If the over-current recovery enable bit is set (input register 1) the output is automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (bit 21). If the over-current recovery bit is not set the microcontroller has to clear the over-current bit (reset bit) to reactivate the output driver. A logical NOR-combination of all bits 1 to 22 in both status registers. 27/35 Functional description of the SPI Table 19. L9954LXP SPI - input data and status registers 1 Input register 1 (write) Status register 1 (read) Bit Name Comment 23 Enable bit If enable bit is set the device is switched in active mode. If enable bit is cleared device goes into standby mode and all bits are cleared. After poweron reset device starts in standby mode. 22 OUT6 OC recovery enable VS overvoltage 21 x (don’t care) VS undervoltage 20 19 18 28/35 OUT5 OC recovery enable OUT4 OC recovery enable In case of an over-current event the over-current status bit (status register 0) is set and the output is switched off. If the over current recovery enable bit is set the output is automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle (bit 21 of input data register 0). Depending on occurrence of overcurrent event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero. x (don’t care) Doc ID 16186 Rev 3 Name Comment Always 1 A broken VCC or SPI connection of the L9954LXP can be detected by the microcontroller, because all 24 bits low or high is not a valid frame. In case of an overvoltage or under voltage event the corresponding bit is set and the outputs are deactivated. If VS voltage recovers to normal operating conditions outputs are reactivated automatically. In case of a thermal shutdown all outputs are switched off. The Thermal shutdown microcontroller has to clear the TSD bit by setting the reset bit to reactivate the outputs. Temperature warning The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown. The microcontroller has to clear the TW bit. Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. This bit is only present during start up time. Since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times). L9954LXP Functional description of the SPI Table 19. SPI - input data and status registers 1 (continued) Input register 1 (write) Status register 1 (read) Bit Name Comment Name 17 Enable high RDSon OUT5 16 x (don’t care) 0 15 x (don’t care) OUT5 – HS open-load 14 OUT3 OC recovery enable 13 OUT2 OC recovery enable 12 OUT1 OC recovery enable 0 11 OUT6 PWM1 enable 0 10 x (don’t care) 0 9 OUT5 PWM2 enable 0 8 OUT4 PWM1 enable 7 x (don’t care) 6 Enable high RDSon OUT4 5 x (don’t care) 4 x (don’t care) 3 OUT3 PWM1 enable OUT2– LS open-load 2 OUT2 PWM1 enable OUT1 – HS open-load 1 OUT1 PWM1 enable OUT1 – LS open-load 0 Comment OUT6 – HS open-load After 50ms the bit can be cleared. If over-current condition still exists, a wrong load can be assumed. OUT4 – HS open-load 0 If the PWM1/2 enable bit is set and the output is enabled (input register 0) the output is switched on if PWM1/2 input is high and switched off if PWM1/2 input is low. OUT5 is controlled by PWM2 input. All other outputs are controlled by PWM1 input. 1 0 0 OUT3 – HS open-load OUT3 – LS open-load OUT2 –HS open-load No error bit Doc ID 16186 Rev 3 The open-load detection monitors the load current in each activated output stage. If the load current is below the open-load detection threshold for at least 1 ms (tdOL) the corresponding open-load bit is set. Due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3 ms) can be used to test the openload status without changing the mechanical/electrical state of the loads. A logical NORcombination of all bits 1 to 22 in both status registers. 29/35 Packages thermal data 5 L9954LXP Packages thermal data Figure 10. Packages thermal data 30/35 Doc ID 16186 Rev 3 L9954LXP Package and packing information 6 Package and packing information 6.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.2 PowerSSO-36 package information Figure 11. PowerSSO-36 package dimensions Doc ID 16186 Rev 3 31/35 Package and packing information Table 20. L9954LXP PowerSSO-36 mechanical data Millimeters Symbol 32/35 Min. Typ. Max. A 2.15 - 2.47 A2 2.15 - 2.40 a1 0 - 0.075 b 0.18 - 0.36 c 0.23 - 0.32 D 10.10 - 10.50 E 7.4 - 7.6 e - 0.5 - e3 - 8.5 - G - - 0.1 G1 - - 0.06 H 10.1 - 10.5 h - - 0.4 L 0.55 - 0.85 N - - 10 deg X 4.3 - 5.2 Y 6.9 - 7.5 Doc ID 16186 Rev 3 L9954LXP 6.3 Package and packing information PowerSSO-36 packing information Figure 12. PowerSSO-36 tube shipment (no suffix) Base Qty Bulk Qty Tube length (±0.5) A B C (±0.1) C B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 13. PowerSSO-36 tape and reel shipment (suffix “TR”) Reel dimensions Base Qty Bulk Qty A (max) B (min) C (±0.2) F G (+2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (±0.1) P D (±0.05) D1 (min) F (±0.1) K (max) P1 (±0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets sealed with cover tape. User direction of feed Doc ID 16186 Rev 3 33/35 Revision history 7 L9954LXP Revision history Table 21. 34/35 Document revision history Date Revision Description of changes 12-Feb-2010 1 Initial release. 17-May-2010 2 Table 20: PowerSSO-36 mechanical data: – Changed X: minimum value from 4.1 to 4.3 and maximum value from 4.7 to 5.2 – Changed Y: minimum value from 6.5 to 6.9 and maximum value from 7.1 to 7.5 19-Sep-2013 3 Updated disclaimer. Doc ID 16186 Rev 3 L9954LXP Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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