L99CL01XP
8 channel high-side LED driver for automotive applications
Datasheet - production data
Applications
Automotive interior lighting
Automotive exterior lighting
Description
*$3*&)7
The L99CL01XP is designed to provide a cost
effective solution for exterior and interior
automotive lighting applications with LEDs.
PowerSSO-36
Features
Octal fully protected high-side switches with
programmable overcurrent threshold and
RDSON
Split supply for flexible application
assignment (6 V to 24V)
SPI communication interface with daisy
chain capability
Digital diagnosis individually for each switch
Analogue current sense output with SPI
programmable multiplexer
Integrated synchronous PWM module with
programmable phase shift, pulse skipping
feature and quick access via direct drive pins
Improved EMC behavior by phase shift
control and output edge shaping
Limp home function with 6 independent
direct drive pins
Integrated fail mode handling
Ultra low power mode (< 5 µA max at 25°C)
Table 1. Device summary
Order code
Package
PowerSSO-36
September 2013
This is information on a product in full production.
Tube
Tape and real
Root part number 1
L99CL01XPTR
DocID023902 Rev 4
1/60
www.st.com
1
Contents
L99CL01XP
Contents
1
2
3
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Power supply (VS, GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2
VDD (logic interface supply voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3
ENABLE (active high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1
Switch supply terminals (VSA, VSB, VSC and VSD) . . . . . . . . . . . . . . . . .11
2.2
Power Outputs [OUT1 ~ OUT8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3
Current Sense (CS) – analog diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Control inputs (IN1, IN2, IN3, IN5, IN6, IN7) . . . . . . . . . . . . . . . . . . . . . . 12
2.5
PWMCLK input / wake output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PWMCLK input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5.2
WAKE output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
Limp input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7
Control, protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7.1
Smart switches and gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7.2
PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.7.3
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7.4
External resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7.5
Channel voltage level comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7.6
Device protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
3.2
2/60
2.5.1
SPI communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1
CSN (chip select (active low)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2
SCK (serial input clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3
SDI (serial data input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.4
SDO (serial data output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.5
Control Data Registers (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1.6
Status Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.1
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.2.2
Wake up and operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID023902 Rev 4
L99CL01XP
4
5
Contents
7
Cold start – power up reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.4
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.2.5
Fail Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2.6
Warm start – (Transition from FailMode to Normal over Internal Reset) 44
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1
6
3.2.3
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2
PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DocID023902 Rev 4
3/60
List of tables
L99CL01XP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
4/60
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PWM mode selection for OUTx (x = 1, 2, 3, 5, 6 or 7) when INx is disabled . . . . . . . . . . . 14
PWM mode selection for OUTx (x = 1, 2, 3, 5, 6 or 7) when INx is enabled and INx = 0 . . 15
PWM mode selection for OUTx (x = 1, 2, 3, 5, 6 or 7) when INx is enabled and INx = 1 . . 15
Examples of settings for INSELx[1:0] and PWMSELx[1:0] resulting in OUTx states, which
are independent from INx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Examples of settings for INSELx[1:0] and PWMSELx[1:0] resulting in OUTx states, which
are dependent from INx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM mode selection for OUT4 and OUT8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Duty cycle selection (PSF enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CDR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Control Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SDR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Status Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Mapping between the input pins and the outputs in Fail Mode. . . . . . . . . . . . . . . . . . . . . . 42
Events leading to Fail Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Control registers in Fail Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Digital timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Electrical characteristics (logic + inputs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dynamic characteristics (SPI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Switching (VS = 12 V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical characteristics (OUT1 - OUT8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
DocID023902 Rev 4
L99CL01XP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Toggle signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Fail mode status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Rthj-amb vs PCB copper area in open box free air condition (one channel ON) . . . . . . . . . 54
PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DocID023902 Rev 4
5/60
Block diagram and pin description
1
L99CL01XP
Block diagram and pin description
Figure 1. Application block diagram
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6/60
DocID023902 Rev 4
L99CL01XP
Block diagram and pin description
Figure 2. Device block diagram
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DocID023902 Rev 4
&6
*$3*&)7
7/60
Block diagram and pin description
L99CL01XP
Figure 3. Configuration diagram (top view)
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Table 2. Pin function
Pin
Symbol
1,18
GND
Ground:
This terminal is the ground for the logic and analogue circuitry of the device.
2
REXT
External Resistor:
The Resistor is used to improve internal current precision.
3
VDD
Logic supply voltage:
SPI and logic I/O structure power supply.
4
CS
5
6
7,8,
9,10,
11,12
8/60
Function
Current sense output:
This terminal is used to supply a current proportional to the output current in the
power output stages. The selection of the output is SPI programmable.
Enable (active high):
ENABLE This input enables the device. After wakeup the internal configuration is in
default state. The terminal has an internal pull down resistor.
LIMP
Limp home input (active high):
The fail mode of the component can be activated by logic [1] at this input. The
LIMP state is internally filtered by a 10ms digital filter. This terminal has an
internal pull down resistor.
Direct Drive input 1,2,3,5,6,7:
IN1, IN2, These inputs enable the device and are used to control the corresponding power
IN3, IN5, outputs 1,2,3,5,6,7 in case of fail mode (direct drive). During normal mode the
IN6, IN7 control of the outputs is SPI programmable. All input terminals have an internal
pull down resistor.
DocID023902 Rev 4
L99CL01XP
Block diagram and pin description
Table 2. Pin function (continued)
Pin
Function
CSN
SPI chip select input (active low):
When this digital signal is logical [1], SPI signals are ignored. Asserting this
terminal [0] an SPI transaction starts. The transaction is indicated as complete
when this signal returns to [1]. This terminal has an internal pull up resistor.
14
SDO
SPI data-out:
SPI data is sent to the microcontroller by this terminal. This data output changes
on the positive edge of SCLK. When CSN is [1], this terminal is at high
impedance.
15
SDI
SPI data-in:
This data input is sampled on the negative edge of the SCK. The terminal has an
internal pull down resistor.
16
SCK
SPI clock input:
This digital input terminal is connected to the controller providing the clock (up to
4MHz) for SPI communication. The terminal has an internal pull down resistor.
13
17
Note:
Symbol
PWM clock input, (WAKE output if ENABLE low):
This clock defines the frequency of the internal generated PWM. The terminal
PWMCLK has an internal pull down resistor.
If ENABLE is low, this pin is used as a WAKE output. This output indicates if
another wakeup source, beside ENABLED, is active.
Power output 1~8:
Fully protected high-side switches with individually programmable RDSON and
over current shutdown threshold.
The output current is up to 1A per channel. However the total current of the
device is limited due to the max power dissipation of the component and the
total thermal resistance/capacitances of the PCB.
The outputs OUT1~OUT3 and OUT5~OUT7 are controlled by the corresponding
inputs IN1, IN2, IN3, IN5, IN6, IN7 during fail mode (OUT4 and OUT8 are off).
During normal mode the outputs are controlled by the internal PWM generator or
the selected direct drive input.
19, 22,
23, 26,
29, 32,
33, 36
OUT1 ~
OUT8
20, 21
VSD
Supply voltage pins for outputs 7 and 8.
Pins must be tied together on PCB.
24, 25
VSC
Supply voltage pins for outputs 5 and 6.
Pins must be tied together on PCB.
27, 28
VS
30, 31
VSB
Supply voltage pins for outputs 3 and 4.
Pins must be tied together on PCB.
34, 35
VSA
Supply voltage pins for outputs 1 and 2.
Pins must be tied together on PCB.
Battery supply voltage:
Power supply terminal.
The Heat Slug is internally connected to GND.
DocID023902 Rev 4
9/60
Block diagram and pin description
1.1
L99CL01XP
Power supply (VS, GND)
The VS terminal is the power supply pin of the device and it is also used to supply the
internal logic of the device. This pin is protected against reverse battery conditions without
any external components, down to -24 V.
Overvoltage and undervoltage events on the VS pin are reported by the OVF, respectively
the UVF status bits (refer to Device Status #2). Once one of these events has occurred, the
corresponding status bit is latched.
The GND is the signal ground and power ground terminal of the device.
1.2
VDD (logic interface supply voltage)
The VDD is the logic interface supply voltage terminal, used to supply the SPI
communication interface and logic I/Os of the device.
The VDD is monitored by an internal circuitry. In case an under voltage condition is
detected, the L99CL01XP enters the Fail Mode after the filter time tVDD_UV.
1.3
ENABLE (active high)
The ENABLE is used to enable the device by the microcontroller (normal mode).
When the ENABLE input is
logic [0] the device is in standby mode (WAKE output enabled)
logic [1] the device is in active mode (PWMCLK input enabled)
ENABLE has an internal pull down resistor.
Please check for other wakeup sources the Section 2.4: Control inputs (IN1, IN2, IN3, IN5,
IN6, IN7).
10/60
DocID023902 Rev 4
L99CL01XP
Functional description
2
Functional description
2.1
Switch supply terminals (VSA, VSB, VSC and VSD)
The device has four groups of output supplies in order to achieve flexible application fuse
assignment. The VSA terminal is the drain (power supply pin) of the output switches 1 and
2, while VSB is the supply of switches 3 and 4, VSC is the supply of switches 5 and 6 and
VSD is the supply of switches 7 and 8. The supply pins belonging to the same supply group
must be connected together in order to ensure proper current capability for PowerMOS
devices.
Overvoltage and undervoltage events on the VSX pins are reported by the corresponding
OVF_X, respectively the UVF_X status bits (refer to Device Status #3). Once one of these
events has occurred, the corresponding status bit is latched, the corresponding outputs are
latched off and the OUTENx (see control register OUT enable, #10) is set to 0.
The device is fully protected against loss of any supply terminal.
2.2
Power Outputs [OUT1 ~ OUT8]
The power outputs are used to control LED arrays with either integrated current source or
series resistors.
Each output offers a fully protected p-channel MOSFET (programmable Ron) driver with
digital switch diagnosis and analogue current sense circuitry. Paralleling of two or more
outputs is possible in order to reduce power dissipation without restriction in performance.
The outputs are protected against:
output over load and short circuit (incl. very low resistive short circuit and shorts with
line inductance)
overtemperature
overvoltage/undervoltage
The digital switch diagnosis by SPI communication (see Section 3.1.6: Status Data
Registers) contains reporting of
overcurrent shutdown status
overtemperature shutdown status incl. over temperature warning status
undervoltage/overvoltage status
In case of undervoltage, thermal shutdown or overcurrent the corresponding OUT is
switched off with edge shaping to reduce internal power dissipation in case of hard short.
In normal mode, after a thermal shutdown, an overcurrent, an undervoltage or overvoltage
at VSA, VSB, VSC or VSD, the corresponding outputs are latched off until a read and clear
command of the corresponding status register is sent.
In fail mode, an overtemperature of an output leads to a latch off, whereas, an auto restart
strategy is implemented after an overcurrent, an undervoltage or overvoltage at VSA, VSB,
VSC or VSD.
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Functional description
2.3
L99CL01XP
Current Sense (CS) – analog diagnosis
The current sense terminal delivers a current which is proportional to the output current.
Depending on the programmed RDSON [#9] (see Section 3.1.5: Control Data Registers
(CDR)) the ratio is defined to IOUT/1000 for 1 and IOUT/2000 for 600m.
The MUX[2:0] bits select which output channel is connected to the CS pin [#0:D7~D4] (see
Section 3.1.5: Control Data Registers (CDR)).
Fast output settling is provided in order to enable processing with synchronous sampling
and peak detector as well as diagnosis at very small duty cycle.
2.4
Control inputs (IN1, IN2, IN3, IN5, IN6, IN7)
The control inputs are used to
provide wakeup capability (see Section 3.2.2: Wake up and operating modes).
directly control the corresponding outputs during fail mode (see Section 3.2.5: Fail
Mode).
control the outputs during normal mode, when the output control is enabled by SPI
register [#11, #12 and #13]. By default, the Control Inputs (INx) are disabled. For more
detail see Section 2.7.2: PWM module.
The inputs have internal pull down resistors.
2.5
PWMCLK input / wake output pin
2.5.1
PWMCLK input
When the device is enabled with the ENABLE pin to logic ‘1’, the pin acts as an input with
which the PWM frequency is generated from PWMCLK terminal by the integrated PWM
module (see Section 2.7.2: PWM module).
The clock input frequency is the factor 256 of the PWM switching frequency.
(fPWM=100Hz…400Hz=>fCLK=25.6kHz…102.4kHz). Therefore the internal PWM module
provides an 8-bit resolution PWM.
The PWM module is disabled in case of PWMCLK failure and the outputs are set according
to the OUTxEN control bits (control register #10). The status bit PCLKF is set (Status
register #3, bit3). This bit is latched until a Read and Clear command is sent to this register.
A PWMCLK failure is detected when the frequency at the PWMCLK input is lower than 5kHz
(tpos_lock_edge+1 - tpos_lock_edge > 1/5kHz => failure). This failure is reported in the SPI
register [#1:D3] (see Section 3.1.6: Status Data Registers).
The input terminal has an internal pull down resistor.
2.5.2
WAKE output
When the device is not enabled via the ENABLE, this pin is used as an output to indicate the
wake state of the device which is related to the INx pins.
[0] no wakeup source detected
[1] INx wakeup source detected or 2sec wake timer running
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L99CL01XP
2.6
Functional description
Limp input
The fail mode (limp home mode) of the component is activated by this digital input port in
addition to the internal fail mode detection circuit of the device (see Section 3.2.5: Fail
Mode).
The limp home mode is activated by a logic [1] signal at the input. During limp home mode
the outputs are directly controlled by the inputs IN1, IN2, IN3, IN5, IN6, IN7. and the PWM
module is disabled.
The limp input has an internal pull down resistor.
2.7
Control, protection and diagnosis
2.7.1
Smart switches and gate drivers
The smart switches are controlled by dedicated gate driver including:
Output pulse shaping
Overload protection incl. protection against low resistive short circuit and shorts with
line inductance
Over temperature protection incl. over temperature warning signals
The outputs are switched with active pulse shaping to provide an excellent EMC
performance of the system.
Therefore the output current of each driver is monitored by a feedback loop in order to
control the switching speed of the output. Thereby a compromise between edge shaping
and propagation delay of the switch is necessary to achieve low duty cycle values (3% < dc
< 97% @ 250Hz).
2.7.2
PWM module
PWM control
In order to minimize the microcontroller’s work load, a synchronous PWM module is
integrated. The frequency and timing is derived from the PWMclock input (see
Section 2.5.1: PWMCLK input), the control of the PWM module is provided by SPI and INx
(see Section : PWM control)
The smart switches can be controlled in the range of 0%...100% with a resolution of
1/256%. The value 00h in the Individual and Global PWM registers refers to OFF state, the
value FFh refers to 255/256 ON state of the switches. The PWM timing includes 4
programmable switching phases (0°, 90°, 180° and 270°). The phase can be controlled
individually for each channel depending on the channel control registers [#1~#8 D10~D9]
The synchronization of the switching phases between different devices is provided by the
PWMsync bit in Initialisation register [#0:D8].
To guarantee a proper generation and smooth PWM duty cycle change via SPI the duty
cycle start point is defined by the internal PWM counter zero crossing. Therefore every SPI
programmed duty cycle change and duty cycle source change will not take effect till the
PWM counter zero crossing is reached (this strategy is also known as buffered PWM).
Setting the output to OFF or 100% ON, the setting will occur immediately and independently
from PWM counter.
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Functional description
L99CL01XP
For generation of output duty cycles close to 100% the pulse skipping feature is integrated
(see Pulse skipping feature).
The PWM module is disabled in case of
fail mode (direct drive)
clock input signal failure (controlled by PWMxEN register)
PWM module in normal mode with OUTENx bit = 1
This section describes the PWM control modes for OUT1-8, provided that the corresponding
OUTENx bit is set (OUTx is enabled).
If OUTENx bit = 0, the corresponding output is disabled.
PWM control modes in normal mode for OUTx (x = 1, 2, 3, 5, 6 or 7)
In normal mode, the state of the OUTx, x=1,2,3,5,6 or 7 is determined by the combinations
between INSELx[1:0], PWMSELx[1:0] and the state of INx, provided that OUTENx bit is set
to 1.
3 cases must be considered:
Case 1: direct input INx is disabled (INSELx[1:0] = [0,0])
Case 2: direct input INx is enabled (INSELx[1:0] [0,0]) and INx = Low
Case 3: direct input INx is enabled (INSELx[1:0] [0,0]) and INx = High
Case 1: INx is disabled: The output behaves according to the Table 3.
Table 3. PWM mode selection for OUTx (x = 1, 2, 3, 5, 6 or 7) when INx is disabled
State of OUTx
OUTENx
INx
INSELx1
INSELx0
PWMSELx1
PWMSELx0
1
X(1)
0
0
0
0
Individual PWM
1
X
0
0
0
1
GPWM1
1
X
0
0
1
0
GPWM2
1
X
0
0
1
1
100% ON
x = 1, 2, 3, 5, 6 or 7
1. X: do not care.
Individual PWM selected:
In this mode the PWM control of the channels is provided individually for each channel
by the corresponding channel control register [#1~#8:D7~D0].
GPWM1 selected:
in this mode the PWM control of the switches is provided by the global PWM1 value
[#14:D7~D0].
GPWM2 selected:
in this mode the PWM control of the switches is provided by the global PWM2 value
[#15:D7~D0].
100% ON selected:
In this mode the output is fully on.
OFF selected:
In this mode the output is OFF.
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L99CL01XP
Functional description
Case 2: direct input INx is enabled (INSELx[1:0] [0,0]) and INx = Low
In this case, the state of the output is independent from the settings of PWMSELx[1:0]. It is
determined only by setting of INSELx[1:0] according to the Table 4.
Table 4. PWM mode selection for OUTx (x = 1, 2, 3, 5, 6 or 7) when INx is enabled and
INx = 0
State of OUTx
INx
INSELx1
INSELx0
PWMSELx1
PWMSELx0
Low
0
1
X(1)
X
GPWM1
Low
1
0
X
X
GPWM2
Low
1
1
X
X
OFF
x = 1, 2, 3, 5, 6 or 7
1. X: do not care.
Case 3: direct input INx is enabled (INSELx[1:0] [0,0]) and INx = High
If the direct input INx is High, the state of the output is independent from the settings of
INSELx[1:0]. It is determined only by the setting of PWMSELx[1:0] according to the Table 5.
Table 5. PWM mode selection for OUTx (x = 1, 2, 3, 5, 6 or 7) when INx is enabled and
INx = 1
State of OUTx
OUTxEN
INx
INSELx1
INSELx0
PWMSELx1
PWMSELx0
1
High
X(1)
X
0
0
Individual PWM
1
High
X
X
0
1
GPWM1
1
High
X
X
1
0
GPWM2
1
High
X
X
1
1
100% ON
x = 1, 2, 3, 5, 6 or 7
1. X: do not care, provided that INSELx[1:0] is different from [0,0]
Table 6 and Table 7 show some examples of SPI settings resulting in states of OUTx, which
are independent (Table 6) or dependent (Table 7) from the levels at INx. Other settings are
possible.
Table 6. Examples of settings for INSELx[1:0] and PWMSELx[1:0] resulting in OUTx
states, which are independent from INx
OUTxEN
INx
INSELx1
INSELx0
PWMSELx1
PWMSELx0
State of OUTx
x = 1, 2, 3, 5, 6 or 7
0
X(1)
X
X
X
X
OFF
1
X
0
0
1
1
100% ON
1
X
0
0
0
0
Individual PWM
1
X
0
1
0
1
GPWM1
1
X
1
0
1
0
GPWM2
1. X: do not care.
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Functional description
L99CL01XP
Table 7. Examples of settings for INSELx[1:0] and PWMSELx[1:0] resulting in OUTx
states, which are dependent from INx.
OUTxEN
INSELx1
INSELx0
PWMSELx1
PWMSELx0
State of OUTx
x = 1, 2, 3, 5, 6 or 7
1
1
1
0
0
(Individual PWM) AND (INx)
1
1
1
0
1
(GPWM1) AND (INx)
1
1
1
1
0
(GPWM2) AND (INx)
1
1
1
1
1
According to INx
PWM control modes in normal mode for OUTx, x = 4 or 8, if OUTENx = 1
OUT4 and OUT8 do not have any direct input or INSELx[1:0] control bits. In normal mode,
their behaviour is only determined by the control registers PWMSEL4[1:0] and
PWMSEL8[1:0], according to the following table:
Table 8. PWM mode selection for OUT4 and OUT8
PWMSELx1
PWMSELx0
State of OUTx
x = 4 or 8
0
0
Individual PWM
0
1
GPWM1
1
0
GPWM2
1
1
100% ON
Pulse skipping feature
Due to the output pulse shaping feature and the thereof resulting propagation delay time of
the smart switches, the duty cycle range close to 100% can not be generated by the device.
Therefore the pulse skipping feature (PSF) is integrated to generate this output duty cycle
range in normal mode.
The pulse skipping consists of fixed duty cycle patterns with 8 PWM cycles.
When the corresponding PSF bit [#1~#8:D8] is set, the PWM values 97.25%...99.61%
(C3h…C7h) are generated individually for each channel by modulation of the duty cycle in
discrete steps by the pulse skipping logic according to the following table:
Table 9. Duty cycle selection (PSF enabled)
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Duty Cycle
(%)
HEX
(9bit)
#1
#2
#3
#4
#5
#6
#7
#8
100.00%
0x100
256
256
256
256
256
256
256
256
99.61%
0x0FF
248
256
256
256
256
256
256
256
99.22%
0x0FE
248
256
256
256
248
256
256
256
98.82%
0x0FD
248
248
256
256
256
248
256
256
98.43%
0x0FC
248
248
256
256
248
248
256
256
98.04%
0x0FB
248
248
248
256
256
248
248
256
DocID023902 Rev 4
L99CL01XP
Functional description
Table 9. Duty cycle selection (PSF enabled) (continued)
Duty Cycle
(%)
HEX
(9bit)
#1
#2
#3
#4
#5
#6
#7
#8
97.65%
0x0FA
248
248
248
256
248
248
248
256
97,25%
0x0F9
248
248
248
248
248
248
248
256
The PSF is started with the next PWM cycle after SPI communication. The start step
number can not be guaranteed. In reset condition PSFx = [0], the pulse skipping feature is
disabled.
The PSF is not available in Fail Mode.
2.7.3
Overcurrent detection
The over current shutdown threshold (IOC) combined with the RDSON can be programmed
individually for each switch in two different levels by SPI command Mode Control
[#9: D7~D0] (see Section 3.1.5: Control Data Registers (CDR)):
when RON bit is [0] the over current shutdown threshold is 1.5 A and the RDSON is
600 m
when RON bit is [1] the over current shutdown threshold is 750 mA and the RDSON is
1
The setting of the RON bits can be monitored by SDO register Mode Control [#9:D7~D0]
(see Section 3.1.6: Status Data Registers).
In case of overcurrent failure the corresponding OUTxEN bit is automatically reset and the
corresponding OCx status bit is set. This bit is latched once an OC event is detected.
To reset the diagnosis register, the condition has to be removed and an SPI read and clear
operation of the corresponding register has to be performed.
2.7.4
External resistor
To achieve the precise internal slope control and timings, an accurate external resistor is
needed.
The resistance has to be 12.4 k (1% tolerance) connected to GND.
If the resistor is removed or shorted, an RFAIL failure is reported via SPI [#1:D2] (see
Section 3.1.6: Status Data Registers).
2.7.5
Channel voltage level comparator
In addition to the digital diagnosis a multiplexed channel OUT voltage comparator is
implemented. The compared threshold is 5 V.
The channel is selected via the MUXEN and the MUX2:1 bits in the Control Data Register
[#0:D7:4]. The OUTL bit can be found in the Status Data Registers [#5,#6,#7,#8:D7].
2.7.6
Device protection
A protection strategy enables light functionality even in case of failures inside the
component of the light module.
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Functional description
L99CL01XP
Therefore the component is protected against
loss of any supply line
loss of communication interface and PWMCLK fail
Reverse polarity protection
VS has an integrated active reverse polarity protection. VSA, VSB, VSC and VSD have to
be protected against reverse polarity by using external protection devices (i.e. series
diodes) in the battery supply lines.
Loss of supply lines
The device is protected against loss of any supply line.
During loss of
VS: the device can not drive any loads, and no communication via SPI is possible. The
Device is in Power Down Mode (refer to Figure 4: State diagram). When a valid VS
voltage is applied again, the content of the registers are set to their default value. This
event is reflected in the Reset bit, at the first SPI access.
VSA, VSB, VSC or VSD: the device can not drive the corresponding load group, but
sends UVF_A / UVF_B / UVF_C or UVF_D flag via SPI to the microcontroller.
VDD: if the condition VDD < VDDUV is present for more than tVDDUV, the device enters
in Fail Mode. The refreshing of the WD is disabled as long as VDD < VDDUV.
All I/O lines have to be protected by external series resistors.
Loss of communication interface
The following failures are considered as a loss of SPI communication: loss of SCK or CSN,
or CSN is stuck to High or Low. These failures are detected by the monitoring of the WD bit.
In case of WD time-out, the device enters Fail Mode and the failure is reported by the status
bit WDCERR (#1,bit 1).
Note:
A short circuit of CSN to Low for a duration exceeding CSN time-out, additionally causes
SDO to go in tri-state, in order to avoid a blocking of the whole SPI bus.
If SDI stuck to High of Low, or if the number of SCK cycles is not a multiple of 16, during a
SPI transaction, the device directly enters Fail Mode. Moreover the status register SPIF is
set (#1, bit 5).
Logic Input supervision
The logic inputs are supervised by the device with different check strategies and
consequential failures:
Table 10. Error handling
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Input/Output
Signal check strategy
System failure reaction
PWM Clock
frequency too low
No PWM feature
a PWMCLK Fail is reported
SPI
WD bit time-out
Fail Mode
SPI
SDI, SCK, CSN stuck at High or Low
Fail Mode
SPI
SCK fail
Fail Mode
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L99CL01XP
3
SPI interface
SPI interface
A 16 bit SPI interface (fmax = 2 MHz) is used for control and diagnosis of the component.
The SPI offers daisy-chain-capability to provide high data rate, minimum circuit overheads
and overall synchronization of multiple PWM modules.
During each SPI cycle a 16 bit word is transferred into the control register of each device
and a 16 bit word is received from each device.
The data includes the toggling of a watchdog bit, which indicates the proper operation of the
SPI interface. The watchdog bit has to be toggled by every SPI access starting after reset
with ‘0’.
3.1
SPI communication
3.1.1
CSN (chip select (active low))
The CSN terminal enables the SPI communication with the microcontroller:
the SDO output driver is enabled
the device status data is latched to the output shift registers on the falling edge of the
CSN
the input shift register data is latched into the addressed registers on the rising edge of
CSN
CSN has an internal pull up resistor and a CSN timeout is implemented. If CSN is kept low
for a duration, which is longer than tCSN time-out, the incoming frame is considered as
invalid and the SDO goes to tri-state. The CSN time-out avoids that a short circuit of CSN to
GND blocks the SPI bus.
3.1.2
SCK (serial input clock)
The SCK terminal clocks the internal shift registers of the device.
The SDI terminal accepts data into the input shift register on the falling edge of the SCK
signal, while the SDO terminal shifts output data to the SDO line driver on the rising edge of
the SCK signal (MCU setting: CPHA = 1; CPOL = 0).
The SCK terminal has to be in logic [0] state whenever CSN makes any transition.
When CSN is logic [1] state, signals at the SCK and SDI inputs are ignored and SDO driver
output is in tri-state condition (high impedance). The L99CL01XP requires a number of SCK
cycles, which is a multiple of 16, during an SPI transaction. If this condition is not met, the
device enters Fail Mode.
SCK has an internal pull down resistor.
3.1.3
SDI (serial data input)
The SDI pin is the data input terminal of the SPI communication interface.
The input has an internal pull down resistor. Writing all [0] or all [1] to SDI within one SPI
frame will generate an SPI fail (stuck @ error).
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SPI interface
L99CL01XP
The implemented SPI requires a 16 bit stream of serial data, starting with D15 and ending
with D0.
3.1.4
SDO (serial data output)
The SDO pin is the data output terminal of the SPI communication interface.
The SDO terminal is in tri-state condition unless CSN input is in logic [0] state. When CSN is
in logic [0] state, the data from the output shift registers is sent via the SDO pin.
The SDO terminal changes the state at the rising edge of the SCK input and reads out on
the falling edge of SCLK.
3.1.5
Control Data Registers (CDR)
The data sent to the device will be latched into the internal Control Registers with the rising
edge of CSN after a valid SPI cycle is performed.
The written data can be read back by setting the RAMREAD bit D9 in the Initialization
register #0. After Reset all registers are by default [0] (except SDOA0 is [1]).
CDR base address = 0x00h
The CDR register are shown in Table 11: CDR registers
Table 11. CDR registers
Register
Address offset
Reset value
0x00h
0x0001h
Address #1 CHx control
0x01h
0x1000h
Address #2 CHx control
0x02h
0x2000h
Address #3 CHx control
0x03h
0x3000h
Address #4 CHx control
0x04h
0x4000h
Address #5 CHx control
0x05h
0x5000h
Address #6 CHx control
0x06h
0x6000h
Address #7 CHx control
0x07h
0x7000h
Address #8 CHx control
0x08h
0x8000h
Address #9 mode control
0x09h
0x9000h
Address #10 OUT enable
0x0Ah
0xA001h
Address #11 PWMSEL / INSEL CH1 + CH2
0x0Bh
0xB000h
Address #12 PWMSEL / INSEL CH3 + CH4 + CH5
0x0Ch
0xC001h
Address #13 PWMSEL / INSEL CH6 + CH7 + CH8
0x0Dh
0xD000h
Address #14 Global PWM1
0x0Eh
0xE000h
Address #15 Global PWM2
0x0Fh
0xF000h
Initialization Register
Address #1-#8 CHx control
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L99CL01XP
SPI interface
11
10
9
8
7
Address
WD
RAM READ
PWMsync
MUXEN
15
NO CLEAR
Initialization Register
14
13
12
R
R/W
R/W
R/W
R/W
R/W
Address:
Base address + 0x00h
Type:
R, R/W
Reset:
0x0001h
Note:
6
5
4
3
2
1
0
MUX2 MUX1 MUX0 SOA3 SOA2 SOA1 SOA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Writing all [0] to this register will generate a SPI fail (stuck @ ‘0’).
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10 NOCLEAR: With this bit set to:
0: every read access clears the read out status bits
1: any reported status from the read and clear flags are not cleared by a read
The clear of the read and clear flags will be re-enabled by writing a [0] to this bit.
Bit 9 READRAM: With this bit set to:
0: the addressed status data register (see Section 3.1.4: SDO (serial data output)) is
sent back via SDO
1: the addressed control data register is sent back via SDO. This is to verify the written
data in the device.
Note:
The read back of the Status Data Registers will be re-enabled by
writing a [0] to this bit.
Bit 8 PWMsync: internal PWM counter reset. Writing a ‘1’ to this Register will reset the
internal PWM counter after valid SPI command and CSN high. This bit is automatically
reset after synchronization.
Bit 7 MUXEN: Enable current sense output and the OUT voltage level comparator
0: CS pin disabled / OUT voltage comparator disabled (default)
1: CS pin enable / OUT voltage comparator enabled (see MUX[2:0]) setting
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SPI interface
L99CL01XP
Bit 6:4 MUX[2:0]: Binary decoded selection of current sense output and the OUT voltage level
comparator
000: Channel 1 selected (default
001: Channel 2 selected
010: Channel 3 selected
011: Channel 4 selected
100: Channel 5 selected
101: Channel 6 selected
110: Channel 7 selected
111: Channel 8 selected
Bit 3:0 SDOA[3:0]: Address of next SDO data word (also see READRAM bit)
0000: READRAM = 0: Address #1 selected, else Address #0
0001: Address #1 selected (default)
0010: Address #2 selected
0011: Address #3 selected
0100: Address #4 selected
0101: Address #5 selected
0110: Address #6 selected
0111: Address #7 selected
1000: Address #8 selected
1001: Address #9 selected
1010: Address #10 selected
1011: Address #11 selected
1100: Address #12 selected
1101: Address #13 selected
1110: Address #14 selected
1111: Address #15 selected
Address #1-#8 CHx control
15
14
11
10
9
8
Address
13
12
WD
PHx1
PHx0
PSFx
R
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
R/W
Address:
Base address + 0x0Yh (Y = 0x01h to 0x08h)
Type:
R, R/W
Reset:
0xY000h
R/W
R/W
R/W
R/W
R/W
R/W
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
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IxDC7 IxDC6 IxDC5 IxDC4 IxDC3 IxDC2 IxDC1 IxDC0
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L99CL01XP
SPI interface
Bit 10:9 PHx[1:0]: Binary decoded PWM phase shift selection (0°, 90°, 180°, 270°)
00: 0° Phase (default)
01: 90° Phase
10: 180° Phase
11: 270° Phase
Bit 8 PSFx: Pulse skipping enable
0: disabled
1: enabled
Bit 7:0 DCx7:0: Channel individual duty cycle programmable from 0x00 to 0xFF
DutyCycle value in % DC[%] = value*100/256
0x00h: 0%
0x01h: 0.39%
0x02h: 0.78%
....
0xFFh: 99.61%
Address #9 mode control
15
14
13
12
11
10
Address
WD
res
0
R
R/W
R
R
Address:
Base address + 0x09h
Type:
R, R/W
Reset:
0x9000h
9
8
7
OCBLN RON8
R/W
R/W
6
5
4
3
2
1
0
RON7 RON6 RON5 RON4 RON3 RON2 RON1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10 Reserved bits have to be written with 0
Bit 9 0
Bit 8 OCBLN: OC Blanking disable
0: OC blanking = 150us blanking after OUTx on enabled (default)
1: OC blanking = 150us blanking after OUTx on disabled
Bit 7:0 RON8:1: Defines over current threshold and RDSON value
0: OC threshold = 1.5A and RDSON = 600m (OL high threshold) (default)
1: OC threshold = 750mA and RDSON = 1 (OL low threshold)
DocID023902 Rev 4
23/60
SPI interface
L99CL01XP
11
10
9
8
Address
WD
res
res
res
OUT7EN
OUT6EN
OUT5EN
OUT4EN
OUT3EN
OUT2EN
OUT1EN
15
OUT8EN
Address #10 OUT enable
14
13
12
R
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Base address + 0x0Ah
Type:
R, R/W
Reset:
0xA001h
7
6
5
4
3
2
1
0
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10:8 Reserved bits have to be written with 0
Bit 7:0 OUTEN8:1: Enables the Output in Normal Mode. In case of OVx, UVx, TSDx or OCx the
corresponding bits are cleared and therefore the OUTx is switched off.
0: disabled (default)
1: enabled (OUT corresponding INSELx, PWMSELx and INx)
11
10
9
8
Address
WD
res
res
res
INSEL20
PWMSEL21
PWMSEL20
INSEL11
INSEL10
PWMSEL11
PWMSEL10
15
INSEL21
Address #11 PWMSEL / INSEL CH1 + CH2
14
13
12
R
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Base address + 0x0Bh
Type:
R, R/W
Reset:
0xB000h
7
6
5
4
3
2
1
0
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10:8 Reserved bits have to be written with 0
Bit 7:6 - Bit 3:2 INSELx[1:0]: INx function selector see Section 2.7.2: PWM module
Bit 5:4 - Bit 1:0 PWMSELx[1:0]: PWM function selector see Section 2.7.2: PWM module
24/60
DocID023902 Rev 4
L99CL01XP
SPI interface
11
10
Address
WD
res
INSEL50
PWMSEL51
PWMSEL50
PWMSEL41
PWMSEL40
INSEL31
INSEL30
PWMSEL31
PWMSEL30
15
INSEL51
Address #12 PWMSEL / INSEL CH3 + CH4 + CH5
14
13
12
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Base address + 0x0Ch
Type:
R, R/W
Reset:
0xC001h
9
8
7
6
5
4
3
2
1
0
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10 Reserved bits have to be written with 0
Bit 9:8 - Bit 3:2 INSELx[1:0]: INx function selector see Section 2.7.2: PWM module
Bit 7:4 - Bit 1:0 PWMSELx[1:0]: PWM function selector see Section 2.7.2: PWM module
11
10
Address
WD
res
PWMSEL80
INSEL71
INSEL70
PWMSEL71
PWMSEL70
INSEL61
INSEL60
PWMSEL61
PWMSEL60
15
PWMSEL81
Address #13 PWMSEL / INSEL CH6 + CH7 + CH8
14
13
12
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Base address + 0x0Dh
Type:
R, R/W
Reset:
0xD000h
9
8
7
6
5
4
3
2
1
0
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10 Reserved bits have to be written with 0
Bit 7:6 - Bit 3:2 See Section 2.7.2: PWM module
Bit 5:4 - Bit 1:0 See Section 2.7.2: PWM module
DocID023902 Rev 4
25/60
SPI interface
L99CL01XP
11
10
9
8
Address
WD
0
0
0
G1DC6
G1DC5
G1DC4
G1DC3
G1DC2
G1DC1
G1DC0
15
G1DC7
Address #14 Global PWM1
14
13
12
R
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address:
Base address + 0x0Eh
Type:
R, R/W
Reset:
0xE000h
7
6
5
4
3
2
1
0
Bit 15:12 Address
Bit 11
Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI access)
Bit 10:8
0
Bit 7:0
G1DCx: Global 1 duty cycle programmable from 0x00 to 0xFF:
DutyCycle value in %; DC[%] = value * 100/256
0x00h: 0%
0x01h: 0.39%
0x02h: 0.78%
....
0xFFh: 99.61%
Note:
11
10
9
8
Address
WD
0
0
0
G2DC6
G2DC5
G2DC4
G2DC3
G2DC2
G2DC1
G2DC0
15
G2DC7
Address #15 Global PWM2
14
13
12
R
R/W
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
6
5
4
Writing all [1] to this register will generate a SPI fail (stuck @ ‘1’).
Address:
Base address + 0x0Fh
Type:
R, R/W
Reset:
0xF000h
26/60
7
DocID023902 Rev 4
3
2
1
0
L99CL01XP
SPI interface
Bit 15:12 Address
Bit 11 WD: Watchdog toggle bit (75ms, start with [0] after Reset, toggled with every SPI
access)
Bit 10:8 0
Bit 7:0 G2DCx: Global 2 duty cycle programmable from 0x00 to 0xFF
DutyCycle value in %; DC[%] = value * 100/256
0x00h: 0%
0x01h: 0.39%
0x02h: 0.78%
....
0xFFh: 99.61%
All SDI input data values, are latched into the registers at the rising edge of CSN if the
communication is valid (multiple of 16 SCKs and data consistency check).
DocID023902 Rev 4
27/60
Address
Control data
Register
#
D15 D14 D13 D12 D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Initialization
0
0
0
0
0
WD NO CLEAR
RAM READ
PWMsync
MUXEN
MUX2
MUX1
MUX0
SOA3
SOA2
SOA1
SOA0
CH1 control
1
0
0
0
1
WD
PH11
PH10
PSF1
I1DC7
I1DC6
I1DC5
I1DC4
I1DC3
I1DC2
I1DC1
I1DC0
CH2 control
2
0
0
1
0
WD
PH21
PH20
PSF2
I2DC7
I2DC6
I2DC5
I2DC4
I2DC3
I2DC2
I2DC1
I2DC0
CH3 control
3
0
0
1
1
WD
PH31
PH30
PSF3
I3DC7
I3DC6
I3DC5
I3DC4
I3DC3
I3DC2
I3DC1
I3DC0
CH4 control
4
0
1
0
0
WD
PH41
PH40
PSF4
I4DC7
I4DC6
I4DC5
I4DC4
I4DC3
I4DC2
I4DC1
I4DC0
CH5 control
5
0
1
0
1
WD
PH51
PH50
PSF5
I5DC7
I5DC6
I5DC5
I5DC4
I5DC3
I5DC2
I5DC1
I5DC0
CH6 control
6
0
1
1
0
WD
PH61
PH60
PSF6
I6DC7
I6DC6
I6DC5
I6DC4
I6DC3
I6DC2
I6DC1
I6DC0
CH7 control
7
0
1
1
1
WD
PH71
PH70
PSF7
I7DC7
I7DC6
I7DC5
I7DC4
I7DC3
I7DC2
I7DC1
I7DC0
I8DC0
DocID023902 Rev 4
CH8 control
8
1
0
0
0
WD
PH81
PH80
PSF8
I8DC7
I8DC6
I8DC5
I8DC4
I8DC3
I8DC2
I8DC1
Mode control
9
1
0
0
1
WD
res
0
OCBLN
RON8
RON7
RON6
RON5
RON4
RON3
RON2
RON1
OUT enable
10
1
0
1
0
WD
res
res
res
OUT8EN
OUT7EN
OUT6EN
OUT5EN
OUT4EN
OUT3EN
OUT2EN
OUT1EN
PWMSEL / INSEL
CH1 + CH2
11
1
0
1
1
WD
res
res
res
INSEL21
INSEL20
PWMSEL21
PWM
SEL20
INSEL11
INSEL10
PWMSEL11
PWMSEL10
PWMSEL / INSEL
12
CH3 + CH4 + CH5
1
1
0
0
WD
res
INSEL51
INSEL50
PWM
SEL51
PWM
SEL50
PWMSEL41
PWMSEL40
INSEL31
INSEL30
PWMSEL31
PWMSEL30
PWMSEL / INSEL
13
CH6 + CH7 + CH8
1
1
0
1
WD
res
PWMSEL81
PWMSEL80
INSEL71
INSEL70
PWMSEL71
PWMSEL70
INSEL61
INSEL60
PWMSEL61
PWMSEL60
Global PWM1
14
1
1
1
0
WD
0
0
0
G1DC7
G1DC6
G1DC5
G1DC4
G1DC3
G1DC2
G1DC1
G1DC0
Global PWM2
15
1
1
1
1
WD
0
0
0
G2DC7
G2DC6
G2DC5
G2DC4
G2DC3
G2DC2
G2DC1
G2DC0
L99CL01XP
Table 12. Control Data Register
SPI interface
28/60
L99CL01XP
Status Data Registers
By accessing the Status Registers, the read and clear flags are cleared after rising CSN
edge. All read and clear flags are latched and keep the status till read out. All other flags
report the actual status and are therefore not clearable. By setting the NOCLEAR flag D10
in Initialisation register #0, this automatic clear is prohibited.
If a flag is set during read out phase the flag is latched and will be reported with the next
read.
The SPI output delivers the data set programmed by the bits D9 (READRAM option) and
D3:0 (SDOA3:0) inside the control data register [#0] of the SPI:
SDR base address = 0x00h
The SDR register are shown in Table 13: SDR registers
Table 13. SDR registers
Register
Address offset
Reset value
Address #0
0x00h
0x00h
Address #1 Device Status 1
0x01h
0x00h
Address #2 Device Status 2
0x02h
0x00h
Address #3 Device Status 3
0x03h
0x00h
Address #4 Quick Status
0x04h
0x00h
Address #5 Status CH1+CH2
0x05h
0x00h
Address #6 Status CH31+CH4
0x06h
0x00h
Address #7 Status CH5+CH6
0x07h
0x00h
Address #8 Status CH7+CH8
0x08h
0x00h
Address #9 Mode Control
0x09h
0x00h
Address #10 OUT enable
0x0Ah
0x00h
Address #11 INx Status
0x0Bh
0x00h
Address #12 Silicon Version
0x0Ch
0x01h
Address #5-#8 Status CHx+CHy
Address #0
A read access to Status Register #0 is not allowed. It is interpreted as SDO is shorted to "0"
and lead the device to enter Fail Mode
11
10
9
8
7
6
5
4
3
2
1
0
Address
SVF
X(1)
DSF
VDDF
SPIF
LIMP
PCLKF
RFAIL
WDC ERR
15
CHIP RESET
Address #1 Device Status 1
FAILSAFE
3.1.6
SPI interface
14
13
12
WDC0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
DocID023902 Rev 4
29/60
SPI interface
L99CL01XP
Address:
Base address + 0x01h
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: logical OR combination of all OV, UV, OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7 CHIP RESET: indicates if all registers are previously reset, cleared with the first SPI
read (by default #1)
0: device has not been previously reset
1: all registers are in reset state (cleared with first valid SPI command after reset)
Bit 6 VDDF: VDD fail occurred
0: no VDD fail detected
1: VDD fail detected
Bit 5 SPIF: SPI clock fail or SDI stuck @ detected
0: no SPI fail detected
1: SPI fail detected (SPI clock cycles during a transaction is not a multiple of 16, stuck @
0 or 1 at SDI detected)
Bit 4 LIMP: LIMP pin high detected
0: no LIMP high detected
1: LIMP high detected
Bit 3 PCLKF: PWMCLK fail detected
0: no PWMCLK fail detected
1: PWMCLK fail detected
Bit 2 RFAIL: External R failure detected
0: R external connected correctly
1: R external fail detected
Bit 1 WDCERR: WDC time-out or WD toggle bit fail detected
0: no watchdog failure
1: watchdog fail detected
Bit 0 WDC0: WDC 50% flag
0: watchdog 50% time-out not reached
1: watchdog 50% time-out reached
30/60
DocID023902 Rev 4
L99CL01XP
SPI interface
15
11
10
9
8
7
6
5
4
3
2
1
0
Address
FAILSAFE
Address #2 Device Status 2
14
13
12
SVF
X(1)
DSF
0
0
0
0
TSD
TW
OVF
UVF
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
Address:
Base address + 0x02h
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OV, UV, OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: Logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7:4 0
Bit 2 TW: Logical OR combination of all TWx
0: no thermal warning detected
1: thermal warning detected
Bit 1 OVF: OverVoltage at VS detected
0: no over voltage detected
1: over voltage detected (OVF is latched once an overvoltage on VS is detected)
Bit 0 UVF: UnderVoltage at VS detected
0: no under voltage detected
1: under voltage detected (UVF is latched once an undervoltage on VS is detected)
11
10
9
8
Address
SVF
X(1)
DSF
OVF_A
UVF_A
OVF_B
UVF_B
OVF_C
UVF_C
OVF_D
UVF_D
15
FAILSAFE
Address #3 Device Status 3
14
13
12
7
6
5
4
3
2
1
0
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
DocID023902 Rev 4
31/60
SPI interface
L99CL01XP
Address:
Base address + 0x03h
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: Logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7 OVF_A(1): OverVoltage at VSA detected
0: no over voltage detected
1: over voltage detected, OUT1EN and OUT2EN are cleared automatically (channel
OFF)
Bit 6 UVF_A(1): UnderVoltage at VSA detected
0: no under voltage detected
1: under voltage detected, OUT1EN and OUT2EN are cleared automatically (channel
OFF)
Bit 5 OVF_B(1): OverVoltage at VSB detected
0: no over voltage detected
1: over voltage detected, OUT3EN and OUT4EN are cleared automatically (channel
OFF)
Bit 4 UVF_B(1): UnderVoltage at VSB detected
0: no under voltage detected
1: under voltage detected, OUT3EN and OUT4EN are cleared automatically (channel
OFF)
Bit 3 OVF_C(1): OverVoltage at VSC detected
0: no over voltage detected
1: over voltage detected, OUT5EN and OUT6EN are cleared automatically (channel
OFF)
32/60
DocID023902 Rev 4
L99CL01XP
SPI interface
Bit 2 UVF_C(1): UnderVoltage at VSC detected
0: no under voltage detected
1: under voltage detected, OUT5EN and OUT6EN are cleared automatically (channel
OFF)
Bit 1 OVF_D(1): OverVoltage at VSD detected
0: no over voltage detected
1: over voltage detected, OUT7EN and OUT8EN are cleared automatically (channel
OFF)
Bit 0 UVF_D(1): UnderVoltage at VSD detected
0: no under voltage detected
1: under voltage detected, OUT7EN and OUT8EN are cleared automatically (channel
OFF)
1. OVF_X and UVF_X are latched, once an overvoltage, respectively, and undervoltage is detected on VS_X.
15
11
10
9
8
7
Address
FAILSAFE
Address #4 Quick Status
14
13
12
SVF
X(1)
DSF
QSF8
R
R/W
R/W
R
R/W
R/W
6
5
QSF7 QSF6
R/W
R/W
4
3
QSF5
QSF4
R/W
R/W
2
1
QSF3 QSF2
R/W
R/W
0
QSF1
R/W
1. X: do not care
Address:
Base address + 0x04h
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7:0 QSFx[7:0]: channel specific logical OR combination of TSDx or TWx_th2 or TWx_th1 or
OCx or OLx
0: no fail detected
1: fail detected
DocID023902 Rev 4
33/60
SPI interface
L99CL01XP
13
12
11
10
9
8
Address
SVF
X(1)
DSF
R
R/W
R/W
R
R/W
7
6
OUTL TSDxy
R/W
R/W
5
4
3
2
1
0
TWxyth1
14
TWxyth2
15
FAILSAFE
Address #5-#8 Status CHx+CHy
OCy
X(1)
OCx
X(1)
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
Address:
Base address + 0x0Yh (Y = 0x05 to 0x08h)
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7 OUTL: logical read back value of selected [#0:D7~D4] OUTx channel. This information
can be used to distinguish between open load and short to VSx in OFF state.
0: OUTx is low
1: OUTx is high
Bit 6 TSDxy: thermal shutdown flag of channel x or y
0: no thermal shutdown detected
1: thermal shutdown detected, the corresponding OUTxEN are cleared automatically
(channel OFF). TSDxy is latched off once an thermal shutdown occured.
Bit 5 TWxy_th2: thermal warning threshold2 flag of channel x or y
0: no thermal warning detected
1: thermal warning detected. This bit is not latched. Once the temperature on outputs
x/y is below TjTW2, this status bit is reset.
Bit 4 TWxy_th1: thermal warning threshold1 flag of channel x or y
0: no thermal warning detected
1: thermal warning detected
Bit 3, 1 OCx/y: channel specific over current flag
1: overcurrent detected, the corresponding OUTxEN is cleared automatically (channel
OFF)
Bit 2, 0 X: do not care
34/60
DocID023902 Rev 4
L99CL01XP
SPI interface
11
10
9
8
Address
SVF
X(1)
DSF
RON8
RON7
RON6
RON5
RON4
RON3
RON2
RON1
15
FAILSAFE
Address #9 Mode Control
14
13
12
7
6
5
4
3
2
1
0
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
Address:
Base address + 0x09h
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7:0 RON8:1: Copy of over current threshold and RDSON value defined in input register #9
0: OC threshold = 1.5A and RDSON = 500m (OL high threshold)
1: OC threshold = 750mA and RDSON = 1 (OL low threshold)
11
10
9
8
Address
SVF
X(1)
DSF
OUT8EN
OUT7EN
OUT6EN
OUT5EN
OUT4EN
OUT3EN
OUT2EN
OUT1EN
15
FAILSAFE
Address #10 OUT enable
14
13
12
7
6
5
4
3
2
1
0
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
DocID023902 Rev 4
35/60
SPI interface
L99CL01XP
Address:
Base address + 0x0Ah
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7:0 OUTEN8:1: Copy of output enable in Normal Mode status defined in input register #10
0: disabled
1: enabled (OUT corresponding INSELx and PWMSELx)
15
11
10
9
8
7
6
5
4
3
2
1
0
Address
FAILSAFE
Address #11 INx Status
14
13
12
SVF
X(1)
DSF
0
IN7
IN6
IN5
0
IN3
IN2
IN1
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1. X: do not care
Address:
Base address + 0x0Bh
Type:
R, R/W
Reset:
0x00h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
36/60
DocID023902 Rev 4
L99CL01XP
SPI interface
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7:4 - Bit 2:0 IN7, IN6, IN5, IN3, IN2, IN1: corresponding INx pin value
0: input logical [0] detected
1: input logical [1] detected
Bit 3 0
DocID023902 Rev 4
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SPI interface
L99CL01XP
15
11
10
9
8
7
6
5
4
3
2
1
0
Address
FAILSAFE
Address #12 Silicon Version
14
13
12
SVF
X(1)
DSF
0
0
0
0
SV3
SV2
SV1
SV0
R
R/W
R/W
R
R/W
R
R
R
R
R/W
R/W
R/W
R/W
1. X: do not care
Address:
Base address + 0x0Ch
Type:
R, R/W
Reset:
0x01h
Bit 15:12 Address
Bit 11 FAILSAFE:
0: Device is in Normal Mode
1: Device is in Fail Mode (DirectDrive enabled)
Bit 10 SVF: Logical OR combination of all OVx, UVx
0: supply voltage in operating range
1: supply voltage failure
Bit 9 X: do not care
Bit 8 DSF: logical OR combination of VDDF or SPIF or LIMP or PCLKF or RFAIL or
WDCERR
0: no fail detected
1: fail detected
Bit 7:4 0
Bit 3:0 SV3:0: Binary coded version of Silicon
0001: Silicon version
38/60
DocID023902 Rev 4
Address
Register
#
Control data
D1 D1 D1 D1
5
4
3
2
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DocID023902 Rev 4
NA
0
0
0
0
0
X(2)
X
X
X
X
X
X
X
X
X
X
X
Device status 1
1
0
0
0
1
FAIL SAFE
SVF
X
DSF
CHIP
RESET
VDDF
SPIF
LIMP
PCLKF
RFAIL
WDC
ERR
WDC0
Device status 2
2
0
0
1
0
FAIL SAFE
SVF
X
DSF
0
0
0
0
TSD
TW
OVF
UVF
Device status 3
3
0
0
1
1
FAIL SAFE
SVF
X
DSF
OVF_A
UVF_A
OVF_B
UVF_B
OVF_C
UVF_C
OVF_D
UVF_D
Quick status
4
0
1
0
0
FAIL SAFE
SVF
X
DSF
X
X
X
X
X
X
X
X
Diag CH1 + 2
5
0
1
0
1
FAIL SAFE
SVF
X
DSF
OUTL
TSD12
TW12th2
TW12th1
OC2
X
OC1
X
Diag CH3 + 4
6
0
1
1
0
FAIL SAFE
SVF
X
DSF
OUTL
TSD34
TW34th2
TW34th1
OC4
X
OC3
X
Diag CH5 +6
7
0
1
1
1
FAIL SAFE
SVF
X
DSF
OUTL
TSD56
TW56th2
TW56th1
OC6
X
OC5
X
Diag CH7 + 8
8
1
0
0
0
FAIL SAFE
SVF
X
DSF
OUTL
TSD78
TW78th2
TW78th1
OC8
X
OC7
X
Mode control
9
1
0
0
1
FAIL SAFE
SVF
X
DSF
RON8
RON7
RON6
RON5
RON4
RON3
RON2
RON1
OUT enable
1
0
1
0
1
0
FAIL SAFE
SVF
X
DSF
OUT8EN
OUT7EN
OUT6EN
OUT5EN
OUT4EN
OUT3EN
OUT2EN
OUT1EN
INx status
1
1
1
0
1
1
FAIL SAFE
SVF
X
DSF
0
IN7
IN6
IN5
IN4
IN3
IN2
IN1
Silicon version
1
2
1
1
0
0
FAIL SAFE
SVF
X
DSF
0
0
0
0
SV3
SV2
SV1
SV0
SPI interface
39/60
Table 14. Status Data Register(1)
1. Grey cells: read and clear flags.
2. X: do not care.
L99CL01XP
SPI interface
L99CL01XP
3.2
Operating modes
3.2.1
Standby mode
The standby mode is the default mode of the device after power on (VS > VSUV) without
applying any wake up signals (High signal on one of the INx pins or on EN pin).
During standby mode
3.2.2
The current consumption of the device is minimized (VDD, VS, VSx)
The internal circuitry is deactivated
All outputs are OFF and protected against mistreatment
Wake up and operating modes
The device leaves the standby mode if one of the following wake-up events occurs. Refer to
Figure 4:
Figure 4. State diagram
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DocID023902 Rev 4
("1($'5
L99CL01XP
SPI interface
Wakeup sources are as follows:
ENABLE
input signals IN1, IN2, IN3, IN5, IN6, IN7
toggle signal: this signal is an OR combination from all input signals by a retriggerable
mono stable. It keeps the device active for a dedicated time (ttoggle) after the last
negative edge at any input signal IN1, IN2, IN3, IN5, IN6, IN7:
Figure 5. Toggle signal
t_toggle
IN1 or IN2 or IN3 or IN5
or IN 6 or IN7
toggle
When ENABLE is off but another wakeup source is still active this can be monitored by the
PWMCLK(WAKE) pin which is an active high output during pending WAKE.
By leaving the FailMode all internal registers will be reset to default state.
3.2.3
Cold start – power up reset
The cold start sequence describes the power up and the startup of the device. When VS is
in the specified ranges and the INx or the ENABLE pin are on a logical [0] level the device is
in STANDBY. When INx or ENABLE change their levels to logical [1] the internal EN for the
power on reset circuit (POR) and the oscillator (OSC) will be set to [1] and the two blocks
will be enabled. The device is started. The internal POR is released and the oscillator is
running. The internal registers are reset. to their default value and the device enter
NORMAL MODE
3.2.4
Normal Mode
The device enters Normal mode:
either from Standby Mode if VDD > VDDUV, LIMP =Low, and EN goes from Low to
High. Refer to Section 3.2.3: Cold start – power up reset
or from Fail Mode, refer to Section 3.2.6: Warm start – (Transition from FailMode to
Normal over Internal Reset)
In Normal mode, the SPI is active and the output stages are controlled by the SPI and the
INx settings. The SPI diagnostics and the CurrentSense pin are both available. The
protections are fully functional.
Normal mode is left with the following conditions:
VDD falls below VDDUV
A watchdog failure occurs: wrong toggling of WD Bit or No toggling of the WD bit for a
duration exceeding TWD
EN goes Low
An SPI failure occurs
LIMP goes to Low
DocID023902 Rev 4
41/60
SPI interface
3.2.5
L99CL01XP
Fail Mode
The L99CL01XP offers the possibility to control OUT1-3 and OUT5-7 in case of fail safe
event by the corresponding INx pins (refer to Table 15)
Table 15. Mapping between the input pins and the outputs in Fail Mode
Pin
Corresponding output
IN1
OUT1
IN2
OUT2
IN3
OUT3
IN5
OUT5
IN6
OUT6
IN7
OUT7
The Fail Mode is activated if one of the conditions listed in the following table occurs. The
operation in Fail Mode is reported by the status bit Fail Safe (any Status Register, bit11) and
by one of the status bits: VDDUV, SPIF, WDCERR, LIMP, depending on the cause of the
activation of the Fail Mode.
Table 16. Events leading to Fail Mode
Event
Related status bit
Delay to Fail Mode
VDDUV
After tVDD_UV
SPIF
Immediate
WDCERR
After WDTimeout
LIMP
After tLIMP
WDCERR
After WDTimeout
VDD undervoltage
SPI Failure
Watchdog check error
LIMP = High
During Active Mode, EN goes from High to Low
while one of the INx,x= 1-3, 5-6 is High (1)
1. When this condition occurs, the device prevents the refresh of the WD toggle bit, leading to a Watchdog
timeout failure. As long as EN = Low, the refresh of the WD is blocked and the device cannot go to Normal
Mode.
In this mode, the device’s SPI is active unless a VDD undervoltage occurs.
The control registers behaves as described in the Table 17. The content of the status
registers are kept during the transition to Fail Mode.
Table 17. Control registers in Fail Mode
Control registers
42/60
Content during transition
to Fail Mode
Write protection
Valid content
Initialization, #0
As before Fail mode
No
Yes
CHx Control, #1-8
As before Fail mode
No
No(1)
Mode Control, #9
Reset to default value
Yes(2)
Yes
OUT enable, #10
As before Fail mode
No
No(2)
DocID023902 Rev 4
L99CL01XP
SPI interface
Table 17. Control registers in Fail Mode
Control registers
Content during transition
to Fail Mode
Write protection
Valid content
PWMEN/INSEL, #11-13
As before Fail mode
No
No(2)
Global PWMx, #1-2
As before Fail mode
No
No(2)
1. The PWM unit is disabled and the state of OUTx is according to the corresponding INx,x=1-3,5-7
regardless to the content of these registers. OUT4 and OUT8 are OFF.
2. While entering the Fail Mode, the content of the Mode Control register is reset to its default value and the
device behaves accordingly: the Rdson of the Output is set to the low value and the overcurrent blank time
is enabled. This control register is write-protected in Fail Mode.
The current sense is active and the Kfactor is the one, which corresponds to the Low Ron
setting.
Auto restart feature
The auto restart feature is used to control the smart switches in case of overcurrent, under
or over voltage failure conditions to provide a high availability of the outputs even when no
supervising intelligence of the microcontroller is available (Fail Mode).
Auto restart is enabled in case of
Overcurrent condition (OCx) of the corresponding channel
Under or over voltage condition (UVx or OVx) on the corresponding supply line
In case of OC, UV or OV the corresponding output or outputs are deactivated. In case of OC
failure the output returns to Fail Mode direct drive after a dedicated time
(tautorestart = 100 ms). During this ON phase the diagnosis is restarted. When the failure is
still present and the channel is turned off again. Therefore the output stays in this cyclic loop
as long as the failure is present.
In case of UV or OV the diagnosis is continuously running. After removing the failure
condition (UV or OV) the switch returns to Fail Mode direct drive after a dedicated time
within tautorestart.
In case of over temperature shutdown (OTS) the switch enters “Latch OFF” state which can
only be removed by a mode change to “Normal Mode” or “Standby” (seeChapter 3.2:
Operating modes).
DocID023902 Rev 4
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SPI interface
L99CL01XP
Figure 6. Fail mode status diagram
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3.2.6
Warm start – (Transition from FailMode to Normal over Internal Reset)
Due to a possible unknown state of the internal registers a reset of the device is necessary
by leaving FAIL mode. Therefore a reset is generated when the device leaves FAIL mode
with two consecutive valid SPI commands with WD ‘0’ and WD ‘1’. This is only possible
when ENABLE is logical [1] and the failure is removed (read and clear) before the two
consecutive SPI commands are sent. This kind of reset has no impact on the POR and the
OSC.
Figure 7. Reset mode
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44/60
DocID023902 Rev 4
L99CL01XP
Electrical specifications
4
Electrical specifications
4.1
Absolute maximum rating
Stressing the device above the rating listed in Table 18 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
condition above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table 18. Absolute maximum rating
Symbol
VSA, VSB,
VSC, VSD
Parameter
Test condition
Supply voltage range for channel
couples A, B, C and D
Value
Unit
Short circuit; single pulse;
Tj = 25°C(1)
6 to 24
V
Short circuit; repetitive pulse;
-40°C < Tj < 150°C(1)
6 to 20
V
40
V
-24
V
-0.3 to VDD+0.3
V
5
mA
-1.5 to VS+0.3
V
load dump (400 ms)
range(2)
VSREV
reverse polarity voltage
VIO
logic input voltage range
Iin clamp
input clamping current
VOUT
Output voltage range
Maximum value of each pin
VCLAMP_high
OUTx, INx, LIMP, CSN, ENABLE, VS,
VSA, VSB, VSC, VSD
42
V
VCLAMP_low
SDO, SDI, SCK, PWMCLK, CS, VDD,
REXT
7
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
VS(3), GND, OUT1 ~ OUT8
±4
kV
All other pins
±2
kV
1000
V
Tj
Tstg
Electrostatic discharge (Human Body
Model, 100pF/1,5k)
VESD
Charge device model (CDM-AECQ100-011)
1. Also valid for VSA, VSB, VSC, VSD < 6 V
2. Valid for VS.
3. Valid for VSA, VSB, VSC, VSD.
DocID023902 Rev 4
45/60
Electrical specifications
4.2
L99CL01XP
Thermal data
Table 19. Temperature warning and thermal shutdown
Symbol
Parameter
Min.
Typ.
Max.
Unit
TjTW1(1)
Temperature warning threshold junction
temperature
125
165
°C
TjTW2(1)
Temperature warning threshold junction
temperature
135
175
°C
TjTSD(1)
Thermal shutdown threshold junction temperature
155
195
°C
1. Parameter guaranteed by design and characterization; not subject to production test.
Table 20. Thermal data
Symbol
Parameter
Typ. value
Unit
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(2)
48.5
°C/W
51-7)(2)(3)
19.5
°C/W
Rthj-amb Thermal resistance junction-ambient (JEDEC JESD
2
1. Device mounted on two-layers 2s0p PCB with 2 cm heatsink copper trace
2. One channel ON.
3. Device mounted on four-layers 2s2p PCB
Table 21. Digital timings
Symbol
Parameter
fINT
tTSD(1)
tVDD_UV
(1)
tVS_OV/UV(1)
tLIMP(1)
tREXTF
(1)
tTOGGLE(1)
tAUTORESTART
(1)
tWD(1)
tOC(1)
tOCBLANK
(1)
tCSN timeout
(1)
Min.
Typ.
Max.
Unit
Internal oscillator clock frequency
1.75
2
2.25
MHz
Internal TWx and TSD filter time
20
25
30
µs
VDDUV detection time
20
25
30
µs
VS UV/OV detection time
20
25
30
µs
Limp mode settling time
0.9
1.15
1.4
ms
R extern fail deglitch time
20
25
30
µs
Input toggle time
1.65
2.1
2.55
s
Auto restart delay time
100
130
160
ms
Watchdog timeout
60
75
90
ms
Overcurrent shutdown delay time
40
50
60
µs
OC blanking time
160
200
240
µs
CSN timeout
100
130
160
ms
1. Parameter guaranteed by design and characterization; not subject to production test.
46/60
DocID023902 Rev 4
L99CL01XP
4.3
Electrical specifications
Electrical characteristics
VS = 6 V to 24 V, VDD = 4.5 V to 5.5 V, Tj = -40°C to 150°C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 22. Electrical characteristics (logic + inputs)
Symbol
Parameter
Test condition
Min.
VDD
Digital I/O supply voltage range
3.0
VDDUV
Digital I/O supply undervoltage
threshold at Tj = 25°C
2.0
Typ.
2.5
Digital I/O supply undervoltage
VDDUVHyst threshold hysteresis at Tj =
25°C
IDD
Supply current in ON-state from
VDD
IQDD
Standby current consumption
from VDD at Tj = 25°C
VSUV
Battery supply under voltage
flag at Tj = 25°C(1)
5.0
5.5
Max. Unit
5.5
V
3.0
V
0.4
V
500
µA
5
µA
6.0
V
0.4
V
VSUVHyst
Battery supply undervoltage flag
hysteresis at Tj = 25°C
VSOV
Battery supply overvoltage flag
30
32
34
V
VSOVHyst
Battery supply overvoltage flag
hysteresis
1
1.5
2
V
Supply current in ON-state from
IOUTx = 0 A
VS at VS = 12 V
10
mA
Standby current consumption
from VS at Tj = 25°C, VS = 12 V
5
µA
IS
IQS
Logic input high level(2)
All digital inputs
connected to VDD
0.56
VDD
0.66
VDD
0.76
VDD
V
Logic input high level(3)
All digital inputs
connected to VDD
0.52
VDD
0.58
VDD
0.64
VDD
V
Input hysteresis(4)
All digital inputs
connected to VDD
0.16
VDD
0.22
VDD
0.26
VDD
V
VintH
Logic input high level(5)
All digital inputs
connected to internal 5V
1.4
1.7
2.0
V
VintHyst
Logic input hysteresis(5)
All digital inputs
connected to internal 5V
0.4
0.6
0.8
V
IL(off)
Off-state output current at
VS = VSx = 12 V
Channel OFF;
VOUT = 0 V
1
µA
VOL
Output low voltage(6)
Iout = 5mA
0.5
V
VOH
Output high voltage(6)
Iout = -5mA
VVDDH
VVDDHyst
DocID023902 Rev 4
VDD –
1.3
V
47/60
Electrical specifications
L99CL01XP
Table 22. Electrical characteristics (logic + inputs) (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max. Unit
VPORH
Power on reset high threshold
for VS at VDD = 5 V
2
2.8
4
V
VPORL
Power on reset high threshold
for VS at VDD = 5 V
2
2.9
4
V
Rup(3)
Pull up resistor for logic pin
9
20
44
k
Pull down resistor for logic pin
36
100
250
k
fPWM
PWM frequency range
100
400
Hz
fCLK
Clock input frequency range
25.6
Rdown
(7)
PWM
PWM duty cycle resolution
REXT
External resistor range for
REXT pin
102.4 kHz
1/256
10
12.4
%
15
15
RfailH
k
RfailL
VREXT
fCLK fail low(8)
k
10
k
2.6
V
10
kHz
Max.
Unit
2
MHz
Cout = 100pF
120
ns
Cout = 100pF
4
s
Cout = 100pF
20
ns
REXT output voltage
Iout = 200 µA
Clock frequency fail detection
range
Low frequency
2.4
2.5
1. Valid for VS, VSA, VSB, VSC, VSD.
2. Valid for ENABLE, SDI, SCK, PWMCLK
3. Valid for CSN
4. Valid for ENABLE, SDI, SCK, PWMCLK, CSN.
5. Valid for IN1, IN2, IN3, IN5, IN6, IN7, LIMP
6. Valid for SDO
7. Valid for ENABLE, SDI, SCK, INx, PWMCLK, LIMP.
8. Parameter guaranteed by design and characterization; not subject to production test.
Table 23. Dynamic characteristics (SPI)
Symbol
Parameter
SPIclk(1)
SPI clock frequency
tCSNQV(1)
CSN falling until SDO valid
tCSNQT(1) CSN rising until SDO tristate
tSCKQV
(1)
Min.
Typ.
tSCSN(1)
CSN setup time before SCK rising
20
ns
(1)
SDI setup time before SCK falling
20
ns
tHSCK(1)
minimum SCK high time
125
ns
tLSCK(1)
minimum SCK low time
125
ns
minimum CSN high time
5
µs
SCK setup time before CSN rising
50
ns
tSSDI
tHCSN
(1)
tSSCK(1)
48/60
SCK rising until SDO valid
Test Condition
DocID023902 Rev 4
L99CL01XP
Electrical specifications
1. Parameter guaranteed by design and characterization; not subject to production test.
Table 24. Switching (VS = 12 V; Tj = 25°C)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
Turn-on delay time
RON[x] = 0
RLOAD = 32
—
25
µs
td(on)
Turn-on delay time
RON[x] = 1
RLOAD = 16
—
25
µs
td(off)
Turn-off delay time
RON[x] = 0
RLOAD = 32
—
25
µs
td(off)
Turn-off delay time
RON[x] = 1
RLOAD = 16
—
25
µs
(dVOUt/dt)on Turn-on voltage slope
—
0.14
V/µs
(dVOUt/dt)off Turn-off voltage slope
—
0.32
V/µs
tSKEW
Differential pulse skew
—
-200
µs
Figure 8. SPI timing
tHCSN
CSN
t CSNQV
t SCKQV
tCSNQT
Data out
SDO
Data out
t SSCK
tSCSN
SCK
t SSDI
SDI
t LSCK
tHSCK
Data in
Data in
Table 25. Electrical characteristics (OUT1 - OUT8)
Symbol
RDSon
IOC
VOUTL
Parameter
Test condition
Min.
Typ.
Max.
Unit
RONx = [1]; I = 800 mA
0.35
0.6
1
RONx = [0]; I = 400 mA
0.65
1
1.7
1.2
1.5
1.8
A
0.6
0.75
0.9
A
4.5
5
5.5
V
output resistance
(1)
Overcurrent shutdown OC high range; ON state
threshold
OC low range; ON state(1)
Selected OUTx
voltage threshold
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Electrical specifications
L99CL01XP
Table 25. Electrical characteristics (OUT1 - OUT8) (continued)
Symbol
tDSENSE1H
(2)
(2)
(2)
Current sense ratio
drift with temperature
Current sense ratio at
different currents
K4
50/60
Current sense ratio
drift with temperature
Current sense ratio at
different currents
K3
dK4/K4
Current sense ratio
drift with temperature
Current sense ratio at
different currents
K2
dK3/K3
Max.
Unit
IOUT = 0 A; VCS = 0 V;
Channels in OFF-state;
Current sense multiplexer
enabled on one of the outputs
0.5
µA
IOUT = 0 A; VCS = 0 V;
Channels in ON-state;
Current sense multiplexer
disabled
0.5
µA
µs
Current sense settling
Maximum value for setting to
time from rising edge
90%
of CS pin
Current sense ratio at
different currents
K1
dK2/K2
Test condition
Min.
Typ.
Analog sense
ISENSE0
dK1/K1
Parameter
(2)
Current sense ratio
drift with temperature
5
130
250
IOUT/ICS; RON[x] = 0;
IOUT = 50 mA
450
1450
3500
IOUT/ICS; RON[x] = 1;
IOUT = 30 mA
300
725
1500
IOUT/ICS; RON[x] = 0;
IOUT = 50 mA
-40
40
%
IOUT/ICS; RON[x] = 1;
IOUT = 30 mA
-35
35
%
IOUT/ICS; RON[x] = 0;
IOUT = 100 mA
1000
1650
2500
IOUT/ICS; RON[x] = 1;
IOUT = 50 mA
500
825
1250
IOUT/ICS; RON[x] = 0;
IOUT = 100 mA
-25
25
%
IOUT/ICS; RON[x] = 1;
IOUT = 50 mA
-25
25
%
IOUT/ICS; RON[x] = 0;
IOUT = 300 mA
1500
1900
2200
IOUT/ICS; RON[x] = 1;
IOUT = 100 mA
650
900
1100
IOUT/ICS; RON[x] = 0;
IOUT = 300 mA
-10
10
%
IOUT/ICS; RON[x] = 1;
IOUT = 100 mA
-15
15
%
IOUT/ICS; RON[x] = 0;
IOUT = 800 mA
1800
2000
2200
IOUT/ICS; RON[x] = 1;
IOUT = 400 mA
900
1000
1100
IOUT/ICS; RON[x] = 0;
IOUT = 800 mA
-7.5
7.5
%
IOUT/ICS; RON[x] = 1;
IOUT = 400 mA
-7.5
7.5
%
DocID023902 Rev 4
L99CL01XP
Electrical specifications
Table 25. Electrical characteristics (OUT1 - OUT8) (continued)
Symbol
Parameter
ICS_offset
ICS offset current
@25°C
Test condition
ICS @ IOUT = 0 A
Min.
Typ.
Max.
Unit
0
9
25
µA
-60
60
%
ICS_drift_ratio(2)
ICS_offset variation
between ICS at 25°C
and ICS at 150°C or
ICS at -40°C
KLRON
Offset compensated
K-factor at low RON
IOUT = 50 mA
1725
2090
KHRON
Offset compensated
K-factor at high RON
IOUT = 30 mA
850
1040
ICS_max
Current sense full
scale range
Typical value for OC at 25°C
Current sense output
voltage
Nominal voltage range
VCS
0
850
µA
VDD - 1
V
1. Value can be higher and vary during active pulse shaping
2. Parameter guaranteed by design and characterization; not subject to production test.
Table 26. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
test pulse
Test levels (1)
III
IV
1
-75V
-100V
2a
+37V
3a
Number of
pulses or
test times
Burst cycle / pulse
repetition time
Delays and
impedance
Min.
Max.
5000 pulses
0.5s
5s
2 ms, 10
+50V
5000 pulses
0.2s
5s
50µs, 2
-100V
-150V
1h
90ms
100ms
0.1µs, 50
3b
+75V
+100V
1h
90ms
100ms
0.1µs, 50
4
-6V
-7V
1 pulse
100ms, 0.01
+65V
+87V
1 pulse
400ms, 2
5b
(2)
1. The above test levels must be considered referred to VS = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground (-40°C < Tj < 150°C).
Table 27. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004E
test pulse
Test level results
III
VI
1
E
E
2a
C
C
3a
C
C
3b
C
C
DocID023902 Rev 4
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Electrical specifications
L99CL01XP
Table 27. Electrical transient requirements (part 2/3) (continued)
ISO 7637-2:
2004E
test pulse
III
VI
4
C
C
C
C
5b
(1)
Test level results
1. Valid in case of external load dump clamp: 40V maximum referred to ground (-40°C < Tj < 150°C).
Table 28. Electrical transient requirements (part 3/3)
Class
52/60
Contents
C
All functions of the device performed as designed after exposure to disturbance.
E
One or more functions of the device did not perform as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
DocID023902 Rev 4
L99CL01XP
Package and PCB thermal data
5
Package and PCB thermal data
5.1
PowerSSO-36 thermal data
Figure 9. PowerSSO-36 PC board
Note:
Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board dimension 129x60; Board Material FR4; Cu
thickness 0.070 mm (outer layers); Cu thickness 0.035 mm (inner layers); Thermal vias separation 1.2 mm; Thermal via
diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint dimension 4.1 mm x 6.5 mm
DocID023902 Rev 4
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Package and PCB thermal data
L99CL01XP
Figure 10. Rthj-amb vs PCB copper area in open box free air condition (one channel
ON)
24(J?AMB #7
24(JAMB
24(JAMB
0#"#UHEATSINKAREACM>
'!0'#&4
54/60
DocID023902 Rev 4
L99CL01XP
Package information
6
Package information
6.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID023902 Rev 4
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Package information
6.2
L99CL01XP
PowerSSO-36™ mechanical data
Figure 11. PowerSSO-36™ package dimensions
("1($'5
56/60
DocID023902 Rev 4
L99CL01XP
Package information
l
Table 29. PowerSSO-36™ mechanical data
millimeters
Symbol
Min
Typ
Max
A
2.15
—
2.45
A2
2.15
—
2.35
a1
0
—
0.1
b
0.18
—
0.36
c
0.23
—
0.32
D
10.10
—
10.50
E
7.4
—
7.6
e
—
0.5
—
e3
—
8.5
—
F
—
2.3
—
G
—
—
0.1
H
10.1
—
10.5
h
—
—
0.4
k
0°
—
8°
L
0.55
—
0.85
M
—
4.3
—
N
—
-
10°
O
—
1.2
—
Q
—
0.8
—
S
—
2.9
—
T
—
3.65
—
U
—
1.0
—
(1)
X
4.3
—
5.2
Y(1)
6.9
—
7.5
1. Corresponding to internal variation C.
DocID023902 Rev 4
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Package information
6.3
L99CL01XP
Packing information
Figure 12. PowerSSO-36 tube shipment (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 13. PowerSSO-36 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
Start
Top
cover
tape
No components
Components
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
58/60
DocID023902 Rev 4
No components
500mm min
L99CL01XP
7
Revision history
Revision history
Table 30. Document revision history
Date
Revision
08-Nov-2012
1
Initial release.
2
Table 19: Temperature warning and thermal shutdown:
– added note
Table 21: Digital timings:
– added note
Table 22: Electrical characteristics (logic + inputs):
– fCLK fail low: added note
Table 23: Dynamic characteristics (SPI):
– added note
Table 24: Switching (VS = 12 V; Tj = 25°C):
– td(on), td(off), tSKEW: updated max. value
Table 25: Electrical characteristics (OUT1 - OUT8):
– ICS_offset, ICS_drift_ratio: updated values
– KLRON, KHRON: added rows
24-Apr-2013
3
Updated Features list
Updated Section 1.1: Power supply (VS, GND) and Section 2.3:
Current Sense (CS) – analog diagnosis
Removed Figure 4: Typical output voltage waveforms (rising/falling
edge)
Updated introduction of Chapter 3: SPI interface
Updated Table 13: SDR registers
Updated Section : Address #12 Silicon Version
Updated Table 20: Thermal data
Table 22: Electrical characteristics (logic + inputs):
– VPORH, VPORL: updated parameter and values
– tDSENSE1H, KLRON, KHRON: updated values
– K0, dK0/K0: removed rows
Added Figure 10: Rthj-amb vs PCB copper area in open box free air
condition (one channel ON)
19-Sep-2013
4
Updated Disclaimer.
03-Dec-2012
Changes
DocID023902 Rev 4
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L99CL01XP
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