L99DZ120
Automotive door actuator driver with embedded LIN
Datasheet - production data
– Overcurrent
– Thermal warning
– Thermal shutdown
Fully protected driver for external MOSFETs in
H-bridge configuration
Two 5 V voltage regulators for microcontroller
and peripheral supply
Features
Programmable reset generator for power-on
and undervoltage
AEC-Q100 qualified
Configurable window watchdog
1 half bridge for 7.5 A load (RON = 100 mΩ)
LIN 2.2a compliant (SAEJ2602 compatible)
transceiver
1 half bridge for 7.5 A load (RON = 150 mΩ)
2 half bridges for 3 A load (RON = 300 mΩ)
1 configurable high-side driver for up to 1.5 A
(RON = 500 mΩ) or 0.35 A (RON = 1600 mΩ)
load
1 configurable high-side driver for 0.8 A
(RON = 800 mΩ) or 0.35 A (RON = 1600 mΩ)
load
3 configurable high-side drivers for
0.15 A/0.35 A (RON =2 Ω)
1 configurable high-side driver for 0.25 A/0.5 A
(RON = 2 Ω)
Separated (Isolated) fail-safe block with 2 LS
(RON = 1 Ω) to pull down the gates of the
external HS MOSFETs
Thermal clusters
A/D conversion of supply voltages and internal
temperature sensors
Embedded and programmable VS duty cycle
adjustment for LED driver outputs
Applications
Door zone applications.
4 configurable high-side drivers for
0.15 A/0.25 A (RON = 5 Ω)
Table 1. Device summary
Internal 10bit PWM timer for each stand-alone
high-side driver
Buffered supply for voltage regulators and 2
high-side drivers (OUT15 & OUT_HS / both
P-channel) to supply e.g. external contacts
Order codes
Package
LQFP-64 epad
Programmable soft-start function to drive loads
with higher inrush currents as current limitation
value (for OUT1-6, OUT7, OUT8 and
OUT_HS) with thermal expiration feature
Tray
Tape and reel
L99DZ120
L99DZ120TR
Product label
All the embedded outputs come with protection
and supervision features:
– Current Monitor (high-side only)
– Open-load
March 2019
This is information on a product in full production.
DS11567 Rev 5
1/161
www.st.com
Contents
L99DZ120
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2
Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.1
3.4
2/161
LQFP64 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.4.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.3
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.4
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.5
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.6
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4.7
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.8
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.9
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.10
Outputs OUT1 - OUT15, OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.11
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.4.12
Over Current Recovery settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.4.13
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4.14
H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.4.15
Gate drivers for the external Power-MOS switching times . . . . . . . . . . 42
3.4.16
Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . 45
3.4.17
Open-load monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4.18
Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.19
Wake up input WU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4.20
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.4.21
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.22
Input LIN_FLASH for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.4.23
Inputs DIR, DIRH, PWMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.4.24
Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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4
Contents
3.4.25
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.4.26
Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.27
Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.4.28
Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.4.29
SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1
Supply VS, VSREG
4.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3
4.4
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.1
Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.2
Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2.3
Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.4
Short to ground detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.2.5
Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3.1
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3.2
Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3.3
SW-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3.4
V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3.5
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.3.6
VBAT_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Wake-up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.4.1
Wake up input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.6
Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.6.1
4.7
Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Fail-safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7.1
Temporary failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7.2
Non-recoverable failures – forced Vbat_standby mode . . . . . . . . . . . . . 70
4.8
Reset output (NReset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.9
LIN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.10
4.9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.9.2
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.9.3
Wake up from Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
4.9.4
Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Serial Peripheral Interface (ST SPI Standard) . . . . . . . . . . . . . . . . . . . . . 74
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Contents
L99DZ120
4.11
Power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.11.1
VS supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.11.2
VSREG supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.12
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 77
4.13
Power outputs OUT1..15 and OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.14
Auto-recovery alert and thermal expiration . . . . . . . . . . . . . . . . . . . . . . . 79
4.15
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.16
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.17
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.18
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.19
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.20
PWM mode of the power outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.21
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
4.22
Programmable soft-start function to drive loads with higher inrush current .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5
4.23
H-bridge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.24
H-bridge driver slew-rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.25
Resistive low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.26
Short circuit detection / drain source monitoring . . . . . . . . . . . . . . . . . . . 87
4.27
H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.28
Programmable cross current protection . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.29
Power window H-bridge safety switch off block . . . . . . . . . . . . . . . . . . . . 91
4.30
Temperature warning and shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.31
Thermal clusters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.32
VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . 95
4.33
Analog digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.1
ST SPI 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.1.1
5.2
4/161
Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.2.1
Clock and Data Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.2.2
Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.2.3
Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DS11567 Rev 5
L99DZ120
Contents
5.2.4
Protocol failure detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6
Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7
SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.1
Global Status Byte GSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.2
Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
7.3
Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7.4
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.5
8
7.4.1
Control Register CR1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
7.4.2
Control Register CR2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
7.4.3
Control Register CR3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
7.4.4
Control Register CR4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.4.5
Control Register CR5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.4.6
Control Register CR6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4.7
Control Register CR7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
7.4.8
Control Register CR8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.4.9
Control Register CR9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
7.4.10
Control Register CR10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
7.4.11
Control Register CR11 (0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.4.12
Control Register CR12 (0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.4.13
Control Register CR13 (0x0D) to CR17 (0x11) . . . . . . . . . . . . . . . . . . 139
7.4.14
Control Register CR18 (0x12) to CR22 (0x16) . . . . . . . . . . . . . . . . . . 140
7.4.15
Control Register CR34 (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
7.4.16
Configuration Register (0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.5.1
Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
7.5.2
Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
7.5.3
Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
7.5.4
Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
7.5.5
Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
7.5.6
Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
7.5.7
Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . 153
7.5.8
Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
7.5.9
Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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8.1
LQFP-64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
8.2
LQFP-64 marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DS11567 Rev 5
L99DZ120
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Power-on reset (VSREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Current monitor output (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Charge pump electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Outputs OUT1 - OUT15, OUT_HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Power outputs switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Half bridges (OUT1, OUT4, OUT5 and OUT6) OCR timing parameters . . . . . . . . . . . . . . 38
High-side (OUT7, OUT8 and OUT_HS) OCR timing parameters. . . . . . . . . . . . . . . . . . . . 38
Current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
H-bridge driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Gate drivers for the external Power-MOS switching times . . . . . . . . . . . . . . . . . . . . . . . . . 42
Drain source monitoring external H-bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Open-load monitoring external H-bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Fail safe low-side switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIN transmit data input: pin TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIN receive data output: pin RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DI, CLK and CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Inputs LIN_FLASH for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Inputs DIR, DIRH, PWMH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Debug input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Temperature diode characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Timer1 and Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SGND loss comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Wake-up events description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Status of different functions/features vs operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 64
Temporary failures description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Non-recoverable failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DS11567 Rev 5
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9
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
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L99DZ120
Power output settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
H-bridge control truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
H-bridge monitoring in off-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Thermal cluster definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Operation codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Global Status Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Device application access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Device information read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
RAM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
ROM address range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Information Registers Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
SPI Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Burst Read Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
SPI Data Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Data Consistency Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
WD Type/Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
WD bit position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Global Status Byte (GSB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
GSB signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Control Register CR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
CR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Wake-up input1 filter configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Voltage regulator V2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Standby transition configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Control Register CR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
CR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Configuration of Timer x on-time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Control Register CR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
CR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Control Register CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
CR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Control Register CR5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
OUTx Configuration bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Control Register CR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Control Register CR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
CR7 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Control Register CR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
CR8 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Control Register CR9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
CR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Control Register CR10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
CR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Control Register CR11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
CR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Control Register CR12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
CR12 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Control Register CR13 to CR17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
CR13 to CR17 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
DS11567 Rev 5
L99DZ120
List of tables
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Control Register CR18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
CR18 to CR22 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Control Register CR34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
CR34 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
CR signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Status Register SR1 (0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
SR1 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Status Register SR2 (0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SR2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Status Register SR3 (0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SR3 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Status Register SR4 (0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
SR4 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Status Register SR5 (0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
SR5 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Status Register SR6 (0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SR6 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Status Register SR7 (0x37) to SR9 (0x39) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
SR7 to SR9 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Status Register SR10 (0x3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SR10 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Status Register SR11 (0x3B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SR11 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
LQFP-64 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
DS11567 Rev 5
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9
List of figures
L99DZ120
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
10/161
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Activation profile 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Activation profile 1 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Activation profile 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Activation profile 2 (first cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LQFP64 package and PCB thermal configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Voltage regulator V1 characteristics (quiescent current and accuracy) . . . . . . . . . . . . . . . 28
Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Hard Short case, the OC threshold is reached before end of blanking time. . . . . . . . . . . . 39
Overload case, the OC threshold is reached after end of blanking time. . . . . . . . . . . . . . . 39
H-driver delay times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IGHxr ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
IGHxf ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SPI input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
SPI output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SPI CSN - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI – CSN high to low transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 58
Voltage regulator behaviour and diagnosis during supply voltage . . . . . . . . . . . . . . . . . . . 61
NINT pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
NReset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RxDL pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Wake-up behavior according to LIN 2.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR, thermal
expiration occurs after a ∆T = 30° . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Block diagram of physical realization of AR alert and thermal expiration . . . . . . . . . . . . . . 81
Charge pump low filtering and start up implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Software strategy for half bridges before applying auto-recovery mode. . . . . . . . . . . . . . . 84
Overcurrent recovery mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
H-bridge GSHx slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
H-bridge diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
H-bridge open-load-detection (no open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
H-bridge open-load-detection (open-load detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
H-bridge open-load-detection (short to ground detected) . . . . . . . . . . . . . . . . . . . . . . . . . . 90
H-bridge open-load detection (short to VS detected) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PWMH cross current protection time implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
LSx_FSO: low-side driver “passively” turned on, taking supply from output pin (if main supply
fails), can guarantee VLSx_FSO < VOUT_max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Safety concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Thermal clusters identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DS11567 Rev 5
L99DZ120
List of figures
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Block diagram VS compensation (duty cycle adjustment) module . . . . . . . . . . . . . . . . . . . 95
Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6 . . . . . . . . . . . . . . . . . 96
SPI pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SDO pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SDI Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
SDO frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Window watchdog operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Timer_x controlled by DIR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
LQFP-64 package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
LQFP-64 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
LQFP-64 marking information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
DS11567 Rev 5
11/161
11
Description
1
L99DZ120
Description
The L99DZ120 is a door zone systems IC providing electronic control modules with
enhanced power management power supply functionality, including various standby modes,
as well as LIN physical communication layers.
The two low-drop voltage regulators of the devices supply the system microcontroller and
external peripheral loads such as sensors and provide enhanced system standby
functionality with programmable local and remote wake-up capability. In addition 8 high-side
drivers to supply LEDs, 2 high-side drivers to supply bulbs increase the system integration
level.
Up to 3 DC motors and 4 external MOS transistors in H-bridge configuration can be driven.
All outputs are SC protected and implement an open-load diagnosis.
The ST standard SPI interface (4.0) allows control and diagnosis of the device and enables
generic software development.
12/161
DS11567 Rev 5
L99DZ120
Block diagram and pin descriptions
Figure 1. Block diagram
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Block diagram and pin descriptions
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Table 2. Pin definitions and functions
Pin
Symbol
Function
1
WU
Wake-up Input: Input pin for static or cyclic monitoring of external contacts
2
CP2M
Charge pump pin for capacitor 2, negative side
3
CP2P
Charge pump pin for capacitor 2, positive side
4
CP
5
CP1P
Charge pump pin for capacitor 1, positive side
6
CP1M
Charge pump pin for capacitor 1, negative side
Charge pump output
DS11567 Rev 5
13/161
160
Block diagram and pin descriptions
L99DZ120
Table 2. Pin definitions and functions (continued)
Pin
Symbol
7
NC
Not connected
8
NC
Not connected
9
OUT14
High-side-driver output to drive LEDs
10
OUT13
High-side-driver output to drive LEDs
11
OUT12
High-side-driver output to drive LEDs
12
OUT9
High-side-driver output to drive LEDs
13
OUT10
High-side-driver-output
14
OUT11
High-side-driver output to drive LEDs
15
LS1_FSO
Fail Safe low-side switch (Active low)
16
LS2_FSO
Fail Safe low-side switch (Active low)
Power supply voltage for power stage outputs (external reverse battery
protection required), for this input a ceramic capacitor as close as
possible to GND is recommended. Important: For the capability of driving,
the full current at the outputs all pins of VS must be connected externally!
17
VS
18
VS; 2nd pin
19
OUT7
High-side-driver output to drive LEDs or a 10 Watt bulb (programmable
Rdson)
OUT6
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
21
OUT1
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
22
NC
20
14/161
Function
23
OUT5
24
OUT5; 2nd pin
25
VSREG
26
OUT_HS
Current capability (pin description see above)
Not connected
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
Current capability (pin description see above)
Power supply voltage to supply the internal voltage regulators, OUT15
and the OUT_HS (external reverse battery protection required / Diode) for
this input a ceramic capacitor as close as possible to GND and an
electrolytic back up capacitor is recommended.
High-side-driver output to drive LEDs or to supply contacts
DS11567 Rev 5
L99DZ120
Block diagram and pin descriptions
Table 2. Pin definitions and functions (continued)
Pin
Symbol
Function
27
OUT4
Half-bridge outputs: the output is built by a high-side and a low-side switch
which are internally connected. The output stage of both switches is a
power DMOS transistor. Each driver has an internal parasitic reverse
diode (bulk-drain-diode: high-side driver from output to VS, low-side driver
from GND to output)
28
OUT4; 2nd pin
29
NC
30
VS; 3rd pin
31
OUT15
High-side-driver output to drive LEDs
32
PGND
Power GND
33
OUT8
High-side-driver output to drive LEDs or a 5 Watt bulb (programmable
Rdson)
34
NC
Not connected
35
SGND
Signal Ground
Current capability (pin description see above)
Not connected
Current capability (for the pin description see above)
36
CM
Current monitor output: depending on the selected multiplexer bits
CM_SEL_x (CR 7) of the; Control Register this output sources an image
of the instant current; through the corresponding high-side driver with a
fixed ratio
37
NC
Not connected
38
CLK
SPI: serial clock input
39
DO
SPI: serial data output (push pull output stage)
40
DI
SPI: serial data input
41
CSN
42
TxD_L
43
RxD_L/NINT
RxDL -> LIN receive data output; NINT -> indicates local/remote wake-up
events (push pull output stage)
44
LIN_FLASH
LIN Flash Mode enable (former TxD_C pin, to guarantee family
compatibility)
45
NC
46
DIR1
47
PWMH
PWMH input: this input signal can be used to control the H-bridge Gate
Drivers.
48
DIRH
Direction Input: this input controls the H-bridge Drivers for the external
MOSFETs
49
DIR2
Direct Drive Input 2
50
NRESET
51
5V_1
52
NC
SPI: chip select not input
LIN Transmit data input
Not connected
Direct Drive Input 1
NReset output to micro controller; (reset state = LOW) (low-side switch
with drain connected to the output pin and internal pull up resistance to
5V_1)
Voltage regulator 1 output: 5 V supply e.g. micro controller
Not connected
DS11567 Rev 5
15/161
160
Block diagram and pin descriptions
L99DZ120
Table 2. Pin definitions and functions (continued)
16/161
Pin
Symbol
Function
53
NINT
Interrupt output (low active; push-pull output stage) to indicate VSREG
early warning (Active mode); indicates wake-up events from V1_standby
mode
54
NC
Not connected
55
NC
Not connected
56
Debug
57
LIN
58
5V_2
Voltage regulator 2 output: 5 V supply for external loads (potentiometer,
sensors). V2 is protected against reverse supply
59
GL1
Gate driver for PowerMOS low-side switch in half-bridge 1
60
SH1
Source of high-side switch in half-bridge 1
61
GH1
Gate driver for PowerMOS high-side switch in half-bridge 1
62
GH2
Gate driver for PowerMOS high-side switch in half-bridge 2
63
SH2
Source of high-side switch in half-bridge 2
64
GL2
Gate driver for PowerMOS low-side switch in half-bridge 2
Debug input to deactivate the window watchdog (high active)
LIN bus line
DS11567 Rev 5
L99DZ120
Block diagram and pin descriptions
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DS11567 Rev 5
17/161
160
Electrical specifications
L99DZ120
3
Electrical specifications
3.1
Absolute maximum ratings
Stressing the device above the rating listed in Table 3 may cause permanent damage to the
device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability
Table 3. Absolute maximum ratings
Symbol
Value [DC voltage]
Unit
DC supply voltage / “jump start”
-0.3 to +28
V
Load dump
-0.3 to +40
V
Stabilized supply voltage, logic supply
-0.3 to 6.5
V1 < VSREG
V
Stabilized supply voltage
-0.3 to +28(2)
V
Logic input / output voltage range
-0.3 to V1+0.3
V
-0.3 to 40
V
Debug input pin voltage range
-0.3 to 40
V
Output voltage range of Fail-Safe low-side
Switches
-0.3 to 35
V
DC Wake up input voltage / “jump start”
-0.3 to +28
V
Load dump
-0.3 to +40
V
LIN bus I/O voltage range
-20 to +40
V
Current injection into VS related input pins
20
mA
Current injection into VS related outputs
20
mA
-0.3 to VS+0.3
V
VGH1, VGH2 (VGxy) High Voltage Signal Pins
VSxy-0.3 to
VSxy+13; VCP+0.3
V
VGL1, VGL2, (VGxy) High Voltage Signal Pins
VSxy-0.3 to
VSxy+13; VCP-0.3V
to +12V; Vcp+0.3V
V
-1 to 40
V
-5 to 40
V
VS, VSREG
5V_1
5V_2(1)
VDI, VCLK VCSN
VDO, VRXDL/NINT,
VNRESET, VCM,
VDIR, VDIR2,
VPWMH, VDIRH,
VINT
Parameter / test condition
VLIN_FLASH, VTXDL Multi Level Inputs
VDebug
VLS1_FSO,
VLS2_FSO
VWU
VLIN
IInput(3)
IOUT_INJ
(3)
VOUTn, Vout_HS
Output voltage (n = 1 to 15)
High Voltage Signal Pins
VSH1, VSH2 (VSxy) High Voltage Signal Pins; single pulse with
tmax = 200ns
18/161
VCP1P
High Voltage Signal Pins
VS-0.3 to VS+14
V
VCP2P
High Voltage Signal Pins
VS-0.6 to VS+14
V
DS11567 Rev 5
L99DZ120
Electrical specifications
Table 3. Absolute maximum ratings (continued)
Symbol
Value [DC voltage]
Unit
-0.3 to VS+0.3
V
High Voltage Signal Pin VS ≤ 26 V
VS-0.3 to VS+14
V
High Voltage Signal Pin VS > 26 V
VS-0.3 to +40
V
±1.25
A
±2.5
A
IOUT7
±5
A
IOUT1,6
±5
A
IOUT4,5
±10
A
Maximum cumulated current at VS drawn by
OUT1(2)
±7.5
A
Maximum cumulated current at VS drawn by
OUT8 & OUT10(2)
±2.5
A
Maximum cumulated current at VS drawn by
OUT4(2)
±10
A
Maximum cumulated current at VS drawn by
OUT5(2)
±10
A
Maximum cumulated current at VS drawn by
OUT6 & OUT7(2)
±7.5
A
Maximum cumulated current at VS drawn by
OUT9, OUT11, OUT12, OUT13, OUT14, OUT15
and CP
±2.5
A
Maximum current at VSREG pin (2) (5V_1. 5V_2
and OUT_HS)
±2.5
A
Maximum cumulated current at PGND drawn by
OUT1 & OUT6(2)
±7.5
A
Maximum cumulated current at PGND drawn by
OUT5(2)
±12.5
A
Maximum cumulated current at PGND drawn by
OUT4(2)
±12.5
A
Maximum current at SGND(2)
±1.25
A
-0.3 to 0.3
V
VCP1M, VCP2M
VCP
Parameter / test condition
High Voltage Signal Pins
IOUT9, IOUT10,
IOUT11, IOUT12,
IOUT13, IOUT14,
IOUT15, IOUT_HS
IOUT8
IVScum
IVSREG
IPGNDcum
ISGND
GND pins
Output current(2)
PGND versus SGND
1. 5V_2 is robust against SC to 28 V only in case VSREG is supplied.
2. Values for the absolute maximum DC current through the bond wires. This value does not consider
maximum power dissipation or other limits.
3. Guaranteed by design.
Note:
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
DS11567 Rev 5
19/161
160
Electrical specifications
L99DZ120
Note:
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds,
the current load must be limited to this nominal current.
3.2
ESD protection
Table 4. ESD protection
Parameter
All
pins(1)
All power output pins (2): OUT1 – OUT15, OUT_HS
Value
Unit
+/-2
kV
+/-4
kV
+/-8(2)
LIN
+/-10(3)
+/-6(4)
kV
+/-500
V
+/-750(6)
V
+/- 200
V
All pins(5)
Corner
pins(5)
All pins
(7)
1. HBM (human body model, 100 pF, 1.5 kΩ) according to MIL 883C, Method 3015.7 or EIA/JESD22A114-A.
2. HBM with all none zapped pins grounded.
3. Indirect ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω) and ‘Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
4. Direct ESD Test according to IEC 61000-4-2 (150 pF, 330 Ω) and ‘Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications’ (version 1.3, 2012-05-04).
5. Charged device model.
6. For WU, these limits are referred to one-zap stress; in case of three-zap stress, the limits are +750V/-400V.
7. Machine model; C = 220 pF, R = 0 Ω.
3.3
Thermal data
Table 5. Operating junction temperature
Symbol
Tj
Parameter
Operating junction temperature
Value
Unit
-40 to 175
°C
All parameters are guaranteed in the junction temperature range -40 to 150°C (unless
otherwise specified); the device is still operative and functional at higher temperatures (up to
175°C).
Note:
Parameters limits at higher junction temperatures than 150°C may change respect to what
is specified as per the standard temperature range.
Note:
Device functionality at high junction temperature is guaranteed by characterization.
20/161
DS11567 Rev 5
L99DZ120
Electrical specifications
Table 6. Temperature warning and thermal shutdown
Symbol
TW
Parameter
Thermal overtemperature warning threshold
Min.
Typ.
Max.
Unit
140
150
160
°C
Cluster 1-4
Cluster 5-6
165
165
175
175
185
190
°C
Tj(1)
175
185
195
°C
Tj(1)
Tj(1)
TSD1
TSD2
TSD12hys
Tjtft
Thermal shutdown junction temperature 1
Thermal shutdown junction temperature 2
Hysteresis
Thermal warning / shutdown filter time
5
°C
32
µs
1. Non-overlapping.
3.3.1
LQFP64 thermal data
Devices belonging to L99DZxxx family embed a multitude of junctions (i.e. Outputs based
on a PowerMOSFET stage) housed in a relatively small piece of silicon. The most complex
device contains, among all the described features, 6 half-bridges (12 N-Channel
PowerMOS), 10 high-sides and two voltage regulators; all the other derivatives, even if
smaller than the family super set device, still contain a significant number of junctions.
For this reason, using the Thermal Impedance of a single junction (i.e. voltage regulator or
major power dissipation contributor) does not allow to predict thermal behavior of the whole
device and therefore it is not possible to assess if a device is thermally suitable for a given
activation profile and loads characteristics.
Thermal information is provided as temperature reading by different clusters placed close to
the most dissipative junctions.
Some representative and realistic worst-case thermal profiles are described in the below
paragraph.
Following measurement methods can be easily implemented, by final user, for a specific
activation profile.
L99DZ120 thermal profiles
Profile 1
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 Ω resistor (DC activation)
OUT12: 300 Ω resistor (DC activation)
OUT13: 300 Ω resistor (DC activation)
OUT14: 300 Ω resistor (DC activation)
DS11567 Rev 5
21/161
160
Electrical specifications
L99DZ120
Cyclic activation
OUT4 – OUT5: 3,3 Ω resistor placed across those outputs
–
10 activations of Lock/Un-lock (250 ms ON Lock; 500 ms wait; 250 ms ON Unlock unlock; 500 ms wait)
OUT5 – OUT6: 10 Ω resistor placed across those outputs
–
(250 ms ON Safe Lock; 500 ms wait; 250 ms ON Safe unlock; 500 ms wait)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation”
sequence is applied.
Temperature reading is logged just at the end of the whole sequence.
Figure 3. Activation profile 1
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Figure 4. Activation profile 1 (first cycle)
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DS11567 Rev 5
L99DZ120
All curves are plotted interpolating measured samples with 15 ms of period.
Profile 2
Battery Voltage: 16V, Ambient temperature start: 85°C
DC activation
V1 charged with 70 mA (DC activation)
V2 charged with 30 mA (DC activation)
OUT7: 1 x10W bulb (DC activation)
OUT8: 1 x 5W bulb (DC activation)
OUT11: 300 Ω resistor (DC activation)
OUT12: 300 Ω resistor (DC activation)
OUT13: 300 Ω resistor (DC activation
OUT14: 300 Ω resistor (DC activation)
Cyclic activation
OUT1 – OUT6: 6,8 Ω resistor placed across those outputs
–
2 activations (3s ON; 1s OFF; 2x)
Test execution:
Once thermal equilibrium is reached with all DC load active, the “Cyclic Activation”
sequence is applied.
Figure 5. Activation profile 2
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Electrical specifications
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DS11567 Rev 5
23/161
160
Electrical specifications
L99DZ120
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Figure 6. Activation profile 2 (first cycle)
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Note:
All curves are plotted interpolating measured samples with 15 ms of period.
Figure 7. LQFP64 package and PCB thermal configuration
Note:
24/161
Layout condition for Thermal Characterization (board finishing thickness 1.5 mm +/- 10%,
board four layers, board dimension 77 mm x 114 mm, board material FR4, Cu thickness
0,070 mm for outer layers, 0.0035 mm for inner layers, thermal vias separation 1.2 mm).
DS11567 Rev 5
L99DZ120
Electrical specifications
3.4
Electrical characteristics
3.4.1
Supply and supply monitoring
All SPI communication, logic and oscillator parameters are working down to VSREG = 3.5 V
and parameters are as specified in the following chapters (guaranteed by design).
SPI thresholds
Oscillator frequency (delay times correctly elapsed)
Internal register status correctly kept (reset at default values for VSREG< VPOR)
Reset threshold correctly detected
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 7. Supply and supply monitoring
Symbol
Parameter
VSUV
VS undervoltage threshold
Vhyst_UV
VS undervoltage hysteresis
VSOV
VS overvoltage threshold
Vhyst_OV
VS overvoltage hysteresis
VSREG_UV
VSREG undervoltage threshold
Vhyst_UV
VSREG undervoltage hysteresis
VSREG_OV
VSREG overvoltage threshold
Vhyst_OV
VSREG overvoltage hysteresis
tovuv_filt
VS/VSREG over/undervoltage filter
time
Test condition
VS increasing / decreasing
Min.
Typ.
4.7
0.04
0.1
Max.
Unit
5.4
V
0.2
V
VS increasing
20
22.5
VS decreasing
18.5
22.5
0.5
VSREG increasing / decreasing
1
4.2
0.04
0.1
1.5
V
4.9
V
0.2
V
VSREG increasing
20
22.5
VSREG decreasing
18.5
22.5
0.5
1
1.5
64
IV(act)
Current consumption in Active
mode
VS = VSREG = 12 V;
TxD LIN = high; V1 = ON;
V2 = ON; HS/LS Driver OFF;
CP = ON
IV(BAT)
Current consumption in
Vbat_standby mode (1)
VS = 12 V; Both voltage
regulators deactivated; HS/LS
Driver OFF
IV(BAT)CS
Current consumption in
Vbat_standby mode with cyclic
sense enabled (1)
IV(BAT)CW
Current consumption in
Vbat_standby mode with cyclic
wake enabled (1)
V
V
V
µs
11
14
mA
8
16
30
µA
VS = 12 V; Both voltage
regulators deactivated;
T = 50 ms, tON = 100 µs
30
80
130
µA
VS = 12 V; Both voltage
regulators deactivated during
standby phase
30
80
130
µA
DS11567 Rev 5
25/161
160
Electrical specifications
L99DZ120
Table 7. Supply and supply monitoring (continued)
Symbol
IV(V1stby)
IqLIN
IOUT_HS
Parameter
Test condition
Min.
Typ.
Max.
Unit
Current consumption in
V1_standby mode (1)
VS = 12 V; Voltage regulator V1
active; (IV1 = 0); HS/LS Driver
OFF
16
50
70
µA
Current consumption in
V1_standby mode (1) (2)
VS = 12 V; Voltage regulator V1
active; (IV1 = ICMP); HS/LS
Driver OFF
196
µA
Current consumption in
V1_standby mode (1)
VS = 12V; Voltage regulator V1
active; (IV1 = IPEAK); HS/LS
Driver OFF
436
µA
Quiescent current adder for LIN
wake up activated
Guaranteed by design
0
Additional bias quiescent current
for switched on OUT_HS or
Guaranteed by design
OUT15 by DIR or Timer; value for
1 output
µA
620
1100
µA
IOUTHS_DIR
Quiescent current adder if
OUT_HS and/or OUT15 are
configured for Direct Drive; value
during output off
Guaranteed by design
0
5
µA
Itimer
Quiescent current adder if timer1
and/or timer 2 are active to
provide interrupt on NINT upon
timer expiration
Guaranteed by design
65
110
µA
1. Conditions for specified current consumption:
— VLIN > (VS-1.5 V)
— VWU < 1 V or VWU > (VS – 1.5 V)
2. Iq = Iq0 + 2% * ILOAD (see also Figure 8: Voltage regulator V1 characteristics (quiescent current and accuracy)
3.4.2
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 8. Oscillator
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
fCLK1(1)
Oscillation frequency OSC1
1.66
2.0
2.34
MHz
fCLK2(1)
Oscillation frequency OSC2
30.4
32.0
33.6
MHz
1. OSC1: charge pump, SPI, output drivers, watchdog
OSC2: ADC
3.4.3
Power-on reset (VSREG)
All outputs open; Tj = -40 °C to 150 °C, unless otherwise specified.
26/161
DS11567 Rev 5
L99DZ120
Electrical specifications
Table 9. Power-on reset (VSREG)
Symbol
VPOR_R
VPOR_F
Parameter
VPOR threshold
VPOR threshold
Test condition
Min.
VSREG rising
(1)
VSREG falling
Typ.
Max.
Unit
3.45
4.5
V
3.5
V
2.45
1. This threshold is valid if VSREG had already reached VPOR_R(max) previously.
3.4.4
Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V ≤ VS ≤ 28 V; 4.5 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 10. Voltage regulator V1
Symbol
V1
Parameter
Test condition
Output voltage
VSREG = 13.5V
VSREG absolute
minimum value for
controlling NRESET
output
VSREG rising/falling
V1_low_acc
Output voltage
tolerance low accuracy
mode
ILOAD = 0 mA to ICMP; (Active
mode) or ILOAD = 0 mA to IPEAK
(V1stdby); VSREG = 13.5 V
VSREG_absmin
Min.
Typ.
Max.
5.0
Unit
V
2
V
-3
3
%
V1_hi_acc
ILOAD = ICMP to 100 mA; (Active
Output voltage
mode) or ILOAD = IPEAK to
tolerance high accuracy
100 mA (V1stdby);
mode
VSREG = 13.5 V
-2
2
%
V1_250mA
Output voltage
tolerance (100 to
250mA)
-3
3
%
VDP1
ICC1
ICCmax1
Cload1
tTSD
Drop-out Voltage
ILOAD = 250 mA;
VSREG = 13.5 V
ILOAD = 50 mA; VSREG = 5 V
0.2
0.4
V
ILOAD = 100 mA; VSREG = 5 V
0.3
0.5
V
ILOAD = 150 mA; VSREG = 5 V
0.45
0.6
V
250
mA
900
mA
Output current in Active
Max. continuous load current
mode
Short circuit output
current
Current limitation
Load capacitor1
Ceramic (+/- 20%)
340
600
0.22(1)
V1 deactivation time
after thermal shut-down
µF
1
sec
ICMP_ris
Current comp. rising
thresh
Rising current
2
4
6
mA
ICMP_fal
Current comp. falling
threshold
Falling current
1.4
2.8
4.2
mA
DS11567 Rev 5
27/161
160
Electrical specifications
L99DZ120
Table 10. Voltage regulator V1 (continued)
Symbol
ICMP_hys
Parameter
Test condition
Min.
Current comp.
Hysteresis
Typ.
Max.
1.2
Unit
mA
IPeak_ris(2)
Current comp. rising
thresh.
Rising current
6
12
18
mA
IPeak_fal(2)
Current comp. falling
threshold
Falling current
5
10
15
mA
IPeak_hys(2)
Current comp.
Hysteresis
mA
2
V
V1fail
V1 fail threshold
tV1fail
V1 fail filter time
2
µs
V1 short filter time
4
ms
tV1FS
V1 Fail-Safe Filter Time
2
ms
tV1off
V1 deactivation time
after 8 consecutive WD
failures
tV1short
V1 forced
2
Tested by scan
150
200
250
ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be
located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.
2. In Active mode, V1 regulator is switched to high accuracy mode, dropping below the ICMP threshold regulator switches to
low accuracy mode.
Figure 8. Voltage regulator V1 characteristics (quiescent current and accuracy)
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DS11567 Rev 5
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L99DZ120
3.4.5
Electrical specifications
Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V ≤ VS ≤ 28 V; 4.5 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 11. Voltage regulator V2
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Output voltage
VSREG = 13.5 V
V2_1mA
Output voltage tolerance
(0 to 1 mA)
ILOAD = 1 mA; VSREG = 13.5 V
-6.5
6.5
%
V2_25mA
Output voltage tolerance
(1 to 25 mA)
ILOAD = 25 mA; VSREG = 13.5 V
-3
3
%
V2_50mA
Output voltage tolerance
(25 to 50 mA)
ILOAD = 50 mA; VSREG = 13.5 V
-4
4
%
V2_100mA
Output voltage tolerance
(50 to 100 mA)
ILOAD = 100 mA; VSREG = 13.5 V
-4
4
%
V2
VDP2
Drop-out voltage
5.0
Unit
ILOAD = 25 mA; VSREG = 5.25 V
0.3
0.4
V
ILOAD = 50 mA; VSREG = 5.25 V
0.4
0.8
V
ILOAD = 100 mA; VSREG = 13.5 V
1
1.6
V
50
mA
250
mA
Output current in Active
mode
Max. continuous load current
Short circuit output
current
Current limitation
Cload
Load capacitor
Ceramic (+/- 20%)
V2fail
V2 fail threshold
V2 forced
tV2fail
ICC2
ICCmax2
tV2short
V
100
150
0.22 (1)
μF
2
V
V2 fail filter time
2
µs
V2 short filter time
4
ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%). Capacitor must be
located close to the regulator output pin. A 2.2 µF capacitor is recommended to minimize the DPI stress in the application.
3.4.6
Reset output
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4V ≤ VSREG ≤ 28V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 12. Reset output
Symbol
Parameter
VRT1falling
Reset threshold
voltage1
VRT2falling
VRT3falling
Test condition
Min.
Typ.
Max.
Unit
VV1 decreasing
3.25
3.5
3.7
V
Reset threshold
voltage2
VV1 decreasing
3.55
3.8
4
V
Reset threshold
voltage3
VV1 decreasing
3.75
4.0
4.2
V
DS11567 Rev 5
29/161
160
Electrical specifications
L99DZ120
Table 12. Reset output (continued)
Symbol
30/161
Parameter
Test condition
Min.
Typ.
Max.
Unit
VRT4falling
Reset threshold
voltage4
VV1 decreasing
4.1
4.3
4.5
V
VRTrising
Reset threshold
voltage4
VV1 increasing
4.67
4.8
4.87
V
VRESET
Reset Pin low output
V1 > 1 V; IRESET = 5 mA
voltage
0.2
0.4
V
RRESET
Reset pull up int.
resistor
20
30
kΩ
40
µs
10
tRR
Reset reaction time
ILOAD = 1 mA
6
tUV1
V1 undervoltage
filter time
tV1R
Reset pulse duration
(V1 undervoltage
and V1 power on
reset)
1.5
2.0
2.5
ms
tWDR
Reset pulse duration
(watchdog failure)
3
4
5
ms
16
DS11567 Rev 5
µs
L99DZ120
3.4.7
Electrical specifications
Watchdog timing
4.5 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 13. Watchdog timing
Symbol
tLW
Parameter
Test condition
Long open window
Min.
Typ.
Max.
Unit
160
200
240
ms
4.5
ms
TEFW1
Early Failure Window 1
TLFW1
Late Failure Window 1
20
TSW1
Safe Window 1
7.5
TEFW2
Early Failure Window 2
TLFW2
Late Failure Window 2
100
TSW2
Safe Window 2
37.5
TEFW3
Early Failure Window 3
TLFW3
Late Failure Window 3
200
TSW3
Safe Window 3
75
TEFW4
Early Failure Window 4
TLFW4
Late Failure Window 4
400
TSW4
Safe Window 4
150
DS11567 Rev 5
ms
12
ms
22.3
ms
ms
60
ms
45
ms
ms
120
ms
90
ms
ms
240
ms
31/161
160
Electrical specifications
L99DZ120
Figure 9. Watchdog timing
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32/161
DS11567 Rev 5
L99DZ120
Electrical specifications
Figure 10. Watchdog early, late and safe windows
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3.4.8
Current monitor output (CM)
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified
Table 14. Current monitor output (CM)
Symbol
VCM
Parameter
Test condition
Functional voltage range
ICM/IOUT8 (low on-resistance)
Typ.
0
Current monitor output ratio:
ICM/IOUT1,4,5,6 and 7 (low onresistance)
ICMr
Min.
Max.
Unit
V1-1V
V
1/10000
0 V ≤ VCM ≤ (V1 - 1 V)
1/6500
ICM/IOUT 7,8 (high on-resistance)
1/2000
ICM/IOUT9,10,11,12,13,14,15 and HS
1/1000
DS11567 Rev 5
33/161
160
Electrical specifications
L99DZ120
Table 14. Current monitor output (CM) (continued)
Symbol
ICM acc
Parameter
Current monitor accuracy
accICMOUT1,4,5,6 and 7(low onresistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 500 mA;
IOUT4,5max=7.4 A;
IOUT1,6max = 2.9 A;
IOUT7max = 1.4 A
Current monitor accuracy
accICMOUT 8 (low on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 100 mA;
IOUT8max=0.9 A
Current monitor accuracy
accICMOUT9,10,11,12,13,14,15 ,HS
and OUT7,8 (high on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUT.min = 100 mA; IOUT11,12,
15 HS = 0.2 A; IOUT7,8
max = 0.3 A
Current monitor accuracy
accICMOUT1,4,5,6 and 7 (low onresistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 2 * IOLD;
IOUT4,5max = 7.4 A;
IOUT1,6max = 2.9 A;
IOUT7max = 1.4 A
Current monitor accuracy
accICMOUT 8(low on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUTmin = 2 * IOLD;
IOUT8max = 0.9 A
Current monitor accuracy
accICMOUT9,11,12,13,14,15, HS and
OUT7,8 (high on-resistance)
0 V ≤ VCM ≤ (V1 - 1 V);
IOUT.min = 2 * IOLD;
IOUT9,13,14max = 0.3 A;
IOUT11,12,15 HS = 0.2 A;
IOUT7,8 max = 0.3 A
Current monitor accuracy
accICMOUT10
0 V ≤ VCM ≤ (V1 - 1 V);
IOUT.min = 2 * IOLD;
IOUT10max = 0.4 A
ICM acc_2ol
tcmb
Test condition
Min.
Current monitor blanking time
Typ.
Max.
4% + 1%
FS(1)
8% + 2%
FS(1)
4% + 1%
FS(1)
8% + 2%
FS(1)
4% + 1%
FS(1)
8% + 4%
FS(1)
32
Unit
µs
1. FS (full scale) = IOUTmax * ICMr
3.4.9
Charge pump
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VS ≤ 28V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 15. Charge pump electrical characteristics
Symbol
Parameter
VCP
Charge pump output voltage
ICP
Charge pump output current(1)
34/161
Test condition
Min.
Typ.
VS = 6 V, ICP = -15 mA
VS+6
VS+7
VS ≥ 10 V, ICP = -15 mA
VS+11
VS+12
VCP = VS + 10 V;
VS = 13.5 V;
C1 = C2 = CCP = 100 nF
22.5
DS11567 Rev 5
Max.
Unit
V
VS+13.5
V
mA
L99DZ120
Electrical specifications
Table 15. Charge pump electrical characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
VCP = VS;
VS = 13.5 V;
C1 = C2 = CCP = 100 nF
Max.
Unit
70
mA
VS+5.5
V
ICPlim
Charge pump output current
limitation(2)
VCP_low
Charge pump low threshold
voltage
TCP
Charge pump low filter time
64
µs
fCP
Charge Pump frequency
400
kHz
VS+4.5
VS+5
1. ICP is the minimum current the device can provide to an external circuit without VCP going below VS + 10 V.
2. ICPlim is the maximum current, which flows out of the device in case of a short to VS.
3.4.10
Outputs OUT1 - OUT15, OUT_HS
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V, all outputs open;
Tj = -40 °C to 150 °C, unless otherwise specified.
Table 16. Outputs OUT1 - OUT15, OUT_HS
Symbol
Parameter
rON OUT1,6
On-resistance to supply or
GND
rON OUT4
rON OUT5
On-resistance to supply or
GND
On-resistance to supply or
GND
On-resistance to supply in
low resistance mode
rON OUT7
On-resistance to supply in
high resistance mode
Test condition
VS = 13.5 V; Tj = 25 °C;
IOUT1,6 = ±1.5A
Min.
Typ.
300
VS = 13.5V; Tj = 130°C
IOUT1,6 = ±1.5 A
VS = 13.5V; Tj = 25 °C;
IOUT4 = ±3 A
150
VS = 13.5 V; Tj = 25 °C;
IOUT7 = -0.8 A
100
VS = 13.5 V; Tj = 25°C;
IOUT7 = -0.2 A
VS = 13.5 V; Tj = 130 °C;
IOUT7 = -0.2 A
DS11567 Rev 5
mΩ
mΩ
200
500
VS = 13.5 V; Tj = 130 °C;
IOUT7 = -0.8 A
mΩ
mΩ
300
VS = 13.5 V; Tj = 130 °C;
IOUT5 = 3 A
Unit
mΩ
600
VS = 13.5 V; Tj = 130 °C;
IOUT4 = ±3 A
VS = 13.5 V; Tj = 25°C;
IOUT5 = ±3 A
Max.
mΩ
mΩ
1000
1600
mΩ
mΩ
3200
mΩ
35/161
160
Electrical specifications
L99DZ120
Table 16. Outputs OUT1 - OUT15, OUT_HS (continued)
Symbol
Parameter
On-resistance to supply in
low resistance mode
rON OUT8
On-resistance to supply in
high resistance mode
rON OUT9,10,13,14
On-resistance to supply
rON OUT11,12,15, HS On-resistance to supply
36/161
Test condition
Min.
VS = 13.5 V; Tj = 25 °C;
IOUT8 = -0.4 A
Typ.
800
VS = 13.5 V; Tj = 130 °C;
IOUT8 = -0.4 A
1600
VS = 13.5 V; Tj = 130 °C;
IOUT8 = -0.2 A
2000
VS = 13.5 V; Tj = 130 °C;
IOUT9,10,13,14 = -75 mA
5
VS = 13.5 V; Tj = 130 °C;
IOUT11,12,15, HS = -75 mA
Switched-off output current VOUT = 0 V; standby mode
high-side drivers of OUT7VOUT = 0 V; active mode
15, OUT_HS
IQLH
Switched-off output current VOUT = 0 V; standby mode
high-side drivers of OUT1-6 V
OUT = 0 V; Active mode
IQLL
VOUT = VS; standby mode
Switched-off output current
low-side drivers of OUT1-6 VOUT = VS - 0.5 V; active
mode
DS11567 Rev 5
mΩ
mΩ
4000
VS = 13.5 V; Tj = 25 °C;
IOUT11,12,15, HS = -75 mA
mΩ
mΩ
3200
VS = 13.5 V; Tj = 25 °C;
IOUT9,10,13,14 = -75 mA
Unit
mΩ
1600
VS = 13.5 V; Tj = 25 °C;
IOUT8 = -0.2 A
IQLH
Max.
mΩ
Ω
10
Ω
-5
µA
-10
µA
-5
µA
-100
µA
165
-100
µA
µA
L99DZ120
3.4.11
Electrical specifications
Power outputs switching times
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 17. Power outputs switching times
Symbol
td ON H
td OFF H
Parameter
Output delay time high-side driver
on (OUT1,4,5,6)
Output delay time high-side driver
on (OUT7,8)
Output delay time high-side driver
off (OUT1,4,5,6)
Output delay time high-side driver
off (OUT7,8)
Test condition
VS = 13.5 V; V1 = 5 V;
corresponding low-side
driver is not active (1)(2)(3)
(from CSN 50% to OUT
50%) see Figure 20
VS = 13.5 V;
(1)(2)(3) (from
V1 = 5 V
CSN 50% to
OUT 50%) see Figure 20
Min.
Typ.
Max.
Unit
15
40
80
µs
20
40
90
µs
50
150
300
µs
20
70
130
µs
td ON H
Output delay time high-side driver
on (OUT9 …OUT15, OUT_HS)
VS/VSREG = 13.5 V;
V1 = 5 V; (from CSN 80% to
OUT 80%)
30
µs
td OFF H
Output switch off delay time highside driver on (OUT9 …OUT15,
OUT_HS)
VS/VSREG = 13.5 V;
V1 = 5 V; (from CSN 80% to
OUT 20%)
35
µs
td ON L
Output delay time low-side driver
(OUT1-6) on
VS = 13.5 V; V1 = 5 V;
corresponding high-side
driver is not active (1)(2)(3)
(from CSN 50% to OUT
50%) see Figure 20
td OFF L
Output delay time low-side driver
(OUT1-6) off
td HL
td LH
Cross current protection time
(OUT1-6)
VS = 13.5 V;
(1)(2)(3) (from
V1 = 5 V
CSN 50% to
OUT 50%) see Figure 20
tcc ONLS_OFFHS – td OFF H(4)
tcc ONHS_OFFLS – td OFF L (4)
VS = 13.5 V; V1 = 5 V
15
30
70
µs
40
150
300
µs
50
200
400
µs
0.1
0.2
0.6
V/µs
dVOUT/dt
Slew rate of OUT1-OUT8
dVmax/dt
Maximum external applied slew
rate on OUT1-OUT6 without
Guaranteed by design
switching on the LS and HS (only in
Active mode)
dVOUT/dt
Slew rate of OUT9-OUT15,
OUT_HS
VS/VSREG = 13.5 V;
V1 = 5 V (1)(2)(3)
2
V/µs
fPWMx(00)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
100
Hz
fPWMx(01)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
200
Hz
(1)(2)(3)
DS11567 Rev 5
20
V/µs
37/161
160
Electrical specifications
L99DZ120
Table 17. Power outputs switching times (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
fPWMx(10)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
330
Hz
fPWMx(11)
PWM switching frequency
VS/VSREG = 13.5 V;
V1 = 5 V
500
Hz
1. RLOAD = 16 Ω at OUT1,6 and OUT7,8 in low on-resistance mode
2. RLOAD = 4 Ω at OUT4,5
3. RLOAD = 128 Ω at OUT4,9,10,11,12,13,15,15,HS and OUT7,8 in high on-resistance mode
4. tCC is the switch-on delay time if complement in half bridge has to switch off
3.4.12
Over Current Recovery settings
Table 18. Half bridges (OUT1, OUT4, OUT5 and OUT6) OCR timing parameters
Symbol
Parameter
Tblanking
Tocr_hb
Toff_hb
Over current filter time
for half bridges
OFF Time for half
bridges OCR_FREQ=0
OFF Time for half
bridges OCR_FREQ=1
Test condition
Min.
Typ.
Max.
Unit
Guaranteed by Design
33
40
47
µs
Guaranteed by Design
26
32
38
µs
218
264
310
µs
106
128
150
µs
Guaranteed by Design
Table 19. High-side (OUT7, OUT8 and OUT_HS) OCR timing parameters
Symbol
Parameter
Tblanking
Tocr_hs
Toff_hs
38/161
Over current filter time
for high-side
OFF Time for high-side
OCR_FREQ=0
OFF Time for high-side
OCR_FREQ=1
Test condition
Min.
Typ.
Max.
Unit
Guaranteed by Design
33
40
47
µs
Guaranteed by Design
53
64
75
µs
398
480
562
µs
192
232
272
µs
Guaranteed by Design
DS11567 Rev 5
L99DZ120
Electrical specifications
Figure 11. Hard Short case, the OC threshold is reached before end of blanking time
Figure 12. Overload case, the OC threshold is reached after end of blanking time
3.4.13
Current monitoring
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
DS11567 Rev 5
39/161
160
Electrical specifications
L99DZ120
Table 20. Current monitoring
Symbol
Parameter
|IOC1|,
|IOC6|
Test condition
Min.
VS = 13.5 V; V1 = 5 V; sink
and source
Typ.
Max.
Unit
3
5
A
7.5
10
A
6
10
A
VS = 13.5 V; V1 = 5 V; sink
and source; Tj = -40 °C to
|IOC4|
70 °C
Overcurrent threshold HS & LS
VS = 13.5 V; V1 = 5 V; sink
and source; Tj = 130 °C
|IOC5_1|
3
4
5
A
4.5
6
7.5
A
7.5
10
A
Overcurrent threshold HS in low onresistance mode
1.5
2.5
A
Overcurrent threshold HS in high
on-resistance mode
0.35
0.65
A
Overcurrent threshold HS in low onresistance mode
0.7
1.3
A
Overcurrent threshold HS in high
on-resistance mode
0.35
0.65
A
0.35
0.7
A
0.15
0.3
A
Overcurrent threshold HS in high
current mode
0.5
1
A
Overcurrent threshold HS in low
current mode
0.25
0.5
A
Overcurrent threshold HS in high
current mode
0.25
0.5
A
Overcurrent threshold HS in low
current mode
0.15
0.3
A
VS = 13.5 V; V1 = 5 V; sink
and source
|IOC5_2|
|IOC5_3|
|IOC7|
|IOC8|
|IOC9|,
|IOC13|,
|IOC14|
|IOC10|
|IOC11|,
|IOC12|,
|IOC15|,
|IOC_HS|
tAR
|IOLD1|,
|IOLD6|
|IOLD4|,
|IOLD5|
40/161
Overcurrent threshold HS in high
current mode
Overcurrent threshold to HS in low
current mode
Auto recovery time limit
Under-current threshold HS & LS
VS/VSREG = 13.5 V;
V1 = 5 V; source
OUT1 to OUT6
100
ms
OUT7, OUT8, OUT_HS
120
ms
VS = 13.5 V; V1 = 5 V; sink
and source
DS11567 Rev 5
10
30
80
mA
60
150
300
mA
L99DZ120
Electrical specifications
Table 20. Current monitoring (continued)
Symbol
|IOLD7|
|IOLD8|
IOLD9|,
|IOLD13|,
|IOLD14|
|IOLD10|
|IOLD11|,
|IOLD12|,
|IOLD15|,
|IOLD_HS|
tOL_out
3.4.14
Parameter
Test condition
Min.
Typ.
Max.
Unit
Under-current threshold HS in low
on-resistance mode
15
40
60
mA
Under-current threshold HS in high
on-resistance mode
5
10
15
mA
Under-current threshold HS in low
on-resistance mode
10
30
45
mA
Under-current threshold HS in high
on-resistance mode
5
10
15
mA
6
12
mA
0.5
4
mA
Under -current threshold HS in high
current mode
10
30
mA
Under -current threshold HS in low
current mode
0.3
4
mA
Under -current threshold HS in high
current mode
6
12
mA
Under -current threshold HS in low
current mode
0.85
4
mA
250
µs
Under-current threshold HS in high
current mode
VS/VSREG = 13.5 V;
V1 = 5 V; source
Under-current threshold HS in low
current mode
Duration of open-load
condition to set the status
bit
Filter time of open-load signal
150
200
H-bridge driver
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40°C to 150 °C, unless
otherwise specified.
Table 21. H-bridge driver
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Drivers for external high-side PowerMOS
IGHx(Ch)
RGHx
VGHHx
Average charge current
(charge stage)
On-resistance (dischargestage)
Gate-on voltage
Tj = 25 °C
VSHx = 0 V; IGHx = 50 mA;
Tj = 25 °C
0.3
6
VSHx = 0 V; IGHx = 50 mA;
Tj = 130 °C
VS = SH = 6 V; ICP = 15 mA
VSHx + 6
VS = SH = 12 V; ICP = 15 mA
VSHx + 8
DS11567 Rev 5
A
10
14
Ω
14
20
Ω
V
VSHx + 10 VSHx + 11.5
V
41/161
160
Electrical specifications
L99DZ120
Table 21. H-bridge driver (continued)
Symbol
RGSHx
Parameter
Test condition
Passive gate-clamp
resistance
Min.
Typ.
VGHx = 0.5 V
Max.
Unit
15
kΩ
0.3
A
Drivers for external low-side Power-MOS
IGLx(Ch)
RGLx
Average charge-current
(charge stage)
On-resistance (dischargestage)
VGHLx
Gate-on voltage
RGSLx
Passive gate-clamp
resistance
3.4.15
Tj = 25 °C
VSLx = 0 V; IGHx = 50 mA;
Tj = 25 °C
6
VSLx = 0 V; IGHx = 50 mA;
Tj = 130 °C
VS = 6 V; ICP = 15 mA
VSLx + 6
VS = 12 V; ICP = 15 mA
VSLx + 8
10
14
Ω
14
20
Ω
V
VSLx + 10 VSLx + 11.5
15
V
kΩ
Gate drivers for the external Power-MOS switching times
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
Table 22. Gate drivers for the external Power-MOS switching times
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
TG(HL)xHL
Propagation delay time high to low
(switch mode(1)
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
1.5
µs
TG(HL)xLH
Propagation delay time low to high
(switch mode)(1)
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF
1.5
µs
IGHxrmax
Maximum source current (current
mode)
VS = 13.5 V; VSHx = 0;
VGHx = 1 V;
SLEW = 1 FH
32
mA
IGHxfmax
Maximum sink current (current
mode)
VS = 13.5 V, VSHx = 0;
VGHx = 2 V;
SLEW = 1 FH
32
mA
dIIGHxr
Source current accuracy
VS = 13.5 V; VSHx = 0;
VGHx = 1 V
See Figure 14: IGHxr
ranges
dIIGHxf
Sink current accuracy
VS = 13.5 V; VSHx = 0;
VGHx = 2 V
See Figure 15: IGHxf
ranges
Switching voltage (VS-VSH)
VDSHxrSW between current mode and switch
mode (rising)
VS = 13.5 V
2.8
V
Switching voltage (VS-VSH)
VDSHxfSW between switch mode and current
mode (falling)
VS = 13.5 V
2.8
V
42/161
DS11567 Rev 5
L99DZ120
Electrical specifications
Table 22. Gate drivers for the external Power-MOS switching times (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
t0GHxr
Rise time (switch mode)
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
45
ns
t0GHxf
Fall time (switch mode)
VS = 13.5 V; VSHx = 0;
RG = 0 Ω; CG = 2.7 nF
85
ns
t0GLxr
Rise time
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF
45
ns
t0GLxf
Fall time
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF
85
ns
tccp0001
Programmable cross-current
protection time
500
ns
tccp0010
Programmable cross-current
protection time
750
ns
tccp0011
Programmable cross-current
protection time
1000
ns
tccp0100
Programmable cross-current
protection time
1250
ns
tccp0101
Programmable cross-current
protection time
1500
ns
tccp0110
Programmable cross-current
protection time
1750
ns
tccp0111
Programmable cross-current
protection time
2000
ns
tccp1000
Programmable cross-current
protection time
2250
ns
tccp1001
Programmable cross-current
protection time
2500
ns
tccp1010
Programmable cross-current
protection time
2750
ns
tccp1011
Programmable cross-current
protection time
3000
ns
tccp1100
Programmable cross-current
protection time
3250
ns
tccp1101
Programmable cross-current
protection time
3500
ns
tccp1110
Programmable cross-current
protection time
3750
ns
tccp1111
Programmable cross-current
protection time
4000
ns
fPWMH
PWMH switching frequency
VS = 13.5 V; VSLx = 0;
RG = 0 Ω; CG = 2.7 nF;
PWMH-Duty-Cycle = 50%;
tccp configured as 0001
50
kHz
1.
DS11567 Rev 5
43/161
160
Electrical specifications
L99DZ120
Figure 13. H-driver delay times
7* +/ [/+
7* +/ [+/
9 &613:0+',5
W
9&613:0+',5
W
9 *6 +/ [
W
*$3*&)7
Figure 14. IGHxr ranges
,*+[U DFFXUDF\
,*+[U0D[
,*+[U7\S
,*+[U0LQ
'DWDLQSXW
("1($'5
44/161
DS11567 Rev 5
L99DZ120
Electrical specifications
Figure 15. IGHxf ranges
,*+[I DFFXUDF\
,*+[I0D[
,*+[I7\S
,*+[I0LQ
'DWDLQSXW
3.4.16
("1($'5
Drain source monitoring external H-bridge
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40°C to 150 °C, unless
otherwise specified.
Table 23. Drain source monitoring external H-bridge
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSCd1_HB
Drain-source threshold voltage
0.375
0,5
0.625
V
VSCd2_HB
Drain-source threshold voltage
0.6
0,75
0.9
V
VSCd3_HB
Drain-source threshold voltage
0,85
1
1,15
V
VSCd4_HB
Drain-source threshold voltage
1,06
1,25
1,43
V
VSCd5_HB
Drain-source threshold voltage
1,27
1,5
1,73
V
VSCd6_HB
Drain-source threshold voltage
1,49
1,75
2,01
V
VSCd7_HB
Drain-source threshold voltage
1,7
2
2,3
V
tSCd_HB
Drain-source monitor filter time
tscs_HB
Drain-source comparator settling
time
3.4.17
6
VS = 13.5 V;
VSH = jump from GND to VS
µs
5
µs
Open-load monitoring external H-bridge
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 28 V; 6 V ≤ VSREG ≤ 28 V; Tj = -40 °C to 150 °C, unless
otherwise specified.
DS11567 Rev 5
45/161
160
Electrical specifications
L99DZ120
Table 24. Open-load monitoring external H-bridge
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VODSL
Low-side drain-source monitor low
off-threshold voltage
VSLx = 0 V; VS = 13.5 V
0.15 VS
V
VODSH
Low-side drain-source monitor high
off-threshold voltage
VSLx = 0 V; VS = 13.5 V
0.85 VS
V
VOLSHx
Output voltage of selected SHx in
open-load test mode
VSLx = 0 V; VS = 13.5 V
0.5 VS
V
RpdOL
Pull-down resistance of the nonVSLx = 0 V; VS = 13.5 V;
selected SHx pin in open-load mode VSHX = 4.5 V
20
kΩ
tOL_HB
Open-load filter time
2
ms
3.4.18
Fail safe low-side switch
The voltages are referred to power ground and currents are assumed positive, when the
current flows into the pin. 6 V ≤ VS ≤ 18 V; Tj = 40 °C to 150 °C, unless otherwise specified.
Table 25. Fail safe low-side switch
Symbol
VOUT_max
Parameter
Max output voltage in
case of missing supply
RDSON
DC output resistance
IOLimit
Overcurrent limitation
tONHL
Test condition
Min.
IOUT = 1 mA; VS = VSREG = 0 V
ILOAD = 250 mA; Tj = 25 °C
Typ.
Max.
Unit
2
2.5
V
1.4
ILOAD = 250 mA; Tj = 130 °C
Ω
2.2
Ω
1500
mA
Turn on delay time to
10% VOUT
100
µs
tOFFLH
Turn off delay time to
90% VOUT
100
µs
tSCF
Short circuit filter time
dVmax/dt
46/161
8 V < VS < 16 V
500
64
Maximum external
applied slew rate on
Guaranteed by design
LS1_FSO and LS2_FSO
without switching on LS
DS11567 Rev 5
60
µs
V/µs
L99DZ120
3.4.19
Electrical specifications
Wake up input WU
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 28 V; Tj = 40 °C to 150 °C, unless otherwise specified.
Table 26. Wake-up inputs
Symbol
Parameter
VWUthn
Test condition
Min.
Typ.
Max.
Unit
Wake-up negative
edge threshold voltage
0.4
VSREG
0.45
VSREG
0.5
VSREG
V
VWUthp
Wake-up positive edge
threshold voltage
0.5
VSREG
0.55
VSREG
0.6
VSREG
V
VHYST
Hysteresis
0.05
VSREG
0.1
VSREG
0.15
VSREG
V
tWU_stat
Static wake filter time
VWU < 1 V or
VWU > (VSREG – 1.5 V)
IWU_stdby
Input current in
standby mode
RWU_act
Input resistor to GND
in Active mode and in
Standby mode during
Wake-up input sensing
tWU_cyc
Cyclic wake filter time
3.4.20
64
µs
5
30
60
μA
80
160
300
kΩ
16
µs
LIN transceiver
LIN 2.2 compliant for bit-rates up to 20 kBit/s SAE J2602 compatible.
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V; Tjunction = -40 °C to 150°C unless otherwise
specified.
Table 27. LIN transmit data input: pin TxD
Symbol
Parameter
Test condition
Min.
VTXDLOW
Input voltage dominant level
Active mode
VTXDHIGH
Input voltage recessive level
Active mode
VTXDHYS
VTXDHIGH-VTXDLOW
Active mode
0.2
RTXDPU
TXD pull up resistor
Active mode
13
Typ.
Max.
1.0
Unit
V
2.3
V
V
29
46
kΩ
Typ.
Max.
Unit
0.2
0.5
V
Table 28. LIN receive data output: pin RxD
Symbol
Parameter
Test condition
VRXDLOW
Output voltage dominant level
Active mode
VRXDHIGH
Output voltage recessive level
Active mode
DS11567 Rev 5
Min.
V1-0.5
V1-0.2
V
47/161
160
Electrical specifications
L99DZ120
Table 29. LIN transmitter and receiver: pin LIN
Symbol
Parameter
VTHdom
Receiver threshold voltage
recessive to dominant state
VBusdom
Receiver dominant state
Test condition
Min.
Typ.
Max.
Unit
0.4
VSREG
0.45
VSREG
0.5
VSREG
V
0.4VSRE
G
0.55
VSREG
0.6
VSREG
V
VTHrec
Receiver threshold voltage
dominant to recessive state
0.5
VSREG
VBusrec
Receiver recessive state
0.6
VSREG
VTHhys
Receiver threshold
hysteresis: VTHrec -VTHdom
0.07
VSREG
0.1
VSREG
0.175
VSREG
V
VTHcnt
Receiver tolerance center
value: (VTHrec +VTHdom)/2
0.475
VSREG
0.5
VSREG
0.525
VSREG
V
V
V
VTHwkup
Activation threshold for
wake-up comparator
1.0
1.5
2
V
VTHwkdwn
Activation threshold for
wake-up comparator
VSREG 3.5
VSREG 2.5
VSREG1.5
V
tLINBUS
LIN Bus Wake-up Dominant
Sleep mode; edge: rec-dom
Filter time
tdom_LIN
LIN Bus Wake-up Dominant Sleep mode; edge: rec-domFilter time
rec
28
Transmitter input current
limit in dominant state
40
ILINDomSC
VTXD = VTXDLOW;
VLIN = VBATMAX = 18 V
Ibus_PAS_dom
Input leakage current at the VTXD = VTXDHIGH; VLIN = 0 V;
receiver incl. pull-up resistor VBAT = 12 V; Slave mode
Ibus_PAS_rec
Transmitter input current in
recessive state
In standby modes;
VTXD = VTXDHIGH; VLIN > 8 V;
VBAT < 18 V; VLIN ≥ VBAT
Ibus_NO_GND
Input current if loss of GND
at device
GND = VSREG;
0 V < VLIN < 18 V;
VBAT = 12 V
Ibus
Input current if loss of VBAT
at device
μs
100
180
-1
mA
mA
μA
1
mA
GND = VS; 0 V < VLIN < 18 V
Tj=-40 °C ....105 °C(1)
30
μA
GND = VS; 0 V < VLIN < 18 V
Tj= 130 °C(2)
35
μA
1.2
V
LIN voltage level in
dominant state
Active mode;
VTXD = VTXDLOW;
Rbus = 500 Ω
VLINrec
LIN voltage level in
recessive state
Active mode;
VTXD = VTXDHIGH;
ILIN = 10 µA
RLINup
LIN output pull up resistor
VLIN = 0 V
LIN input capacitance
Guaranteed by design
48/161
μs
20
VLINdom
CLIN
64
DS11567 Rev 5
-1
0.8*VS
20
V
40
60
kΩ
100
pF
L99DZ120
Electrical specifications
1. 105°C is the maximum junction temperature of an unpowered device according to this test condition within the specified
ambient temperature range
2. Used for device test only
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V < VS < 28V; Tj = -40 °C to 150 °C, unless otherwise specified.
Table 30. LIN transceiver timing
Symbol
tRXpd
tRXpd_sym
D1
D2
D3
D4
tdom(TXDL)
Parameter
Test condition
Min.
Receiver propagation
delay time
tRXpd = max(tRXpdr, tRXpdf);
tRXpdf = t(0.5 VRXD)-t(0.45 VLIN);
tRXpdr = t(0.5 VRXD)-t(0.55 VLIN);
VSREG = 12 V; CRXD=20 pF;
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Symmetry of receiver
propagation delay time
(rising vs. falling edge)
tRXpd_sym = tRXpdr - tRXpdf; VSRE = 12 V;
Rbus = 1 kΩ; Cbus = 1 nF; CRXD = 20 pF
-2
Duty Cycle 1
THRec(max) = 0.744 * VSREG;
THDom(max) = 0.581 * VSREG;
VSREG = 7 to 18 V, tbit = 50 µs;
D1 = tbus_rec(min) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
0.396
Duty Cycle 2
THRec(min) = 0.422* VSREG;
THDom(min) = 0.284* VSREG;
VSREG = 7.6 to 18 V, tbit = 50 µs;
D2 = tbus_rec(max) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Duty Cycle 3
THRec(max) = 0.778* VSREG;
THDom(max) = 0.616* VSREG; VSREG = 7
to 18 V, tbit = 96 µs;
D3 = tbus_rec(min) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
Duty Cycle 4
THRec(min) = 0.389* VSREG;
THDom(min) = 0.251* VSREG;
VSREG = 7.6 to 18 V, tbit = 96 µs;
D4 = tbus_rec(max) / (2 x tbit);
Rbus = 1 kΩ, Cbus = 1 nF; Rbus = 660 Ω,
Cbus = 6.8 nF; Rbus = 500 Ω,
Cbus = 10 nF
TXDL dominant timeout
Typ.
Unit
6
μs
2
μs
0.581
0.417
0.590
12
DS11567 Rev 5
Max.
ms
49/161
160
Electrical specifications
L99DZ120
Table 30. LIN transceiver timing (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tLIN
LIN permanent
recessive time-out
40
μs
tdom(bus)
LIN Bus permanent
dominant time-out
12
ms
Figure 16. LIN transmit, receive timing
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3.4.21
SPI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VSREG < 18 V; V1 = 5 V; all outputs open; Tj = -40 °C to 150 °C,
unless otherwise specified.
Table 31. Input: CSN
Symbol
Parameter
Test condition
Min.
Typ.
VCSNLOW
Input voltage low level
Normal mode
VCSNHIGH
Input voltage high level
Normal mode
VCSNHYS
VCSNHIGH - VCSNLOW
Normal mode
0.2
ICSNPU
CSN Pull up resistor
Normal mode
13
29
Min.
Typ.
Max.
1.0
Unit
V
2.3
V
V
46
kΩ
Max.
Unit
Table 32. Inputs: CLK, DI
Symbol
tset
tset_CP
50/161
Parameter
Test condition
Delay time from standby Time until SPI, ADC and
to Active mode
OUT15/OUT_HS are operative
Delay time from standby Time until power stages that are
to Active mode
supplied by the CP are operative
DS11567 Rev 5
10
560
750
µs
960
µs
L99DZ120
Electrical specifications
Table 32. Inputs: CLK, DI (continued)
Symbol
Parameter
Vin_L
Input low level
Vin_H
Input high level
Test condition
Min.
Typ.
Max.
1.0
V
2.3
Vin_Hyst Input hysteresis
0.2
Ipdin
Pull down current at
input
Vin = 1.5 V
Cin(1)
Input capacitance at
input CSN, CLK, DI and
PWM1,2
Guaranteed by design
fCLK
SPI input frequency at
CLK
5
Unit
V
V
30
60
µA
15
pF
4
MHz
Max.
Unit
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 33. DI, CLK and CSN timing
Symbol
Note:
Parameter
Test condition
Min.
Typ.
tCLK
Clock period
250
ns
tCLKH
Clock high time
100
ns
tCLKL
Clock low time
100
ns
tset_CSN
CSN setup time, CSN low
before rising edge of CLK
150
ns
tset_CLK
CLK setup time, CLK high
before rising edge of CSN
150
ns
tset_DI
DI setup time
25
ns
thold_DI
DI hold time
25
ns
tr_in
Rise time of input signal DI,
CLK, CSN
25
ns
tf_in
Fall time of input signal DI,
CLK, CSN
25
ns
Max.
Unit
0.5
V
See Figure 18: SPI input timing.
Table 34. Output: DO
Symbol
Parameter
Test condition
VDOL
Output low level
IDO = -4 mA
VDOH
Output high level
IDO = 4 mA
IDOLK
3-state leakage
current
VCSN = V1, 0 V < VDO < V1
CDO
3-state input
capacitance
Guaranteed by design
DS11567 Rev 5
Min.
Typ.
V1 - 0.5
V
-10
10
10
μA
15
pF
51/161
160
Electrical specifications
L99DZ120
Table 35. DO timing
Symbol
Test condition
Min.
Typ.
Max.
Unit
tr DO
DO rise time
CL = 50 pF; ILOAD = -1 mA
25
ns
tf DO
DO fall time
CL = 50 pF; ILOAD = -1 mA
25
ns
ten DO tri L
DO enable time from
3-state to low level
CL = 50 pF; ILOAD = -1 mA;
pull-up load to V1
50
100
ns
tdis DO L tri
DO disable time from
low level to 3-state
CL = 50 pF; ILOAD = -1 mA;
pull-up load to V1
50
100
ns
ten DO tri H
DO enable time from
3-state to high level
CL = 50 pF; ILOAD = -1 mA;
pull-down load to GND
50
100
ns
tdis DO H tri
DO disable time from
high level to 3-state
CL = 50 pF; ILOAD = -1 mA;
pull-down load to GND
50
100
ns
DO delay time
VDO < 0.3 V1;
VDO > 0.7 V1; CL = 50 pF
30
60
ns
Typ.
Max.
Unit
td DO
Note:
Parameter
See Figure 19: SPI output timing.
Table 36. CSN timing
Symbol
Parameter
tCSN_HI,min
Minimum CSN
high time, active
mode
tCSNfail
CSN low timeout
Test condition
Transfer of SPI-command to
Input Register
Min.
6
μs
20
Note:
See Figure 20: SPI CSN - output timing.
3.4.22
Input LIN_FLASH for Flash mode
35
50
ms
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6V ≤ VSREG ≤ 18; V1 = 5 V; Tj = -40 °C to 150 °C.
Table 37. Inputs LIN_FLASH for Flash mode
Symbol
Test condition
Min.
Typ.
Max. Unit
VflashL
Input low level (VLIN_FLASH
for exit from Flash mode)
6.1
7.25
8.4
V
VflashH
Input high level (VLIN_FLASH
for transition into Flash
mode)
7.4
8.4
9.4
V
Input voltage hysteresis
0.6
0.8
1.0
V
VflashHYS
52/161
Parameter
DS11567 Rev 5
L99DZ120
3.4.23
Electrical specifications
Inputs DIR, DIRH, PWMH
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V; Tj = -40 °C to 150 °C.
Table 38. Inputs DIR, DIRH, PWMH
Symbol
Test condition
Min.
VIL
Input voltage low level
VSREG = 13.5 V
VIH
Input voltage high level
VSREG = 13.5 V
Input hysteresis
VSREG = 13.5 V
0.2
Input pull-down current
VSREG = 13.5 V
5
VIHYS
Iin
3.4.24
Parameter
Typ.
Max.
1
Unit
V
2.3
V
V
30
60
µA
Debug input
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V; Tj = -40 °C to 150 °C.
Table 39. Debug input
Symbol
Test condition
Min.
VdIL
Input voltage low level
VSREG = 13.5 V
VdIH
Input voltage high level
VSREG = 13.5 V
Input hysteresis
VSREG = 13.5 V
0.2
Pull-down resistor
VDEBUG = 6 to 18 V
2.5
VdIHYS
Rdin
3.4.25
Parameter
Typ.
Max.
1
Unit
V
2.3
V
V
5
7.5
kΩ
ADC characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V, Tj = -40 °C to 150 °C.
Table 40. ADC characteristics
Symbol
Parameter
Test condition
tcon
Conversion time
fADC
Clock frequency (see
fclk2)
Acc
Accuracy
Min.
Typ.
Max.
2.5
µs
8
MHz
Voltage divider + reference(1)
-2
2
Overall accuracy for WU
input: WU = 22 V
-3
3
Overall accuracy for WU
input: WU = 18 V
-3.5
3.5
Overall accuracy for WU
input: WU = 6 V
-4
4
Overall accuracy for WU
input: WU = 4.5 V
-4.6
4.6
DS11567 Rev 5
Unit
%
53/161
160
Electrical specifications
L99DZ120
Table 40. ADC characteristics (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
IEII
Integral linearity error
4
LSB
IEDI
Differential linearity
error
2
LSB
VAINVS
Conversion voltage
range (VS, VSREG &
WU)
1
22
V
VAINTemp
Conversion voltage
range (TCL1 …TCL6)
0
2
V
1. Guaranteed by design.
3.4.26
Temperature diode characteristics
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V, Tj = -40 °C to 150 °C
Table 41. Temperature diode characteristics
Symbol
3.4.27
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTROOM 1-6
TSENSE output
voltage at 25 °C
VS = 12 V; T = 25 °C
—
1.4
V
VTSENSE1-6
TSENSE output
voltage 1 - 8
T = 25 °C; T = 130 °C;
T = -40 °C
—
-4
mV/K
Interrupt outputs
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V ≤ VSREG ≤ 18 V, Tj = -40 °C to 150°C
Table 42. Interrupt outputs
Symbol
54/161
Parameter
Test condition
VINTL
Output low level
IINT = -4 mA
VINTH
Output high level
IINT = 4 mA
IINTLK
3-state leakage current
0 V < VINT < V1
tInterrupt
Interrupt pulse duration
(NINT, RxD_L/NINT)
tInt_react
Interrupt reaction time
Min.
Typ.
Max.
Unit
0.5
V
V1 - 0.5
V
-10
10
s
56
Tested by scan chain
DS11567 Rev 5
6
μA
40
µs
L99DZ120
3.4.28
Electrical specifications
Timer1 and Timer2
6 V ≤ VSREG ≤ 18 V; Tj = -40 °C to 150 °C
Table 43. Timer1 and Timer2
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
ton 1
Timer on time
0.1
ms
ton 2
Timer on time
0.3
ms
ton 3
Timer on time
1
ms
ton 4
Timer on time
10
ms
ton 5
Timer on time
20
ms
T1
Timer period
10
ms
T2
Timer period
20
ms
T3
Timer period
50
ms
T4
Timer period
100
ms
T5
Timer period
200
ms
T6
Timer period
500
ms
T7
Timer period
1000
ms
T8
Timer period
2000
ms
Figure 17. SPI – transfer timing diagram
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The SPI can be driven by a micro controller with its SPI peripheral running in the following
mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
DS11567 Rev 5
55/161
160
Electrical specifications
L99DZ120
Figure 18. SPI input timing
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56/161
DS11567 Rev 5
L99DZ120
Electrical specifications
Figure 19. SPI output timing
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DS11567 Rev 5
57/161
160
Electrical specifications
L99DZ120
Figure 20. SPI CSN - output timing
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Figure 21. SPI – CSN high to low transition and global status bit access
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3.4.29
SGND loss comparator
Tj = -40 °C to 150 °C, unless otherwise specified.
Table 44. SGND loss comparator
Symbol
Parameter
Test condition
VSGNDloss VSGND loss threshold (VSGND – VPGND )
tSGNDloss
58/161
VSGND loss filter time
DS11567 Rev 5
Min.
Typ.
Max.
Unit
100
270
500
mV
5
7
9
µs
L99DZ120
Application information
4
Application information
4.1
Supply VS, VSREG
VSREG supplies voltage regulators V1 and V2, all internal regulated voltages for analog and
digital functionality, LIN and both P-channel high-side switches OUT15 and OUT_HS.
All other high-sides, Fail Safe block and the charge pump are supplied by VS.
In case the VSREG pin is disconnected, all power outputs connected to VS are automatically
switched off.
4.2
Voltage regulators
The device contains two independent and fully protected low drop voltage regulators
designed for very fast transient response and do not require electrolytic output capacitors
for stability.
The output voltage is stable with ceramic load capacitors >220 nF.
4.2.1
Voltage regulator: V1
The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load
current to supply the system microcontroller. The V1 regulator is embedded in the power
management and fail-safe functionality of the device and operates according to the selected
operating mode. The V1 voltage regulator is supplied by pin VSREG.
In addition, the V1 regulator supplies the devices internal loads. The voltage regulator is
protected against overload and overtemperature. An external reverse current protection has
to be provided by the application circuitry to prevent the input capacitor from being
discharged by negative transients or low input voltage. Current limitation of the regulator
ensures fast charge of external bypass capacitors. The output voltage is stable for ceramic
load capacitors >220 nF.
In case the device temperature exceeds the TSD1 threshold (either cluster or grouped
mode) the V1 regulator remains on. The micro controller has the possibility for interaction or
error logging. If the chip temperature exceeds the TSD2 threshold (TSD2 > TSD1), V1 will
be deactivated and all wakeup sources (LIN, WU and Timer) are disabled. After tTSD, the
voltage regulator will restart automatically. If the restart fails 7 times within one minute the
devices enter the Forced Vbat_standby mode. The status bit
FORCED_SLEEP_TSD2/V1SC (SR1) is set.
4.2.2
Voltage regulator: V2
The voltage regulator V2 is supplied by pin VSREG and can supply additional 5 V loads such
as sensors or potentiometers. The maximum continuous load current is 50 mA. The
regulator is protected against:
Overload
Overtemperature
Short-circuit (short to ground and battery supply voltage)
Reverse biasing
DS11567 Rev 5
59/161
160
Application information
4.2.3
L99DZ120
Voltage regulator failure
The V1, and V2 regulator output voltages are monitored.
In case of a drop below the failure thresholds (V1 < V1fail for t > tV1fail, V2 < V2fail for
t > tV2fail), the failure bits V1FAIL, V2FAIL (SR 2) are latched.
4.2.4
Short to ground detection
At turn-on of the V1 and V2 regulators, a short-to-GND condition is detected by monitoring
the regulator output voltage.
If V1 or V2 is below the V1fail (or V2fail) threshold for t > tV1short (t > tV2short) after turn-on, the
devices will identify a short circuit condition at the related regulator will be switched off.
In case of V1 short-to-GND the device enters Forced Vbat_standby mode automatically. Bits
FORCED_SLEEP_TSD2/V1SC and (SR 1) V1FAIL (SR 2) are set.
In case of a V2 short-to-GND failure the V2SC (SR 2) and V2FAIL (SR 2) bits are set.
Once the output voltage of the corresponding regulator exceeded the V1fail (V2fail) threshold
the short-to-ground detection is disabled. In case of a short-to-ground condition, the
regulator is switched off due to thermal shutdown. V1 is switched off at TSD2, V2 is
switched off at TSD1.
60/161
DS11567 Rev 5
L99DZ120
4.2.5
Application information
Voltage regulator behavior
Figure 22. Voltage regulator behaviour and diagnosis during supply voltage
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4.3
Operating modes
The devices can be operated in the following operating modes:
4.3.1
Active
LIN Flash
V1_standby
VBAT_standby
Debug
Active mode
All functions are available and the device is controlled by SPI.
DS11567 Rev 5
61/161
160
Application information
4.3.2
L99DZ120
Flash mode
To program the system microcontroller via LIN bus signals, the devices can be operated in
LIN Flash mode. The watchdog is disabled in this mode.
The Flash mode is entered by applying an external voltage at the pin:
VLIN_FLASH ≥ VFlashH (LIN Flash mode)
In LIN Flash mode the maximum bitrate is increased to 100 kbit/s automatically
(LIN_HS_EN = 1).
A transition from Flash mode to V1_standby or Vbat_standby mode is not possible.
At exit from Flash modes (VLIN_FLASH < VFlashL) no NReset pulse is generated. The
watchdog starts with a Long Open Window (tLW).
4.3.3
SW-debug mode
To allow software debugging, the watchdog can be deactivated by applying an external
voltage to the DEBUG input pin (Vdebug > VdiH).
In Debug mode, all device functionality and Operating modes are available. The watchdog
is deactivated. At Exit from Debug mode (Vdebug < VdiL) the watchdog starts with a Long
Open Window.
Note:
The device includes a test mode. This mode is activated by a dedicated sequence which
includes a high voltage at the Debug Pin. The Debug Pin must be kept at nominal voltage
levels in order to avoid accidental activation of the test mode.
4.3.4
V1_standby mode
The transition from Active mode to V1_standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the V1 voltage regulator remains active.
After the V1_standby command (CSN low to high transition), the device enters V1_standby
mode immediately and the watchdog starts a Long Open Window (tLW). The watchdog is
deactivated as soon as the V1 load current drops below the ICMP threshold (IV1< Icmp_fal).
The V1 load current monitoring can be deactivated by setting ICMP = 1. In this configuration
the watchdog will be deactivated upon transition into V1_standby mode without monitoring
the V1 load current.
Writing ICMP (CR 34) = 1 is only possible with the first SPI command after setting
ICMP_CONFIG_EN (Config Reg) = 1.
The ICMP_CONFIG_EN bit is reset to 0 automatically with the next SPI command.
Power outputs (except OUT_HS & OUT15) are switched off in V1_standby mode. OUT_HS
& OUT15 remain in the configuration programmed prior to the standby command in order to
enable (cyclic) supply of external contacts. The timer signal (Timer1 or Timer2) can be
mirrored to the NINT output pin during V1_standby mode.
LIN transmitter (TxDL) is off.
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DS11567 Rev 5
L99DZ120
4.3.5
Application information
Interrupt
Figure 23. NINT pins
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RxDL/NINT indicates:
a wake-up event from V1_standby mode and the programmable timer interrupt
RxDL/NINT pin is pulled low for t = tinterrupt.
NINT indicates:
In Active mode:
VSREG dropped below the programmed early warning threshold in Control Register 3
(VSREG < VSREG_EW_TH); feature is deactivated if VSREG_EW_TH is set to 0 V.
In V1_standby mode
–
Programmable timer interrupt; An NINT pulse is generated at the beginning of the
timer on-time (Timer 1 or Timer2)
–
Wake-up from V1_standby mode by any wake-up source
NINT is pulled low for t = tinterrupt
In case of increasing V1 load current during V1_standby mode (IV1 > Icmp_ris), the device
remains in standby mode and the watchdog starts with a Long Open Window. No Interrupt
signal is generated.
4.3.6
VBAT_standby mode
The transition from Active mode to Vbat_standby mode is initiated by an SPI command. In
Vbat_standby mode, the voltage regulators V1 and V2 (depending on configuration in
CR 1), the power outputs (except OUT15 and OUT_HS) as well as LIN transmitter are
switched off.
An NReset pulse is generated upon wake-up from Vbat_standby mode.
4.4
Wake-up from Standby modes
A wake-up from standby mode will switch the device to Active mode. This can be initiated by
one or more of the following events:
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L99DZ120
Table 45. Wake-up events description
Wake up source
LIN bus activity
Level change of WU
IV1 >Icmp_ris
Description
Always enabled
Can be configured or disabled by SPI
Device remains in V1_standby mode but watchdog is enabled (If
ICMP = 0). No interrupt is generated.
Programmable by SPI:
– V1_standby mode: device wakes up after programmable timer
Timer Interrupt / Wake up
expiration. NINT and RxDL/NINT interrupt signals are generated
of µC by TIMER
– Vbat_standby mode: device wakes up after programmable timer
expiration, V1 regulator is turned on and NReset signal is generated
SPI Access
4.4.1
Always active (except in VBAT_STANDBY mode)
Wake up event: CSN is low and first rising edge on CLK
Wake up input
The WU input can be configured as wake-up source. The wake-up input is sensitive to any
level transition (positive and negative edge) and can be configured for static or cyclic
monitoring of the input voltage level.
For static contact monitoring, a filter time of tWU_STAT is implemented. The filter is started
when the input voltage passes the specified threshold VWU_THP or VWU_THN.
Cyclic contact monitoring allows periodical activation of the wake-up input to read the status
of the external contact. The periodical activation can be configured to Timer 1 or Timer 2.
The input signal is filtered with a filter time of tWU_CYC after a delay (80% of the configured
Timer on-time). A Wake-up will be processed if the status has changed versus the previous
cycle. The buffered output OUT_HS can be used to supply the external contacts with the
timer setting according to the cyclic monitoring of the wake-up input.
In standby modes, the input WU is configurable with an internal pull-up or pull-down current
source according to the setup of the external contact. In Active mode the inputs have an
internal pull down resistor (RWU_act) and the input status can be read by SPI. Static sense
should be configured before the read operation is started in order to reflect the actual input
level.
4.5
Functional overview (truth table)
Table 46. Status of different functions/features vs operating modes
Operating modes
Function
Voltage regulator V1
Voltage regulator V2
Reset generator
64/161
Comments
VOUT = 5 V
VOUT = 5 V
Active mode
V1-standby static
mode (cyclic sense)
On
On(1)
On/
Off(2)
On
DS11567 Rev 5
On(2)
/ Off
On
Vbat-standby static
mode (cyclic sense)
Off
On(2)
/ Off
Off
L99DZ120
Application information
Table 46. Status of different functions/features vs operating modes (continued)
Operating modes
Function
Comments
Active mode
V1-standby static
mode (cyclic sense)
Vbat-standby static
mode (cyclic sense)
On
Off (on if IV1 > ICMP
and ICMP = 0)
Off
Off
Active(3)
Active(3)
Oscillator time
base
On / Off
On(2) / Off
On(2) / Off
LIN 2.2a
On
Off(4)
Off(4)
Oscillator OSC1
2 MHz
On
On/Off(5)
On/Off(5)
Oscillator OSC2
32 MHz
ON
Off
Off
VSREG-Monitor
On
(6)
(6)
VS-Monitor
On
Off
Off
H-bridge Gate Driver, bridge
drivers, all high-side drivers
(except OUT_HS & OUT15)
supplied by VS
On/ Off(2)
Off
Off
Fail-safe low-side switches
On/ Off(7)
On
On
On
On
On
On/ Off(2)
On/ Off (2)
On/ Off(2)
Charge pump
On
Off
Off
ADC (SPI read out and
VSREG early warning
interrupt)
On
Off
Off
Thermal shutdown TSD2
On
On
Off
Thermal shutdown TSD1x for
OUT_HS and OUT15 (Pchannel HS)
On
On/ Off(2)
On/ Off(2)
Window watchdog
V1 monitor
Wake up
HS-cyclic supply
LIN
Short circuit protection for
fail-safe low-side switches (in
case LS is switched on)
OUT_HS & OUT15 (Pchannel HS) supplied by
VSREG
1. Supply the processor in low current mode.
2. According to SPI setting and DIR.
3. Unless disabled by SPI.
4. The bus state is internally stored when going to standby mode. A change of bus state will lead to a wake-up after exceeding
of internal filter time.
5. ON, if cyclic sense is enabled or during wake-up request.
6. Cyclic activation = pulsed ON during cyclic sense.
7. ON in Fail-Safe mode; if standby mode is entered with active Fail-safe mode the output remains ON in standby mode.
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L99DZ120
Figure 24. Main operating modes
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4.6
Configurable window watchdog
During normal operation, the watchdog monitors the micro controller within a programmable
trigger cycle.
After power-on or standby mode, the watchdog is started with a timeout (Long Open
Window tLW). The timeout allows the micro controller to run its own setup and then to start
the window watchdog by setting TRIG (CR1,ConfigReg) =1
Subsequently, the micro controller has to serve the watchdog by alternating the watchdog
trigger bit TRIG (CR1,Config Reg) within the safe trigger area TSWX.
The trigger time is configurable by SPI. A correct watchdog trigger signal will immediately
start the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off
for tV1OFF. After 7 additional watchdog failures the V1 regulator is turned off permanently
and the device goes into Forced Vbat_standby mode. The status bit FORCED_SLEEP_WD
(SR 1) is set. A wake-up is possible by LIN.
After wake-up from Forced Vbat_standby mode and the watchdog trigger still fails, the
device enters Forced Vbat_standby mode again after one Long Open Window.
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L99DZ120
Application information
This actually produces an additional watchdog failure but the watchdog fail counter will
remain at maximum value of 15 failures.
This sequence is repeated until a valid watchdog trigger event is performed by writing
TRIG = 1.
In case of a Watchdog failure, the power outputs and V2 are switched off and the status bit
WDFAIL (SR 1) is set to 1. A reset pulse is generated at NReset output and the device
enters Fail-safe mode. Control registers are set to their Fail Safe values and the Fail-safe
low-side switches are turned on. Please refer to chapter Section 4.7: Fail-safe mode for
more details.
The following diagrams illustrate the Watchdog behavior of the devices. The diagrams are
split into 3 parts. The first diagram shows the functional behavior of the watchdog without
any error. The second diagram covers the behavior covering all the error conditions, which
can affect the watchdog behavior. Figure 27: Watchdog in Flash mode shows the transition
in and out of Flash modes. Figure 25, Figure 26 and Figure 27 can be overlapped to get all
the possible state transitions under all circumstances. For a better readability, they were
split in normal operating, operating with errors and Flash mode.
Figure 25. Watchdog in normal operating mode (no errors)
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DS11567 Rev 5
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Application information
L99DZ120
Figure 26. Watchdog with error conditions
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Note:
Whenever the device is operated without servicing the mandatory watchdog trigger events,
a sequence of 15 consecutive reset events is performed and the device enters the
Forced_Vbat_Stby mode with bit FORCED_SLEEP_WD in SR1 set.
If the device is woken up after such a forced VBAT_Standby condition and the watchdog is
still not serviced, the device, after one long open watchdog window will re-enter the same
Forced_Vbat_Stby mode until the next wake up event. In this case, an additional watchdog
failure is generated, but the fail counter is not cleared, keeping the maximum number of 15
failures. This sequence is repeated until a valid watchdog trigger event is performed by
writing TRIG = 1.
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DS11567 Rev 5
L99DZ120
4.6.1
Application information
Change watchdog timing
The watchdog trigger time is configured by setting WD_TIME_x (CR 2). Writing to these bits
is possible only using the first SPI command after setting WD_CONFIG_EN = 1 (Config
Reg). The WD_CONFIG_EN bit is reset to 0 automatically with the next SPI command.
4.7
Fail-safe mode
4.7.1
Temporary failures
The devices enter Fail-safe mode in case of:
Watchdog failure
V1 turn on failure
V1 failure (V1 < VRTxfalling for t > tV1FS)
Thermal Shutdown TSD2
–
V1 short (V1 < V1fail for t > tV1short)
The Fail Safe functionality is also available in V1_Standby mode. During V1_Standby mode
the Fail Safe mode is entered in the following cases:
V1 failure (V1 < VRTxfalling for t > tV1FS)
Watchdog failure (if watchdog still running due to IV1 > Icmp_fal)
Thermal Shutdown TSD2
In Fail Safe mode the devices return to a fail safe state. The Fail Safe condition is indicated
to the system in the Global Status Byte. The conditions during Fail Safe mode are:
All outputs beside LS1_FSO and LS2_FSO are turned off
All Control Registers are set to fail safe default values
Write operations to Control Registers are blocked until the Fail Safe condition is
cleared. The following bits are not WRITE protected:
–
TRIG (CR1, Config Register ): watchdog trigger bit
–
V2_x (CR1): Voltage Regulator V2 control
–
CR2 (bit ): Timer1 and Timer2 settings
–
OUT_HS_x (CR5 ): OUT_HS configuration
–
OUT15_x (CR6): OUT15 configuration
–
PWMx_freq_y (CR12): PWM frequency configuration
–
PWMx_DC_y (CR13 – CR17): PWM duty cycle configuration
LIN transmitter and SPI remain on (transmitters are deactivated in case of thermal
shutdown TSD1 (TSD1 cluster 5 or 6 in cluster mode)
Corresponding Failure Bits in Status Registers are set
FS Bit (Global Status Byte) is set
LS1_FSO and LS2_FSO will be turned on
Charge pump is switched off
If the Fail Safe mode was entered it keeps active until the Fail safe condition is removed and
the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the
actions to exit Fail safe mode are as shown in the following table.
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Application information
L99DZ120
Table 47. Temporary failures description
Failure source
Failure condition
Microcontroller
(oscillator)
Watchdog early write
failure or expired
window
FS (Global Status Byte) =1;
WDFAIL (SR 1) =1;
WDFAIL_CNT_x (SR 1) = n+1
TRIG (CR 1) = 1 during long
open window Read&Clear
SR1
Short at turn-on
FS (Global Status Byte) =1;
FORCED_SLEEP_TSD2/V1SC
(SR 1) =1
Wake-up;
Read&Clear SR1
Undervoltage
FS (Global Status Byte) = 1; V1UV
(SR 1) = 1; V1fail (SR 2) = 1(1)
V1 >VRTrising;
Read&Clear SR1
Tj > TSD2
FS (Global Status Byte) = 1; TW
(SR 2) = 1;
TSD1 (SR 1) =1;
TSD2 (SR 1) =1
Tj < TSD2;
Read&Clear SR1
V1
Temperature
Diagnosis
Exit from Fail-safe mode
1. If V1 < V1fail (for t > tV1fail). The Fail-safe Bit is located in the Global Status Register.
4.7.2
Non-recoverable failures – forced Vbat_standby mode
If the Fail-safe condition persists and all attempts to return to normal system operation fail,
the devices enter the Forced Vbat_standby mode in order to prevent damage to the system.
The Forced Vbat_standby mode can be terminated by any wake-up source. The root cause
of the Forced Vbat_standby mode is indicated in the SPI Status Registers.
In Forced Vbat_standby mode, all Control Registers are set to power-on default values
except:
CP_DITH_DIS (Config. Reg )
The Forced Vbat_standby mode is entered in case of:
Multiple watchdog failures: FORCED_SLEEP_WD (SR 1) = 1 (15 x watchdog failure)
Multiple thermal shutdown 2: FORCED_SLEEP_TSD2/V1SC (SR 1) = 1 (7 x TSD2)
V1 short at turn-on (V1 < V1fail for t > tV1short):
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Table 48. Non-recoverable failure
Failure source
Failure condition
Temperature
70/161
Exit from Fail-safe mode
FS (Global Status Byte) = 1; WDFAIL (SR
1) = 1; FORCED_SLEEP_WD (SR 1) = 1
Wake-up;
TRIG (CR 1) = 1 during long
open window; Read&Clear
SR1
Short at turn-on
FS (Global Status Byte) = 1;
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Wake-up;
Read&Clear SR1
7 times TSD2
FS (Global Status Byte) =1; TW (SR 2) = 1;
Wake-up;
TSD1 (SR 1) = 1; TSD2 (SR 1) = 1;
Read&Clear SR1
FORCED_SLEEP_TSD2/V1SC (SR 1) = 1
Microcontroller 15 consecutive
(Oscillator)
Watchdog Failures
V1
Diagnosis
DS11567 Rev 5
L99DZ120
4.8
Application information
Reset output (NReset)
Figure 28. NReset pin
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If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output NReset is
pulled up to V1 by an internal pull-up resistor after a reset delay time (tV1R). This is
necessary for a defined start of the micro controller when the application is switched on.
Since the NReset output is realized as an open drain output it is also possible to connect an
external NReset open drain NReset source to the output. As soon as the NReset is released
by the devices the watchdog starts with a long open window.
A reset pulse is generated in case of:
4.9
V1 drops below VRTxfalling (configurable by SPI) for t > tUV1
Watchdog failure
Turn-on of the V1 regulator (VSREG Power-on or wake-up from Vbat_standby mode)
LIN Bus Interface
Figure 29. RxDL pin
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DS11567 Rev 5
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Application information
4.9.1
L99DZ120
Features
LIN 2.2a compliant (SAEJ2602 compatible) transceiver
LIN Cell has been designed according to “Hardware requirements for transceivers
(version 1.3)”
Bitrate up to 20 kbit/s
Dedicated LIN Flash mode with bitrate up to 100 kbit/s
GND disconnection fail safe at module level
Off mode: does not disturb network
GND shift operation at system level
Micro controller Interface with CMOS-compatible I/O pins
Internal pull-up resistor
Receive-only mode
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
Matched output slopes and propagation delay
Wake-up behaviour according to LIN2.2a and Hardware Requirements for LIN, CAN
and Flexray Interfaces (version 1.3)
At VSREG > VPOR (i.e. VSREG power-on reset threshold), the LIN transceiver is enabled. The
LIN transmitter is disabled in case of the following errors:
Dominant TxDL time out
LIN permanent recessive
Thermal shutdown 1
VSREG overvoltage/ undervoltage
The LIN receiver is not disabled in case of any failure condition.
The default bitrate of the transceiver allows communication up to 20 kbit/s. To enable fast
flashing via the LIN bus, the transceiver can be operated in high speed mode by setting bit
LIN_HS_EN (Config Reg) = 1. This feature is enabled automatically in LIN Flash mode.
4.9.2
Error handling
The devices LIN transceiver provides the following 3 error handling features.
Dominant TxDL time out
If TXD_L is in dominant state (low) for t > tdom(TXDL) the transmitter will be disabled, the
status bit LIN_TXD_DOM (SR 2) will be set.
The transmitter remains disabled until the status bit is cleared.
The TxD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT_EN = 0).
Permanent recessive
If TXD_L changes to dominant (low) state but RXD_L signal does not follow within t < tLIN
the transmitter will be disabled, the status bit LIN_PERM_REC (SR 2) will be set.
The transmitter remains disabled until the status bit is cleared.
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Application information
Permanent dominant
If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure will be
detected. The status bit LIN_PERM_DOM (SR 2) will be set.
The transmitter will not be disabled.
4.9.3
Wake up from Standby modes
In low power modes (V1_standby mode and Vbat_standby mode) the devices can receive
two types of wake up signals from the LIN bus (configurable by SPI bit LIN_WU_CONFIG
(Config Reg)):
Recessive-Dominant-recessive pattern with t > tdom_LIN (default, according to LIN 2.2a)
State Change recessive-to-dominant or dominant-to-recessive (according to LIN 2.1)
Pattern Wake-up (default)
Figure 30. Wake-up behavior according to LIN 2.2a
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Status change wake-up - Recessive-to-dominant
Normal wake-up can occur when the LIN transceiver was set in standby mode while LIN
was in recessive (high) state. A dominant level at LIN for t > tLINBUS, will switch the devices
to Active mode.
Status change wake-up - Dominant-to-recessive
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for t > tLINBUS, will switch the devices to Active mode.
4.9.4
Receive-only mode
The LIN transmitter can be disabled in Active mode by setting the bit LIN_REC_ONLY
(CR2). In this mode it is possible to listen to the bus but not sending to it.
DS11567 Rev 5
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Application information
4.10
L99DZ120
Serial Peripheral Interface (ST SPI Standard)
A 32-bit SPI is used for bi-directional communication with the microcontroller.
The SPI is driven by a microcontroller with its SPI peripheral running in following mode:
CPOL = 0 and CPHA = 0. For this mode input data is sampled by the low to high transition
of the clock CLK, and output data is changed from the high to low transition of CLK.
This device is not limited to microcontroller with a built-in SPI. Only three CMOS-compatible
output pins and one input pin is needed to communicate with the device. A fault condition
can be detected by setting CSN to low. If CSN = 0, the DO-Pin reflects the global error flag
(fault condition) of the device.
Chip Select Not (CSN)
The input Pin is used to select the serial interface of this device. When CSN is high, the
output Pin (DO) is in high impedance state. A low signal activates the output driver and
a serial communication can be started.
The state during CSN = 0 is called a communication frame.
If CSN = low for t > tCSNfail the DO output is switched to high impedance in order not to
block the signal line for other SPI nodes.
Serial Data In (DI)
The input Pin is used to transfer data serial into the device. The data applied to the DI is
sampled at the rising edge of the CLK signal and shifted into an internal 32-bit shift
register. At the rising edge of the CSN signal the content of the shift register is
transferred to Data Input Register. The writing to the selected Data Input Register is
only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN
low). If more or less clock pulses are counted within one frame the complete frame is
ignored. This safety function is implemented to avoid an activation of the output stages
by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go
from high impedance to a low or high level depending on the global error flag (fault
condition). The first rising edge of the CLK input after a high to low transition of the
CSN Pin will transfer the content of the selected status register into the data out shift
register. Each subsequent falling edge of the CLK will shift the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data
input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change
with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up
to 4 MHz.
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L99DZ120
Application information
4.11
Power supply failure
4.11.1
VS supply failure
VS overvoltage
If the supply voltages VS reaches the overvoltage threshold VSOV:
LIN remains enabled
OUT1 to OUT_14 are turned off (default).
The shutdown of outputs may be disabled by SPI (VS_OV_SD_EN (CR 3) = 0)
Charge pump is disabled (and is switched on automatically in case the supply voltage
recovers to normal operating voltage)
H-bridge gate driver is switched into sink condition
Recovery of outputs after overvoltage condition is configurable by SPI:
–
VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_OV (SR 2).
–
VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS overvoltage
condition has recovered.
The overvoltage bit VS_OV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The overvoltage bit is reset automatically if VS_LOCK_EN (CR 3) = 0 and
the overvoltage condition has recovered.
VS undervoltage
If the supply voltage VS drops below the under voltage threshold voltage (VSUV):
LIN remains enabled
OUT1 to OUT14 are turned off (default).
The shutdown of outputs may be disabled by SPI (VS_UV_SD_EN (CR 3) = 0)
Recovery of outputs after undervoltage condition is configurable by SPI:
–
VS_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VS_UV (SR 2).
–
VS_LOCK_EN (CR 3) = 0: outputs turned on automatically after VS undervoltage
condition has recovered.
The undervoltage bit VS_UV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The undervoltage bit is removed automatically if VS_LOCK_EN (CR 3) = 0
and the undervoltage condition has recovered.
DS11567 Rev 5
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Application information
4.11.2
L99DZ120
VSREG supply failure
VSREG overvoltage
If the supply voltages VSREG reaches the overvoltage threshold VSREG_OV:
LIN is switched to high impedance
OUT15 and OUT_HS are turned off (default).
The shutdown of outputs may be disabled by SPI (VSREG_OV_SD_EN (CR 3) = 0)
Recovery of outputs after overvoltage condition is configurable by SPI:
–
VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_OV
(SR 2).
–
VSREG_LOCK_EN (CR 3) = 0: outputs turned on automatically after VSREG
overvoltage condition has recovered.
The overvoltage bit VSREG_OV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The overvoltage bit is reset automatically if VSREG_LOCK_EN (CR 3) = 0
and the overvoltage condition has recovered.
VSREG undervoltage
If the supply voltage VSREG drops below the under voltage threshold voltage (VSREG_UV):
LIN is switched to high impedance
OUT15 and OUT_HS are turned off (default).
The shutdown of outputs may be disabled by SPI (VSREG_UV_SD_EN (CR 3) = 0)
Recovery of outputs after undervoltage condition is configurable by SPI:
76/161
–
VSREG_LOCK_EN (CR 3) = 1: outputs are off until Read&Clear VSREG_UV
(SR 2).
–
VSREG_LOCK_EN (CR 3) = 0: Outputs turned on automatically after VSREG
undervoltage condition has recovered.
The undervoltage bit VSREG_UV (SR 2) is set and can be cleared with a ‘Read&Clear’
command. The undervoltage bit is removed automatically if
VSREG_LOCK_EN (CR 3) = 0 and the undervoltage condition has recovered.
DS11567 Rev 5
L99DZ120
4.12
Application information
Temperature warning and thermal shutdown
Figure 31. Thermal shutdown protection and diagnosis
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Note:
The Thermal State machine will recover the same state as before entering Standby mode. In
case of a TSD2 it will enter TSD1 state.
DS11567 Rev 5
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Application information
4.13
L99DZ120
Power outputs OUT1..15 and OUT_HS
The component provides a total of 4 half bridges outputs OUT1, OUT4-6 to drive motors and
10 stand alone high-side outputs OUT7..15 and OUT_HS to drive e.g. LED’s, bulbs or to
supply contacts. All high-side outputs beside OUT_HS and OUT15 are supplied by the pin
VS and OUT_HS and OUT15 are supplied by the buffered supply VSREG. OUT_HS is
intended to be used as contact supply. Beside OUT15 and OUT_HS the high-side switches
can be activated only in case of running charge pump. OUT15 and OUT_HS can be
activated also in standby modes.
All high-side and low-side outputs switch off in case of:
VS (VSREG) overvoltage and undervoltage (depending on configuration, see
Section 4.11.2: VSREG supply failure)
Overcurrent (depending on configuration, auto recovery mode (see below)
Overtemperature (TSD1x/ cluster or single mode)
Fail safe event
Loss of GND at SGND pin
In case of overcurrent or overtemperature (TSD1_CLx (SR 6)) condition, the drivers will
switch off. The relevant status bit will be latched and can be read and optionally cleared by
SPI. The drivers remain off until the status is cleared. In case overvoltage/ undervoltage
condition, the drivers will be switched off. The relevant status bit will be latched and can be
read and optionally cleared by SPI. If VSREG_LOCK_EN (CR 3) respectively
VS_LOCK_EN (CR 3) are set, the drivers remain off until the status is cleared. If the
VS_LOCK_EN or VSREG_LOCK_EN) bit is set to 0, the drivers will switch on automatically
if the error condition disappears. Undervoltage and overvoltage shutdown can be disabled
by SPI. In case of open-load condition, the relevant status register will be latched. The
status can be read and optionally cleared by SPI. The high and low-side outputs are not
switched off in case of open-load condition.
For OUT1, OUT4-8 and OUT_HS the auto recovery feature (OUTx_OCR (CR 7)) can be
enabled; half-bridges and high-side drivers have different Auto recovery frequencies
(frecx_hs and frecx_hb). If these bits are set to 1 the driver will automatically restart from an
overload condition. This overload recovery feature is intended for loads which have an initial
current higher than the overcurrent limit of the output (e.g. Inrush current of cold light bulbs).
The SPI bits OUTx_OCR_ALERT (SR4) indicate that the output reached auto-recovery
condition.
Note:
The maximum voltage and current applied to the high-side Outputs is specified in the
‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to
respect these limits under application conditions. In case of outputs switch off due to loss of
ground at SGND pin, the device has to be re-started through a power off on both VS and
VSREG.
Each of the stand alone high-side driver outputs OUT7 … OUT15 and OUT_HS can be
driven with an internally generated PWM signal, an internal Timer or with DIR1 respectively
DIR2. See Table 49.
78/161
DS11567 Rev 5
L99DZ120
Application information
Table 49. Power output settings
OUTx_3 OUTx_2
4.14
OUTx_1
OUTx_0
Description
0
0
0
0
OFF
0
0
0
1
ON
0
0
1
0
Timer1 output is controlled by timer1; starting with ON
phase after timer restart
0
0
1
1
Timer2 output is controlled by timer2; starting with ON
phase after timer restart
0
1
0
0
PWM1
0
1
0
1
PWM2
0
1
1
0
PWM3
0
1
1
1
PWM4
1
0
0
0
PWM5
1
0
0
1
PWM6
1
0
1
0
PWM7
1
0
1
1
PWM8
1
1
0
0
PWM9
1
1
0
1
PWM10
1
1
1
0
DIR1
1
1
1
1
DIR2
Auto-recovery alert and thermal expiration
The thermal expiration feature provides a robust protection against possible microcontroller
malfunction, switching off a given channel if continuously driven in auto-recovery. If the
temperature of the related cluster increases by more than 30 °C after reaching the autorecovery time tAR, the channel is switched off. The thermal expiration status bit
OUTx_TH_EX (SR 3) is set.
During auto-recovery condition, OUTx_OCR_ALERT (SR 4) is set. The Alert bit indicates
that an overload condition (load in-rush, short-circuit, etc) is present.
The thermal expiration feature is controlled by SPI (OUTx_OCR_THX_EN (CR 8).
DS11567 Rev 5
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Application information
L99DZ120
Figure 32. Example of long auto-recovery on OUT7. Temperature acquisition starts after tAR,
thermal expiration occurs after a ∆T = 30°
80/161
DS11567 Rev 5
L99DZ120
Application information
Figure 33. Block diagram of physical realization of AR alert and thermal expiration
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4.15
Charge pump
The charge pump uses two external capacitors, which are switched with fCP. The output of
the charge pump has a current limitation. In standby mode and after a thermal shutdown
has been triggered the charge pump is disabled. If the charge pump output voltage remains
too low for longer than TCP, the power-MOS outputs and the EC-control are switched off.
The H-bridge MOSFET gate drivers are switched to resistive low and CP_LOW (SR 2) is
set. This bit has to be cleared to reactivate the drivers. If the bit CP_LOW_CONFIG
(Configuration Register 0x3F) is set to ‘1’, CP_LOW (SR2) behaves as a ‘live’ bit and the
outputs are re-activated automatically upon recovery of the charge pump output voltage.
In case of reaching the overvoltage shutdown threshold VSOV the charge pump is disabled
and automatically restarted after VS recovered to normal operating voltage.
Figure 34. Charge pump low filtering and start up implementation
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4.16
Inductive loads
Each of the half bridges is built by internally connected high-side and low-side power DMOS
transistors. Due to the built-in reverse diodes of the output transistors, inductive loads can
DS11567 Rev 5
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Application information
L99DZ120
be driven at the outputs OUT1 and OUT4-6 without external freewheeling diodes. The highside drivers OUT7 to OUT15 and OUT_HS are intended to drive resistive loads only.
Therefore only a limited energy (E < 1 mJ) can be dissipated by the internal ESD-diodes in
freewheeling condition. For inductive loads (L > 100 μH) an external freewheeling diode
connected between GND and the corresponding output is required.
4.17
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for t > tOL_OUT the corresponding openload bit OUTx_OL (SR 5) is set in the status register.
4.18
Overcurrent detection
An overcurrent condition is detected after a filter time (see Figure 11 and Figure 12) and is
indicated by the status bit OUTx_OC (SR 3). In case of overcurrent, the corresponding
driver switches off to reduce the power dissipation and to protect the integrated circuit. If the
outputs are not configured in recovery mode, the microcontroller has to clear the relevant
status bits to reactivate the corresponding drivers.
4.19
Current monitor
The current monitor sources a current image of the power stage output current at the
current monitor pin CM, which has a fixed ratio (ICMr) of the instantaneous current of the
selected high-side driver. The signal at output CM is blanked for tcmb after switching on the
driver until the correct settlement of the circuitry. The bits CM_SELx (CR 7) define which of
the outputs is multiplexed to the current monitor output CM. The current monitor output
allows a more precise analysis of the actual state of the load rather than the detection of an
open-load or overload condition. For example, it can be used to detect the motor state
(starting, free running, stalled). The current monitor output is enabled after the currentmonitor blanking time, when the selected output is switched on. If this output is off, the
current monitor output is in high impedance mode. The current monitor can be deactivated
by CM_EN (CR 7).
4.20
PWM mode of the power outputs
Description see Section 7.3: Status register overview.
4.21
Cross-current protection
The four half-bridges of the device are cross-current protected by an internal delay time. If
one driver (LS or HS) is turned off, the activation of the other driver of the same half-bridge
will be automatically delayed by the crosscurrent protection time. After the crosscurrent
protection time is expired the slew-rate limited switch-off phase of the driver is changed to a
fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. Due to this
behavior, it is always guaranteed that the previously activated driver is completely turned off
before the opposite driver starts to conduct.
82/161
DS11567 Rev 5
L99DZ120
4.22
Application information
Programmable soft-start function to drive loads with higher
inrush current
Loads with start-up currents higher than the overcurrent limits (e.g. inrush current of lamps,
start current of motors) can be driven by using the programmable soft-start function (i.e.
overcurrent recovery mode). Each driver has a corresponding overcurrent recovery bit
OUTx_OCR (CR 7). If this bit is set, the device automatically switches the outputs on again
after a programmable recovery time. The PWM modulated current will provide sufficient
average current to power up the load (e.g. heat up the bulb) until the load reaches operating
condition.
The PWM frequency is defined by setting OCR_FREQ (CR7).
The device itself cannot distinguish between a real overload (e.g. short-circuit condition) and
a load characterized by operation currents exceeding the short-circuit threshold.
Examples are non-linear loads like a light bulb used on the HS outputs or a motor used on
the half bridge output with inrush and stall currents that shall be limited by the auto recovery
feature.
For the bulb, a real overload condition can only be qualified by time. For overload detection
the microcontroller can switch on the light bulbs by setting the overcurrent recovery bit for
the first e.g. 50 ms. After clearing the recovery bit, the output will be switched off
automatically if the overload condition remains.
For the half bridges the high current can be present during all motor activation and another
SW strategy must be applied to identify a SC to GND or Supply. Before running the motor
e.g. with a first SPI command all bridges LS are switched on (without auto recovery
functionality / cleared overcurrent recovery bit), all HS are switched off and a SC to Battery
can be diagnosed. With a next SPI command, all HS are switched on (without auto recovery
functionality/ cleared overcurrent recovery bit) and all LS are switched off. In this sequence,
a short to GND can be diagnosed. If in both sequences no overload condition is identified,
the motor can be run by switching on the relevant HS and LS each configured in auto
recovery mode (see Figure 35). Such sequence can be applied before any motor activation
to identify SC just before operating the motor (in case the delay due to the 2 additional SPI
commands is not limiting the application) or in case of power up of the system resp. applied
on a certain time base.
DS11567 Rev 5
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160
Application information
L99DZ120
Figure 35. Software strategy for half bridges before applying auto-recovery mode
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As soon as an output reaches auto-recovery condition, OUTx_OCR_ALERT (SR 4)) is set.
The Alert bit indicates that an overload condition (load in-rush, short-circuit, etc) is present.
84/161
DS11567 Rev 5
L99DZ120
Application information
Figure 36. Overcurrent recovery mode
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4.23
H-bridge control
The PWMH and DIRH inputs control the drivers of the external H-bridge transistors. In
single Motor mode the motor direction can be chosen with the direction input (DIRH), the
duty cycle(a) and frequency with the PWMH input (single mode). With the SPI bits SD (CR
10) and SDS (CR 10) four different slow-decay modes (via drivers and via diode) can be
selected using the high-side or the low-side transistors. Unconnected inputs are defined by
internal pull-down current.
a. If tccp is programmed to 4 µs and frequency to 50 kHz, max duty cycle achievable is 92%.
DS11567 Rev 5
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160
Application information
L99DZ120
Table 50. H-bridge control truth table
Control
Control bits
pins
Output pins
Nb
HEN
SD
SDS
CP_LOW
VS_OV
VS_UV
DS
TSD1
GH1
GL1
GH2
GL2
Comment
PWMH
Motor
config
DIRH
Failure bits
1
x
x
0
x
x
x
x
x
x
x
RL
RL
RL
RL
H-bridge disabled
2
x
x
1
x
x
1
0
0
0
0
RL
RL
RL
RL
Charge pump voltage too low
3
x
x
1
x
x
0
x
x
x
1
RL
RL
RL
RL
Thermal shutdown
4
x
x
1
x
x
0
1
0
0
0
L
L
L
L
L(1)
L(1)
L(1)
Overvoltage
5
x
x
1
x
x
0
0
0
1
0
L(1)
Short-circuit(1)
6
0
1
1
x
x
0
0
0
0
0
L
H
H
L
Bridge H2/L1 on
7
x
0
1
0
0
0
0
0
0
0
L
H
L
H
Slow-decay mode LS1 and
LS2 on
8
0
0
1
0
1
0
0
0
0
0
L
H
L
L
9
1
0
1
0
1
0
0
0
0
0
L
L
L
H
Slow-decay mode LS2 on
10
1
1
1
x
x
0
0
0
0
0
H
L
L
H
Bridge H1/L2 on
11
x
0
1
1
0
0
0
0
0
0
H
L
H
L
Slow-decay mode HS1 and
HS2 on
12
0
0
1
1
1
0
0
0
0
0
L
L
H
L
Slow-decay mode HS1 on
13
1
0
1
1
1
0
0
0
0
0
H
L
L
L
Slow-decay mode HS2 on
Single
Slow-decay mode LS1 on
1. Only the H-bridge leg (low-side and high-side), in which one MOSFET is in short-circuit condition is switched off. Both
MOSFETs of the other H-bridge leg remain active and driven by DIRH and PWMH.
During watchdog long-open window, the H-bridge drivers are forced off until the first valid
watchdog trigger in window mode (setting TRIG = 0 during safe window). The Control
Registers remain accessible during long open window.
4.24
H-bridge driver slew-rate control
The rising and falling slope of the drivers for the external high-side Power-MOS can be slew
rate controlled. If this mode is enabled the gate of the external high-side Power-MOS is
driven by a current source instead of a low-impedance output driver switch as long as the
drain-source voltage over this Power-MOS is below the switch threshold. The current is
programmed using the bits SLEW_x (CR 10), which represent a binary number. This
number is multiplied by the minimum current step. This minimum current step is the
maximum source-/sink-current (IGHxrmax / IGHxfmax) divided by 31. Programming
SLEW_x to 0 disables the slew rate control and the output is driven by the lowimpedance output driver switch.
86/161
DS11567 Rev 5
L99DZ120
Application information
Figure 37. H-bridge GSHx slope
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4.25
Resistive low
The resistive output mode protects the devices and the H-bridge in the standby mode and in
some failure modes (thermal shutdown TSD1 (SR 1), charge pump low CP_LOW (SR 2)
and DI pin stuck at ‘1’ SPI_INV_CMD (SR 2)). When a gate driver changes into the resistive
output mode due to a failure a sequence is started. In this sequence the concerning driver is
switched into sink condition for 32 μs to 64 μs to ensure a fast switch-off of the H-bridge
transistor. If slew rate control is enabled, the sink condition is slew-rate controlled.
Afterwards the driver is switched into the resistive output mode (resistive path to source).
4.26
Short circuit detection / drain source monitoring
The Drain - Source voltage of each activated external MOSFET of the H-bridge is monitored
by comparators to detect shorts to ground or battery. If the voltage-drop over the external
MOSFET exceeds the configurable threshold voltage VSCd_HB (DIAG_x (CR 10) for longer
t > tSCd_HB the corresponding gate driver switches off the external MOSFET and the
corresponding drain source monitoring flag DS_MON_x (SR 2) is set. The DSMON_x bits
have to be cleared through the SPI to reactivate the gate drivers. This monitoring is only
active while the corresponding gate driver is activated. If a drain-source monitor event is
detected, the corresponding gate-driver remains activated for at maximum the filter time.
When the gate driver switches on, the drain-source comparator requires the specified
settling time until the drain-source monitoring is valid. During this time, this drain-source
DS11567 Rev 5
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160
Application information
L99DZ120
monitor event may start the filter time. The threshold voltage VSCd_HB can be programmed
using the SPI bits DIAG_x (CR 10).
Figure 38. H-bridge diagnosis
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4.27
H-bridge monitoring in off-mode
The drain source voltages of the H-bridge driver external transistors can be monitored, while
the transistors are switched off. If either bit OL_H1L2 (CR 10) or OL_H2L1 (CR 10) is set to
1, while bit HEN (CR 1) = 1, the H-drivers enter resistive low mode and the drain-source
voltages can be monitored. Since the pull-up resistance is equal to the pull-down resistance
on both sides of the bridge a voltage of 2/3 VS on the pull-up highside and 1/3 VS on the lowside is expected, if they drive a low-resistive inductive load (e.g. motor). If the drain source
voltage on each of these Power-MOS is less than 1/6 VS, the drain-source monitor bit of the
associated driver is set.
The open-load filter time is tOL_HB.
88/161
DS11567 Rev 5
L99DZ120
Application information
Figure 39. H-bridge open-load-detection (no open-load detected)
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Figure 40. H-bridge open-load-detection (open-load detected)
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DS11567 Rev 5
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160
Application information
L99DZ120
Figure 41. H-bridge open-load-detection (short to ground detected)
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Figure 42. H-bridge open-load detection (short to VS detected)
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Table 51. H-bridge monitoring in off-mode
Control bits
Failure bits
Comments
Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2
90/161
1
0
0
0
0
0
Drain-Source monitor
disabled
2
1
0
x
0
0
No open-load detected
3
1
0
0
0
1
Open-load SH2
4
1
0
0
1
1
Short to GND
5
1
0
1
1
1
Short to VS
6
0
1
x
0
0
No open-load detected
7
0
1
0
1
0
Open-load SH1
DS11567 Rev 5
L99DZ120
Application information
Table 51. H-bridge monitoring in off-mode (continued)
Control bits
Failure bits
Comments
Nb OL H1L2 OL H2L1 H OLTH High DSMON LS1 DSMON LS2
4.28
8
0
1
0
1
1
Short to GND
9
0
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1
1
1
Short to VS
Programmable cross current protection
The external PowerMOSFETs transistors in H-bridge (two half-bridges) configuration are
switched on with an additional delay time tCCP to prevent cross current in the halfbridge. The
cross current protection time tCCP can be programmed with the SPI bits COPT_x
(CR 10). The timer is started when the gate driver is switched on in the device.
The PWMH module has 2 timers to configure locking time for high-side and freewheeling
low-side. The programmable time tCCP-TIM1 / tCCP-TIM2 is the same. Sequence for switching
in PWM mode is the following:
HS switch off after locking tCCP-TIM1
LS switch on after 2nd locking tCCP-TIM1
HS switch on after locking tCCP-TIM2 which starts with rising edge on PWM input
Figure 43. PWMH cross current protection time implementation
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4.29
Power window H-bridge safety switch off block
The two LS Switches LS1_FSO and LS2_FSO are intended to be used to switch off the
gates of the external high-side MOSFETs in the power window h-bridge if a fatal error
happens. This block must work also in case the MOSFET driver and the according control
blocks on the chip are destroyed. Therefore it is necessary to have a complete separated
safety block on the device, which has it’s own supply and GND connection, separated from
the other supplies and GNDs. In the block is implemented an own voltage regulator and
oscillator.
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Application information
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The safety block is surrounded by a GND isolation ring realized by deep trench isolation.
The LS driver must work down to a lower voltage than the other circuits. The block has its
own internal supply and an own oscillator for monitoring the failure signals (WWD, V1 fail,
SPI fail & Tj) which are Manchester encoded and decoupled by high ohmic resistances. In
case of fail-safe event, both LS switches LS1_FSO and LS2_FSO are switched on.
In case of entering V1_standby mode or Vbat_standby mode both fail safe low-side
switches are switched on to minimize the current drawn by the fail safe block (e.g. oscillator
is switched off and Manchester Encoding is deactivated). Short circuit protection to VS is
active in both standby modes limiting the current to IOLimit for a filter of tSCF.
After this filter time the fail-safe switches are switched off and LSxFSO_OC (SR 3) is set. To
reactivate the low-side functionality this bit has to be set back by a read and clear command.
In case of VS loss the fail safe switches are biased by their own output voltage to turn on the
low-side switches down to VOUT_max.
To allow verification of the Fail-Safe path, the low-side switches LS1_FSO and LS2_FSO
can be turned on by SPI (Configuration Register 0x3F bit 4: FS_FORCED)
Figure 44. LSx_FSO: low-side driver “passively” turned on, taking supply from output
pin (if main supply fails), can guarantee VLSx_FSO < VOUT_max
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DS11567 Rev 5
L99DZ120
Application information
Figure 45. Safety concept
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4.30
Temperature warning and shutdown
If any of the cluster (see Section 4.31: Thermal clusters) junction temperatures rises above
the temperature warning threshold TW, the temperature warning flag TW (SR 2) is set after
the temperature warning filter time tjtft and can be read via SPI. If the junction temperature
increases above the temperature shutdown threshold (TSD1), the thermal shutdown bit
TSD1 (SR 1) is set and the power transistors of all output stages are switched off to protect
the device after the thermal shutdown filter time. The gates of the H-bridge is discharged by
the ‘Resistive Low’ mode. After these bits have been cleared, the output stages are
reactivated. If the temperature is still above the thermal warning threshold, the thermal
warning bit is set after tjtft. Once this bit is set and the temperature is above the temperature
shutdown threshold, temperature shutdown is detected after tjtft and the outputs are
switched off. Therefore the minimum time after which the outputs are switched off after the
bits have been cleared in case the temperature is still above the thermal shutdown threshold
is twice the thermal warning/ thermal shutdown filter time tjtft.
4.31
Thermal clusters
In order to provide an advanced on-chip temperature control, the power outputs are
grouped in six clusters with dedicated thermal sensors. The sensors are suitably located on
the device (see Figure 46: Thermal clusters identification). In case the temperature of an
output cluster reaches the thermal shutdown threshold, the outputs assigned to this cluster
are shut down (all other outputs remain active). Each output cluster has a dedicated
temperature warning and shutdown flag (SR 6) and the cluster temperature can be read out
by SPI.
Hence, the thermal cluster concept allows to identify a group of outputs in which one or
more channels are in overload condition.
If thermal shutdown has occurred within an output cluster, or if temperature is rising within a
cluster, it may be desired to identify which of the output (s) is (are) determining the
temperature increase. An additional evaluation, based on current monitoring and cluster
temperature read-out, supports identification of the outputs mainly contributing to the
temperature increase. The cluster temperatures are available in SR 7, SR 8 and SR 9 and
can be calculated from the binary coded register value using the following formula:
Decimal code = (350 – Temp) / 0.488
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Example:
T = -40 °C => decimal code is 799 (0x31F)
T = 25 °C => decimal code is 666 (0x29A)
Thermal clusters can be configured using bit TSD_CONFIG (Config Reg):
Standard mode (default): as soon as any cluster reaches thermal threshold the device
is switched off. V1 regulator remains on and is switched off reaching TSD2.
Cluster mode: only the cluster which reached shutdown temperature is switched off.
If Cluster Th_CL6 (global) or Cluster Th_CL5 (Voltage Regulators) reachTSD1, the whole
device is OFF (beside V1).
Note:
Clusters related to power outputs (clusters 1 to 4, see Figure 46: Thermal clusters
identification) will be managed digitally only, by mean of the ADC conversion of related
thermal sensors, while clusters 5 and 6 will be managed in an analog way (comparators)
since ADC can be off, e.g. in V1_standby mode. Temperature reading provided by ADC may
differ from real junction temperature of a specific output due to spatial placement of thermal
sensor. Such an effect is more visible during fast thermal increases of junction temperature.
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DS11567 Rev 5
L99DZ120
Application information
Table 52. Thermal cluster definition
Th_CL1
Th_CL2
5 W Driver +
OUT15
Door lock +
OUT_HS
Th_CL3
Th_CL4
Th_CL5
Th_CL6
OUT1 + OUT6
10W driver high
ohmic channels
VREG 1
VREG 2
Global
TW digitally
managed
TSD1 & TSD2
Both analog
managed
TW digitally
managed
TSD1 Analog
managed
TW & TSD1 Both TW & TSD1 Both TW & TSD1 Both TW & TSD1 Both
digitally managed digitally managed digitally managed digitally managed
4.32
VS compensation (duty cycle adjustment) module
All stand-alone HS outputs can be programmed to calculate some internal duty cycle
adjustment to adapt the duty cycle to a changing supply voltage at VS. This feature is aimed
to avoid LED brightness flickering in case of alternating supply voltage. The correction of the
duty cycle is based on the following formula:
Equation 1: Duty cycle correction
V th – V LED
DutyCycle = --------------------------------- DC nom
V Bat – V LED
Vth = Duty cycle reference voltage: defined as 10 V
VBat = Reference voltage: defined as voltage at pin VS
VLED = Voltage drop on the external LED
DCnom = Nominal Duty Cycle programmed by SPI< PWMx DCx>
To be compatible to different LED load characteristics the value for VLED can be
programmed for each output by a dedicated control register OUT7_VLED …
OUT_HS_VLED (CR 18 to CR 22). Auto compensation features can be activated for all HS
outputs each by setting OUTx_AUTOCOMP_EN (CR 18 to CR 22).
The programmed LED voltage (OUTx_V_LED (CR18 to CR22)) must be lower than Vth
(10 V).
Figure 47. Block diagram VS compensation (duty cycle adjustment) module
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DS11567 Rev 5
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Application information
4.33
L99DZ120
Analog digital converter
Voltage signals VS, VSREG, VWU and TH_CL1..6 are read out sequentially. The voltage
signals are multiplexed to an ADC. The ADC is realized as a 10 Bit SAR, that is sampled
with the main clock fclk2 / fADC.
Each channel will be converted with a conversion time tcon, therefore an update of the ADC
value is available every tcon * 9. In case of WU is directly connected to Clamp 30, the input
must be protected by a series resistance of typical 1kΩ to sustain reverse battery condition.
Figure 48. Sequential ADC Read Out for VSREG, VS, WU and THCL1 ..THCL6
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96/161
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5
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
A 32-bit SPI is used for bi-directional communication with the microcontroller.
The SPI is driven by a microcontroller with its SPI peripheral running in the following mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK. This device is not limited to
microcontroller with a built-in SPI. Only three CMOS-compatible output Pins and one input
Pin will be needed to communicate with the device. A fault condition can be detected by
setting CSN to low. If CSN = 0, the DO-Pin will reflect the global error flag (fault condition) of
the device.
Chip Select Not (CSN)
The input Pin is used to select the serial interface of this device. When CSN is high, the
output Pin (DO) is in high impedance state. A low signal activates the output driver and
a serial communication can be started. The state during CSN = 0 is called a
communication frame. If CSN = low for t > tCSNfail the DO output will be switched to
high impedance in order to not block the signal line for other SPI nodes.
Serial Data In (DI)
The input Pin is used to transfer data serial into the device. The data applied to the DI
will be sampled at the rising edge of the CLK signal and shifted into an internal 32-bit
shift register. At the rising edge of the CSN signal the content of the shift register will be
transferred to Data Input Register. The writing to the selected Data Input Register is
only enabled if exactly 32-bit are transmitted within one communication frame (i.e. CSN
low). If more or less clock pulses are counted within one frame the complete frame will
be ignored. This safety function is implemented to avoid an activation of the output
stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and will go
from high impedance to a low or high level depending on the global error flag (fault
condition). The first rising edge of the CLK input after a high to low transition of the
CSN Pin will transfer the content of the selected status register into the data out shift
register. Each subsequent falling edge of the CLK will shift the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data
input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change
with the falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up
to 4 MHz.
5.1
ST SPI 4.0
The ST-SPI is a standard used in ST Automotive ASSP devices.
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This chapter describes the SPI protocol standardization. It defines a common structure of
the communication frames and defines specific addresses for product and status
information.
The ST-SPI allows usage of generic software to operate the devices while maintaining the
required flexibility to adapt it to the individual functionality of a particular product. In addition,
failsafe mechanisms are implemented to protect the communication from external
influences and wrong or unwanted usage.
The devices Serial Peripheral Interface are compliant to the ST SPI Standard Rev. 4.0.
5.1.1
Physical layer
Figure 49. SPI pin description
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Signal description
Chip Select Not (CSN)
The communication interface is de-selected, when this input signal is logically high. A
falling edge on CSN enables and starts the communication while a rising edge finishes
the communication and the sent command is executed when a valid frame was sent.
During communication start and stop the Serial Clock (SCK) has to be logically low.
The Serial Data Out (SDO) is in high impedance when CSN is high or a communication
timeout was detected.
Serial Clock (SCK)
This SCK provides the clock of the SPI. Data present at Serial Data Input (SDI) is
latched on the rising edge of Serial Clock (SCK) into the internal shift registers while on
the falling edge data from the internal shift registers are shifted out to Serial Data Out
(SDO).
Serial Data Input (SDI)
This input is used to transfer data serially into the device. Data is latched on the rising
edge of Serial Clock (SCK).
Serial Data Output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out
on the falling edge of Serial Clock (SCK).
98/161
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Serial Peripheral Interface (SPI)
Figure 50. SDO pin
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Clock and Data Characteristics
The ST-SPI can be driven by a microcontroller with its SPI peripheral running in the
following mode:
CPOL = 0
CPHA = 0
Figure 51. SPI signal description
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The communication frame starts with the falling edge of the CSN (Communication Start).
SCK has to be low.
The SDI data is then latched at all following rising SCK edges into the internal shift registers.
After Communication Start the SDO will leave 3-state mode and present the MSB of the
data shifted out to SDO. At all following falling SCK edges data is shifted out through the
internal shift registers to SDO.
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The communication frame is finished with the rising edge of CSN. If a valid communication
took place (e.g. correct number of SCK cycles, access to a valid address), the requested
operation according to the Operating Code will be performed (Write or Clear operation).
5.2.2
Communication protocol
SDI Frame
The devices Data-In Frame consist of 32-bit (OpCode (2 bits) + Address (6 bits) + Data Byte
3 + Data Byte 2 + Data Byte 1). The first two transmitted bits (MSB, MSB-1) contain the
Operation Code which represents the instruction which will be performed. The following 6
bits (MSB-2 to MSB-7) represent the address on which the operation will be performed. The
subsequent bytes contain the payload.
Figure 52. SDI Frame
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Operating code
The operating code is used to distinguish between different access modes to the registers of
the slave device.
Table 53. Operation codes
OC1
OC0
Description
0
0
Write Operation
0
1
Read Operation
1
0
Read & Clear Operation
1
1
Read Device Information
A Write Operation will lead to a modification of the addressed data by the payload if a write
access is allowed (e.g. Control Register, valid data). Beside this a shift out of the content
(data present at Communication Start) of the registers is performed.
A Read Operation shifts out the data present in the addressed register at Communication
Start. The payload data will be ignored and internal data will not be modified. In addition a
Burst Read can be performed.
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Serial Peripheral Interface (SPI)
A Read & Clear Operation will lead to a clear of addressed status bits. The bits to be cleared
are defined first by address, second by payload bits set to ‘1’. Beside this a shift out of the
content (data present at Communication Start) of the registers is performed.
Note:
Status registers which change status during communication could be cleared by the actual
Read & Clear Operation and are neither reported in actual communication nor in the
following communications. To avoid a loss of any reported status it is recommended just
clear status registers which are already reported in the previous communication (Selective
Bitwise Clear).
Advanced operation codes
To provide the separate write of all control registers and the bitwise clear of all status
registers, two Advanced Operation Codes can be used to set all control registers to the
default value and to clear all status registers. A ‘set all control registers to default’ command
is performed when an OpCode ‘11’ at address b’111111 is performed.
Note:
Please consider that potential device specific write protected registers cannot be cleared
with this command in therefore a device Power-on-Reset is needed.
A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address
b’111111 is performed.
Data-in payload
The Payload (Data Byte 1 to Data Byte 3) is the data transferred to the devices with every
SPI communication. The Payload always follows the OpCode and the Address bits. For
Write access the Payload represents the new data written to the addressed register. For
Read & Clear operations the Payload defines which bits of the adressed Status Register will
be cleared. In case of a ‘1’ at the corresponding bit position the bit will be cleared.
For a Read Operation the Payload is not used. For functional safety reasons it is
recommended to set unused Payload to ‘0’.
SDO frame
The data-out frame consists of 32-bit (GSB + Data Byte 1 to 3).
The first eight transmitted bits contain device related status information and are latched into
the shift register at the time of the Communication Start. These 8-bit are transmitted at every
SPI transaction. The subsequent bytes contain the payload data and are latched into the
shift register with the eighth positive SCK edge. This could lead to an inconsistency in data
between the GSB and Payload due to different shift register load times. Anyhow, no
unwanted Status Register clear should appear, as status information should just be cleared
with a dedicated bit clear after.
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Figure 53. SDO frame
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Global Status Byte (GSB)
The bits (Bit0 to Bit4) represent a logical OR combination of bits located in the Status
Registers. Therefore no direct Read & Clear can be performed on these bits inside the GSB.
Table 54. Global Status Byte
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Bit 25
Bit 24
GSBN
RSTB
SPIE
PLE
FE
DE
GW
FS
Global Status Bit Not (GSBN)
The GSBN is a logical NOR combination of Bit 24 to Bit 30. This bit can also be used as
Global Status Flag without starting a complete communication frame as it is present directly
after pulling CSN low.
Reset Bit (RSTB)
The RSTB indicates a device reset. In case this bit is set, specific internal Control Registers
are set to default and kept in that state until the bit is cleared. The RSTB bit is cleared after
a Read & Clear of all the specific bits in the Status Registers which caused the reset event.
SPI Error (SPIE)
The SPIE is a logical OR combination of errors related to a wrong SPI communication.
Physical Layer Error (PLE)
The PLE is a logical OR combination of errors related to the LIN transceiver.
Functional Error (FE)
The FE is a logical OR combination of errors coming from functional blocks (e.g. high-side
overcurrent).
Device Error (DE)
The DE is a logical OR combination of errors related to device specific blocks (e.g. VS
overvoltage, overtemperature
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Serial Peripheral Interface (SPI)
Global Warning (GW)
The GW is a logical OR combination of warning flags (e.g. thermal warning).
Fail Safe (FS)
The FS bit indicates that the device was forced into a safe state due to mistreatment or
fundamental internal errors (e.g. Watchdog failure, Voltage regulator failure).
Data-Out Payload
The Payload (Data Bytes 1 to 3) is the data transferred from the slave device with every SPI
communication to the master device. The Payload always follows the OpCode and the
address bits of the actual shifted in data (In-frame-Response).
5.2.3
Address definition
Table 55. Device application access
Operating Code
OC1
OC0
0
0
0
1
1
0
Table 56. Device information read access
Operating Code
OC1
OC0
1
1
Table 57. RAM address range
RAM Address
Description
Access
3FH
Configuration Register
R/W
3CH
Status Register 12
R/C
…
…
32H
Status Register 2
R/C
31H
Status Register 1
R/C
…
…
22H
Control Register 34
R/W
1DH
Control Register 29
R/W
…
02H
…
Control Register 2
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Table 57. RAM address range (continued)
RAM Address
Description
01H
Control Register 1
00H
reserved
Access
R/W
Table 58. ROM address range
ROM Address
Description
Access
3FH
W
3EH
R
20H
R
16H
R
15H
R
14H
R
13H
R
12H
R
11H
R
10H
R
R
06H
R
05H
R
04H
R
03H
R
02H
R
01H
R
00H
R
…
…
0AH
…
Information registers
The Device Information Registers can be read by using OpCode ‘11’. After shifting out the
GSB the 8-bit wide payload will be transmitted. By reading Device Information Registers a
communication width which is minimum 16-bit plus a multiple by 8 can be used. After
shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the
SDO.
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Serial Peripheral Interface (SPI)
Table 59. Information Registers Map
ROM
Adress
Description
Access
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3FH
3EH
R
→
0
0
0
0
0
0
0
0
20H
R
→
0
1
0
1
0
1
0
1
16H
R
→
C0H
15H
R
→
7FH
14H
R
→
C0H
13H
R
→
41H
12H
R
→
91H
11H
R
→
28H
10H
R
→
B0H
…
…
0AH
→
R
…
→
major revision
minor revision
→
06H
R
L99DZ120: 01H
05H
R
→
06H
04H
R
→
4DH
03H
R
→
41H
02H
R
→
55H
01H
R
→
01H
00H
R
→
00H
Device Identification Registers
These registers represent a unique signature to identify the device and silicon version.
: 00H (STMicroelectronics)
: 01H (BCD Power Management)
: 55H
: 41H
: 4DH
: 06H
: for L99DZ120: 01H
SPI modes
By reading out the register general information of SPI usage of the Device
Application Registers can be read.
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Table 60. SPI Mode Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BR
DL2
DL1
DL0
0
0
S1
S0
1
0
1
1
0
0
0
0
: B0H (Burst mode read available, 32-bit, no data consistency check)
SPI Burst Read
Table 61. Burst Read Bit
Bit 7
Description
0
BR not available
1
BR available
The SPI Burst Read bit indicates if a burst read operation is implemented. The intention of a
Burst Read is e.g. used to perform a device internal memory dump to the SPI Master.
The start of the Burst Read is like a normal Read Operation. The difference is, that after the
SPI Data Length the CSN is not pulled high and the SCK will be continuously clocked. When
the normal SCK max count is reached (SPI Data Length) the consecutive addressed data
will be latched into the shift register. This procedure is performed every time when the SCK
payload length is reached.
In case the automatic incremented address is not used by the device, undefined data is
shifted out. An automatic address overflow is implemented when address 3FH is reached.
The SPI Burst Read is limited by the CSN low timeout.
SPI Data Length
The SPI Data Length value indicates the length of the SCK count monitor which is running
for all accesses to the Device Application Registers. In case a communication frame with an
SCK count is not equal to the reported one it will lead to a SPI Error and the data will be
rejected.
Table 62. SPI Data Length
Bit 6
Bit 5
Bit 4
Description
DL2
DL1
DL0
0
0
0
invalid
0
0
1
16-bit SPI
0
1
0
24-bit SPI
0
1
1
32-bit SPI
…
1
1
Data Consistency Check (Parity/CRC)
N/A
106/161
DS11567 Rev 5
1
64-bit SPI
L99DZ120
Serial Peripheral Interface (SPI)
Table 63. Data Consistency Check
Bit 1
Bit 0
Description
S1
S0
0
0
not used
0
1
Parity used
1
0
CRC used
1
1
Invalid
Watchdog Definition
In case a watchdog is implemented the default settings can be read out via the Device
Information Registers.
Table 64. WD Type/Timing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WD1
WD0
0
0
0
1
WT5
WT4
WT3
1
1
0
1
Bit 2
Bit 1
Bit 0
WT2
WT1
WT0
0
0
0
Register is not used
Watchdog Timeout / Long Open Window WT[5:0] * 5ms
1
0
OW2
OW1
OW0
CW2
CW1
CW0
1
0
0
1
0
0
0
1
Open Window OW[2:0] *
5ms
1
1
Closed Window CW[2:0] *
5ms
Invalid
: 28H (Long Open Window: 200ms)
: 91H (Open Window. 10ms, Closed Window: 5ms)
indicates the Long Open Window (timeout) which is opened at the start of the
watchdog. The binary value of WT[5:0] times 5ms indicates the typical value of the Timeout
Time.
describes the default timing of the window watchdog.
The binary value of CW[2:0] times 5ms defines the typical Closed Window time and OW[2:0]
times 5ms defines the typical Open Window time.
DS11567 Rev 5
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160
Serial Peripheral Interface (SPI)
L99DZ120
Figure 54. Window watchdog operation
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The watchdog trigger bit location is defined by the registers.
Table 65. WD bit position
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
WB1
WB0
0
0
0
1
WBA5
WBA4
WBA3
0
1
0
0
0
1
1
1
Bit 2
Bit 1
Bit 0
WBA2
WBA1
WBA0
0
0
0
1
1
1
1
1
Register is not used
Defines the register addresses of the WD trigger bits
1
0
WBA5
WBA4
WBA3
WBA2
WBA1
WBA0
Defines the stop address of the address range (previous
is a WB = ‘01’). The consecutive has to be a WB = ‘11’
1
1
0
WBP 4
WBP3
WBP2
WBP1
WBP0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Defines the binary bit position of the WD trigger
bit within the register
: 41H;watchdog trigger bit located at address 01H (CR1)
: C0H; watchdog trigger bit location is bit0
: 7FH;watchdog trigger bit located at address 3FH (Config Register)
: C0H; watchdog trigger bit location is bit0
108/161
DS11567 Rev 5
L99DZ120
Serial Peripheral Interface (SPI)
Device Application Registers (RAM)
The Device Application Registers are all registers accessible using OpCode ‘00’, ‘01’ and
‘10’. The functions of these registers are defined in the device specification.
5.2.4
Protocol failure detection
To realize a protocol which covers certain failsafe requirements a basic set of failure
detection mechanisms is implemented.
Clock monitor
During communication (CSN low to high phase) a clock monitor counts the valid SCK clock
edges. If the SCK edges do not correlate with the SPI Data Length an SPIE is reported with
the next command and the actual communication is rejected.
By accessing the Device Information Registers (OpCode = ‘11’) the Clock Monitor is set to a
minimum of 16 SCK edges plus a multiple by 8 (e.g. 16, 25, 32, …). Providing no SCK edge
during a CSN low to high phase is not recognized as an SPIE. For a SPI Burst Read also
the SPI Data Length plus multiple numbers of Payloads SCK edges are assumed as a valid
communication.
SCK Polarity (CPOL) check
To detect the wrong polarity access via SCK the internal Clock monitor is used. Providing
first a negative edge on SCK during communication (CSN low to high phase) or a positive
edge at last will lead to an SPI Error reported in the next communication and the actual data
is rejected.
SCK Phase (CPHA) check
To verify, that the SCK Phase of the SPI master is set correctly a special Device Information
Register is implemented. By reading this register the data must be 55H. In case AAH is read
the CPHA setting of the SPI master is wrong and a proper communication cannot be
guaranteed.
CSN timeout
By pulling CSN low the SDO is set active and leaves its 3-state condition. To ensure
communication between other SPI devices within the same bus even in case of CSN stuck
at low a CSN timeout is implemented. By pulling CSN low an internal timer is started. After
timer end is reached the actual communication is rejected and the SDO is set to 3-state
condition.
SDI stuck at GND
As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be
distinguished between a valid command and a SDI stuck at GND this communication is not
allowed. Nevertheless, in case a stuck at GND is detected the communication will be
rejected and the SPIE will be set with the next communication.
SDI stuck at HIGH
As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be
distinguished between a valid command and a SDI stuck at HIGH this communication is not
DS11567 Rev 5
109/161
160
Serial Peripheral Interface (SPI)
L99DZ120
allowed. In case a stuck at HIGH is detected the communication will be rejected and the
SPIE will be set with the next communication.
SDO stuck @
The SDO stuck at GND and stuck at HIGH have to be detected by the SPI master. As the
definition of the GSB guarantees at least one toggle, a GSB with all-‘0’ or all –‘1’ reports a
stuck at error.
110/161
DS11567 Rev 5
L99DZ120
6
Application
Application
Figure 55. Typical application diagram
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DS11567 Rev 5
111/161
160
SPI Registers
L99DZ120
7
SPI Registers
7.1
Global Status Byte GSB
Table 66. Global Status Byte (GSB)
31
30
29
28
27
26
25
24
Bit name
GSBN
RSTB
SPIE
PLE
FE
DE
GW
FS
Reset
1
0
0
0
0
0
0
0
Access
R
Table 67. GSB signals description
Bit
31
30
29
112/161
Name
Description
GSBN
Global Status Bit Inverted
The GSBN is a logically NOR combination of GSB Bits 24 to Bit 30(1).
This bit can also be used as Global Status Flag without starting a complete
communication frame as it is present at SDO directly after pulling CSN low.
0: error detected (1 or several GSB bits from 24 to 30 are set)
1: no error detected (default after Power-on)
Specific failures may be masked in the Configuration Register 0x3F. A
masked failure will still be reported in the GSB by the related failure flag,
however it is not reflected in the GSBN (bit 31).
RSTB
Reset
The RSTB indicates a device reset and it is set in case of the following
events:
– VPOR (SR1 - 0x31)
– WDFAIL (SR1 - 0x31)
– V1UV (SR1 - 0x31)
– FORCED_SLEEP_TSD2/V1SC (SR1 - 0x31)
0: no reset signal has been generated (default)
1: Reset signal has been generated
RSTB is cleared by a Read & Clear command to all bits in Status Register 1
causing the Reset event.
SPIE(2)
SPI Error Bit
The SPIE indicates errors related to a wrong SPI communication.
– SPI_INV_CMD (SR2 - 0x32)
– SPI_SCK_CNT (SR2 - 0x32)
The bit is also set in case of an SPI CSN Time-out detection
0: no error (default)
1: error detected
SPIE is cleared by a valid SPI command.
DS11567 Rev 5
L99DZ120
SPI Registers
Table 67. GSB signals description (continued)
Bit
28
27
26
Name
Description
PLE(2)
Physical Layer Error
The PLE is a logical OR combination of errors related to the LIN transceiver.
– LIN_PERM_DOM (SR2 - 0x32)
– LIN_TXD_DOM (SR2 - 0x32)
– LIN_PERM_REC (SR2 - 0x32)
0: no error (default)
1: error detected
PLE is cleared by a Read & Clear command to all related bits in Status
Registers 2 and 12.
FE
Functional Error Bit
The FE is a logical OR combination of errors coming from functional blocks.
– V2SC (SR2 - 0x32)
– DSMON_HSx (SR2 - 0x32)
– DSMON_LSx (SR2 - 0x32)
– OUTxHS_OC TH EX (SR3 - 0x33)
– OUTxLS_OC TH EX (SR3 - 0x33)
– OUTHS_OC TH EX (SR3 - 0x33)
– OUTx_OC (SR3 - 0x33)
– LSxFS_OC (SR3 - 0x33)
– OUTxHS_OL (SR5 - 0x35)(3)
– OUTxLS_OL (SR5 - 0x35)
– OUTx_OL (SR5 - 0x35)
– OUTHS_OL (SR5 - 0x35)
0: no error (default)
1: error detected
FE is cleared by a Read & Clear command to all related bits in Status
Registers 2, 3, 4, 5
DE
Device Error Bit
DE is a logical OR combination of global errors related to the device.
– VS_OV (SR2 - 0x32)
– VS_UV (SR2 - 0x32)
– VSREG_OV (SR2 - 0x32)
– VSREG_UV (SR2 - 0x32)
– CP_LOW (SR2 - 0x32)
– TSD1_CLx (SR6 - 0x36)
0: no error (default)
1: error detected
DE is cleared by a Read & Clear command to all related bits in Status
Registers 2 and 6
DS11567 Rev 5
113/161
160
SPI Registers
L99DZ120
Table 67. GSB signals description (continued)
Bit
25
24
Name
Description
GW (2)
Global Warning Bit
GW is a logical OR combination of warning flags. Warning bits do not lead to
any device state change or switch off of functions.
– VSREG_EW (SR2 - 0x32)
– V1_FAIL (SR2 - 0x32)
– V2_FAIL (SR2 - 0x32)
– TW (3) (SR2 - 0x32)
– SPI_INV_CMD (SR2 - 0x32)
– SPI_SCK_CNT (SR2 - 0x32)
0: no error (default)
1: error detected
GW is cleared by a Read & Clear command to all related bits in Status
Register 2.
FS
Fail Safe
The FS bit indicates the device was forced into a safe state due to the
following failure conditions:
– WDFAIL (SR1 - 0x31)
– V1UV (SR1 - 0x31)
– TSD2 (SR1 - 0x31)
– FORCED_SLEEP_TSD/V1SC (SR1 - 0x31)
All Control Registers are set to default
Control Registers are blocked for WRITE access except the following bits:
– TRIG (CR1 - 0x01)
– V2_0 (CR1 - 0x01)
– V2_1 (CR1 - 0x01)
– Timer settings (bits 8…23) (CR2 - 0x02)
– OUTHS_x (bits 0…3) (CR5 - 0x05)
– OUT15_x (bits 0…3) (CR6 - 0x06)
– CR12 (0x0C) to CR17 (0x11); PWM frequency and duty cycles
0: Fail Safe inactive (default)
1: Fail Safe active
FS is cleared upon exit from Fail-Safe mode (refer to chapter ‘Fail-Safe
mode’)
1. Individual failure flags may be masked in the Configuration Register (0x3F).
2. Bit may be masked in the Configuration Register (0x3F), i.e. the bit will not be included in the Global Status
Bit (GSBN).
3. Open-load status flags may be masked in the Configuration register (0x3F), i.e. the open-load flag will be
included in the FE flag, but will not set the GSBN. TW failure status flags may be masked in the
Configuration register (0x3F), i.e. the TW flag will be included in the GW flag, but will not set the GSBN.
114/161
DS11567 Rev 5
OUT11_2
OUT11_1
OUT11_0
OUT6_OCR
OUT7_OCR
OUT8_OCR
OUT8_0
OUT8_1
OUT8_2
TIMER_NINT_WAKE_SEL
TIMER_NINT_EN
T2_RESTART
T2_DIR
DS11567 Rev 5
LIN_REC_ONLY
LIN_TXD_TOUT_EN
VSREG_EWTH_7
VSREG_EWTH_6
OUT14_3
OUT14_2
OUT14_1
OUT14_0
OUT15_3 OUTHS_3
OUT15_2 OUTHS_2
OUT15_1 OUTHS_1 OUT6_HS
OUT5_OC1
OUT5_OC0
CM_EN
Reserved
CM_SEL_3
CM_SEL_2
CM_SEL_1
R/W
R/W
R/W
R/W
R/W
WD_TIME_0
R/W
TRIG
Access
0
R/W
VSREG_EWTH_0
GO_STBY
STBY_SEL
1
OUT15_0 OUTHS_0 OUT6_LS
WD_TIME_1
V1_RESET_0
PARITY
2
VSREG_EWTH_1
VSREG_EWTH_2
V1_RESET_1
V2_0
3
CM_SEL_0
Reserved
VSREG_EWTH_3
4
Reserved
VSREG_EWTH_4
OUT5_LS
5
V2_1
Reserved
VSREG_EWTH_5
Reserved
6
HEN
7
OUT5_HS
8
Reserved
T2_PER_0
VSREG_EWTH_8
OUT13_0 OUT10_0 OUT4_LS
OCR_FREQ
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
T2_PER_1
VSREG_EWTH_9
OUT13_1 OUT10_1 OUT4_HS
Reserved
T2_PER_2
Reserved
OUT13_2 OUT10_2
Reserved
T2_ON_0
Reserved
OUT13_3 OUT10_3
T2_ON_1
T2_ON_2
WU_FILT_0
T1_PER_0
Reserved
WU_FILT_1
T1_PER_2
VS_UV_SD_EN
T1_PER_1
T1_ON_0
WU_PU
Reserved
WU_EN
Reserved
0x00
OUT12_0
OUT12_1
OUT12_2
OUTHS_OCR OUT12_3
OUT11_3
OUT5_OCR
VS_OV_SD_EN
T1_ON_1
OUT1_LS VSREG_UV_SD_EN
OUT7_0
0x07 CR7
OUT9_0
0x05 CR5
OUT4_OCR
0x04 CR4
OUT8_3
T1_ON_2
OUT1_HS VSREG_OV_SD_EN
OUT7_1
OUT9_1
T1_DIR
0x03 CR3
VS_LOCK_EN
OUT7_2
OUT9_2
T1_RESTART
0x01 CR1
Reserved
0x02 CR2
VSREG_LOCK_EN
OUT9_3
7.2
Reserved
OUT7_3
0x06 CR6
OUT1_OCR
L99DZ120
SPI Registers
Control register overview
Table 68. Control register overview
Bit
115/161
160
Reserved
0x0D CR13
116/161
PMW1_FREQ_0
PMW1_FREQ_1
0x0C CR12
Reserved
0x0F CR15
DIAG_1
0x0B CR11
DS11567 Rev 5
OUT9_OL
OUTHS_OC
OUT15_OC
OUT14_OC
OUT13_OC
OUT12_OC
OUT11_OC
OUT10_OC
OUT9_OC
COPT_0
H_OLTH_HIGH
OL_H1L2
OL_H2L1
SLEW_4
SLEW_3
SLEW_2
SLEW_1
SLEW_0
PWM6_DC_8 PWM4_DC_8 PWM2_DC_8 PMW8_FREQ_0
PWM6_DC_7 PWM4_DC_7 PWM2_DC_7 PMW9_FREQ_1
PWM6_DC_6 PWM4_DC_6 PWM2_DC_6 PMW9_FREQ_0
PWM6_DC_5 PWM4_DC_5 PWM2_DC_5 PMW10_FREQ_1
PWM6_DC_4 PWM4_DC_4 PWM2_DC_4 PMW10_FREQ_0
Reserved
R/W
Reserved
Access
0
R/W
1
R/W
2
R/W
3
R/W
4
PWM6_DC_0 PWM4_DC_0 PWM2_DC_0
5
PWM6_DC_1 PWM4_DC_1 PWM2_DC_1
6
PWM6_DC_2 PWM4_DC_2 PWM2_DC_2
7
PWM6_DC_3 PWM4_DC_3 PWM2_DC_3
PMW7_FREQ_0
PMW7_FREQ_1
8
R/W
OUT10_OL
COPT_1
PWM6_DC_9 PWM4_DC_9 PWM2_DC_9 PMW8_FREQ_1
Reserved
OUTHS_OCR_THX_EN
OUT8_OCR_THX_EN
OUT7_OCR_THX_EN
OUT6_OCR_THX_EN
OUT5_OCR_THX_EN
OUT4_OCR_THX_EN
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R/W
OUT11_OL
COPT_2
Reserved
R/W
OUT12_OL
COPT_3
Reserved
PWM5_DC_0 PWM3_DC_0 PWM1_DC_0 PMW6_FREQ_0
PWM5_DC_1 PWM3_DC_1 PWM1_DC_1 PMW6_FREQ_1
OUT13_OL
OUT15_OL
OUTHS_OL
SDS
Reserved
OUT14_OL
Reserved
SD
PWM5_DC_2 PWM3_DC_2 PWM1_DC_2 PMW5_FREQ_0
OUT8_RDSON
DIAG_2
Reserved
PWM5_DC_3 PWM3_DC_3 PWM1_DC_3 PMW5_FREQ_1
PWM5_DC_4 PWM3_DC_4 PWM1_DC_4 PMW4_FREQ_0
PWM5_DC_5 PWM3_DC_5 PWM1_DC_5 PMW4_FREQ_1
PWM5_DC_6 PWM3_DC_6 PWM1_DC_6 PMW3_FREQ_0
PWM5_DC_7 PWM3_DC_7 PWM1_DC_7 PMW3_FREQ_1
PWM5_DC_8 PWM3_DC_8 PWM1_DC_8 PMW2_FREQ_0
OUT7_RDSON
0x0A CR10
Reserved
OUT1_OCR_THX_EN
0x09 CR9
DIAG_0
0x08 CR8
PWM5_DC_9 PWM3_DC_9 PWM1_DC_9 PMW2_FREQ_1
0x0E CR14
Reserved
SPI Registers
L99DZ120
Table 68. Control register overview (continued)
Bit
Reserved
OUT9_AUTOCOMP_EN
OUT9_VLED_9
OUT9_VLED_8
OUT9_VLED_7
OUT9_VLED_6
OUT9_VLED_5
OUT9_VLED_4
OUT9_VLED_3
OUT9_VLED_2
OUT9_VLED_1
OUT9_VLED_0
Reserved
0x14 CR20
OUT11_AUTOCOMP_EN
OUT11_VLED_9
OUT11_VLED_8
OUT11_VLED_7
OUT11_VLED_6
OUT11_VLED_5
OUT11_VLED_4
OUT11_VLED_3
OUT11_VLED_2
OUT11_VLED_1
OUT11_VLED_0
Reserved
0x12 CR18
DS11567 Rev 5
PWM9_DC_3 PWM7_DC_3
PWM9_DC_2 PWM7_DC_2
PWM9_DC_1 PWM7_DC_1
PWM9_DC_0 PWM7_DC_0
OUT7_VLED_3
OUT7_VLED_2
OUT7_VLED_1
OUT7_VLED_0
OUT10_VLED_5
OUT10_VLED_4
OUT10_VLED_3
OUT10_VLED_2
OUT10_VLED_1
OUT12_VLED_5
OUT12_VLED_4
OUT12_VLED_3
OUT12_VLED_2
OUT12_VLED_1
R/W
R/W
Access
0
R/W
PWM10_DC_0 PWM8_DC_0
1
OUT8_VLED_0
PWM10_DC_1 PWM8_DC_1
2
OUT8_VLED_1
PWM10_DC_2 PWM8_DC_2
3
OUT8_VLED_2
PWM10_DC_3 PWM8_DC_3
4
OUT8_VLED_3
PWM10_DC_4 PWM8_DC_4
PWM10_DC_5 PWM8_DC_5
PWM10_DC_6 PWM8_DC_6
5
OUT8_VLED_4
OUT8_VLED_5
OUT8_VLED_6
PWM10_DC_7 PWM8_DC_7
6
R/W
OUT10_VLED_6
OUT12_VLED_6
OUT8_VLED_7
PWM10_DC_8 PWM8_DC_8
7
R/W
OUT10_VLED_7
OUT12_VLED_7
OUT8_VLED_8
PWM10_DC_9 PWM8_DC_9
8
OUT10_VLED_0
OUT10_VLED_8
OUT12_VLED_8
OUT8_VLED_9
Reserved
PWM9_DC_4 PWM7_DC_4
OUT7_VLED_4
Reserved
PWM9_DC_5 PWM7_DC_5
OUT7_VLED_5
Reserved
PWM9_DC_6 PWM7_DC_6
PWM9_DC_7 PWM7_DC_7
PWM9_DC_8 PWM7_DC_8
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OUT12_VLED_0
OUT10_VLED_9
OUT12_VLED_9
Reserved
PWM9_DC_9 PWM7_DC_9
Reserved
OUT7_VLED_6
OUT7_VLED_7
OUT7_VLED_8
OUT7_VLED_9
OUT7_AUTOCOMP_EN
0x11 CR17
Reserved
0x10 CR16
OUT12_AUTOCOMP_EN OUT10_AUTOCOMP_EN OUT8_AUTOCOMP_EN
0x13 CR19
Reserved
L99DZ120
SPI Registers
Table 68. Control register overview (continued)
Bit
117/161
160
0x3F
Note:
118/161
Conf
Reg
DS11567 Rev 5
Reserved
OUT13_VLED_7
OUT13_VLED_6
OUT13_VLED_5
OUT13_VLED_4
OUT13_VLED_3
OUT13_VLED_2
OUT15_VLED_7
OUT15_VLED_6
OUT15_VLED_5
OUT15_VLED_4
OUT15_VLED_3
OUT15_VLED_2
Reserved
OUT13_VLED_0
OUT14_VLED_3
OUTHS_VLED_6
OUTHS_VLED_5
OUTHS_VLED_4
OUTHS_VLED_3
CP_LOW_CONFIG
CP_DITH_DIS
FS_FORCED
OUTHS_VLED_1
OUTHS_VLED_0
R/W
ICMP
WD_EN
R/W
TRIG
R/W
Access
0
R/W
1
OUT14_VLED_0
2
OUT14_VLED_1
3
OUT14_VLED_2
4
OUTHS_VLED_2
5
CP_OFF
6
OUT14_VLED_5
7
OUT14_VLED_6
OUT14_VLED_7
8
Reserved
OUT14_VLED_4
OUTHS_VLED_7
CP_OFF_EN
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OUT14_VLED_8
OUTHS_VLED_8
MASK_GW
OUT14_VLED_9
OUTHS_AUTOCOMP_EN OUT14_AUTOCOMP_EN
Reserved
OUT15_VLED_0
OUT13_VLED_1
OUT13_VLED_8
OUT15_VLED_8
OUT15_VLED_1
OUT13_VLED_9
OUT15_VLED_9
OUTHS_VLED_9
Reserved
MASK_PLE
MASK_SPIE
MASK_OL
Reserved
MASK_TW
0x22 CR34
MASK_OL_LS1
MASK_OL_HS1
WD_CONFIG_EN
ICMP_CONFIG_EN
DM
Reserved
TSD_CONFIG
LIN_HS_EN
Reserved
0x16 CR22
OUT15_AUTOCOMP_EN OUT13_AUTOCOMP_EN
0x15 CR21
LIN_WU_CONFIG
WU_CONFIG
SPI Registers
L99DZ120
Table 68. Control register overview (continued)
Bit
All reserved bits (RES) are read-only (R) and will be read as ‘0’. Writing ‘1’ to a reserved bit
is ignored and does not cause an SPI error.
0x33 SR3
0x34 SR4
0x35 SR5
Reserved
Reserved
Reserved
WDFAIL_CNT_2
WDFAIL_CNT_1
WDFAIL_CNT_0
DEVICE_STATE_1
DEVICE_STATE_0
TSD2
TSD1
FORCED_SLEEP_TSD2/V1SC
FORCED_SLEEP_WD
WDFAIL
VPOR
SPI_SCK_CNT
CP_LOW
TW
V2SC
V2FAIL
V1FAIL
VSREG_EW
VSREG_OV
VSREG_UV
VS_OV
VS_UV
OUT8_OC_TH_EX
OUT9_OC
OUT10_OC
OUT11_OC
OUT12_OC
OUT13_OC
OUT14_OC
OUT15_OC
OUTHS_OC_TH_EX
LS2FSO_OC
LS1FSO_OC
R
DS11567 Rev 5
OUT8_OCR_ALERT
OUT8_OL
OUTHS_OCR_ALERT
Reserved
R
Reserved
Reserved
OUTHS_OL
OUT15_OL
OUT14_OL
OUT13_OL
OUT12_OL
OUT11_OL
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
OUT10_OL
OUT9_OL
WDFAIL_CNT_3
SPI_INV_CMD
V1_RESTART_0
DSMON_LS1
OUT6_LS_OL OUT6_LS_OCR_ALERT OUT6_LS_OC_TH_EX
OUT7_OC_TH_EX
V1_RESTART_1
DSMON_LS2
OUT6_HS_OL OUT6_HS_OCR_ALERT OUT6_HS_OC_TH_EX
R
OUT7_OCR_ALERT
V1_RESTART_2
DSMON_HS1
OUT5_LS_OL OUT5_LS_OCR_ALERT OUT5_LS_OC_TH_EX
R
OUT7_OL
V1UV
DEBUG_ACTIVE
WAKE_TIMER
WAKE_LIN
Reserved
WU_WAKE
Reserved
DSMON_HS2
Reserved
OUT5_HS_OL OUT5_HS_OCR_ALERT OUT5_HS_OC_TH_EX
OUT4_LS_OL OUT4_LS_OCR_ALERT OUT4_LS_OC_TH_EX
OUT4_HS_OL OUT4_HS_OCR_ALERT OUT4_HS_OC_TH_EX
LIN_PERM_REC
WU_STATE
0x32 SR2
OUT1_LS_OL OUT1_LS_OCR_ALERT OUT1_LS_OC_TH_EX LIN_TXD_DOM
0x31 SR1
Reserved
Bit
Access
7.3
OUT1_HS_OL OUT1_HS_OCR_ALERT OUT1_HS_OC_TH_EX LIN_PERM_DOM
L99DZ120
SPI Registers
Status register overview
Table 69. Status register overview
8
7
6
5
4
3
2
1
0
R
119/161
160
0x3A SR10
0x3B SR11
120/161
VSREG_3 TEMP_CL6_3 TEMP_CL4_3 TEMP_CL2_3
VSREG_2 TEMP_CL6_2 TEMP_CL4_2 TEMP_CL2_2
VSREG_1 TEMP_CL6_1 TEMP_CL4_1 TEMP_CL2_1
VSREG_0 TEMP_CL6_0 TEMP_CL4_0 TEMP_CL2_0
VS_3
VS_2
VS_1
VS_0
DS11567 Rev 5
VWU_0
VWU_1
VWU_2
VWU_3
VWU_4
5
4
3
2
1
0
TSD1_CL6
TSD1_CL5
TSD1_CL4
TSD1_CL3
TSD1_CL2
TSD1_CL1
TEMP_CL5_4 TEMP_CL3_4 TEMP_CL1_4
TEMP_CL5_3 TEMP_CL3_3 TEMP_CL1_3
TEMP_CL5_2 TEMP_CL3_2 TEMP_CL1_2
TEMP_CL5_1 TEMP_CL3_1 TEMP_CL1_1
TEMP_CL5_0 TEMP_CL3_0 TEMP_CL1_0
Reserved
6
TEMP_CL5_5 TEMP_CL3_5 TEMP_CL1_5
TEMP_CL5_6 TEMP_CL3_6 TEMP_CL1_6
7
VWU_5
VWU_6
TEMP_CL5_7 TEMP_CL3_7 TEMP_CL1_7
TW_CL1
TEMP_CL5_8 TEMP_CL3_8 TEMP_CL1_8
8
VWU_7
TW_CL2
TEMP_CL5_9 TEMP_CL3_9 TEMP_CL1_9
Addr. Reg. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
VWU_8
VWU_9
TW_CL3
TW_CL4
VSREG_4 TEMP_CL6_4 TEMP_CL4_4 TEMP_CL2_4
VS_4
Reserved
VSREG_5 TEMP_CL6_5 TEMP_CL4_5 TEMP_CL2_5
VS_5
Reserved
VSREG_6 TEMP_CL6_6 TEMP_CL4_6 TEMP_CL2_6
VS_6
Reserved
TW_CL5
VSREG_7 TEMP_CL6_7 TEMP_CL4_7 TEMP_CL2_7
VS_7
Reserved
Reserved
TW_CL6
VSREG_8 TEMP_CL6_8 TEMP_CL4_8 TEMP_CL2_8
WD_TIMER_STATE_0
WD_TIMER_STATE_1
VS_8
Reserved
0x39 SR9
VSREG_9 TEMP_CL6_9 TEMP_CL4_9 TEMP_CL2_9
Reserved
0x38 SR8
VS_9
0x37 SR7
Reserved
0x36 SR6
Reserved Reserved
Bit
Access
SPI Registers
L99DZ120
Table 69. Status register overview (continued)
Reserved
R
R
R
R
R
R
L99DZ120
SPI Registers
7.4
Control registers
7.4.1
Control Register CR1 (0x01)
0
0
0
R
0
0
0
4
3
2
1
0
TRIG
1
5
GO_STBY
0
Reserved
6
STBY_SEL
R/W
0
7
PARITY
R
0
8
V2_0
R R/W
0
0
9
V2_1
Access
0
TIMER_NINT_EN
0
TIMER_NI0NT_WAKE_SEL
0
WU_FILT_0
1
WU_FILT_1
0
19 18 17 16 15 14 13 12 11 10
Reserved
Reset
Bit name
WU_PU
20
Reserved
21
WU_EN
22
Reserved
23
HEN
Table 70. Control Register CR1
0
0
0
0
0
0
0
R/W
Table 71. CR1 signals description
Bit
Name
23
Reserved
22
WU_EN
21
Reserved
20
19
18
WU_PU
Reserved
17
WU_FILT_1
16
WU_FILT_0
15
Description
—
Wake-up Input 1 (WU) enable(1)
0: WU disabled
1: WU enabled (default)
—
Wake-up Input1 Pull-up/down configuration: configuration of internal current
source(1)
0: pull-down (default)
1: pull-up
—
Wake-up Input1 Filter configuration Bits: configuration of input filter(1)
See Table 72: Wake-up input1 filter configuration
Select Timer for NINT / Wake: select timer for periodic interrupt in standby
modes
TIMER_NINT_WAKE_SEL
0: Timer 2 (default)
1: Timer 1
DS11567 Rev 5
121/161
160
SPI Registers
L99DZ120
Table 71. CR1 signals description (continued)
Bit
Name
Description
14
TIMER_NINT_EN
13:7
Reserved
6
HEN
5
V2_1
4
V2_0
3
PARITY
2
STBY_SEL
1
GO_STBY
0
TRIG
Timer NINT enable: enable timer interrupt in standby modes
0: timer interrupt disabled (default)
1: timer interrupt enabled
V1_standby mode: periodic NINT pulse generated by timer (NINT pulse
at start of timer on-phase)
Vbat_standby mode: device wakes up after timer expiration and
generates NReset
—
Enable H-bridge
0: H-bridge disabled (default)
1: H-bridge enabled
Refer to chapter H-bridge Control for details
Voltage Regulator V2 Configuration
See Table 73: Voltage regulator V2 configuration
PARITY: Standby Command Parity Bit
STBY SEL: Select Standby mode
GO_STBY: Execute transition into Standby mode
The STBY_SEL and GO_STBY bits are protected by a parity check.
The bits STBY_SEL, GO_STBY and PARITY must represent an even
number of '1', otherwise the command is ignored and the SPI_INV_CMD bit
is set.
Table 74: Standby transition configuration shows the valid settings.
All other settings are invalid; command will be ignored and SPI_INV_CMD
will be set. The GO_STBY bit is not cleared automatically after wake-up.
Watchdog Trigger Bit
1. Setting is only valid if input is configured as wake-up input in Configuration Register (0x3F).
Table 72. Wake-up input1 filter configuration
WU_FILT_1
WU_FILT_0
0
0
Wake-up inputs monitored in static mode (filter time twu_stat) (default)
0
1
Wake- up inputs monitored in cyclic mode with Timer2 (filter time:
tWU_cyc; blanking time 80% of timer ON time)
1
0
Wake- up inputs monitored in cyclic mode with Timer1 (filter time:
tWU_cyc; blanking time 80% of timer ON time)
1
1
Invalid setting; command will be ignored and SPI INV CMD will be set
Table 73. Voltage regulator V2 configuration
122/161
V2_1
V2_0
0
0
V2 OFF in all modes (default)
0
1
V2 ON in Active mode; OFF in Standby modes
DS11567 Rev 5
L99DZ120
SPI Registers
Table 73. Voltage regulator V2 configuration (continued)
V2_1
V2_0
1
0
V2 ON in Active and V1_standby mode; OFF in Vbat_standby mode
1
1
V2 ON in all modes
Table 74. Standby transition configuration
7.4.2
PARITY
STBY_SEL
GO_STBY
0
1
1
Go to V1 standby
1
0
1
Go to Vbat_standby
0
0
0
1
1
0
No transition to standby
Control Register CR2 (0x02)
T2_ON_1
T2_ON_0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
WD_TIME_0
T2_ON_2
0
2
WD_TIME_1
T2_DIR
0
3
V1_RESET_0
T2_RESTART
0
4
V1_RESET_1
T1_PER_0
0
5
Reserved
T1_PER_1
LIN_TXD_TOUT_EN
T1_PER_2
6
LIN_REC_ONLY
T1_ON_0
7
T2_PER_0
19 18 17 16 15 14 13 12 11 10
T1_ON_1
8
T2_PER_1
20
Access
9
T2_PER_2
21
T1_ON_2
Reset
22
T1_DIR
Bit name
23
T1_RESTART
Table 75. Control Register CR2
0
0
0
0
R/W
Table 76. CR2 signals description
Bit
Name
23
T1_RESTART
22
T1_DIR1
21
T1_ON_2
20
T1_ON_1
19
T1_ON_0
Description
Timer 1 Restart: Restart of Timer 1
0: timer is running with period and on-time according to configuration (default)
1: restart of timer at CSN low to high transition; starting with ON phase(1)
Bit is automatically reset with next SPI frame.
T1_DIR1: Timer 1 Direct Drive by DIR1
T1_ON_x: Timer 1 On-Time Bits
Configuration of Timer 1 on-time, for details see Table 77 and Figure 56
DS11567 Rev 5
123/161
160
SPI Registers
L99DZ120
Table 76. CR2 signals description (continued)
Bit
Name
18
T1_PER_2
17
T1_PER_1
16
T1_PER_0
15
T2_RESTART
14
T2_DIR1
13
T2_ON_2
12
T2_ON_1
11
T2_ON_0
10
T2_PER_2
9
T2_PER_1
8
T2_PER_0
7
LIN_REC_ONLY
6
5:4
124/161
Description
Configuration of Timer 1 Period
000: T1 (default)
001: T2
010: T3
011: T4
100: T5
101: T6
110: T7
111: T8
Timer 2 Restart: restart of timer 2
0: timer is running with period and on-time according to configuration (default)
1: restart of timer at CSN low to high transition; starting with ON phase(1)
Bit is automatically reset with next SPI frame.
T2_DIR1: Timer 2 Direct Drive by DIR1
T2_ON_x: Timer 2 On-Time Bits
Configuration of Timer 2 on-time, for details see Table 77 and Figure 56
Configuration of Timer 2 Period
000: T1 (default)
001: T2
010: T3
011: T4
100: T5
101: T6
110: T7
111: T8
LIN Transceiver Receive Only mode
0: LIN receive only mode disabled (default)
1: LIN receive only mode enabled
LIN TxD Timeout Enable
LIN_TXD_TOUT_EN 0: LIN TxD timeout detection disabled
1: LIN TxD timeout detection enabled (default)
Reserved
—
DS11567 Rev 5
L99DZ120
SPI Registers
Table 76. CR2 signals description (continued)
Bit
Name
3
V1_RESET_1
2
V1_RESET_0
1
WD_TIME_1
0
WD_TIME_0
Description
Voltage Regulator V1 Reset Threshold
00: Vrt4 (default)
01: Vrt3
10: Vrt2
11: Vrt1
thresholds are monitored in Active mode and V1_standby mode
Watchdog Trigger Time
00: TSW1 (default)
01: TSW2
10: TSW3
11: TSW4
Writing to WD_TIME_x is blocked unless WD CONFIG EN = 1.
The modified WD Trigger Time is valid immediately after the Write command (CSN
transition low-high).
The watchdog timer is reset when the trigger time is modified (restart at CSN
transition low-high).
1. Timer restart behavior:
Write to CR2 when Tx_ON_x and Tx_PERx remain unchanged:
Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time
Tx_RESTART = 0: write operation to CR2 has no effect on timers
Write to CR2 when Tx_ON_x and Tx_PERx are modified
Tx_RESTART = 1: timers restart at end of SPI frame, starting with ON time and according to new setting (ON time and
period)
Tx_RESTART = 0: behavior is not defined; if a predictable behavior is needed, it is recommended to set Tx_RESTART = 1
Table 77. Configuration of Timer x on-time
Tx_DIR1
Tx_ON_2
Tx_ON_1
Tx_ON_0
0
0
0
0
ton1 (default)
0
0
0
1
ton2
0
0
1
0
ton3
0
0
1
1
ton4
0
1
0
0
ton5
0
1
0
1
0
1
1
0
0
1
1
1
(1)
1
0
0
0
ton1 controlled by DIR1 input signal (logical AND)
1(1)
0
0
1
ton2 controlled by DIR1 input signal (logical AND)
1(1)
0
1
0
ton3 controlled by DIR1 input signal (logical AND)
(1)
0
1
1
ton4 controlled by DIR1 input signal (logical AND)
(1)
1
0
0
ton5 controlled by DIR1 input signal (logical AND)
1
1
Invalid setting; command will be ignored and SPI
INV CMD will be set
DS11567 Rev 5
125/161
160
SPI Registers
L99DZ120
Table 77. Configuration of Timer x on-time (continued)
Tx_DIR1
Tx_ON_2
Tx_ON_1
Tx_ON_0
(1)
1
1
0
1
1(1)
1
1
0
1(1)
1
1
1
Invalid setting; command will be ignored and SPI
INV CMD will be set
1. Tx_DIR1 = 1 is only valid for OUT7-OUT15 and OUT_HS control; the DIR1 signal has no influence for WU
monitoring if WU is monitored by timer.
Figure 56. Timer_x controlled by DIR1
7[',5
7[
WRQ[
7LPHU;
',5
287[
("1($'5
7.4.3
Control Register CR3 (0x03)
0
0
0
0
0
Access
R/W
126/161
DS11567 Rev 5
0
0
2
1
0
VSREG_EWTH_0
0
3
VSREG_EWTH_1
1
4
VSREG_EWTH_2
1
5
VSREG_EWTH_3
1
6
VSREG_EWTH_4
VS_UV_SD_EN
1
7
VSREG_EWTH_5
VS_OV_SD_EN
1
8
VSREG_EWTH_6
VSREG_UV_SD_EN
1
Reserved
9
VSREG_EWTH_7
19 18 17 16 15 14 13 12 11 10
VSREG_EWTH_8
20
VSREG_EWTH_9
21
VSREG_OV_SD_EN
Reset
22
VS_LOCK_EN
Bit name
23
VSREG_LOCK_EN
Table 78. Control Register CR3
0
0
0
0
0
0
0
0
0
0
L99DZ120
SPI Registers
Table 79. CR3 signals description
Bit
23
22
21
20
Name
Description
VSREG_LOCK_EN
VSREG lockout enable: Lockout of VSREG related outputs after VSREG overvoltage/
undervoltage shutdown
0: VSREG related Outputs are turned on automatically and status bits
(VSREG_UV, VSREG_OV) are cleared
1: VSREG related Outputs remain turned off until status bits (VSREG_UV,
VSREG_OV) are cleared (default)
Lockout is always disabled in standby modes in order to ensure supply of external
contacts and detect wake-up conditions
VS_LOCK_EN
VS lockout enable: Lockout of VS related outputs after VS over/undervoltage
shutdown
0: VS related Outputs are turned on automatically and status bits (VS_UV,
VS_OV) are cleared
1: VS related Outputs remain turned off until status bits (VS_UV, VS_OV) are
cleared (default)
Lockout is always disabled in standby modes in order to ensure supply of external
contacts and detect wake-up conditions
VSREG_OV_SD_EN
VSREG overvoltage shutdown enable: shutdown of VSREG related outputs in case
of VSREG overvoltage
0: no shutdown of VSREG related outputs in case of VSREG overvoltage
1: shutdown of VSREG related outputs in case of VSREG overvoltage (default)
VSREG_UV_SD_EN
VSREG undervoltage shutdown enable: shutdown of VSREG related outputs in
case of VSREG undervoltage
0: no shutdown of VSREG related outputs in case of VSREG undervoltage
1: shutdown of VSREG related outputs in case of VSREG undervoltage (default)
In case of V1 undervoltage due to VSREG_UV, the device enters Fail-Safe mode
and the outputs are turned off
VS_OV_SD_EN
VS overvoltage shutdown enable: shutdown of VS related outputs in case of VS
overvoltage
0: no shutdown of VS related outputs in case of VS overvoltage if charge pump
output voltage is still sufficient (until CPLOW threshold is reached)
1: shutdown of VS related outputs in case of VS overvoltage (default)
18
VS_UV_SD_EN
VS undervoltage shutdown enable: shutdown of VS related outputs in case of VS
undervoltage
0: no shutdown VS related of outputs in case of VS undervoltage
1: shutdown of VS related outputs in case of VS undervoltage (default)
In case of V1 undervoltage due to VS_UV, the device enters Fail-Safe mode and
the outputs are turned off
17:10
Reserved
19
Reserved
DS11567 Rev 5
127/161
160
SPI Registers
L99DZ120
Table 79. CR3 signals description (continued)
Bit
Name
9
VSREG_EW_TH_9
8
VSREG_EW_TH_8
7
VSREG_EW_TH_7
6
VSREG_EW_TH_6
5
VSREG_EW_TH_5
4
VSREG_EW_TH_4
3
VSREG_EW_TH_3
2
VSREG_EW_TH_2
1
VSREG_EW_TH_1
0
VSREG_EW_TH_0
7.4.4
Description
VSREG early warning threshold.
At VSREG < VSREG_EW_TH, an interrupt is generated at NINT and status bit
VSREG_EW in SR2 is set (in Active mode)
0000000000: 0 V (default) feature deactivated
...
1111111111: VAINVS
Control Register CR4 (0x04)
0
0
0
0
0
Access
0
0
0
0
0
0
0
0
0
4
0
0
3
2
0
0
1
0
OUT6_LS
0
5
OUT6_HS
0
6
Reserved
Reserved
7
OUT5_LS
8
OUT5_HS
9
Reserved
19 18 17 16 15 14 13 12 11 10
OUT4_LS
0
20
OUT4_HS
0
21
OUT1_LS
Bit name
Reset
22
Reserved
23
OUT1_HS
Table 80. Control Register CR4
0
0
R/W
Table 81. CR4 signals description
Bit
Name
23:22
Reserved
Reserved
OUT1_HS
OUT1 high-side Driver control
0: OUT1_HS is turned off (default)
1: OUT1_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side
drivers of the half-bridge OUT1 are switched on simultaneously.
20
OUT1_LS
OUT1 low-side Driver control
0: OUT1_LS is turned off (default)
1: OUT1_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side
drivers of the half-bridge OUT1 are switched on simultaneously.
19:10
Reserved
Reserved
21
128/161
Description
DS11567 Rev 5
L99DZ120
SPI Registers
Table 81. CR4 signals description (continued)
Bit
Name
Description
OUT4_HS
OUT4 high-side Driver control
0: OUT4_HS is turned off (default)
1: OUT4_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side
drivers of the half-bridge OUT4 are switched on simultaneously.
8
OUT4_LS
OUT4 low-side Driver control
0: OUT4_LS is turned off (default)
1: OUT4_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side
drivers of the half-bridge OUT4 are switched on simultaneously.
7:6
Reserved
Reserved
OUT5_HS
OUT5 high-side Driver control
0: OUT5_HS is turned off (default)
1: OUT5_HS is turned on
An internal cross-current protection prevents, that both the low- and high-side
drivers of the half-bridge OUT5 are switched on simultaneously.
4
OUT5_LS
OUT5 low-side Driver control
0: OUT5_LS is turned off (default)
1: OUT5_LS is turned on
An internal cross-current protection prevents, that both the low- and high-side
drivers of the half-bridge OUT5 are switched on simultaneously.
3:2
Reserved
Reserved
OUT6_HS
OUT6 high-side Driver control
0: OUT6_HS is turned off (default)
1: OUT6_HS is turned on
An internal cross-current protection prevents, that both the low-side and high-side
drivers of the half-bridge OUT6 are switched on simultaneously.
OUT6_LS
OUT6 low-side Driver control
0: OUT6_LS is turned off (default)
1: OUT6_LS is turned on
An internal cross-current protection prevents, that both the low-side and high-side
drivers of the half-bridge OUT6 are switched on simultaneously.
9
5
1
0
7.4.5
Control Register CR5 (0x05)
Access
0
0
0
0
0
0
0
0
0
0
0
4
Reserved
0
0
0
0
3
2
1
0
OUTHS_0
OUT8_0
0
5
OUTHS_1
OUT8_1
0
6
OUTHS_2
OUT8_2
0
7
OUTHS_3
OUT8_3
0
8
OUT10_0
OUT7_0
0
Reserved
9
OUT10_1
19 18 17 16 15 14 13 12 11 10
OUT10_2
20
OUT10_3
21
OUT7_1
Reset
22
OUT7_2
Bit name
23
OUT7_3
Table 82. Control Register CR5
0
0
0
0
R/W
DS11567 Rev 5
129/161
160
SPI Registers
L99DZ120
Table 83. CR5 signals description
Bit
Name
23
OUT7_3
22
OUT7_2
21
OUT7_1
20
OUT7_0
19
OUT8_3
18
OUT8_2
17
OUT8_1
16
OUT8_0
15:12
Reserved
11
OUT10_3
10
OUT10_2
9
OUT10_1
8
OUT10_0
7:4
Reserved
3
OUTHS_3
2
OUTHS_2
1
OUTHS_1
0
OUTHS_0
Description
OUT7 Configuration Bits: high-side Driver OUT7 Configuration
For OUT7 bits configuration see Table 84: OUTx Configuration bits
OUT8 Configuration Bits: high-side Driver OUT8 Configuration
For OUT8 bits configuration see Table 84: OUTx Configuration bits
—
OUT10 Configuration Bits: high-side Driver OUT10 Configuration
For OUT10 bits configuration see Table 84: OUTx Configuration bits
—
OUTHS Configuration Bits: high-side Driver OUTHS Configuration
For OUTHS bits configuration see Table 84: OUTx Configuration bits
Table 84. OUTx Configuration bits
130/161
OUTx_3
OUTx_2
OUTx_1
OUTx_0
Description
0
0
0
0
Off (default)
0
0
0
1
On
0
0
1
0
Timer1
0
0
1
1
Timer2
0
1
0
0
PWM1
0
1
0
1
PWM2
0
1
1
0
PWM3
0
1
1
1
PWM4
1
0
0
0
PWM5
1
0
0
1
PWM6
1
0
1
0
PWM7
1
0
1
1
PWM8
1
1
0
0
PWM9
DS11567 Rev 5
L99DZ120
SPI Registers
Table 84. OUTx Configuration bits (continued)
7.4.6
OUTx_3
OUTx_2
OUTx_1
OUTx_0
Description
1
1
0
1
PWM10
1
1
1
0
DIR1
1
1
1
1
DIR2
Control Register CR6 (0x06)
OUT13_3
OUT15_0
OUT12_0
0
OUT15_1
OUT12_1
1
OUT15_2
OUT12_2
2
OUT15_3
OUT12_3
3
OUT14_0
OUT11_0
4
OUT14_1
OUT11_1
5
OUT14_2
OUT11_2
6
OUT14_3
OUT11_3
7
OUT13_0
19 18 17 16 15 14 13 12 11 10
OUT9_0
8
OUT13_1
20
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
9
OUT13_2
21
OUT9_1
Reset
22
OUT9_2
Bit name
23
OUT9_3
Table 85. Control Register CR6
0
0
0
0
0
0
0
0
0
0
0
R/W
Table 86. CR6 signals description
Bit
Name
23
OUT9_3
22
OUT9_2
21
OUT9_1
20
OUT9_0
19
OUT11_3
18
OUT11_2
17
OUT11_1
16
OUT11_0
15
OUT12_3
14
OUT12_2
13
OUT12_1
12
OUT12_0
11
OUT13_3
10
OUT13_2
9
OUT13_1
8
OUT13_0
Description
OUT9 Configuration Bits: high-side Driver OUT9 Configuration
For OUT9 bits configuration see Table 84: OUTx Configuration bits
OUT11 Configuration Bits: high-side Driver OUT11 Configuration
For OUT11 bits configuration see Table 84: OUTx Configuration bits
OUT12 Configuration Bits: high-side Driver OUT12 Configuration
For OUT12 bits configuration see Table 84: OUTx Configuration bits
OUT13 Configuration Bits: high-side Driver OUT13 Configuration
For OUT13 bits configuration see Table 84: OUTx Configuration bits
DS11567 Rev 5
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160
SPI Registers
L99DZ120
Table 86. CR6 signals description (continued)
Bit
Name
7
OUT14_3
6
OUT14_2
5
OUT14_1
4
OUT14_0
3
OUT15_3
2
OUT15_2
1
OUT15_1
0
OUT15_0
7.4.7
Description
OUT14 Configuration Bits: high-side Driver OUT14 Configuration
For OUT14 bits configuration see Table 84: OUTx Configuration bits
OUT15 Configuration Bits: high-side Driver OUT15 Configuration
For OUT15 bits configuration see Table 84: OUTx Configuration bits
Control Register CR7 (0x07)
Access
0
0
0
0
1
0
CM_SEL_0
0
2
CM_SEL_1
0
3
CM_SEL_2
0
4
CM_SEL_3
0
5
Reserved
0
6
CM_EN
0
7
OUT5_OC0
0
Reserved
8
OUT5_OC1
OUTHS_OCR
0
9
OCR_FREQ
OUT8_OCR
0
OUT7_OCR
0
19 18 17 16 15 14 13 12 11 10
OUT6_OCR
0
20
OUT5_OCR
Reset
21
Reserved
Bit name
22
OUT1_OCR
23
OUT4_OCR
Table 87. Control Register CR7
0
0
0
1
0
0
0
0
0
R/W
Table 88. CR7 signals description
Bit
Name
23
OUT1_OCR
22:21
Reserved
20
OUT4_OCR
19
OUT5_OCR
18
OUT6_OCR
17
OUT7_OCR
16
OUT8_OCR
15
OUTHS_OCR
14:9
Reserved
132/161
Description
Overcurrent recovery for OUT1
0: overcurrent recovery is turned off (default)
1: overcurrent recovery is turned on
—
Overcurrent recovery for OUTx
0: overcurrent recovery is turned off (default)
1: overcurrent recovery is turned on
Overcurrent recovery for OUTHS
0: overcurrent recovery is turned off (default)
1: overcurrent recovery is turned on
—
DS11567 Rev 5
L99DZ120
SPI Registers
Table 88. CR7 signals description (continued)
Bit
Name
8
OCR_FREQ
7
OUT5_OC1
6
OUT5_OC0
5
CM_EN
4
Reserved
3
CM_SEL_3
2
CM_SEL_2
1
CM_SEL_1
0
CM_SEL_0
Description
Overcurrent recovery frequency
0: freq0 (default)
1: freq1
Overcurrent Threshold for OUT5
00: IOC5_3 overcurrent threshold 3 (default)
01: IOC5_1 overcurrent threshold 1
10: IOC5_2 overcurrent threshold 2
11: IOC5_3 overcurrent threshold 3
Current monitor:
0: off (3-state)
1: on (default)
—
Current Monitor Select Bits.
A current image of the selected binary coded output is multiplexed to the CM
output. If a corresponding output does not exist, the current monitor is deactivated.
0000: OUT1
0001: invalid configuration
0010: invalid configuration
0011: OUT4
0100: OUT5
0101: OUT6
0110: OUT7
0111: OUT8
1000: OUT9
1001: OUT10
1010: OUT11
1011: OUT12
1100: OUT13
1101: OUT14
1110: OUT15
1111: OUT_HS
DS11567 Rev 5
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160
SPI Registers
7.4.8
L99DZ120
Control Register CR8 (0x08)
OUT8_OCR_THX_EN
OUTHS_OCR_THX_EN
1
OUT7_OCR_THX_EN
1
19 18 17 16 15 14 13 12 11 10
OUT6_OCR_THX_EN
1
20
OUT5_OCR_THX_EN
Reset
21
Reserved
Bit name
22
OUT1_OCR_THX_EN
23
OUT4_OCR_THX_EN
Table 89. Control Register CR8
1
1
1
1
1
1
Access
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
Resrved
0
0
0
0
0
0
0
0
0
R/W
Table 90. CR8 signals description
Bit
Name
23
OUT1_OCR_THX_EN
22:21
Reserved
20
OUT4_OCR_THX_EN
19
OUT5_OCR_THX_EN
18
OUT6_OCR_THX_EN
17
OUT7_OCR_THX_EN
16
OUT8_OCR_THX_EN
15
OUTHS_OCR_THX_EN
14:0
Reserved
134/161
Description
Enable Overcurrent Recovery with Thermal Expiration for OUTx.
0: Overcurrent Recovery with Thermal Expiration is off
1: Overcurrent Recovery with Thermal Expiration is on (default)
The output is turned off after Thermal Expiration.
—
Enable Overcurrent Recovery with Thermal Expiration for OUTx.
0: Overcurrent Recovery with Thermal Expiration is off
1: Overcurrent Recovery with Thermal Expiration is on (default)
The output is turned off after Thermal Expiration.
Enable Overcurrent Recovery with Thermal Expiration for OUTHS.
0: Overcurrent Recovery with Thermal Expiration is off
1: Overcurrent Recovery with Thermal Expiration is on (default)
The output is turned off after Thermal Expiration.
—
DS11567 Rev 5
L99DZ120
SPI Registers
7.4.9
Control Register CR9 (0x09)
Access
OUT11_OC
OUT10_OC
OUT9_OC
0
OUT12_OC
1
OUT13_OC
2
OUT14_OC
0
3
OUT15_OC
0
4
OUTHS_OC
0
5
OUT9_OL
0
6
OUT10_OL
0
7
OUT11_OL
0
8
OUT12_OL
Reserved
9
OUT13_OL
19 18 17 16 15 14 13 12 11 10
OUT14_OL
0
20
OUT15_OL
0
21
OUTHS_OL
Reset
22
OUT8_RDSON
Bit name
23
OUT7_RDSON
Table 91. Control Register CR9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
Table 92. CR9 signals description
Bit
Name
Description
23
OUT7_RDSON
Select Rdson for OUT7
0: ron_low (default)
1: ron_high
22
OUT8_RDSON
Select Rdson for OUT8
0: ron_low (default)
1: ron_high
21:16
Reserved
15
OUTHS_OL
14
OUT15_OL
13
OUT14_OL
12
OUT13_OL
11
OUT12_OL
10
OUT11_OL
9
OUT10_OL
8
OUT9_OL
7
OUTHS_OC
6
OUT15_OC
5
OUT14_OC
4
OUT13_OC
3
OUT12_OC
2
OUT11_OC
1
OUT10_OC
0
OUT9_OC
—
Open-load Threshold for OUTx
0: IOLD1 ; high-current mode (default)
1: IOLD1; low-current mode
Overcurrent Threshold for OUTx
0: IOC; high-current mode (default)
1: IOC; low-current mode
DS11567 Rev 5
135/161
160
SPI Registers
7.4.10
L99DZ120
Control Register CR10 (0x0A)
SLEW_1
SLEW_0
0
SLEW_2
1
SLEW_3
0
2
SLEW_4
0
3
OL_H2L1
1
4
OL_H1L2
1
5
H_OLTH_HIGH
1
6
COPT_0
0
7
COPT_1
0
8
COPT_2
1
Reserved
9
COPT_3
1
19 18 17 16 15 14 13 12 11 10
SDS
1
20
SD
21
DIAG_0
Reset
22
DIAG_1
Bit name
23
DIAG_2
Table 93. Control Register CR10
0
0
1
1
1
1
0
0
0
0
0
0
0
0
Access
R/W
Table 94. CR10 signals description
Bit
Name
23
DIAG_2
22
DIAG_1
21
DIAG_0
20:14
Reserved
13
SD
12
SDS
11
COPT_3
10
COPT_2
9
COPT_1
8
COPT_0
7
H_OLTH_HIGH
136/161
Description
Drain-source monitoring threshold for external H-bridge
000: VSCd1_HB
001: VSCd2_HB
010: VSCd3_HB
011: VSCd4_HB
100: VSCd5_HB
101: VSCd6_HB
110: VSCd7_HB
111: VSCd7_HB (default)
—
Slow decay
Slow decay single
Cross current protection time
0000: not allowed
0001: tccp0001
0010: tccp0010
0011: tccp0011
0100: tccp0100
0101: tccp0101
0110: tccp0110
0111: tccp0111
1000: tccp1000
1001: tccp1001
1010: tccp1010
1011: tccp1011
1100: tccp1100
1101: tccp1101
1110: tccp1110
1111: tccp1111 (default)
H-bridge OL high threshold (5/6 * VS) select
DS11567 Rev 5
L99DZ120
SPI Registers
Table 94. CR10 signals description (continued)
Bit
Name
6
OL_H1L2
Test open-load condition between H1 and L2
5
OL_H2L1
Test open-load condition between H2 and L1
4
SLEW_4
3
SLEW_3
2
SLEW_2
1
SLEW_1
0
SLEW_0
7.4.11
Description
Binary coded slew rate of H-bridge (bit0 = LSB; bit4 = MSB)
00000: Control disabled (default)
11111: IGHxmax
Control Register CR11 (0x0B)
Table 95. Control Register CR11
23
22
21
20
19 18 17 16 15 14 13 12 11 10
Bit name
Reset
9
8
7
6
5
4
3
2
1
0
0
0
0
0
1
0
0
0
0
0
3
2
1
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
Access
0
0
0
R/W
Table 96. CR11 signals description
Bit
Name
23:0
Reserved
7.4.12
Description
—
Control Register CR12 (0x0C)
Access
PMW5_FREQ_0
PMW6_FREQ_1
PMW6_FREQ_0
PMW7_FREQ_1
PMW10_FREQ_0
PMW5_FREQ_1
4
PMW10_FREQ_1
PMW4_FREQ_0
5
PMW9_FREQ_0
PMW4_FREQ_1
6
PMW9_FREQ_1
PMW3_FREQ_0
7
PMW8_FREQ_0
19 18 17 16 15 14 13 12 11 10
PMW3_FREQ_1
8
PMW8_FREQ_1
20
PMW2_FREQ_0
9
PMW7_FREQ_0
21
PMW2_FREQ_1
Reset
22
PMW1_FREQ_0
Bit name
23
PMW1_FREQ_1
Table 97. Control Register CR12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
R/W
DS11567 Rev 5
137/161
160
SPI Registers
L99DZ120
Table 98. CR12 signals description
Bit
Name
23
PMW1_FREQ_1
22
PMW1_FREQ_0
21
PMW2_FREQ_1
20
PMW2_FREQ_0
19
PMW3_FREQ_1
18
PMW3_FREQ_0
17
PMW4_FREQ_1
16
PMW4_FREQ_0
15
PMW5_FREQ_1
14
PMW5_FREQ_0
13
PMW6_FREQ_1
12
PMW6_FREQ_0
11
PMW7_FREQ_1
10
PMW7_FREQ_0
9
PMW8_FREQ_1
8
PMW8_FREQ_0
138/161
Description
Frequency of PWM channel PWM1
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM2
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM3
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM4
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM5
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM6
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM7
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
Frequency of PWM channel PWM8
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
DS11567 Rev 5
L99DZ120
SPI Registers
Table 98. CR12 signals description (continued)
Bit
Name
7
PMW9_FREQ_1
6
PMW9_FREQ_0
5
PMW10_FREQ_1 Frequency of PWM channel PWM10
00: fPWMx(00) (default)
01: fPWMx(01)
PMW10_FREQ_0 10: fPWMx(10)
11: fPWMx(11)
4
3:0
Description
Reserved
7.4.13
Frequency of PWM channel PWM9
00: fPWMx(00) (default)
01: fPWMx(01)
10: fPWMx(10)
11: fPWMx(11)
—
Control Register CR13 (0x0D) to CR17 (0x11)
Access
0
0
0
PWMy_DC_0
0
1
PWMy_DC_1
0
2
PWMy_DC_2
0
3
PWMy_DC_3
0
4
PWMy_DC_4
PWMx_DC_0
0
5
PWMy_DC_5
PWMx_DC_1
0
6
PWMy_DC_6
PWMx_DC_2
0
7
PWMy_DC_7
PWMx_DC_3
0
8
PWMy_DC_8
PWMx_DC_4
0
9
PWMy_DC_9
PWMx_DC_5
0
Reserved
19 18 17 16 15 14 13 12 11 10
PWMx_DC_6
0
20
PWMx_DC_7
0
21
PWMx_DC_8
Bit name
Reset
22
Reserved
23
PWMx_DC_9
Table 99. Control Register CR13 to CR17
0
0
0
0
0
0
0
0
0
0
R/W
Where:
x = 1 + (z * 2), z = 0 to 4
y = 2 + (z * 2), z = 0 to 4
Table 100. CR13 to CR17 signals description
Bit
Name
23:22
Reserved
Description
—
DS11567 Rev 5
139/161
160
SPI Registers
L99DZ120
Table 100. CR13 to CR17 signals description (continued)
Bit
Name
21
PWMx_DC_9
20
PWMx_DC_8
19
PWMx_DC_7
18
PWMx_DC_6
17
PWMx_DC_5
16
PWMx_DC_4
15
PWMx_DC_3
14
PWMx_DC_2
13
PWMx_DC_1
12
PWMx_DC_0
11:10
Reserved
9
PWMy_DC_9
8
PWMy_DC_8
7
PWMy_DC_7
6
PWMy_DC_6
5
PWMy_DC_5
4
PWMy_DC_4
3
PWMy_DC_3
2
PWMy_DC_2
1
PWMy_DC_1
0
PWMy_DC_0
7.4.14
Description
Binary coded on-dutycycle of PWM channel PWMx (bit12 = LSB; bit21 = MSB)
00 0000 0000: duty cycle 0% (default)
xx xxxx xxxx: duty cycle 100%/1023 x register value
11 1111 1111. duty cycle 100%
—
Binary coded on-dutycycle of PWM channel PWMy (bit0 = LSB; bit9 = MSB)
00 0000 0000: duty cycle 0% (default)
xx xxxx xxxx: duty cycle 100%/1023 x register value
11 1111 1111. Duty cycle 100%
Binary coded on-dutycycle of PWM channel PWMy
Control Register CR18 (0x12) to CR22 (0x16)
21
20
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OUTx_VLED_9
OUTx_VLED_8
OUTx_VLED_7
OUTx_VLED_6
OUTx_VLED_5
OUTx_VLED_4
OUTx_VLED_3
OUTx_VLED_2
OUTx_VLED_1
OUTx_VLED_0
Reserved
OUTy_AUTOCOMP_EN
OUTy_VLED_9
OUTy_VLED_8
OUTy_VLED_7
OUTy_VLED_6
OUTy_VLED_5
OUTy_VLED_4
OUTy_VLED_3
OUTy_VLED_2
OUTy_VLED_1
OUTy_VLED_0
Reset
22
OUTx_AUTOCOMP_EN
Bit name
23
Reserved
Table 101. Control Register CR18
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
R/W
140/161
DS11567 Rev 5
L99DZ120
SPI Registers
Where:
x = 7 + (z * 2), z = 0 to 4
y = 8 + (z * 2), z = 0 to 4
Table 102. CR18 to CR22 signals description
Bit
Name
23
Reserved
22
OUTx_AUTOCOMP_EN
21
OUTx_VLED_9
20
OUTx_VLED_8
19
OUTx_VLED_7
18
OUTx_VLED_6
17
OUTx_VLED_5
16
OUTx_VLED_4
15
OUTx_VLED_3
14
OUTx_VLED_2
13
OUTx_VLED_1
12
OUTx_VLED_0
11
Reserved
10
OUTy_AUTOCOMP_EN
9
OUTy_VLED_9
8
OUTy_VLED_8
7
OUTy_VLED_7
6
OUTy_VLED_6
5
OUTy_VLED_5
4
OUTy_VLED_4
3
OUTy_VLED_3
2
OUTy_VLED_2
1
OUTy_VLED_1
0
OUTy_VLED_0
Description
—
Setting this bit to ‘1’ enables the automatic VS compensation for OUTx
Binary coded nominal LED voltage of OUTx (bit12 = LSB; bit21 = MSB)
00 0000 0000: VLED = 0 V (default)
xx xxxx xxxx: VLED = VAINVS /1023 x register value
01 1101 0000: VLED = VAINVS
VLED is clamped at 10 V (0x1D0h)
—
Setting this bit to ‘1’ enables the automatic VS compensation for OUTy
Binary coded nominal LED voltage of OUTy (bit0 = LSB; bit9 = MSB)
00 0000 0000: VLED = 0 V (default)
xx xxxx xxxx: VLED = VAINVS /1023 x register value
01 1101 0000: VLED = VAINVS
VLED is clamped at 10 V (0x1D0h)
DS11567 Rev 5
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160
SPI Registers
7.4.15
L99DZ120
Control Register CR34 (0x22)
21
20
19 18 17 16 15 14 13 12 11 10
Bit name
Reset
9
8
7
6
5
4
3
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
Access
0
0
0
2
1
0
WD_EN
22
ICMP
23
CP_OFF
Table 103. Control Register CR34
0
0
1
R/W
Table 104. CR34 signals description
Bit
Name
23:3
Reserved
—
CP_OFF
Charge pump control
0: Enabled; charge pump on in active mode (default)
1: Disabled; charge pump off in active mode
setting CP_OFF = 1 is only possible when CP_OFF_EN = 1
2
1
ICMP
0
WD_EN
7.4.16
Description
V1 load current supervision
0: Enabled; Watchdog is disabled in V1 Standby when Iv1< ICMP (default)
1: Disabled; watchdog is disabled upon transition into V1_standby mode
setting ICMP = 1 is only possible when ICMP_config_en = 1
Watchdog Enable
0: Watchdog disabled
1: Watchdog enabled (default)
Configuration Register (0x3F)
MASK_OL_LS1
MASK_TW
Reserved
MASK_OL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
1
0
0
0
TRIG
MASK_OL_HS1
0
3
Reserved
WD_CONFIG_EN
FS_FORCED
ICMP_CONFIG_EN
4
CP_DITH_DIS
DM
5
CP_LOW_CONFIG
Reserved
0
DS11567 Rev 5
6
CP_OFF_EN
TSD_CONFIG
1
142/161
7
MASK_GW
19 18 17 16 15 14 13 12 11 10
R/W
8
MASK_PLE
20
Access
9
MASK_SPIE
21
LIN_HS_EN
Reset
22
LIN_WU_CONFIG
Bit name
23
WU_CONFIG
Table 105. Configuration Register
0
1
L99DZ120
SPI Registers
Table 106. CR signals description
Bit
23
Name
WU_CONFIG
22
LIN_WU_CONFIG
21
LIN_HS_EN
20
TSD_CONFIG
19
Reserved
18
17
16
15
14
13
DM
ICMP_CONFIG_EN
WD_CONFIG_EN
Description
Configuration of input pin WU
Input configured as wake-up input
0: WU configured as wake-up input
1: WU configured for input voltage measurement (default)
Configuration of LIN wake-up behaviour
0: wake up at recessive - dominant - recessive with tdom > tdom_LIN (default)
(according to LIN 2.2a and Hardware Requirements for Transceivers version
1.3)
1: wake up at recessive - dominant transition
Configuration of LIN transceiver bit rate
0: LIN transceiver in normal communication mode (20kbit/s) (default)
1: LIN transceiver in high speed mode for fast Flashing (115kbit/s)
Configuration of thermal shutdown behaviour
0: in case of TSD1 all power stages are switched off (default)
1: selective shut down of power stage cluster
—
H-bridge configuration
0: single motor mode (default)
1: reserved
ICMP configuration Enable
0: writing ICMP = 1 is blocked (writing ICMP=0 is possible); (default)
1: writing ICMP = 1 is possible with next SPI command
bit is automatically reset to 0 after next SPI command
Watchdog configuration Enable
0: writing to WD Configuration (CR2 [0:1] is blocked (default)
1: writing to WD Configuration Bits is possible with next SPI command
bit is automatically reset to 0 after next SPI command
MASK_OL_HS1
Mask Open-load HS1
0: Open-load condition at HS1 is not masked (default)
1: Open-load condition at HS1 is masked
i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
MASK_OL_LS1
Mask Open-load LS1
0: Open-load condition at LS1 is not masked (default)
1: Open-load condition at LS1 is masked
i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
MASK_TW
Mask Thermal Warning
0: Thermal warning is not masked (default)
1: Thermal warning is masked
i.e. it is reported as a Global Warning (GSB bit 1) but not as a Global Error
(GSB bit 7)
DS11567 Rev 5
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160
SPI Registers
L99DZ120
Table 106. CR signals description (continued)
Bit
Name
12
Reserved
—
MASK_OL
Mask open-load
0: Open-load condition at all outputs are not masked (default)
1: Open-load condition at all outputs are masked
i.e. it is reported as a Functional Error (GSB bit 3) but not as a Global Error
(GSB bit 7)
11
10
9
8
7
6
Description
MASK_SPIE
Mask SPI error
0: SPI errors are not masked (default)
1: SPI errors are masked
i.e. reported as am SPI Error (GSB bit 5) but not as a Global Error (GSB bit 7)
MASK_PLE
Mask physical layer error
0: Physical Layer Errors are not masked (default)
1: Physical Layer Errors are masked
i.e. reported as a Physical Layer Error (GSB bit 4) but not as a Global Error
(GSB bit 7)
MASK_GW
Mask global warning
0: Global Warning conditions are not masked (default)
1: Global Warning conditions are masked
i.e. reported as a Global Warning (GSB bit 1) but not as a Global Error (GSB
bit 7)
CP_OFF_EN
Charge pump control enable
0: writing CP_OFF = 1 is blocked (writing CP OFF = 0 is possible); (default)
1: writing CP_OFF = 1 is possible with next SPI command
Bit is automatically reset to 0 after next SPI command
CP_LOW_CONFIG
Charge pump low configuration
0: CP_low (SR 2, bit 9) is latched and outputs are off until R&C; (default)
1: CP_low (SR 2, bit 9) is a ‘live’ bit; outputs are re-activated automatically
upon recovery of the charge pump output voltage
CP_DITH_DIS
Charge pump clock dithering
0: CP clock dithering is enabled; (default)
1: CP clock dithering is disabled
4
FS_FORCED
Force LSx_FSO ON
LSx_FSO low-side outputs are forced ON (to allow diagnosis of the fail-safe
path)
0: LSx_FSO outputs are controlled by the Fail-safe logic (default)
1: LSx_FSO outputs are forced ON and the device enters Fail-Safe mode; no
NReset is generated
3:1
Reserved
0
TRIG
5
144/161
—
Watchdog Trigger bit
DS11567 Rev 5
L99DZ120
SPI Registers
7.5
Status Registers
7.5.1
Status Register SR1 (0x31)
7
6
5
4
3
2
WDFAIL_CNT_0
DEVICE_STATE_1
DEVICE_STATE_0
TSD2
TSD1
FORCED_SLEEP_TSD2/V1SC
FORCED_SLEEP_WD
R
1
0
VPOR
8
WDFAIL
9
WDFAIL_CNT_1
Reserved
R/C
WDFAIL_CNT_2
WU_WAKE
R
WDFAIL_CNT_3
Reserved
R/C
V1_RESTART_0
WU_STATE
Access
V1_RESTART_1
Bit name
V1_RESTART_2
19 18 17 16 15 14 13 12 11 10
V1UV
20
DEBUG_ACTIVE
21
WAKE_TIMER
22
WAKE_LIN
23
Reserved
Table 107. Status Register SR1 (0x31)
R/C
Table 108. SR1 signals description
Bit
Name
23
Reserved
22
WU_STATE
21
Reserved
20
WU_WAKE
19
Reserved
Description
—
State of WU input
0: input level is low
1: input level is high
The bit shows the momentary status of WU and cannot be cleared (“Live bit”)
Note: The status is only valid if WU is configured as wake-up input in
Configuration Register (0x3F). Otherwise this bit remains at his previous logic
state.
—
Wake-up by WU: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
—
18
WAKE_LIN
Wake-up by LIN: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
17
WAKE_TIMER
Wake-up by Timer: shows wake up source
1: wake-up
Bits are latched until a “Read and clear” command
16
DEBUG_ACTIVE
Debug Mode Active: indicates Device is in Debug mode
1: Debug mode
The bit shows the momentary status and cannot be cleared (“Live bit”)
DS11567 Rev 5
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160
SPI Registers
L99DZ120
Table 108. SR1 signals description (continued)
Bit
Name
Description
Indicates undervoltage condition at voltage regulator V1 (V1 < VRTx)
1: undervoltage
Bit is latched until a “Read and clear” command
15
V1UV
14
V1_RESTART_2
13
V1_RESTART_1
12
V1_RESTART_0
11
WDFAIL_CNT_3
10
WDFAIL_CNT_2
9
WDFAIL_CNT_1
8
WDFAIL CNT_0
7
DEVICE_STATE_1
6
DEVICE_STATE_0
5
TSD2
Thermal Shutdown 2 was reached
Bit is latched until a "Read and clear" command
4
TSD1
Thermal Shutdown 1 was reached (Logical Or combination of all TSD1_CLx;
see status register SR6).
This bit cannot be cleared directly. It is reset if the corresponding TSD1_CLx
bits in SR6 are cleared.
3
FORCED_SLEEP_
TSD2/V1SC
2
FORCED_SLEEP_WD
1
WDFAIL
Watchdog failure
Bit is latched until a "Read and clear" command
0
VPOR
VS Power-on Reset threshold (VPOR) reached
Bit is latched until a "Read and clear" command
146/161
Indicates the number of TSD2 events which caused a restart of voltage
regulator V1
Bits cannot be cleared; counter will be cleared automatically if no additional
TSD2 event occurs within 1 minute.
Indicates number of subsequent watchdog failures.
Bits cannot be cleared; will be cleared with a valid watchdog trigger
State from which the device woke up
00: Active Mode after Read&Clear command or after Flash Mode state
01: Active mode after wake-up from V1_standby mode (before Read&Clear
command)
10: Active Mode after Power-on or after wake-up from Vbat_standby Mode
(before Read&Clear command)
11: Flash mode (LIN Flash mode)
Bit is latched until a “Read and clear” command
After a “read and clear access”, the device state will be updated
Device entered Forced Vbat_standby mode due to:
– Thermal shutdown or
– Short circuit on V1 during startup
Bit is latched until a "Read and clear" command
Device entered Forced Vbat_standby mode due to multiple watchdog failures
Bit is latched until a "Read and clear" command
DS11567 Rev 5
L99DZ120
7.5.2
SPI Registers
Status Register SR2 (0x32)
6
5
4
3
2
SPI_SCK_CNT
CP_LOW
TW
V2SC
V2FAIL
V1FAIL
VSREG_EW
VSREG_OV
VSREG_UV
Reserved
Access
R/C
R
1
0
VS_UV
7
VS_OV
8
SPI_INV_CMD
9
DSMON_LS1
19 18 17 16 15 14 13 12 11 10
DSMON_LS2
LIN_PERM_REC
20
DSMON_HS1
21
DSMON_HS2
22
LIN_TXD_DOM
Bit name
23
LIN_PERM_DOM
Table 109. Status Register SR2 (0x32)
R/C
Table 110. SR2 signals description
Bit
Name
23
LIN_PERM_DOM
Description
LIN bus signal is dominant for t > tdom(bus)
Bit is latched until a “Read and clear” command
22
LIN_TXD_DOM
TxDL pin is dominant for t > tdom(TXDL)
The LIN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
21
LIN_PERM_REC
LIN bus signal does not follow TxDL within tLIN
The LIN transmitter is disabled until the bit is cleared
Bit is latched until a “Read and clear” command
20:16
Reserved
15
DSMON_HS2
14
DSMON_HS1
13
DSMON_LS2
12
DSMON_LS1
—
Drain-Source Monitoring
‘1’ indicates a short-circuit or open-load condition was detected
Bit is latched until a “Read and clear” command
11
SPI_INV_CMD
Invalid SPI command
‘1’ indicates one of the following conditions was detected:
– access to undefined address
– Write operation to Status Register
– DI stuck at '0' or '1'
– CSN timeout
– Parity failure
– invalid or undefined setting
The SPI frame is ignored
Bit is latched until a “Read and clear” command
10
SPI_SCK_CNT
SPI clock counter
‘1’ indicates an SPI frame with wrong number of CLK cycles was detected
Bit is latched until a valid SPI frame
9
CP_LOW
Charge pump voltage low
‘1’ indicates that the charge pump voltage is too low
Bit is latched until a “Read and clear” command
DS11567 Rev 5
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160
SPI Registers
L99DZ120
Table 110. SR2 signals description (continued)
Bit
8
7
6
5
Name
TW
V2SC
Description
Thermal warning
‘1’ indicates the temperature has reached the thermal warning threshold (logical
OR combination of bits TW_CLx in SR6)
Bit is latched until a “Read and clear” command
V2 short circuit detection
‘1’ indicates a short circuit to GND condition of V2 at turn-on of the regulator
(V2 < V2_fail for t > tv2_short)
Bit is latched until a “Read and clear” command
V2FAIL
V2 failure detection
‘1’ indicates a V2 fail event occurred since last readout
(V2 < V2_fail for t > tv2_fail)
Bit is latched until a “Read and clear” command
V1FAIL
V1 failure detection
‘1’ indicates a V1 fail event occurred since last readout
(V1 < V1_fail for t > tv1_fail)
Bit is latched until a “Read and clear” command
4
VSREG_EW
VSREG early warning
‘1’ indicates the voltage at VSREG has reached the early warning threshold
(configured in CR3)
In Active mode, an interrupt pulse is generated at NINT
Bit is latched until a “Read and clear” command.
Bit needs a "Read and clear" command after wake-up from standby modes
3
VSREG_OV
VSREG overvoltage
‘1’ indicates the voltage at VSREG has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
2
VSREG_UV
VSREG undervoltage
‘1’ indicates the voltage at VSREG has reached the undervoltage threshold
Bit is latched until a “Read and clear” command
1
VS_OV
VS overvoltage
‘1’ indicates the voltage at VS has reached the overvoltage threshold
Bit is latched until a “Read and clear” command
0
VS_UV
VS undervoltage
‘1’ indicates the voltage at VS has reached the undervoltage threshold
Bit is latched until a “Read and clear” command
148/161
DS11567 Rev 5
L99DZ120
7.5.3
SPI Registers
Status Register SR3 (0x33)
Access
7
6
5
4
3
2
OUT10_OC
OUT11_OC
OUT12_OC
OUT13_OC
OUT14_OC
OUT15_OC
OUTHS_OC_TH_EX
1
0
LS1FSO_OC
8
LS2FSO_OC
9
OUT9_OC
OUT8_OC_TH_EX
OUT7_OC_TH_EX
OUT6_LS_OC_TH_EX
OUT6_HS_OC_TH_EX
Reserved
OUT5_LS_OC_TH_EX
19 18 17 16 15 14 13 12 11 10
OUT5_HS_OC_TH_EX
20
OUT4_LS_OC_TH_EX
21
OUT4_HS_OC_TH_EX
22
OUT1_LS_OC_TH_EX
Bit name
23
OUT1_HS_OC_TH_EX
Table 111. Status Register SR3 (0x33)
R/C
Table 112. SR3 signals description
Bit
23
22
21:18
17
16
15
14
13
12
11
10
Name
Description
OUT1_HS_OC_TH_EX Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):
Bit is set upon overcurrent condition and output is turned off.
If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):
OUT1_LS_OC_TH_EX In case of overcurrent condition this bit is not set. The output goes into
Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'
In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):
Bit is set after thermal expiration and output is turned off
Bit is latched until a “Read and clear” command
Reserved
—
OUT4_HS_OC_TH_EX Overcurrent shutdown
OUT4_LS_OC_TH_EX ‘1’ indicates the output was shut down due to overcurrent condition.
If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):
OUT5_HS_OC_TH_EX
Bit is set upon overcurrent condition and output is turned off.
OUT5_LS_OC_TH_EX If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):
OUT6_HS_OC_TH_EX In case of overcurrent condition this bit is not set. The output goes into
Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'
OUT6_LS_OC_TH_EX
In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):
OUT7_OC_TH_EX
Bit is set after thermal expiration and output is turned off
Bit is latched until a “Read and clear” command
OUT8_OC_TH_EX
DS11567 Rev 5
149/161
160
SPI Registers
L99DZ120
Table 112. SR3 signals description (continued)
Bit
Name
9
OUT9_OC
8
OUT10_OC
7
OUT11_OC
6
OUT12_OC
5
OUT13_OC
4
OUT14_OC
3
OUT15_OC
Description
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
Bit is latched until a “Read and clear” command
2
OUTHS_OC_TH_EX
1
LS2FSO_OC
0
LS1FSO_OC
7.5.4
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
If Overcurrent Recovery is disabled (CR7: OUTx_OCR = 0):
Bit is set upon overcurrent condition and output is turned off.
If Overcurrent Recovery is enabled (CR7: OUTx_OCR = 1):
In case of overcurrent condition this bit is not set. The output goes into
Overcurrent Recovery mode and OUTx_OCR_alert in SR4 is set to '1'
In case of Thermal Expiration enabled (CR8: OUTx_OCR_THx_en = 1):
Bit is set after thermal expiration and output is turned off
Bit is latched until a “Read and clear” command
Overcurrent shutdown
‘1’ indicates the output was shut down due to overcurrent condition.
Bit is latched until a “Read and clear” command
Status Register SR4 (0x34)
150/161
DS11567 Rev 5
OUT8_OCR_ALERT
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
R
OUT7_OCR_ALERT
OUT6_LS_OCR_ALERT
OUT6_HS_OCR_ALERT
OUT5_LS_OCR_ALERT
Reserved
OUT5_HS_OCR_ALERT
19 18 17 16 15 14 13 12 11 10
OUT4_LS_OCR_ALERT
20
OUT4_HS_OCR_ALERT
21
OUTHS_OCR_ALERT
Access
22
OUT1_LS_OCR_ALERT
Bit name
23
OUT1_HS_OCR_ALERT
Table 113. Status Register SR4 (0x34)
R/C
R
R/C
L99DZ120
SPI Registers
Table 114. SR4 signals description
Bit
Name
Description
23
OUT1_HS_OCR_ALERT
22
OUT1_LS_OCR_ALERT
21:18
Reserved
17
OUT4_HS_OCR_ALERT
16
OUT4_LS_OCR_ALERT
15
OUT5_HS_OCR_ALERT
14
OUT5_LS_OCR_ALERT
13
OUT6_HS_OCR_ALERT
12
OUT6_LS_OCR_ALERT
11
OUT7_OCR_ALERT
10
OUT8_OCR_ALERT
9:3
Reserved
—
Autorecovery Alert
‘1’ indicates that the output reached the overcurrent threshold and is in
autorecovery mode
Bit is not latched and cannot be cleared.
—
2
OUTHS_OCR_ALERT
1:0
Reserved
7.5.5
Autorecovery Alert
‘1’ indicates that the output reached the overcurrent threshold and is in
autorecovery mode
Bit is not latched and cannot be cleared.
Autorecovery Alert
‘1’ indicates that the output reached the overcurrent threshold and is in
autorecovery mode
Bit is not latched and cannot be cleared.
—
Status Register SR5 (0x35)
Access
8
7
6
5
4
3
2
OUT10_OL
OUT11_OL
OUT12_OL
OUT13_OL
OUT14_OL
OUT15_OL
OUTHS_OL
1
0
Reserved
9
OUT9_OL
OUT8_OL
OUT7_OL
OUT6_LS_OL
OUT6_HS_OL
Reserved
OUT5_LS_OL
19 18 17 16 15 14 13 12 11 10
OUT5_HS_OL
20
OUT4_LS_OL
21
OUT4_HS_OL
22
OUT1_LS_OL
Bit name
23
OUT1_HS_OL
Table 115. Status Register SR5 (0x35)
R/C
Table 116. SR5 signals description
Bit
Name
23
OUT1_HS_OL
22
OUT1_LS_OL
21:18
Reserved
Description
Open-load
‘1’ indicates an open-load condition was detected at the output
Bit is latched until a “Read and clear” command
—
DS11567 Rev 5
151/161
160
SPI Registers
L99DZ120
Table 116. SR5 signals description (continued)
Bit
Name
17
OUT4_HS_OL
16
OUT4_LS_OL
15
OUT5_HS_OL
14
OUT5_LS_OL
13
OUT6_HS_OL
12
OUT6_LS_OL
11
OUT7_OL
10
OUT8_OL
9
OUT9_OL
8
OUT10_OL
7
OUT11_OL
6
OUT12_OL
5
OUT13_OL
4
OUT14_OL
3
OUT15_OL
2
OUTHS_OL
1:0
Reserved
7.5.6
Description
Open-load
‘1’ indicates an open-load condition was detected at the output
Bit is latched until a “Read and clear” command
—
Status Register SR6 (0x36)
Access
R
Table 118. SR6 signals description
Bit
23
22
152/161
Name
Description
WD_TIMER_STATE_1 Watchdog timer status
00: 0 - 33%
WD_TIMER_STATE_0 01: 33 - 66%
11: 66 - 100%
DS11567 Rev 5
5
4
3
2
1
0
TSD1_CL4
TSD1_CL3
TSD1_CL2
TSD1_CL1
6
TSD1_CL5
TW_CL1
R/C
7
TSD1_CL6
8
Reserved
9
TW_CL2
Reserved
TW_CL3
19 18 17 16 15 14 13 12 11 10
TW_CL4
20
TW_CL5
21
TW_CL6
22
WD_TIMER_STATE_0
Bit name
23
WD_TIMER_STATE_1
Table 117. Status Register SR6 (0x36)
L99DZ120
SPI Registers
Table 118. SR6 signals description (continued)
Bit
Name
21:14
Reserved
13
TW_CL6
12
TW_CL5
11
TW_CL4
10
TW_CL3
9
TW_CL2
8
TW_CL1
7:6
Reserved
5
TSD1_CL6
4
TSD1_CL5
3
TSD1_CL4
2
TSD1_CL3
1
TSD1_CL2
0
TSD1_CL1
7.5.7
Description
—
Thermal warning for Cluster x
‘1’ indicates Cluster x has reached the thermal warning threshold
Bit is latched until a “Read and clear” command
—
Thermal shutdown of Cluster x
‘1’ indicates Cluster x has reached the thermal shutdown threshold (TSD1) and
the output cluster was shut down
Bit is latched until a “Read and clear” command
Status Register SR7 (0x37) to SR9 (0x39)
R
TEMP_CLy_8
TEMP_CLy_7
TEMP_CLy_6
TEMP_CLy_5
R/C
4
3
2
1
0
TEMP_CLy_0
5
TEMP_CLy_1
6
TEMP_CLy_2
7
TEMP_CLy_3
8
TEMP_CLy_4
9
TEMP_CLy_9
Reserved
TEMP_CLx_0
TEMP_CLx_1
TEMP_CLx_2
TEMP_CLx_3
TEMP_CLx_4
TEMP_CLx_5
R/C
19 18 17 16 15 14 13 12 11 10
TEMP_CLx_6
Access
20
TEMP_CLx_7
Bit name
21
TEMP_CLx_8
22
Reserved
23
TEMP_CLx_9
Table 119. Status Register SR7 (0x37) to SR9 (0x39)
R
Where:
x = 2 + (z * 2), z = 0 to 2
y = 1 + (z * 2), z = 0 to 2
Table 120. SR7 to SR9 signals description
Bit
Name
23:22
Reserved
Description
—
DS11567 Rev 5
153/161
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SPI Registers
L99DZ120
Table 120. SR7 to SR9 signals description (continued)
Bit
Name
21
TEMP_CLx_9
20
TEMP_CLx_8
19
TEMP_CLx_7
18
TEMP_CLx_6
17
TEMP_CLx_5
16
TEMP_CLx_4
15
TEMP_CLx_3
14
TEMP_CLx_2
13
TEMP_CLx_1
12
TEMP_CLx_0
11:10
Reserved
9
TEMP_CLy_9
8
TEMP_CLy_8
7
TEMP_CLy_7
6
TEMP_CLy_6
5
TEMP_CLy_5
4
TEMP_CLy_4
3
TEMP_CLy_3
2
TEMP_CLy_2
1
TEMP_CLy_1
0
TEMP_CLy_0
7.5.8
Description
Temperature Cluster x: Binary coded voltage of temperature diode for cluster x
(bit12 = LSB; bit21 = MSB) (see Section 4.31: Thermal clusters)
Bits cannot be cleared.
—
Temperature Cluster y: binary coded voltage of temperature diode for cluster y
(bit0 = LSB; bit9 = MSB) (see Section 4.31: Thermal clusters)
Bits cannot be cleared.
Status Register SR10 (0x3A)
9
VSREG_0
VSREG_1
VSREG_2
VSREG_3
VSREG_4
VSREG_5
R/C
19 18 17 16 15 14 13 12 11 10
VSREG_6
Access
20
VSREG_7
Bit name
21
VSREG_8
22
Reserved
23
VSREG_9
Table 121. Status Register SR10 (0x3A)
Name
23:22
Reserved
154/161
7
6
5
Reserved
R
R/C
Table 122. SR10 signals description
Bit
8
Description
—
DS11567 Rev 5
4
3
2
1
0
L99DZ120
SPI Registers
Table 122. SR10 signals description (continued)
Bit
Name
21
VSREG_9
20
VSREG_8
19
VSREG_7
18
VSREG_6
17
VSREG_5
16
VSREG_4
15
VSREG_3
14
VSREG_2
13
VSREG_1
12
VSREG_0
11:0
Reserved
7.5.9
Description
Binary coded voltage at VSREG pin (bit12 = LSB; bit21 = MSB)
00 0000 0000: 0V
xx xxxx xxxx: VAINVS/1023 x register value
11 1111 1111: VAINVS
Bits cannot be cleared.
—
Status Register SR11 (0x3B)
R
VWU_8
VWU_7
VWU_6
VWU_5
R/C
4
3
2
1
0
VWU_0
5
VWU_1
6
VWU_2
7
VWU_3
8
VWU_4
9
VWU_9
Reserved
VS_0
VS_1
VS_2
VS_3
VS_4
VS_5
R/C
19 18 17 16 15 14 13 12 11 10
VS_6
Access
20
VS_7
Bit name
21
VS_8
22
Reserved
23
VS_9
Table 123. Status Register SR11 (0x3B)
R
Table 124. SR11 signals description
Bit
Name
23:22
Reserved
21
VS_9
20
VS_8
19
VS_7
18
VS_6
17
VS_5
16
VS_4
15
VS_3
14
VS_2
13
VS_1
12
VS_0
11:10
Reserved
Description
—
Binary coded voltage at VS pin (bit12 = LSB; bit21 = MSB)
00 0000 0000: 0V
xx xxxx xxxx: VAINVS/1023 x register value
11 1111 1111: VAINVS
Bits cannot be cleared.
—
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Table 124. SR11 signals description (continued)
Bit
Name
9
VWU_9
8
VWU_8
7
VWU_7
6
VWU_6
5
VWU_5
4
VWU_4
3
VWU_3
2
VWU_2
1
VWU_1
0
VWU_0
156/161
Description
Binary coded voltage at WU pin (bit0 = LSB; bit9 = MSB)
00 0000 0000: 0V
xx xxxx xxxx: VAINVS/1023 x register value
11 1111 1111: VAINVS
Bits cannot be cleared.
DS11567 Rev 5
L99DZ120
8
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
8.1
LQFP-64 package information
Figure 57. LQFP-64 package dimension
("1($'5
Table 125. LQFP-64 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
Θ
0º
3.5°
6°
Θ1
0º
9°
12°
Θ2
11º
12°
13°
Θ3
11º
12°
13°
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Package information
L99DZ120
Table 125. LQFP-64 mechanical data (continued)
Millimeters
Symbol
Min.
Typ.
A
1.60
A1
0.05
A2
1.35
0.15
1.40
b
0.17
c
0.09
c1
0.09
0.20
0.23
0.20
0.127
D
12.00 BSC
D1
10.00 BSC
D2
0.16
6.85
5.7
e
0.50 BSC
E
12.00 BSC
E1
10.00 BSC
E2
4.79
E3
3.3
L
0.45
0.60
L1
1.00
N
64
R1
0.08
R2
0.08
S
0.20
aaa
0.20
bbb
0.20
ccc
0.08
ddd
0.08
DS11567 Rev 5
0.75
0.20
Tolerance of form and position
158/161
1.45
0.27
b1
D3
Max.
L99DZ120
Package information
Figure 58. LQFP-64 footprint
("1($'5
8.2
LQFP-64 marking information
Figure 59. LQFP-64 marking information
.BSLJOHBSFB
.BSLJOHBSFB
PS
4QFDJBMGVODUJPOEJHJUT
&4&OHJOFFSJOHTBNQMF
CMBOL $PNNFSDJBMTBNQMF
-2'15017*&8
OPUJOTDBMF
("%(."(
Parts marked as ES are not yet qualified and therefore not approved for use in production.
ST is not responsible for any consequences resulting from such use. In no event will ST be
liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted to run a qualification activity prior to any decision to use
these engineering samples.
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Revision history
9
L99DZ120
Revision history
Table 126. Document revision history
160/161
Date
Revision
Changes
27-Apr-2016
1
Initial release.
11-May-2016
2
Updated Section 3.3.1: LQFP64 thermal data
Updated Table 20
Updated Table 22
Updated Table 40
Updated Figure 59
Updated Section 4.14: Auto-recovery alert and thermal
expiration
Updated Section 4.22: Programmable soft-start function
to drive loads with higher inrush current
Updated Figure 43
Updated Table 114
12-Sep-2016
3
Updated Table 29
22-Nov-2016
4
Added AEC-Q100 qualified in Features.
Updated Table 4: ESD protection,
Added Section 3.4.12: Over Current Recovery settings
Updated Section 4.22: Programmable soft-start function
to drive loads with higher inrush current
AddedTable 18: Half bridges (OUT1, OUT4, OUT5 and
OUT6) OCR timing parameters and Table 19: High-side
(OUT7, OUT8 and OUT_HS) OCR timing parameters
Updated Table 20: Current monitoring
Updated Table 110: SR2 signals description
Updated Table 124: SR11 signals description
11-Mar-2019
5
Moved “Device summary” table in cover page.
Added the "Sustainable Technology" logo to the
datasheet in cover page.
DS11567 Rev 5
L99DZ120
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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