L99MD01
Octal half-bridge driver with SPI control
for automotive application
Features
■
8 half bridges
■
RON = typ. 0.9 Ω (HS), 0.64 Ω (LS)
@ Tj = 25 °C
■
Current limit of each output at min. 0.8 A
■
Intrinsic DC/DC step up converter driving an
external MOSFET
■
PWM mode option for all half bridges for hold
current
■
Internal PWM generation
■
Two current monitor outputs
■
SPI interface for data communication
■
Temperature warning
■
All outputs overtemperature protected
■
All outputs short circuit protected
■
VCC supply voltage 3.0 to 5.3 V
■
Very low current consumption in standby mode
typ. 5 µA
■
VS operating range compliant: 6 V – 18 V
Applications
■
Stepper motor driver and / or DC
■
Intended to drive HVAC flaps
*$3*&)7
PowerSSO-36
Description
The L99MD01 is an octal half-bridge driver for
automotive applications.
The device is intended to drive DC and/or stepper
motors. Using the boost converter it’s possible to
drive 4 stepper motors simultaneously. Without
boost converter the system is able to run 3
stepper motors in sequential mode or 2 stepper
motors simultaneously. The octal half bridge
configuration allows also to drive 4 DC-motors
simultaneously and 7 DC-motors sequentially.
The integrated 24 bit standard Serial Peripheral
Interface (SPI) controls all outputs and provides
diagnostic information: normal operation, openload in on-state, overcurrent, temperature
warning and overtemperature.
Table 1.
Device summary
Order codes
Package
PowerSSO-36
September 2013
Doc ID 17242 Rev 6
Tube
Tape and reel
L99MD01XP
L99MD01XPTR
1/54
www.st.com
1
Contents
L99MD01
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Power supply: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Power supply: VSA, VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.4
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.5
SMPS Switched Mode Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.6
Current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.7
Inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.8
Diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.9
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . 9
2.10
VS, VS2, VSA, VSB monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.11
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.12
Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.13
Cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
SPI electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4.2
SPI timing parameter definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional description of the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
5.2
2/54
4.4.1
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.1
Serial clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.2
Serial data input (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 17242 Rev 6
L99MD01
6
Contents
5.2.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2.2
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.4
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5
Read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.6
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPI control and status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
Control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
Application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.1
9
10
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.1
ECOPACK® package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.2
PowerSSO-36™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Doc ID 17242 Rev 6
3/54
List of tables
L99MD01
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
4/54
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
VS, VS2, VSA, VSB monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current monitor dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SMPS switched mode power supply gate driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Command byte (8 bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Global status byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
RAM memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ROM memory map (access with OC0 and OC1 set to ‘1’) . . . . . . . . . . . . . . . . . . . . . . . . . 29
Control status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Wobble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Frequency deviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ratio for CURR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ratio for CURR1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Doc ID 17242 Rev 6
L99MD01
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin connection (top view- not in scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output turn-on/off delays and slew rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SMPS timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock polarity and clock phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPI frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Indication of the global error flag on SDO when CSN is low and SCK is stable. . . . . . . . . 26
Driving 4 bipolar stepper motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Driving 2 bipolar stepper motors simultaneously and 3 DC-motors sequentially . . . . . . . . 40
Driving 2 bipolar stepper motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Driving 1 bipolar stepper motor and 2 DC-motors simultaneously . . . . . . . . . . . . . . . . . . . 42
Driving 3 bipolar stepper motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Driving 4 DC-motors simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Driving 3 DC-motors simultaneously and 2 DC-motors sequentially . . . . . . . . . . . . . . . . . 45
Driving 7 DC-motors sequentially . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Driving simultaneously 4 unipolar winded stepper motors in bipolar mode . . . . . . . . . . . . 46
Cost saving impact using L99MD01 as stepper motor driver inside HVAC systems . . . . . 47
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PowerSSO-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PowerSSO-36™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Doc ID 17242 Rev 6
5/54
Block diagram
1
L99MD01
Block diagram
Figure 1.
Detailed block diagram
9V
9FF
9V
9V$
9V%
9ROWDJH0RQLWRULQJ
9 6WDE
9V$
&XUUHQW
6HQVH
2YHUFXUUHQW
2SHQORDG
6036
287
287
287
287
&XUUHQW
6HQVH
2YHUFXUUHQW
2SHQORDG
(1
9FF
3*1'
/2*,&
&61
9V%
&XUUHQW
6HQVH
2YHUFXUUHQW
2SHQORDG
6&.
287
287
287
287
63,
',
9FF
&XUUHQW
6HQVH
2YHUFXUUHQW
2SHQORDG
'2
3*1'
9FF
&855
9FF
08;
&855
&XUUHQW
0RQLWRU
*1'
6/54
Doc ID 17242 Rev 6
$*9
L99MD01
Detailed description
2
Detailed description
2.1
Power supply: VCC
The supply voltage VCC (3.3 V / 5 V) supplies the whole device. In case of power-on (VCC
increases from undervoltage to VPOR OFF = 2.75 V, typical) the circuit is initialized by an
internally generated power-on-reset (POR). If the voltage VCC decreases under the
minimum threshold (VPOR ON = 2.55 V, typical), the outputs are switched off in 3-state (high
impedance). The status registers are cleared and the control registers are reset to their
default.
Figure 2.
Power on reset
(1
$*9
2.2
Power supply: VSA, VSB
Each VSA and VSB supplies 4 half bridges independently.
VSA Out 1 to Out 4
VSB Out 5 to Out 8
2.3
Standby mode
The standby mode of the L99MD01 is activated by EN pin to low. The inputs and outputs are
switched off. The status registers are cleared and the control registers are reset to their
default values.
In the standby mode the current consumption is typ. 5 µA.
2.4
PWM mode
The PWM Mode is intended to generate a hold current for stepper motors.
PWM frequency typ. 100 Hz.
Duty cycle (SPI 2bit): 15 %, 30 %, 45 % and 60 %.
Each half-bridge is independently addressable (SPI 8bit).
Doc ID 17242 Rev 6
7/54
Detailed description
2.5
L99MD01
SMPS Switched Mode Power Supply
External MOSFET
Spread spectrum technique:
●
Wobble oscillator, programmable by SPI (1.95 K / 3.9 K / 7.8 K / 15.6 KHz).
●
Frequency modulation programmable by SPI (0 / 5 / 10 / 20%).
VS2 level concept:
●
Microcontroller measuring pulse of SMPS frequency (dependent on internal oscillator
frequency).
Due to the Oscillator frequency of L99MD01 the µC can calculate the on/off counts to
program the SMPS frequency and duty cycle.
●
Microcontroller sending by SPI SMPS 6-bit on counter value, microcontroller sending
by SPI SMPS 6-bit off counter value.
Basing on the on and off counter value the duty cycle and the SMPS frequency can be
programmed.
The VS2 voltage is strongly related to the duty cycle of SMPS.
2.6
Current monitor
The current monitor output sources a current image at the current monitor output which has
a programmable ratio (1/250, 1/500, 1/750, 1/1000) of the instantaneous current of the
selected half bridge (high-side or low-side). Via SPI it can be programmed which of the
outputs are multiplexed to the current monitor output.
The current monitor output allows a more precise analysis of the actual state of the load
rather than the detection of an open or overload condition. For example this can be used to
detect the motor state (starting, free-running, stalled).
2.7
Inductive loads
Each half bridge is built by an internally connected high-side and a low-side power DMOS
transistor. Due to the built-in reverse diodes of the output transistors, inductive loads can be
driven at the outputs.
2.8
Diagnostic functions
All diagnostic functions (over/open-load, temperature warning and thermal shutdown,
over/undervoltage) are internally filtered and the condition has to be valid for at least 32 µs
(open-load: typ. 2 ms, respectively) before the corresponding status bit in the status
registers is set. The filters are used to improve the noise immunity of the device. Open-load
and temperature warning function are intended for information purpose and not changes the
state of the output drivers. On contrary, the overload and thermal shutdown condition
disables the corresponding driver (overload) or all drivers (thermal shutdown), respectively.
The microcontroller has to clear the overcurrent status bit to reactivate the corresponding
driver.
8/54
Doc ID 17242 Rev 6
L99MD01
2.9
Detailed description
Temperature warning and thermal shutdown
If the junction temperature rises above Tj TW ON a temperature warning flag is set and is
detectable via the SPI. If the junction temperature increases above the second threshold
Tj SD ON, the thermal shutdown bit is set and power DMOS transistors of all output stages
are switched off to protect the device. Temperature warning flag and thermal shutdown bits
are latched. In order to reactivate the output stages, the junction temperature must
decrease below Tj SD ON and the thermal shutdown bit has to be cleared by the
microcontroller.
2.10
VS, VS2, VSA, VSB monitoring
Table 2.
VS undervoltage:
Status bit is set. All outputs and SMPS are switched off.
The microcontroller needs to clear the status bits to reactivate the
drivers and SMPS.
VS overvoltage:
Status bit is set. All outputs are switched off (default).
The microcontroller needs to clear the status bits to reactivate the
drivers Can be deactivated via SPI.
VSA undervoltage:
Status bit is set. Out 1 to Out 8 are switched off.
The microcontroller needs to clear the status bits to reactivate the
drivers.
VSB undervoltage:
Status bit is set. Out 1 to Out 8 are switched off.
The microcontroller needs to clear the status bits to reactivate the
drivers.
VS2 undervoltage:
Status bit is set. Only if SPMS is active.
The microcontroller needs to clear the status bits to reactivate SMPS
VS2 overvoltage:
Status bit is set. SMPS is switched off (default).
The microcontroller needs to clear the status bits to reactivate
SMPS. If the VS2 recovery bit is set, and the VS2 voltage falls below
the threshold, the SMPS goes in active mode and the status bit is
cleared.
VS, VS2, VSA, VSB monitoring
‘typ
SMPS
Out x
VS undervoltage
5.7 V
Status + off
Status + off
VS overvoltage
22.0 V
X
Status + (off or mask)
VSA undervoltage
5.7 V
X
Status + off
VSB undervoltage
5.7 V
X
Status + off
VS2 undervoltage
VS + 1.5V
Status
X
VS2 overvoltage
35.0 V
Status + (off or (off+ recovery))
Doc ID 17242 Rev 6
9/54
Detailed description
2.11
L99MD01
Open-load detection
The open-load detection monitors the load current in each activated output stage. If the load
current is below the open-load detection threshold for at least 2 ms (tdOL) the corresponding
open load bit is set in the status register. Due to mechanical/electrical inertia of typical loads
a short activation of the outputs (e.g. 3 ms) can be used to test the open-load status without
changing the mechanical/electrical state of the loads.
2.12
Overload detection
In case of an overcurrent condition, a flag is set in the corresponding status register. If the
overcurrent signal is valid for at least tISC = 32 µs, the overcurrent flag is set and the
corresponding switch is switched off to reduce the power dissipation and to protect the
integrated circuit. The microcontroller has to clear the status bit to reactivate the
corresponding driver.
2.13
Cross-current protection
The device is cross-current protected by an internal delay time. If one driver (LS or HS) is
turned-off the activation of the other driver of the same half bridge are automatically delayed
by the cross-current protection time. After the cross-current protection time is expired the
slew-rate limited switch-off phase of the driver is changed to a fast turn-off phase and the
opposite driver is turned-on with slew-rate limitation. Due to this behavior it is always
guaranteed that the previously activated driver is totally turned-off before the opposite driver
starts to conduct. If wrong SPI commands try to turn-on both driver (LS and HS)
simultaneously, the high-side and the low-side are (or stay) deactivated (3-state).
10/54
Doc ID 17242 Rev 6
L99MD01
3
Pin definitions and functions
Pin definitions and functions
Table 3.
Pin description
Pin
Symbol
Function
1, 18, 19, 36
PGND
Power ground: reference potential
9
AGND
Analog ground: reference potential
27
DGND
Digital ground: reference potential
6, 10, 13
N.C.
Not connected
Exposed pad: reference potential connected to PGND
2, 3, 16, 17,
20, 21, 34, 35
Half bridge-output:
the output is built by a high-side and a low-side switch, which are
OUT 1 - 8 internally connected. The output stage of both switches is a power
DMOS transistor. Each driver has an internal parasitic reverse diode
(bulk-drain-diode: high-side driver from output to VSx, low-side driver
from PGND to output).
VCC
Logic voltage supply 3.3 V / 5 V
For this input a ceramic capacitor as close as possible to AGND is
recommended
VSA
Power supply voltage for OUT 1 to 4 (external reverse protection
required):
For this input a ceramic capacitor as close as possible to PGND is
recommended.
Important: for the capability of driving the full current at the outputs all
pins of VSA must be externally connected!
14, 15, 22, 23
VSB
Power supply voltage for OUT 5 to 8 (external reverse protection
required):
For this input a ceramic capacitor as close as possible to PGND is
recommended.
Important: for the capability of driving the full current at the outputs all
pins of VSA must be externally connected!
11
VS2MON
12
VS
25
SMPS
29
4, 5, 32, 33
7, 8
VS2 monitoring
VS supply and monitoring
SMPS gate driver.
For overcurrent and overvoltage protection a external resistor is
recommended
CURR1 / 2 Current monitor 1 / 2
31
EN
Enable the L99MD01
28
DI
SPI data in: the input requires CMOS logic levels and receives serial
data from the microcontroller. The data is a 24 bit control word and the
most significant bit (MSB) is transferred first.
26
DO
SPI data out: the diagnosis data is available via the SPI and this
3-state output. The output remains in 3-state, if the chip is not
selected by the input CSN (CSN = high)
Doc ID 17242 Rev 6
11/54
Pin definitions and functions
Table 3.
Pin
L99MD01
Pin description (continued)
Symbol
Function
24
CSN
SPI CSN chip select: this input is active low and requires CMOS logic
levels. The serial data transfer between the L99MD01 and micro
controller is enabled by pulling the input CSN to low level.
30
SCK
SPI serial clock input: this input controls the internal shift register of
the SPI and requires CMOS logic levels.
Figure 3.
Pin connection (top view- not in scale)
3*1'
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287
287
287
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96$
96$
96$
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96%
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287
287
287
287
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3*1'
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12/54
Doc ID 17242 Rev 6
L99MD01
Electrical specifications
4
Electrical specifications
4.1
Absolute maximum ratings
Table 4.
Absolute maximum ratings
Symbol
Parameter
DC supply voltage
VS
Single pulse tmax < 400 ms
Value
Unit
-0,3…28
V
40
V
-0,3…38
V
40
V
-0.3 to 5.5
V
V
VS2
VSA
VSB
DC supply voltage
VCC
Stabilized supply voltage, logic supply
EN
DI
DO
SCK
CSN
Digital input / output voltage
-0.3 to VCC + 0.3
CURR1/2
Current monitor output
-0.3 to VCC + 0.3
OUT 1-8
Output current capability
SMPS
Single pulse tmax < 400 ms
±2
A
SMPS is not overcurrent protected, external
resistor can be used for protection and EMC
optimizations
Note:
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
4.2
ESD protection
Table 5.
ESD protection
Parameter
Value
Unit
All pins
±2
(1)
kV
Output Pins: OUT1 – 8, VS, VSA, VSB, VS2,
±4(2)
kV
1.
HBM according to EIA/JESD22-A114-E.
2.
HBM with all unzapped pins grounded.
Doc ID 17242 Rev 6
13/54
Electrical specifications
4.3
L99MD01
Thermal data
Table 6.
Operating junction temperature
Symbol
Tj
Table 7.
Parameter
operating junction temperature
Unit
-40 to 150
°C
Temperature warning and thermal shutdown
Symbol
4.4
Value
Parameter
Min.
Typ.
Max.
Unit
TjTW ON
temperature warning threshold
junction temperature
Tj increasing
-
-
150
°C
TjSD ON
thermal shutdown threshold junction
temperature
Tj increasing
-
-
170
°C
Electrical characteristics
VS = 6 to 18 V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 8.
Symbol
VSA/ VSB
IS
IVS
IVS2
IVSX
VCC
14/54
Supply
Parameter
Test condition
operating supply voltage
range
VSA / VSB DC supply current
VS supply current
VS2 DC current
VSx
(VS, VSA, VSB, VS2) quiescent
supply current
Min.
Typ.
6
Max.
Unit
38
V
VSx = 13 V, VCC = 5.0 V
EN = high
Outputs floating
0.5
2
mA
VS = 13 V, VCC = 5 V
EN = high
SMPS output off
1.5
4
mA
VS = 13 V, VCC = 5 V
EN = high
SMPS load = 2 nF, 200 kHz,
duty 50 %
4.2
7
mA
VS2 =26 V, VCC = 5.0 V
EN = high
300
600
µA
VSx = 13 V, VCC = 5 V
EN = low
Tj = -40, 25 °C
Outputs floating
3
10
µA
Tj = 130 °C; TBV
6
20
µA
5,3
V
operating supply voltage range
3,0
Doc ID 17242 Rev 6
L99MD01
Table 8.
Symbol
Electrical specifications
Supply (continued)
Parameter
Symbol
Min.
Typ.
Max.
Unit
VCC DC supply current
VSx = 13 V, VCC = 5.0 V
EN = high
1
3
mA
VCC quiescent supply current
VS = 13 V, VCC = 5.0 V
CSN = VCC
EN = low
Outputs floating
5
20
µA
Typ.
Max.
Unit
3.0
V
ICC
Table 9.
Test condition
Overvoltage and undervoltage detection
Parameter
Test condition
Min.
VPOR OFF
power-on-reset threshold
VCC increasing
VPOR ON
power-on-reset threshold
VCC decreasing
VPOR hyst
power-on-reset hysteresis
VPOR OFF - VPOR ON
VSUV OFF
VS UV-threshold voltage
VS increasing
6.0
6.7
V
VSUV ON
VS UV-threshold voltage
VS decreasing
5.4
6
V
VSUV hyst
VS UV-hysteresis
VSUV OFF - VSUV ON
0.35
VSAUV OFF
VSA UV-threshold voltage
VSA increasing
5.95
6.7
V
VSAUV ON
VSA UV-threshold voltage
VSA decreasing
5.4
6
V
VSAUV hyst
VSA UV-hysteresis
VSAUV OFF - VSAUV ON
0.35
VSBUV OFF
VSB UV-threshold voltage
VSB increasing
5.95
6.7
V
VSBUV ON
VSB UV-threshold voltage
VSB decreasing
5.4
6
V
VSBUV hyst
VSB UV-hysteresis
VSBUV OFF - VSBUV ON
0.35
VSOV ON
VS OV-threshold voltage
VS increasing
VSOV OFF
VS OV-threshold voltage
VS decreasing
VSOV hyst
VS OV-hysteresis
VSOV ON - VSOV OFF
VS2UV OFF
VS2 UV-threshold voltage
VS2 increasing
VS2UV ON
VS2 UV-threshold voltage
VS2 decreasing
VS+1
VS2UV hyst
VS2 UV-hysteresis
VS2UV OFF - VS2UV ON
0.55
VS2OV ON
VS2 OV-threshold voltage
VS increasing
VS2OV OFF
VS2 OV-threshold voltage
VS decreasing
VS2OV hyst
VS2 OV-hysteresis
VS2OV ON - VS2OV OFF
Doc ID 17242 Rev 6
2.3
V
0.2
V
0.5
V
0.5
V
0.5
V
24
18
0.75
V
1
V
VS+5
V
V
0.8
32
0.75
V
1.15
V
38
V
V
1
V
15/54
Electrical specifications
Table 10.
Symbol
rON HS 1-8
Switches
Parameter
On resistance VSA / VSB to
OUT 1-8
On resistance OUT 1-8 to GND
rONLSHC 1-8
in HC mode
On resistance OUT 1-8 to GND
rONLSLC 1-8
in LC mode
ISCHS1-8
L99MD01
HS overcurrent protection
Test condition
Typ.
Max.
Unit
Tj = 25 °C,
IOUT1-8 = -0.25 A
900
1200
mΩ
Tj = 125 °C,
IOUT1-8 = -0.25 A
1300
1800
mΩ
Tj = 25 °C, HC=1
IOUT1-8 = 0.25 A
700
1000
mΩ
Tj = 125 °C, HC=1
IOUT1-8 = 0.25 A
1000
1500
mΩ
Tj = 25 °C, HC=0
IOUT1-8 = 0.125 A
1200
1800
mΩ
Tj = 125 °C, HC=0
IOUT1-8 = 0.125 A
2000
2800
mΩ
0.8
1.4
A
VS = 13.5 V
Min.
ISCLSHC1-8
LS overcurrent protection in HC
VS = 13.5 V, HC = 1
mode
0.8
1.4
A
ISCLSLC1-8
LS overcurrent protection in LC
mode
0.4
0.7
A
td ON1-8 H
Output delay time, HS switch on VS = 13.5 V, Rload = 52 Ω
10
25
80
µs
td OFF1-8 H
Output delay time, HS switch off VS = 13.5 V, Rload = 52 Ω
50
100
300
µs
td ON1-8 L
Output delay time, LS switch on VS = 13.5 V, Rload = 52 Ω
5
15
80
µs
td OFF1-8 L
Output delay time, LS switch off VS = 13.5 V, Rload = 52 Ω
50
100
300
µs
tD LH/tD HL
Cross current protection time
20
200
400
µs
VS = 13.5 V, HC = 0
IQLH
Switched-off output current HS
OUT 1-8
VOUT1-8 = 0 V
IQLL
Switched-off output current LS
OUT 1-8
VOUT1-8 = VS
IOLDHS1-8
Open-load detection current HS Tj = -40 °C
OUT 1-8
Tj = 25 °C to 125 °C
Open-load detection current LS
IOLDLSHC1-8
OUT 1-8 in HC mode
IOLDLSLC1-8
Open-load detection current LS
OUT 1-8 in LC mode
tdOL
Minimum duration of open-load
condition to set the status bit
16/54
HC bit set to 1; Tj = -40 °C
HC bit set to 1;
Tj = 25 °C to 125 °C
HC bit set to 0; Tj = -40 °C
HC bit set to 0;
Tj = 25 °C to 125 °C
Doc ID 17242 Rev 6
-2
µA
2
µA
8
30
60
mA
10
30
60
mA
4.5
30
65
mA
8
30
60
mA
1.8
15
35
mA
4
15
30
mA
500
2000
3000
μs
L99MD01
Table 10.
Electrical specifications
Switches (continued)
Symbol
Parameter
Test condition
Minimum duration of
overcurrent condition to switch
off the driver
tISC
VS = 13.5 V, Rload = 52 Ω
dVOUT1-8/dt Slew rate of OUT 1-8
Figure 4.
Min.
Typ.
Max.
Unit
10
32
100
μs
0.1
0.25
0.5
V/µs
Output turn-on/off delays and slew rates
9287;
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Table 11.
Current monitor output
Symbol
VCURR1/2
ICURRHSLS250
Parameter
Functional voltage range
ICURRHSLS1000
ICURRLSLC125
Typ.
0
Max.
Unit
VCC - 1
V
1/250
-
1/500
-
1/750
-
1/1000
-
1/125
-
Imax = 800 mA, HC = 1
HS/LS current monitor
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
output ratio: ICURR1/2 / IOUT 1- VCC = 5 V; prog. via SPI,
8
Min.
Imax = 800 mA, HC = 1
HS/LS current monitor
0 V ≤ VCURR1/2 ≤VCC - 1 V,
output ratio: ICURR1/2 / IOUT 1- VCC = 5 V; prog. via SPI,
8
ICURRHSLS750
VCC = 5 V
HS/LS current monitor
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
output ratio: ICURR1/2 / IOUT 1- VCC = 5 V; prog. via SPI,
8
ICURRHSLS500
Test condition
Imax = 800 mA, HC = 1
HS/LS current monitor
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
output ratio: ICURR1/2 / IOUT 1- VCC = 5 V; prog. via SPI,
8
Imax = 800 mA, HC = 1
LS current monitor output
ratio in LC mode: ICURR1/2 /
IOUT 1-8
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V; prog. via SPI,
HC = 0; Imax = 400 mA
Doc ID 17242 Rev 6
17/54
Electrical specifications
Table 11.
L99MD01
Current monitor output (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
ICURRLSLC250
LS current monitor output
ratio in LC mode:
ICURRLSLC1/2 / IOUT 1-8
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V; prog. via SPI,
HC = 0; Imax = 400 mA
1/250
-
ICURRLSLC375
LS current monitor output
ratio in LC mode: ICURR1/2 /
IOUT 1-8
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V; prog. via SPI,
HC = 0; Imax = 400 mA
1/375
-
ICURRLSLC500
LS current monitor output
ratio in LC mode: ICURR1/2 /
IOUT 1-8
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V; prog. via SPI,
HC = 0; Imax = 400 mA
1/500
-
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V; IOUT 1-8 max = 0.8 A
HS current monitor accuracy
ICURRHS1/2 acc
(FS = full scale=
800 mA*current ratio); Tj = 40 °C
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V; IOUT 1-8 max = 0.8 A;
(FS = full scale=
800 mA*current ratio);
Tj = 25 °C to 125 °C
ICURRLSHC1/2 acc
ICURRLSLC1/2 acc
Table 12.
Symbol
td-CM
Table 13.
Symbol
LS current monitor accuracy
in HC mode
LS current monitor accuracy
in LC mode
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V;
0.4 A ≤ IOUT1-8 ≤ 0.8 A
(FS = full scale=
800 mA*current ratio)
0 V ≤ VCURR1/2 ≤ VCC - 1 V,
VCC = 5 V;
IOUT 1-8 max = 0.4 A
(FS = full scale=
800 mA*current ratio)
4% +
1%FS
10% +
3%FS
4% +
1%FS
8% +
2%FS
4% +
1%FS
10% +
3%FS
-
4% +
1%FS
10% +
3%FS
-
-
Current monitor dynamic characteristics
Parameter
Output to current monitor delay
time
Test condition
Min.
Typ.
Max.
Unit
IOUT from 100 mA to
200 mA; td-CM measured
from 50 % IOUT to 50 % ICM
—
2
—
µs
Min.
Typ.
Max.
Unit
4.5
5.5
6.5
V
100
mV
SMPS switched mode power supply gate driver output
Parameter
Test condition
VSMPSHI
SMPS output voltage high
VS = 8 V, ISMPS = -10 mA
VSMPL
SMPS output voltage low
VS = 8 V, ISMPS = 10 mA
tSMPSH
Output rise time
VS = 13.5 V, Cout = 2 nF
110
160
ns
tSMPSL
Output fall time
VS = 13.5 V, Cout = 2 nF
110
160
ns
18/54
Doc ID 17242 Rev 6
L99MD01
Table 13.
Electrical specifications
SMPS switched mode power supply gate driver output
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tdONSMPS
Output delay time, switch to
high
VS = 13.5 V, Cout = 2 nF
110
160
ns
tdOFFSMPS
Output delay time, switch to
low
VS = 13.5 V, Cout = 2 nF
30
100
ns
tdON-OFFSMPS
Output delay time difference
ON/OFF
VS = 13.5 V, Cout = 2 nF
80
120
ns
50
100
kΩ
RSMPS
Pull down resistor, SMPS
Figure 5.
23
SMPS timings
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Table 14.
Oscillator
Symbol
fCLK
4.4.1
Parameter
Test condition
Internal clock frequency
Min.
Typ.
Max.
Unit
2.8
4
5.2
MHz
SPI electrical characteristics
VS = 6 to 18 V, VCC = 3.0 to 5.3 V, Tj = -40 to 150 °C, unless otherwise specified.
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
Table 15.
DC characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
0.3VCC
V
SDI, SCK, CSN, EN
VIL
Input low voltage
VIH
Input high voltage
ICSN in
0.7VCC
Pull up current at input CSN
VCSN = 1.5 V;
VCC = 5 V
Doc ID 17242 Rev 6
8
V
20
40
µA
19/54
Electrical specifications
Table 15.
Symbol
L99MD01
DC characteristics (continued)
Parameter
Test condition
Min.
Typ.
Max.
Unit
Pull down current at input SCK
VSCK = 1.5 V;
VCC = 5 V
10
25
50
µA
IDI in
Pull down current at input DI
VDI = 1.5 V;
VCC = 5 V
10
25
50
µA
REN in
Pull down resistor at input EN
VEN = 1.5 V;
VCC = 5 V
25
50
115
kΩ
VOL
Output low voltage
Iout = 2 mA
0.2
0.4
V
VOH
Output high voltage
Iout = +2 mA
VCC 0.4
IDOLK
3-state leakage current
VCSN = VCC,
0 V < VCC
-10
ISCK in
SDO
Table 16.
Symbol
VCC 0.2
V
10
µA
AC characteristics
Parameter
Test condition
Min.
Typ.
Max.
Unit
SDO, SDI, SCK, CSN, EN
COUT(1)
CIN(1)
Output capacitance (SDO)
VOUT = 0 V to 5 V
—
—
10
pF
Input capacitance (SDI)
VIN = 0 V to 5 V
—
—
10
pF
Input capacitance (other pins)
VIN = 0 V to 5 V
—
—
10
pF
Min.
Typ.
Max.
Unit
100
µs
1. Guaranteed by design
Table 17.
Symbol
tEN
Parameter
Test condition
EN high setup time
tSCSN
CSN setup time before SCK
rising
tHCSN
CSN high time
tCSNQV
CSN falling until SDO valid
Cout = 100 pF
100
ns
tCSNQT
CSN rising until SDO 3-state
Cout = 100 pF
150
ns
tSSCK
SCK setup time before CSN
rising
50
ns
tSSDI
SDI setup time before SCK
rising
40
ns
tHSCK
SCK high time
200
ns
tLSCK
SCK low time
200
ns
tSCKQV
20/54
Dynamic characteristics(1)
SCK falling until SDO valid
Cout = 100 pF
Doc ID 17242 Rev 6
400
ns
2
µs
150
ns
L99MD01
Electrical specifications
Table 17.
Symbol
Dynamic characteristics(1)
Parameter
Test condition
Min.
Typ.
Max.
Unit
tQLQH
Output rise time
Cout = 100 pF,
20 % - 80 % x VCC
110
ns
tQHQL
Output fall time
Cout = 100 pF,
80 % - 20 % x VCC
110
ns
fSPI
SPI frequency
1
MHz
1. See Section 4.4.2: SPI timing parameter definition.
4.4.2
SPI timing parameter definition
Figure 6.
SPI timing
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Doc ID 17242 Rev 6
21/54
Functional description of the SPI
L99MD01
5
Functional description of the SPI
5.1
Signal description
5.1.1
Serial clock (SCK)
This input signal provides the timing of the serial interface. Data present at Serial Data Input
(SDI) is latched on the rising edge of Serial Clock (SCK). Data on Serial Data Out (SDO) is
shifted out at the falling edge of Serial Clock (see Figure 7).
2H
The SPI can be driven by a microcontroller with its SPI peripherals running in following
mode: CPOL=0 and CPHA=0 (see Figure 7).
3H
5.1.2
Serial data input (SDI)
This input is used to transfer data serially into the device. It receives the data to be written.
Values are latched on the rising edge of Serial Clock (SCK).
Serial data output (SDO)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (SCK). SDO also reflects the status of the
(Bit 7 of the ) while CSN is low and no clock signal is present.
Chip select not (CSN)
When this input signal is High, the device is deselected and Serial Data Output (SDO) is
high impedance (3-state). Driving this input low enables the communication. The
communication must start and stop on a low level of Serial Clock (SCK).
Figure 7.
Clock polarity and clock phase
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Doc ID 17242 Rev 6
L99MD01
Figure 8.
Functional description of the SPI
SPI frame structure
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Doc ID 17242 Rev 6
23/54
Functional description of the SPI
L99MD01
5.2
SPI communication flow
5.2.1
General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)
signal lines. Maximum SPI frequency is 1 MHz.
At the beginning of each communication the master reads the register
(ROM address 3EH) of the slave device. This 8-bit register indicates the SPI frame length
(24-bit for the L99MD01) and the availability of additional features.
Each communication frame consists of an instruction byte which is followed by 2 data bytes
(see Figure 8).
4H
The data returned on SDO within the same frame always starts with the
register. It provides general status information about the device. It is followed by 2bytes (i. e.
‘In-frame-response’, Figure 8).
For write cycles the register is followed by the previous content of the
addressed register.
For read cycles the register is followed by the content of the addressed
register.
Table 18.
Command byte (8 bit)
Operating code
Address
Bit
23
22
21
20
19
18
17
16
Name
OC1
OC0
A5
A4
A3
A2
A1
A0
Table 19.
Data byte
Data byte 1
Bit
15
14
13
12
11
Data byte 0
10
Name D15 D14 D13 D12 D11 D10
5.2.2
9
8
7
6
5
4
3
2
1
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (, , , ) and a 6 bit address.
Table 20.
24/54
Operating code definition
OC1
OC0
Meaning
0
0
0
1
1
0
1
1
Doc ID 17242 Rev 6
L99MD01
Functional description of the SPI
The and operations allow access to the RAM of the device,
i. e. write to control registers or read status information.
A operation addressed to a device specific status register reads
back and subsequently clear this status register. A operation with
address 3FH clears all status registers at a time and reads back the
register.
A operation addressed to an unused RAM address register is
identical to a operation (in case of unused RAM address, the second byte is
equal to 00H).
allows access to the ROM area which contains device related
information such as the product family, product name, silicon version and register width.
Table 21.
Bit
Global status byte
Description
Polarity
Comment
Depends on bit 5 of :
0
Software reset or
under/overvoltage
Active high
Bit 5
Bit 0
0
Set if software reset (SDI stuck at 1
or 0)
1
Logical OR of the under- /
overvoltage status bits
1
Overcurrent detected
Active high
Set by any overcurrent event
2
Open-load detected
Active high
Set by any open-load event
3
Temp warning
Active high
4
Thermal shutdown /
chip overload
Active high
5
Not (chip reset or
communication error)
Active low
Activated by all internal reset events that change
device state or configuration registers (e. g.
software reset, VCC under-voltage, etc.). The bit is
set after a valid communication with any register.
This bit is initially ‘0’ and is set to ‘1’ by a valid SPI
communication
6
Communication Error
Active high
Bit is set if the number of clock cycles during
CSN = low does not match with the specified
frame width or if an invalid bus condition is
detected (SDI stuck at 1 or 0).
7
Global Error Flag
Active high
Logic OR combination of all failures in the .
The is generated by an OR-combination of all failure events of the
device (i.e. bit 0 to bit 6 of the .
Doc ID 17242 Rev 6
25/54
Functional description of the SPI
Figure 9.
L99MD01
Indication of the global error flag on SDO when CSN is low and SCK is stable.
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The bit 0 of the is a combination of an under/overvoltage warning and
a software warning: If the bit 5 is one (this is the standard after a correct SPI
communication), bit 0 is the logical OR of all under- and overvoltage status bits.
On the other hand, if there has been an SPI communication error or a chip reset (bit 5 is
zero), then bit 0 gives a better indication about the SPI error: An SDI stuck-at error leads to
a software reset and sets bit 0, while a clock pulse error only sets the communication error
bit, clears bit 5 and clears also bit 0. This leads to the following table of possible states
(assuming there is no under/overvoltage, overcurrent, openload or thermal error):
Table 22.
Reset
State
Description
Global status
EN = 0 (power on reset)
All registers reset
Outputs switched off (3-state)
1000 0000
Clock cycles != 24
Ignore frame
No reset
1100 0000
SDI always 0
Software reset
Outputs switched off
1100 0001
SDI always 1
Software reset
Outputs switched off
1100 0001
Writing to the selected data input register is only enabled if exactly one frame length is
transmitted within one communication frame (i.e. CSN low). If more or less clock pulses are
counted within one frame, the complete frame is ignored and a SPI frame error is signaled in
the Global Status register. This safety function is implemented to avoid an unwanted
activation of output stages by a wrong communication frame.
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Doc ID 17242 Rev 6
L99MD01
Functional description of the SPI
For read operations, the bit in the is set, but
the register to be read is still transferred to the SDO pin. If the number of clock cycles is
smaller than the frame width, the data at SDO are truncated. If the number of clock cycles is
larger than the frame width, the data at SDO are filled with ‘0’ bits.
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected ICs is
recommended.
Note:
As the frame width is 24 bits, an initial Read of using a 16 bits
communication sets the of the . A
subsequent correct length transaction is necessary to correct this bit.
5.3
Write operation
OC0, OC1: operating code (00 for ‘write’ mode)
The write operation starts with a command byte followed by 2 data bytes.
For write cycles the register is followed by the previous content of the
addressed register.
The RAM memory area consists of 16 bit registers. All unused RAM addresses are read as
‘0’.
Failures are indicated by activating the corresponding bit of the register.
Note:
RAM address 00H is unused. An attempt to access this address is recognized as a
communication line error (‘Data-in stuck to GND’) and all internal registers are cleared
(software reset).
5.4
Read operation
OC0, OC1: operating code (01 for ‘read’ mode)
The read operation starts with a command byte followed by 2 data bytes. The content of the
data bytes is ‘don’t care’. The content of the addressed register is shifted out at SDO within
the same frame (‘in-frame response’).
The returned data byte represents the content of the register to be read.
Failures are indicated by activating the corresponding bit of the register.
5.5
Read and clear status operation
OC0, OC1: operating code (10 for ‘read and clear status’ mode)
The ‘Read and Clear Status’ operation starts with a command byte followed by 2 data bytes.
The content of the data bytes is ‘don’t care’. The content of the addressed status register is
transferred to SDO within the same frame (‘in-frame response’) and is subsequently
cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all Status registers
simultaneously.
Doc ID 17242 Rev 6
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Functional description of the SPI
L99MD01
A operation addressed to an unused RAM address is identical to
a operation (in case of unused RAM address, the second byte is equal to
00H).
The returned data byte represents the content of the register to be read.
Failures are indicated by activating the corresponding bit of the register.
5.6
Read device information
OC0, OC1: operating code (11 for ‘read device information mode).
The device information is stored at the ROM In the ROM memory area, the first 8 bits are
used. All unused ROM addresses are read as ‘0’.
Note:
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ROM address 3FH is unused. An attempt to access this address is recognized as a
communication line error (‘Data-in stuck to VCC’) all internal registers are cleared (software
reset).
Doc ID 17242 Rev 6
L99MD01
6
SPI control and status register
SPI control and status register
Table 23.
RAM memory map
Address
Name
Access
01h
Control register 1
Read/write
Output switch on/off
02h
Control register 2
Read/write
SMPS driver configuration
03h
Control register 3
Read/write
Low-side high current mode
VS configuration
SMPS configuration
04h
Control register 4
Read/write
Current multiplexer
05h
Control register 5
Read/write
PWM
06h
Control register 6
Read/write
Open-load
10h
Status register 0
Read only
Overcurrent
11h
Status register 1
Read only
Open-load
12h
Status register 2
Read only
TSD
Over/undervoltage
Table 24.
Content
ROM memory map (access with OC0 and OC1 set to ‘1’)
Address
Name
Access
Content
00h
ID Header
Read only
43h (device class ASSP, 2 additional information
bytes)
01h
Version
Read only
00h (engineering samples) (ST-SPI)
02h
ProducCode1
Read only
3Eh (62 ST_SPI)
03h
ProducCode2
Read only
4Eh (N ST_SPI)
3Dh
Fuses
Read only
Fuse data 9 - 0
3Eh
SPI-Frame ID
Read only
02h SPI-Frame-ID Register (24 Bit ST_SPI)
Doc ID 17242 Rev 6
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SPI control and status register
6.1
L99MD01
Control status register
Default reset value is 0, all unused bits read 0, unused bits have to be set to 0
Control status register
Access
Address
Table 25.
Data byte 1
15
01h
R/W
14
13
12
11
Data byte 0
10
9
8
7
6
5
4
3
2
1
0
HS8 LS8 HS7 LS7 HS6 LS6 HS5 LS5 HS4 LS4 HS3 LS3 HS2 LS2 HS1 LS1
Output switch on/off
02h
R/W
15
14
13
12
11
10
9
8
7
6
0
0
ON
ON
ON
ON
ON
ON
0
0
5
4
3
2
1
0
OFF OFF OFF OFF OFF OFF
03h
R/W
14
13
12
11
10
9
8
HC8 HC7 HC6 HC5 HC4 HC3 HC2 HC1
7
6
5
0
VS2 reco.
15
VS OV warn/
shutdown
On/off cycles counter for SMPS driver (OFF must be > 3dec.)
4
Wob Wob
1
0
Freq Freq Rnd/
dev. dev. lin
10
9
8
7
6
5
4
3
2
1
0
OUTx to
CURR2
OUTx to
CURR2
OUTx to
CURR2
OUTx to
CURR1
OUTx to
CURR1
OUTx to
CURR1
OUTx to
CURR1
0
0
0
0
1K-fact
11
1K-fact
12
2K-fact
13
2K- fact
14
7
6
5
4
3
2
1
0
OUT8
15
OUTx to
CURR2
R/W
2
SMPS configuration
Low-side high current (reset value = 1)
04h
3
Current multiplexer
OUT2
OUT1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
disable
OL2
disable
OL1
0
OUT3
0
disable
OL3
0
OUT4
0
disable
OL4
0
8
OUT5
0
9
disable
OL5
10
OUT6
11
disable
OL6
12
OUT7
13
disable
OL7
R/W
14
disable
OL8
05h
15
6
5
4
3
2
1
0
PWM duty
PWM
06h
R/W
Open-load
15
10h
R
14
13
12
11
10
9
8
7
HS8 LS8 HS7 LS7 HS6 LS6 HS5 LS5 HS4 LS4 HS3 LS3 HS2 LS2 HS1 LS1
Status overcurrent
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Doc ID 17242 Rev 6
L99MD01
4
3
2
1
0
0
0
0
0
0
0
0
0
OUT1
5
OUT2
6
6
5
4
3
2
1
0
VSB UV
7
OUT3
8
VS OV
9
OUT4
10
VS UV
11
OUT5
12
VS2 OV
13
OUT6
14
VS2 UV
15
OUT7
Data byte 0
TSD warn
R
Data byte 1
OUT8
11h
Control status register (continued)
Access
Address
Table 25.
SPI control and status register
R
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
VSA UV
12h
15
TSD
Status open-load
Status TSD; over/ undervoltage
Table 26.
Control register 1
Control register 1 (read/write); address 01h
Bit
Name
15
OUT8 – HS on/off
14
OUT8 – LS on/off
13
OUT7 – HS on/off
12
OUT7 – LS on/off
11
OUT6 – HS on/off
10
OUT6 – LS on/off
9
OUT5 – HS on/off
8
OUT5 – LS on/off
7
OUT4 – HS on/off
6
OUT4 – LS on/off
5
OUT3 – HS on/off
4
OUT3 – LS on/off
3
OUT2 – HS on/off
2
OUT2 – LS on/off
1
OUT1 – HS on/off
0
OUT1 – LS on/off
Comment
If a bit is set, the selected output driver is switched on.
If the corresponding PWM enable bit is set the driver is PWMed.
If the bits of HS- and LS-driver of the same half bridge are set, the HS- and the
LS-driver is deactivated.
Doc ID 17242 Rev 6
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SPI control and status register
Table 27.
L99MD01
Control register 2
Control register 2 (read/write); address 02h
Bit
Name
Comment
SMPS frequency and duty cycle.
15
-
14
-
13
SMPS on cycles bit 5
12
SMPS on cycles bit 4
11
SMPS on cycles bit 3
10
SMPS on cycles bit 2
9
SMPS on cycles bit 1
8
SMPS on cycles bit 0
7
-
6
-
5
SMPS off cycles bit 5
4
SMPS off cycles bit 4
3
SMPS off cycles bit 3
2
SMPS off cycles bit 2
1
SMPS off cycles bit 1
0
SMPS off cycles bit 0
Table 28.
Number of ON cycles for SMPS driver, binary coded.
Cycles are based on the internal oscillator
If all bits are set to “1” the SMPS output is high for 63 clock cycles.
Number of OFF cycles for SMPS driver, binary coded.
Cycles are based on the internal Oscillator. If OFF is set to values 3 the SMPS
driver is switched off.
If all bits are set to “1” the SMPS output is low for 63 clock cycles.
Control register 3
Control register 3 (read/write); address 03h
Bit
Name
15
High current LS 8
14
High current LS 7
13
High current LS 6
12
High current LS 5
11
High current LS 4
10
High current LS 3
9
High current LS 2
8
High current LS 1
7
-
6
32/54
VS OV shutdown/warn
Comment
High current mode of low-side switch
“0”: The selected low-side switch is in low current mode. The overcurrent and
open-load thresholds are reduced by ½.
The selected current monitor ratio is doubled.
“1” (default setting) the selected low-side switch is in high current mode
In case of VS overvoltage
“0”: all outputs are switched off + status bit set
“1”: only status bit is set
Doc ID 17242 Rev 6
L99MD01
Table 28.
SPI control and status register
Control register 3 (continued)
Control register 3 (read/write); address 03h
Bit
5
Name
Comment
VS2 recovery
VS2 recovery mode:
“0”: no recovery after VS2 overvoltage
“1”: If the VS2 voltage falls below the threshold after a VS2 overvoltage condition,
the SMPS goes again in active mode and the status bit is cleared
SMPS configuration
4
Wobble bit 1
3
Wobble bit 0
2
Frequency deviation bit 1
1
Frequency deviation bit 0
Wobble defines the modulation frequency deviation of the internal oscillator,
definition see Table 29.
Frequency deviation of the internal oscillator, definition see Table 30
0
Rnd/Lin
Table 29.
Random/linear mode:
“0”: the oscillator is changed in linear mode like a triangle.
“1”: the oscillator frequency is distributed randomly.
Wobble
Bit 4
Bit 3
Wobble
0
0
1.95 KHz
0
1
3.9 KHz
1
0
7.8 KHz
1
1
15.6 KHz
Table 30.
Frequency deviation
Bit 2
Bit 1
Frequency deviation
0
0
0%
0
1
5%
1
0
10 %
1
1
20 %
Doc ID 17242 Rev 6
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SPI control and status register
Table 31.
L99MD01
Control register 4
Control register 4 (read/write); address 04h
Bit
Name
Comment
15
OUTx to CURR2 bit 2
14
OUTx to CURR2 bit 1
13
OUTx to CURR2 bit 0
12
Enable CURR2
11
OUTx to CURR1 bit 2
10
OUTx to CURR1 bit 1
9
OUTx to CURR1 bit 0
8
Enable CURR1
7
-
6
-
5
-
4
-
3
CURR2 K-factor
2
CURR2 K-factor
1
CURR1 K-factor
0
CURR1 K-factor
Table 32.
111
110
101
100
011
010
001
000
To
CURR2
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Enable the current monitor output 2
Bit
setting
111
110
101
100
011
010
001
000
To
CURR1
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
Enable the current monitor output 1
Current monitor ratio IOUTx/ICURR
If the high current bit (register 03h) is set to 0 the ratio for the low-side is the
double of the programmed one.
Ratio for CURR2
Bit3
Bit2
Ratio for CURR2
0
0
1/1000
0
1
1/750
1
0
1/500
1
1
1/250
Bit1
Bit0
Ratio for CURR1
0
0
1/1000
0
1
1/750
1
0
1/500
1
1
1/250
Table 33.
34/54
Bit
setting
Ratio for CURR1
Doc ID 17242 Rev 6
L99MD01
Table 34.
SPI control and status register
Control register 5
Control register 5 (read/write); address 05h
Bit
Name
Comment
15
-
14
-
13
-
12
-
Bit 9
Bit 8
PWM duty cycle
11
-
0
0
15 %
10
-
0
1
30 %
9
PWM duty bit 1
1
0
45 %
8
PWM duty bit 0
1
1
60 %
7
PWM to OUT 8
6
PWM to OUT 7
5
PWM to OUT 6
4
PWM to OUT 5
3
PWM to OUT 4
2
PWM to OUT 3
1
PWM to OUT 2
0
PWM to OUT 1
PWM enable
“0”: PWM disabled for this output
“1”: If the corresponding enable bit is set and the PWM bit is set to “1” the
programmed output is PWM’ed with typical 100 Hz
Doc ID 17242 Rev 6
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SPI control and status register
Table 35.
L99MD01
Control register 6
Control register 6 (read/write); address 06h
Bit
Name
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
Disable OL OUT8
6
Disable OL OUT7
5
Disable OL OUT6
4
Disable OL OUT5
3
Disable OL OUT4
2
Disable OL OUT3
1
Disable OL OUT2
0
Disable OL OUT1
36/54
Comment
Disable the open-load measurement
“0”: open-load is signaled via the corresponding bit in status register 2 and the
global error byte
“1”: in case of an open-load, no register changes. Also the global error register
not changes.
Doc ID 17242 Rev 6
L99MD01
Table 36.
SPI control and status register
Status register 0
Status register 0 (read only); address 10h
Bit
Name
15
HS8
14
LS8
13
HS7
12
LS7
11
HS6
10
LS6
9
HS5
8
LS5
7
HS4
6
LS4
5
HS3
4
LS3
3
HS2
2
LS2
1
HS1
0
LS1
Comment
Overcurrent error detected, driver is deactivated
Table 37.
Status register 1
Status register 1 (read only); address 11h
Bit
Name
15-8
-
7
Open-load Out8
6
Open-load Out7
5
Open-load Out6
4
Open-load Out5
3
Open-load Out4
2
Open-load Out3
1
Open-load Out2
0
Open-load Out1
Comment
-
Open-load detected, information only
No changes if the corresponding disable OL bit (Control register 6) is set
Doc ID 17242 Rev 6
37/54
SPI control and status register
Table 38.
L99MD01
Status register 2
Status register 2 (read only); address 12h
Bit
Name
Comment
15-8
-
7
TSD
Overtemperature detected: all the drivers are switched off
6
TSD warning
Overtemperature warning level detected, information only
5
VS2 UV
VS2 undervoltage
4
VS2 OV
VS2 overvoltage
3
VS UV
VS undervoltage
2
VS OV
VS overvoltage
1
VSB UV
VSB undervoltage
0
VSA UV
VSA undervoltage
38/54
-
Doc ID 17242 Rev 6
L99MD01
7
Application examples
Application examples
Figure 10. Driving 4 bipolar stepper motors simultaneously
$*9
Doc ID 17242 Rev 6
39/54
Application examples
Figure 11.
L99MD01
Driving 2 bipolar stepper motors simultaneously and 3 DC-motors
sequentially
$* 9
40/54
Doc ID 17242 Rev 6
L99MD01
Application examples
Figure 12. Driving 2 bipolar stepper motors simultaneously
$*9
Doc ID 17242 Rev 6
41/54
Application examples
L99MD01
Figure 13. Driving 1 bipolar stepper motor and 2 DC-motors simultaneously
$*9
42/54
Doc ID 17242 Rev 6
L99MD01
Application examples
Figure 14. Driving 3 bipolar stepper motors sequentially
$*9
Doc ID 17242 Rev 6
43/54
Application examples
L99MD01
Figure 15. Driving 4 DC-motors simultaneously
$*9
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Doc ID 17242 Rev 6
L99MD01
Application examples
Figure 16. Driving 3 DC-motors simultaneously and 2 DC-motors sequentially
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Figure 17. Driving 7 DC-motors sequentially
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Application examples
L99MD01
Figure 18. Driving simultaneously 4 unipolar winded stepper motors in bipolar
mode
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Application examples
Figure 19. Cost saving impact using L99MD01 as stepper motor driver inside HVAC systems
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Package and PCB thermal data
L99MD01
8
Package and PCB thermal data
8.1
PowerSSO-36 thermal data
Figure 20. PowerSSO-36 PC board
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Note:
Board finish thickness 1.6 mm +/- 10%; Board double layer and four layers; Board dimension 129 mm x 60 mm;
Board Material FR4; Cu thickness 0.070 mm (outer layers); Cu thickness 0.035mm (inner layers);
Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/-0.08 mm; Cu thickness on vias 0.025 mm;
Footprint dimension 4.1 mm x 6.5 mm
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Package and PCB thermal data
Figure 21. PowerSSO-36 thermal impedance junction ambient
=7+ &:
)RRWSULQW
FP
/D\HU
7LPH V
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Package information
L99MD01
9
Package information
9.1
ECOPACK® package
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
9.2
PowerSSO-36™ mechanical data
Figure 22. PowerSSO-36™ package dimensions
AG00066V1
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Package information
l
Table 39.
PowerSSO-36 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
2.15
-
2.45
A2
2.15
-
2.35
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D(1)
10.10
-
10.50
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
-
2.3
-
G
-
-
0.1
G1
-
-
0.06
H
10.1
-
10.5
h
-
-
0.4
k
0°
-
8°
L
0.55
-
0.85
M
-
4.3
-
N
-
-
10°
O
-
1.2
-
Q
-
0.8
-
S
-
2.9
-
T
-
3.65
-
U
-
1
-
X
4.3
-
5.2
Y
6.9
-
7.5
1. “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm
per side (0.006”).
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Package information
9.3
L99MD01
Packing information
Figure 23. PowerSSO-36 tube shipment (no suffix)
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
GAPGCFT00002
Figure 24. PowerSSO-36 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
GAPGCFT00003
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10
Revision history
Revision history
Table 40.
Document revision history
Date
Revision
22-Mar-2010
1
Initial release.
2
Updated Features list.
Removed Block diagram
Updated following tables:
– Table 1: Device summary
– Table 3: Pin description
– Table 11: Current monitor output
Updated Section 2.3: Standby mode, Section 2.5: SMPS
Switched Mode Power Supply and Section 2.10: VS, VS2, VSA,
VSB monitoring.
Section 9.2: PowerSSO-36™ mechanical data:
– Updated Figure 22: PowerSSO-36™ package dimensions
– Updated Table 39: PowerSSO-36 mechanical data
24-Jan-2011
3
Updated Features list
Updated Figure 2: Power on reset
Table 8: Supply:
– IVS: updated maximum value
– IVSX: updated test condition
Table 9: Overvoltage and undervoltage detection:
– VSUV OFF, VSAUV OFF, VSBUV OFF: updated maximum value
– VSUV hyst, VSAUV hyst, VSBUV OFF, VSBUV hyst, VSOV hyst,
VS2OV hyst: updated minimum value
Table 10: Switches:
– rONLSLC 1-8: updated maximum value
– IQLH, IQLL: updated minimum, typical and maximum values
– IOLDHS1-8, IOLDLSHC1-8, IOLDLSLC1-8: updated test condition,
minimum and maximum values
Table 11: Current monitor output:
– ICURRHS1/2 acc: updated test condition and maximum value
– ICURRLSHC1/2 acc, ICURRLSLC1/2 acc: updated maximum value
Added Table 12: Current monitor dynamic characteristics
Table 13: SMPS switched mode power supply gate driver output:
RSMPS: updated minimun and maximum values
Updated Section 2.9: Temperature warning and thermal
shutdown
Added Chapter 8: Package and PCB thermal data
23-Feb-2011
4
Updated tables Table 12: Current monitor dynamic
characteristics
19-Sep-2013
5
Updated disclaimer.
20-sep-2013
6
Updated disclaimer and revision in all document.
17-May-2010
Changes
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L99MD01
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