L99PM62GXP
Power management IC with LIN and high speed CAN
Features
■
Two 5V voltage regulators for microcontroller
and peripheral supply
■
No electrolytic capacitor required on regulator
outputs
■
Ultra low quiescent current in standby modes
■
Programmable reset generator for power-on
and undervoltage
■
Configurable window watchdog and fail safe
output
■
LIN 2.1 compliant (SAEJ2602 compatible)
transceiver
■
Advanced HS CAN transceiver (ISO 11898-2/5 and SAE J2284 compliant) with local failure
and bus failure diagnosis
■
HS CAN transceiver supports partial
networking
■
Complete 3-channel contact monitoring
interface with programmable cyclic sense
functionality
■
Programmable periodic system wake-up
feature
■
ST SPI interface for mode control and
diagnosis
■
5 fully protected high-side drivers with internal
4-channel PWM generator
■
2 low-side drivers with active Zener clamping
■
4 internal PWM timers
■
2 operational amplifiers with rail-to-rail outputs
(VS) and low voltage inputs
■
Temperature warning and thermal shutdown
PowerSSO-36
Description
The L99PM62GXP is a power management
system IC that provides electronic control units
with enhanced system power supply functionality,
including various standby modes, as well as LIN
and HS CAN physical communication layers. The
device’s two low-drop voltage regulators supply
the system microcontroller and external
peripheral loads such as sensors and provide
enhanced system standby functionality with
programmable local and remote wake-up
capability.
In addition, five high-side drivers, two low-side
drivers and two operational amplifiers increase
the system integration level.
The ST standard SPI interface (3.0) allows control
and diagnosis of the device and enables generic
software development.
Table 1.
Applications
■
Order codes
Package
Automotive ECU's such as door zone and body
control modules
September 2013
Device summary
Tube
PowerSSO-36
Doc ID 17639 Rev 4
L99PM62GXP
Tape and reel
L99PM62GXPTR
1/102
www.st.com
1
Contents
L99PM62GXP
Contents
1
Block diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1
2.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.1
Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.2
Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.3
Increased output current capability for voltage regulator V2 . . . . . . . . . 13
2.1.4
Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.5
Voltage regulator behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1
Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2
Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.3
V1 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.4
VBAT standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.5
Wake up from standby modes
2.2.6
Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.7
Cyclic contact supply
2.2.8
Timer interrupt / wake-up of microcontroller by timer . . . . . . . . . . . . . . . 19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.3
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.4
Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4.1
2.5
Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.1
Single failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.5.2
Multiple failures – entering forced VBAT standby mode . . . . . . . . . . . . . 27
2.6
Reset output (NRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.7
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.8
LIN bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.9
2/102
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8.1
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.8.2
Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.8.3
LIN pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
High speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.9.1
CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.9.2
Wake up (from CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Doc ID 17639 Rev 4
L99PM62GXP
2.10
3
Contents
2.9.3
CAN sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.9.4
CAN receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.9.5
CAN looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Serial peripheral interface (ST SPI standard) . . . . . . . . . . . . . . . . . . . . . . 33
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1
Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.1
VS overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.1.2
Vs undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.2
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 37
3.3
High-side driver outputs
3.4
Low-side driver outputs REL1, REL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.5
SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.4.1
5.5
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.5.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.5.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5.3
Power-on reset (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5.4
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.5.5
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.5.6
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5.7
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.5.8
High-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.5.9
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.5.10
Wake up inputs (WU1... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.11
High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.12
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.13
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Doc ID 17639 Rev 4
3/102
Contents
6
L99PM62GXP
6.2
8
4/102
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.5.15
Inputs TxD_C and TxD_L for Flash mode
. . . . . . . . . . . . . . . . . . . . . . 65
ST SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1
7
5.5.14
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.2
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.3
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1.4
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1.5
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.6
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.1.7
Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . 73
6.1.8
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.1.9
Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . 75
6.1.10
Read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1.11
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.2
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.3
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.2
PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Doc ID 17639 Rev 4
L99PM62GXP
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Wake up sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Persisting fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PWM configuration for high-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Power-on reset (Vs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output (OUT_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Wake up inputs (WU1... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CAN transmit data input: pin TXDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
CAN receive data output: pin RXDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CAN bus common mode stabilization output termination: pin SPLIT . . . . . . . . . . . . . . . . . 56
CAN transmitter and receiver: pins CANH and CANL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
CAN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN transmit data input: pin TXD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN receive data output: pin RXD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LIN pull-up: pin LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Input CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DO output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RXDL/NINT timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Inputs TxD_C and TxD_L for Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Doc ID 17639 Rev 4
5/102
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
6/102
L99PM62GXP
Write command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Write command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Write command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Format of data shifted out at SDO during write cycle: global status register . . . . . . . . . . . 73
Format of data shifted out at SDO during write cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 73
Format of data shifted out at SDO during write cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 73
Read command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Read command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Read command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Format of data shifted out at SDO during read cycle: global status register. . . . . . . . . . . . 75
Format of data shifted out at SDO during read cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 75
Format of data shifted out at SDO during read cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 75
Read and clear status command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Read and clear status command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Read and clear status command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Format of data shifted out at SDO during read and clear status: global status register . . . 76
Format of data shifted out at SDO during read and clear status: data byte 1. . . . . . . . . . . 76
Format of data shifted out at SDO during read and clear status: data byte 2. . . . . . . . . . . 77
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ID-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Silicon version identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
SPI-frame-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI register: CTRL register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI register: STAT register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Overview of control registers data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Control register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Control register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Control register 3: command data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Control register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Control register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Control register 5, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Control register 6: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Control register 6, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Control register 6, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Status register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Status register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Status register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Doc ID 17639 Rev 4
L99PM62GXP
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
List of tables
Status register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Status register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Status register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Doc ID 17639 Rev 4
7/102
List of figures
L99PM62GXP
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
8/102
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage source with external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage source with external PNP and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage source with external NPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage source with external NPN and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-down
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Watchdog in Flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Change watchdog timing within long open window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Change watchdog timing within window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
General procedure to change watchdog timing out of fail safe mode. . . . . . . . . . . . . . . . . 25
Change watchdog timing out of fail safe mode (watchdog failure) . . . . . . . . . . . . . . . . . . . 25
Example: exit fail safe mode from watchdog failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
LIN master node configuration using LIN_PU (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . 30
CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Over voltage and under voltage protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . 36
Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Phase shifted PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Thermal data of PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PowerSSO-36 Thermal Resistance junction to ambient vs PCB copper area (V1 ON) . . . 46
PowerSSO-36 Thermal Impedance junction to ambient vs PCB copper area (single
pulse with V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Watchdog timing (long, early, late and safe window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI – transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
SPI - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
SPI output timing (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI output timing (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SPI – CSN low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 68
Read configuration register(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Write configuration register(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Format of data shifted out at SDO during read and clear status operation . . . . . . . . . . . . 77
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Doc ID 17639 Rev 4
L99PM62GXP
Block diagram and pin descriptions
Figure 1.
Block diagram
9V
/RZ6LGH
P$
2XWSXW&ODPS
7HPS3UHZDUQLQJ
6KXWGRZQ
/RZ6LGH
P$
2XWSXW&ODPS
8QGHUYROWDJH
2YHUYROWDJH
6KXWGRZQ
9
95(*
9P$
1
Block diagram and pin descriptions
9
95(*
9P$
+LJK6LGH
15HVHW
P$
FKDQQHO
3:0*HQHUDWRU
/2*,&
+LJK6LGH
P$
+LJK6LGH
7LPHU
P$
+LJK6LGH
7LPHU
P$
+LJK6LGH
&61
&/.
',
'2
5(/
5(/
23
23
23BRXW
23
23
23BRXW
287B+6
287
287
287)62
P$
287
:DNH8S,Q
:8
:DNH8S,Q
:8
:DNH8S,Q
:8
:LQGRZ
:DWFKGRJ
63,
&$16XSSO\
/,1
/,138
/,1
6$(-
5['B/1,17
+6&$1
,62
7['B&
5['B&
7['B/
/,1FHUWLILHG
$*1'
3*1'
Doc ID 17639 Rev 4
&$1B+
63/,7
&$1B/
$*9
9/102
Block diagram and pin descriptions
Table 2.
L99PM62GXP
Pin definition
Pin
Symbol
1
AGND
Analog ground
2
RxDC
CAN receive data output
3
TxDC
CAN transmit data input
4
CANH
CAN high level voltage I/O
5
CANL
CAN low level voltage I/O
6
SPLIT
CAN reference voltage output, CAN termination
7
CANSUP
CAN supply input; to allow external CAN supply from V1 or V2 regulator.
8
NRESET
NReset output to micro controller; Internal pull-up of typical 100 KΩ (reset state = LOW)
9
V1
Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver
10
V2
Voltage regulator 2 output: 5 V supply for external loads (IR receiver, potentiometer,
sensors) or CAN Transceiver. V2 is protected against reverse supply.
11
TxDL
12
RxDL/NINT
13
OP2+
Non inverting input of operational amplifier 2
14
OP2-
Inverting input of operational amplifier 2
15
OP2_OUT
16
DI
SPI: serial data input
17
DO
SPI: serial data output
18
CLK
SPI: serial clock input
19
CSN
SPI: chip select not input
20…22
WU1…3
23
OP1_OUT
24
OP1-
Inverting input of operational amplifier 1
25
OP1+
Non inverting input of operational amplifier 1
26
OUT4
High-side driver output (7 Ω, typ)
27
OUT3/FSO
28
OUT2
High-side driver output (7 Ω, typ)
29
OUT1
High-side driver output (7 Ω, typ)
30
OUT_HS
31
VS
32
LINPU
33
LIN
34
REL1
10/102
Function
LIN Transmit data input
RxDL -> LIN receive data output
NINT -> indicates local/remote wake-up events or provides a programmable timer
interrupt signal
Output of operational amplifier 2
Wake-up Inputs 1to 3: Input pins for static or cyclic monitoring of external contacts
Output of operational amplifier 1
Configurable as high-side driver output (7 Ω, typ) or fail safe output pin (default)
High-side driver (1 Ω, typ)
Power supply voltage
High-side driver output to switch off LIN master pull up resistor
LIN bus line
Low-side driver output (2 Ω typ)
Doc ID 17639 Rev 4
L99PM62GXP
Table 2.
Block diagram and pin descriptions
Pin definition (continued)
Pin
Symbol
35
REL2
Low-side driver output (2 Ω typ)
36
PGND
Power ground (REL1/2, LIN and CAN GND), to be externally connected to AGND
Figure 2.
Function
Pin connection (top view)
$*1'
3*1'
5['&
5(/
7['&
5(/
&$1+
/,1
&$1/
/,138
63/,7
9V
&$1683
287B+6
15(6(7
287
9
287
9
287)62
7['/
287
5['/1,17
233
233
230
230
23287
23287
:8
',
3RZHU662
:8
'2
:8
&/.
&61
7$% $*1'
Note:
$*9
It is recommended to connect the PGND and AGND pins directly to the TAB.
Doc ID 17639 Rev 4
11/102
Detailed description
L99PM62GXP
2
Detailed description
2.1
Voltage regulators
The L99PM62GXP contains two independent and fully protected low drop voltage
regulators, which are designed for very fast transient response and don’t require electrolytic
output capacitors for stability.
The output voltage is stable with ceramic load capacitors > 220 nF.
2.1.1
Voltage regulator: V1
The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load
current and is mainly intended for supply of the system microcontroller. The V1 regulator is
embedded in the power management and fail-safe functionality of the device and operates
according to the selected operating mode.
It can be used to supply the internal HS CAN Transceiver via the CANSUP pin externally. In
case of a short circuit condition on the CAN bus, the output current of the transmitter is
limited to 100 mA and the transceiver is turned off in order to ensure continued supply of the
microcontroller.
In addition the regulator V1 drives the L99PM62GXP internal 5 V loads. The voltage
regulator is protected against overload and overtemperature. An external reverse current
protection has to be provided by the application circuitry to prevent the input capacitor from
being discharged by negative transients or low input voltage. Current limitation of the
regulator ensures fast charge of external bypass capacitors. The output voltage is stable for
ceramic load capacitors > 220 nF.
If the device temperature exceeds the TSD1 threshold, all outputs (OUTx, RELx, V2, LIN) is
deactivated except V1. Hence the micro controller has the possibility for interaction or error
logging. In case of exceeding TSD2 threshold (TSD2>TSD1), also V1 is deactivated (see
state chart in Chapter 3: Protection and diagnosis). A timer is started and the voltage
regulator is deactivated for tTSD = 1sec. During this time, all other wake up sources (CAN,
LIN, WU1 to3 and wake up of µC by timer) are disabled. After 1 sec, the voltage regulator
tries to restart automatically. If the restart fails 7 times, within one minute, without clearing
and thermal shutdown condition still exists, the L99PM62GXP enters the forced VBAT
standby Mode.
In case of short to GND at “V1” after initial turn on (V1 < 2V for t > tV1short) the L99PM62GXP
enters the forced VBAT standby Mode. Reactivation (wake-up) of the device can be achieved
with signals from CAN, LIN, WU1..3 or periodic wake by timer (see Section 2.2.8: Timer
interrupt / wake-up of microcontroller by timer).
12/102
Doc ID 17639 Rev 4
L99PM62GXP
2.1.2
Detailed description
Voltage regulator: V2
The voltage regulator V2 can supply additional 5 V loads (e.g. logic components or the
integrated HS CAN transceiver or external loads such as sensors or potentiometers). The
maximum continuous load current is 100 mA. The regulator is protected against:
Overload
●
Overtemperature
●
Short circuit (short to ground and battery supply voltage)
●
Reverse biasing
Increased output current capability for voltage regulator V2
For applications which require high output currents, the output current capability of the
regulator can be increased my means of the integrated operational amplifiers and an
external pass transistor.
Figure 3.
Voltage source with external PNP
/ 30
9V
9
&
5
5
5E
23[B287
0-'&
9
&L
23[
5
&
23[
&HP
&
5
5
$*9
Figure 4.
Voltage source with external PNP and current limitation
/ 30
9V
9
5
&
5
%&
5
5E
23[B287
0-'&
2.1.3
●
9
&L
23[
5
&
23[
&HP
5
&
5
$*9
Figure 3 shows a possible configuration with a PNP pass element using voltage regulator 2
to provide the voltage reference for the regulated output voltage V3.
Doc ID 17639 Rev 4
13/102
Detailed description
L99PM62GXP
The Vs operating range for this circuit is 5.5 V to 18 V. It is important the respect the input
common mode range specified for the operational amplifiers.
The output voltage V3 can be calculated using the following formula:
v2 R1 + R2
v 3 = ------ ⋅ --------------------- [ V ]
R2
2
The circuit in Figure 4 provides additional current limitation using an additional PNP
transistor and R6 which allows setting the current limit.
Figure 5.
Voltage source with external NPN
/ 30
9V
9
&
5
23[B287
0-'&
&L
9
5
23[
&
23[
&
5
&HP
5
$*9
Figure 6.
Voltage source with external NPN and current limitation
/ 30
9V
9
&
5
23[B287
0-'&
%&
&L
5
23[
9
5
23[
&
&HP
5
&
5
$*9
Figure 5 shows a possible configuration with an NPN pass element using voltage regulator
2 to provide the voltage reference for the regulated output voltage V3. This circuit requires
fewer components compared to the configuration in Figure 3 but has a limited VS operating
range (6 V to 18 V).
The output voltage V3 can be calculated using the following formula:
v2 R1 + R2
v 3 = ------ ⋅ --------------------- [ V ]
2
R2
The circuit in Figure 6 provides additional current limitation using an additional NPN
transistor and R5 which allows setting the current limit.
14/102
Doc ID 17639 Rev 4
L99PM62GXP
Detailed description
Alternatively, voltage regulator 1 can be used to provide the 5 V reference for this topology.
However, the additional current consumption through R3 and R4 has to be considered in
V1standby mode.
2.1.4
Voltage regulator failure
The V1, and V2 regulator output voltages are monitored.
In case of a drop below the V1, V2 – fail thresholds (V1,2 < 2 V, typ for t > 2 µs), the V1,2-fail
bits are latched. The fail bits can be cleared by a dedicated SPI command.
Short to ground detection
If 4 ms after turn on of the regulator the V1,2 voltage is below the V1,2 fail thresholds,
(independent for V1,2), the L99PM62GXP identifies a short circuit condition at the related
regulator output and the regulator is switched off.
In case of V1 short to GND failure the device enters VBAT standby mode automatically. Bits
Forced VBAT STD2/SHTV1 and V1 fail were set.
In case of a V2 short to GND failure the V2short and V2 fail bit is set.
If the output voltage of the corresponding regulator once exceeded the V1,2 fail thresholds
the short to ground detection is disabled. If a short to ground condition occurs the regulator
outputs switches off due to thermal shutdown (V1 at TSD2; V2 at TSD1).
Doc ID 17639 Rev 4
15/102
Detailed description
L99PM62GXP
2.1.5
Voltage regulator behaviour
Figure 7.
Voltage regulator behaviour and diagnosis during supply voltage ramp-up / rampdown conditions
6SHFLILFDWLRQ3DUDPHWHUV
WXY 9XQGHUYROWDJHILOWHUWLPH
WYIDLO 9IDLOILOWHUWLPH
W YVKRUW 9VKRUWILOWHUWLPH
W55 5HVHWSXOVHUHDFWLRQWLPH
WUG 5HVHWSXOVHGXUDWLRQ
9 V89 9VXQGHUYROWDJHWKUHVKROG
9 SRU 9VSRZHU RQUHVHWWKUHVKROG
9 UWK 9UHVHWWKUHVKROG
9 IDLO 9IDLOWKUHVKROG
9V >9@
9 1 9 '3
9 689
+LJK=*URXQGHG
9 325
3RZHURQ 5HVHWWKUHVKROG
9 $%6PLQ
&RQWURO5HJLVWHUVDUHVHWWRGHIDXOW
YDOXHV
&ROG6WDUWELWLVVHW
9 >9@
W WXY
W!WXY
W!WYIDLO
9 VXY ELWLVWVHW
XV
W!WXY
91
9 57+
9 IDLO
1R5HVHWJHQHUDWHG
1UHVHW>9@
,IW!WYVKRUW
9VKRUWGHWHFWHG
Î 9EDWWVWDQGE\
9 IDLO ELWLVVHW
WUG
WUG
+LJK
W55
W55
/RZ
5HDG &OHDU)62%LW
'LVDEOHG
)DLO6DIH2XWSXW
'LVDEOHG
,QDFWLYH
$FWLYH
,QDFWLYH
&RQWURO5HJLVWHUVDUHVHWWRGHIDXOWYDOXHV
2.2
$*9
Operating modes
The L99PM62GXP can be operated in 4 different operating modes:
●
Active
●
Flash
●
V1 standby
●
VBAT standby
A cyclic monitoring of wake-up inputs and a periodic interrupt/wake-up by timer is available
in standby modes.
2.2.1
Active mode
All functions are available and the device is controlled by the ST SPI Interface.
16/102
Doc ID 17639 Rev 4
L99PM62GXP
2.2.2
Detailed description
Flash mode
To program the system microcontroller, the L99PM62 can be operated in Flash mode where
the internal watchdog is disabled. This mode can also be used for software debugging.
Except for the disabled watchdog, the Flash mode is identical to active mode and all device
features are available.
A transition from Flash mode to V1stby or Vbatstby is not possible.
The mode can be entered if one of the following conditions is applied:
●
VTxDL > VFlash
●
VTxDC > VFlash
At exit from Flash mode (VTxD < VFlash) no NReset pulse is generated and the watchdog
starts with a long open window.
Note:
Setting both TxDL and TxDC to high voltage levels (> VFlash) is not allowed.
Communication at the respective TxD pin is not possible.
2.2.3
V1 standby mode
The transition from active mode to V1 standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the voltage regulator 1 (V1) remains
active. In order to reduce the current consumption, the regulator goes in low current mode
as soon as the supply current of the microcontroller goes below the Icmp current threshold.
At this transition, the L99PM62 also deactivates the internal watchdog.
Relay outputs, LIN and CAN transmitters is switched off in V1 standby mode. High-side
outputs and the V2 regulator remain in the configuration programmed prior to the standby
command.
A cyclic supply of external contacts and a synchronized monitoring of the contact state can
be activated and configured by SPI.
In V1 standby mode various wake up sources can be individually programmed. Each wake
up event puts the device into active mode and forces the RxDL/NINT pin to a low level
indicating the wake-up condition to the microcontroller.
After power ON reset (POR) all wake up sources are activated by default except the
periodic interrupt/wake timer.
With the interrupt timer the micro controller can be forced from ‘stop’ to ‘run’ after a
programmable period. The RxDL/NINT pin is forced low after the timer is elapsed. The
L99PM62GXP enters active mode and is awaiting a valid watchdog trigger.
Both internal timers can be used for this feature.
The interrupt timer (TINT) at pin RxDL/NINT is only available in V1 standby mode.
Note:
Inputs TxDL, TxDC and CSN must be at high level or at high impedance in order to achieve
minimum standby current in V1 standby mode.
Inputs DI and CLK must be at GND or at high impedance to achieve minimum standby
current in V1 standby mode.
Doc ID 17639 Rev 4
17/102
Detailed description
L99PM62GXP
Interrupt
The interrupt signal (linked to RxDL/NINT internally) indicates a wake-up event from V1
standby mode. In case of a wake-up by Wake-up Inputs, activity on LIN or CAN, SPI access
or timer-interrupt the NINT pin is pulled low for 56 µs.
In case of V1 standby mode and (IV1 > Icmp), the device remains in standby mode, the V1
regulator switches to high current mode and the watchdog starts. No Interrupt signal is
generated.
2.2.4
VBAT standby mode
The transition from active mode to VBAT standby mode is initiated by an SPI command.
In VBAT standby mode, the V1 voltage regulator, relay outputs, LIN and CAN transmitters are
switched off. High-side outputs and the V2 regulator remain in the configuration
programmed prior to the standby command.
In VBAT standby mode the current consumption of the L99PM62GXP is reduced to a
minimum level.
Note:
Inputs TXDL, TXDC and CSN must be terminated to GND in VBAT standby to achieve
minimum standby current.
This can be achieved with the internal ESD protection diodes of the microcontroller
(microcontroller is not supplied in this mode; V1 is pulled to GND).
2.2.5
Wake up from standby modes
A wake-up from standby mode switches the device to active mode. This can be initiated by
one or more of the following events:
Table 3.
Wake up sources
Wake up source
Description
LIN bus activity
Can be disabled by SPI
CAN bus activity
Can be disabled by SPI
Level change of WU1 - 3
Can be individually configured or disabled by SPI
IV1 > Icmp
Device remains in V1 standby mode but watchdog is enabled (If
Icmp = 0) and the V1 regulator goes into high current mode (increased
current consumption). No interrupt is generated.
Timer interrupt / wake up
of µC by TIMER
Programmable by SPI
– V1 standby mode: device wakes up and Interrupt signal is generated
at RxDL/NINT when programmable time-out has elapsed
– VBAT standby mode: device wakes up, V1 regulator is turned on and
NReset signal is generated when programmable time-out has elapsed
SPI access
Always active (except in VBAT standby mode)
Wake up event: CSN is low and first rising edge on CLK
To prevent the system from a deadlock condition (no wake up possible) a configuration
where the periodic timer interrupt and wake up by LIN and HS CAN are disabled, is not
18/102
Doc ID 17639 Rev 4
L99PM62GXP
Detailed description
allowed. The default configuration is entered for all wake-up sources in case of such an
invalid setting.
All wake-up events from V1 standby mode (except IV1 > Icmp) are indicated to the
microcontroller by a low-pulse at RxDL/NINT (duration: 56 µs).
Wake-up from V1 standby by SPI Access might be used to check the interrupt service
handler.
2.2.6
Wake-up inputs
The de-bounced digital inputs WU1 to WU3 can be used to wake up the L99PM62GXP from
standby modes. These inputs are sensitive to any level transition (positive and negative
edge)
For static contact monitoring, a filter time of 64 µs is implemented at WU1-3. The filter is
started when the input voltage passes the specified threshold.
In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a
cyclic sense functionality is implemented. This feature allows periodical activation of the
wake-up inputs to read the status of the external contacts. The periodical activation can be
linked to Timer1 or Timer2 (see Section 2.2.7: Cyclic contact supply ). The input signal is
filtered with a filter time of 16 µs after a programmable delay (80 µs or 800 µs) according to
the configured timer on-time. A wake-up is processed if the status has changed versus the
previous cycle.
The outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the
timer setting according to the cyclic monitoring of the wake-up inputs.
If the wake-up inputs are configured for cyclic sense mode the input filter timing and input
filter delay (WUx_filt in control register 2) must correspond to the setting of the high-side
output which supplies the external contact switches (OUTx in control register 0).
In standby mode, the inputs WU1-3 are SPI configurable for pull-up or pull-down current
source configuration according to the setup of the external. In active mode the inputs have a
pull down resistor.
In active mode, the input status can be read by SPI (Status Register 2). Static sense should
be configured (Control Register 2) before the read operation is started (In cyclic sense
configuration, the input status is updated according to the cyclic sense timing; Therefore,
reading the input status in this mode may not reflect the actual status).
2.2.7
Cyclic contact supply
In V1 standby and VBAT standby modes, any high-side driver output (OUT1..4, OUTHS) can
be used to periodically supply external contacts.
The timing is selectable by SPI
Timer 1: period is X s. The on-time is 10 ms resp. 20 ms: With X ∈ {1, 2, 3, 4 s}
Timer 2: period is X ms. The on-time is 100 µs resp. 1ms: With X ∈ {10, 20, 50, 200 ms}
2.2.8
Timer interrupt / wake-up of microcontroller by timer
During standby modes the cyclic wake up feature, configured via SPI, allows waking up the
µC after a programmable timeout according to timer1 or timer2.
Doc ID 17639 Rev 4
19/102
Detailed description
L99PM62GXP
From V1 standby mode, the L99PM62GXP wakes up (after the selected timer has elapsed)
and sends an interrupt signal (via RxDL/NINT pin) to the µC. The device enters active mode
and the watchdog is started with a long open window. The microcontroller can send the
device back into V1 standby after finishing its tasks.
From VBAT standby mode, the L99PM62GXP wakes up (after the selected timer has
elapsed), turns on the V1 regulator and provides an NReset signal to the µC. The device
enters active mode and the watchdog is started with a long open window. The
microcontroller can send the device back into VBAT standby after finishing its tasks.
2.3
Functional overview (truth table)
Table 4.
Functional overview (truth table)
Operating modes
Function
Comments
V1-standby
static mode
VBAT-standby
static mode
(cyclic sense)
(cyclic sense)
Active mode
On
On(1)
On/ Off (2)
On(2)
On
On
On
Off (On: I_V1 > IcmpOff
threshold and Icmp = 0)
Off
Active(3)
Active(3)
On / Off
On(2) / Off
On(2) / Off
Relay driver
On
Off
Off
Operational amplifiers
On
Off
Off
On
Off(4)
Off(4)
On
Off(4)
Off(4)
OUT3/FSO Off(5)
OUT3/FSO Off(5)
OUT3/FSO Off(5)
Oscillator
On
(6)
(6)
Vs-monitor
On
(7)
(7)
Voltage-regulator, V1
Voltage-regulator, V2
VOUT = 5 V
VOUT = 5 V
Reset-generator
Window watchdog
V1 monitor
Wake up
HS-cyclic supply
LIN
Oscillator time
base
LIN 2.1
HS_CAN
FSO (if configured by
SPI), active by default
Fail safe
output
Off
/ Off
On(2) / Off
Off
1. Supply the processor in low current mode.
2. Only active when selected via SPI.
3. Unless disabled by SPI.
4. The bus state is internally stored when going to standby mode. A change of bus state leads a wake-up after exceeding of
internal filter time (if wake-up by LIN or CAN is not disabled by SPI).
5. ON in fail-safe condition: If Standby mode is entered with active Fail Safe mode, the output remains ON in Standby mode.
6. Activation = ON if cyclic sense is selected.
7. cyclic activation = pulsed ON during cyclic sense.
20/102
Doc ID 17639 Rev 4
L99PM62GXP
Figure 8.
Detailed description
Operating modes
9V!9SRU
9EDWVWDUWXS
$OOUHJLVWHUV
6HWWRGHIDXOW
&KLS5HVHWELW *65ELW
DFWLYH
97;'/!9IODVK
25
97;'&!9IODVK
)ODVK0RGH
:DWFKGRJ 2))
97;'/ 9IODVK
$1'
97;'& 9IODVK
$FWLYH
0RGH
97;'/!9IODVK
25
97;'&!9IODVK
63,FRPPDQG
25
[7KHUPDO6KXWGRZQ
25
9VKRUWWR*1'
9 9IRUPVDIWHUVZLWFK21
25
[:')DLOXUH
9 21
5HVHW*HQHUDWRU DFWLYH
:DWFKGRJ DFWLYH
:DNHXS
(YHQW
97;'/!9IODVK
25
97;'&!9IODVK
96WDQGE\
0RGH
9EDW6WDQGE\
0RGH
9 2))
5HVHW*HQHUDWRU 2)) 1UHVHW ORZ
:DWFKGRJ 2))
63,FRPPDQG
:DNHXS
(YHQW
[7KHUPDO6KXWGRZQ76'
25
[:'IDLO
9 21
5HVHW*HQHUDWRU DFWLYH
:DWFKGRJ
2)) LI,Y ,FPSRU,&03
$*9
2.4
Configurable window watchdog
During normal operation, the watchdog monitors the micro controller within a programmable
trigger cycle: (10 ms, 50 ms, 100 ms, 200 ms)
In VBAT standby and Flash program modes, the watchdog circuit is automatically disabled.
In V1 standby mode a wake up by timer is programmable in order to wake up the µC (see
Section 2.2.8: Timer interrupt / wake-up of microcontroller by timer). After wake-up, the
watchdog starts with a long open window. After serving the watchdog, the µC may send the
device back to V1 standby mode.
Doc ID 17639 Rev 4
21/102
Detailed description
L99PM62GXP
After power-on or standby mode, the watchdog is started with a long open window (65 ms
nominal). The long open window allows the micro controller to run its own setup and then to
trigger the watchdog via the SPI. The trigger is processed when the CSN input becomes
HIGH after the transmission of the SPI word.
Writing ‘1’ to the watchdog trigger bit terminates the long open window and start the window
watchdog (the timing is programmable by SPI). Subsequently, the micro controller has to
serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer
to Figure 29). A correct watchdog trigger signal immediately starts the next cycle.
After 8 watchdog failures in sequence, the V1 regulator is switched off for 200ms. If
subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off
and the device goes into VBAT standby mode until a wakeup occurs.
In case of a watchdog failure, the outputs (RELx, OUTx, V2) are switched off and the device
enters fail-safe mode (i.e. all control registers are set to default values except the ‘OUT3
control bit’).
The following diagrams illustrate the watchdog behavior of the L99PM62. The diagrams are
split into 3 parts. First diagram shows the functional behavior of the watchdog without any
error. The second diagram covers the behavior covering all the error conditions, which can
affect the watchdog behavior. Third diagram shows the transition in and out of Flash mode.
All 3 diagrams can be overlapped to get all the possible state transitions under all
circumstances. For a better readability, they were split in normal operating, operating with
errors and Flash mode.
Figure 9.
Watchdog in normal operating mode (no errors)
$FWLYHPRGH
ORQJ
RSHQ
ZLQGRZ
9!9UVWWKU
JR6WDQGE\
:'
2))
75,* Ã
SURSSHUWULJJHULQ
:LQGRZ
0RGH
9%$76WDQGE\
96WDQGE\ , 9 ,&03
JR6WDQGE\
:LQGRZPRGH
$FWLYHPRGH
$*9
22/102
Doc ID 17639 Rev 4
L99PM62GXP
Detailed description
Figure 10. Watchdog with error conditions
:'IDLO
76'
ORQJ
RSHQ
ZLQGRZ
$FWLYHPRGH
9!9UWK
75,* Ã
SURSSHUWULJJHULQ
IRUFHG9%$7
9 9UWK
:'IDLO
76'
:'
2))
9%$76WDQGE\
96WDQGE\ , 9 ,&03
9 9UWK
:LQGRZ
0RGH
:LQGRZPRGH
IRUFHG9%$7 [:'IDLO
[76'
6KRUW9
$FWLYHPRGH
$* 9
Figure 11.
Watchdog in Flash mode
$FWLYHPRGH
ORQJ
RSHQ
ZLQGRZ
([LW)/$6+PRGH
)/$6+PRGH
$FWLYHPRGH
:LQGRZ
0RGH
:'
2))
)/$6+PRGH
)/$6+PRGH
$*9
2.4.1
Change watchdog timing
There are 4 programmable watchdog timings available, which represent the nominal trigger
time in window mode. To change the watchdog timing, a new timing has to be written by
SPI. The new timing gets active with the next valid watchdog trigger. The following figures
illustrate the sequence, which is recommended to use, changing the timing within long open
window and within window mode.
Doc ID 17639 Rev 4
23/102
Detailed description
L99PM62GXP
Figure 12. Change watchdog timing within long open window
:DWFKGRJ
0RGH
ZLQGRZPRGH
>WLPLQJDVSURJUDPPHGLQSUHYLRXV63,FRPPDQG HJPV@
ORQJRSHQZLQGRZ
:'WLPLQJ>HJPV@
&61
63,
&RPPDQG
ZULWHRSHUDWLRQ
&WUO5HJ :'7LPH
>HJPV@
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
UHDGRSHUDWLRQ
&WUO5HJ
63,
)HHGEDFN
)HHGEDFN
)62
ZULWHRSHUDWLRQDFFHSWHG
)HHGEDFN
FKHFN)62
FKDQJHWLPLQJIRU:'
)HHGEDFN
FKHFN)62
FKHFN:'WLPH
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
$*9
Figure 13. Change watchdog timing within window mode
:DWFKGRJ
0RGH
ZLQGRZPRGH>PV@
ZLQGRZPRGH>PV@
:'WLPH>PV@
&61
63,
&RPPDQG
63,
)HHGEDFN
:'WLPH>PV@
ZULWHRSHUDWLRQ
&WUO5HJSURSHUWULJJHU
ZULWHRSHUDWLRQ
&WUO5HJ :'7LPH
>HJPV@
ZULWHRSHUDWLRQ
&WUO5HJSURSHUWULJJHU
UHDGRSHUDWLRQ
&WUO5HJ
)HHGEDFN
)62
ZULWHRSHUDWLRQDFFHSWHG
)HHGEDFN
FKHFN)62
FKDQJHWLPLQJIRU:'
)HHGEDFN
FKHFN)62
FKHFN:'WLPH
ZULWHRSHUDWLRQ
&WUO5HJSURSSHUWULJJHU
$*9
If the device is in fail-safe mode, the control registers are locked for writing. To change the
watchdog timing out of fail-safe mode, first the fail-safe condition must be solved, respective
confirmed from the microcontroller. Afterwards the new watchdog timing can be
programmed using the sequence from Figure 14. Since the actions to remove, a fail-safe
condition can differ from the root cause of the fail safe the following diagram shows the
general procedure how to change the watchdog timing out of fail-safe mode. Figure 15
shows the procedure to change watchdog timing with a previous watchdog failure, since this
is a special fail-safe scenario.
24/102
Doc ID 17639 Rev 4
L99PM62GXP
Detailed description
Figure 14. General procedure to change watchdog timing out of fail safe mode
)DLO6DIH0RGHDFWLYH
:DWFKGRJ
0RGH
)DLO6DIH0RGHLQDFWLYH
ZLQGRZPRGH
>WLPLQJDVSURJUDPPHGLQSUHYLRXV63,FRPPDQG HJPV@
ORQJRSHQZLQGRZ
:'WLPH>HJPV@
&61
63,
&RPPDQG
ZULWHRSHUDWLRQ
&WUO5HJ :'7LPH
>HJPV@
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
UHDGRSHUDWLRQ
&WUO5HJ
63,
)HHGEDFN
)HHGEDFN
)62
ZULWHRSHUDWLRQDFFHSWHG
)HHGEDFN
FKHFN)62
FKDQJHWLPLQJIRU:'
)HHGEDFN
FKHFN)62
FKHFN:'WLPH
$FWLRQVWRH[LW
)DLOVDIH0RGH
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
3URFHGXUHWR:ULWHQHZ:DWFKGRJWLPLQJ
$*9
Figure 15. Change watchdog timing out of fail safe mode (watchdog failure)
)DLO6DIH0RGHDFWLYH
:DWFKGRJ
0RGH
)DLO6DIH0RGHLQDFWLYH
ORQJRSHQZLQGRZ
ZLQGRZPRGH
>WLPLQJDVSURJUDPPHGLQSUHYLRXV63,FRPPDQG HJPV@
ZLQGRZPRGH>PV@
:'WLPH>PV@
:'WLPH>HJPV@
&61
63,
&RPPDQG
ZULWHRSHUDWLRQ
&WUO5HJ :'7LPH
>HJPV@
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
UHDGRSHUDWLRQ
DQ\YDOLGDGGUHVV
ZULWHRSHUDWLRQ
&WUO5HJ :'7LPH
>HJPV@
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
UHDGRSHUDWLRQ
&WUO5HJ
63,
)HHGEDFN
)HHGEDFN
)62
ZULWHRSHUDWLRQEORFNHG
)HHGEDFN
)62
SURYLGHSURSSHUWULJJHU
)HHGEDFN
FKHFN)62
TXLWIDLOVDIHPRGH
)HHGEDFN
)62
ZULWHRSHUDWLRQDFFHSWHG
)HHGEDFN
FKHFN)62
FKDQJHWLPLQJIRU:'
)HHGEDFN
FKHFN)62
FKHFN:'WLPH
$FWLRQVWRH[LW
)DLOVDIH0RGH
ZULWHRSHUDWLRQ
&WUO5HJSURSHUWULJHU
3URFHGXUHWR:ULWHQHZ:DWFKGRJWLPLQJ
$*9
2.5
Fail safe mode
2.5.1
Single failures
L99PM62GXP enters fail safe mode in case of:
●
Watchdog failure
●
V1 turn on failure
–
V1 short (V1 < V1fail for t > tV1short)
●
V1 undervoltage (V1 < Vrth for t > tUV1)
●
Thermal shutdown TSD2
●
SPI failure
–
DI stuck to GND or VCC (SPI frame = ’00 00 00’ or ‘FF FF FF’)
Doc ID 17639 Rev 4
25/102
Detailed description
L99PM62GXP
The fail safe functionality is also available in V1 standby mode. During V1 standby mode the
fails safe mode is entered in the following cases:
●
V1 undervoltage (V1 < Vrth for t > tUV1)
●
Watchdog failure (if watchdog still running due to IV1 > Icmp)
●
Thermal shutdown TSD2
In fail safe mode the L99PM62 returns to a default. The fail safe condition is indicated to the
remaining system in the global status register. The conditions during fails safe mode are:
●
All outputs are turned off
●
All control registers are set to default values (except OUT3/FSO configuration)
●
Write operations to control registers are blocked until the fail safe condition is cleared
(see Table 5)
●
LIN and HS CAN transmitter, OpAmps and SPI remain on
●
Corresponding failure bits in status registers are set.
●
FSO Bit (Bit 0 global status register) is set
●
OUT3/FSO is activated if configured as fail safe output
If OUT3 is configured as FSO, the internal fail safe mode can be monitored at OUT3 (highside driver is turned on in fail-safe mode). Self protection features for OUT3 when
configured as FSO are active (see Section 3.3: High-side driver outputs ).
OUT3 is configured as fail safe output by default. It can be configured to normal high-side
driver operation by SPI. It this case, the configuration remains until Vs power on.
If the fail safe mode was entered it keeps active until the fail safe condition is removed and
the fail safe was read by spi. depending on the root cause of the fail safe operation, the
actions to exit fail safe mode are as shown in the following table.
Table 5.
Fail safe conditions and exit modes
Failure source
Failure condition
Diagnosis
Exit from fail-safe mode
Watchdog early write
failure or expired
window
Fail-safe = 1
WDfail = n+1
TRIG = 1 during LOWi and
read fail-safe bit
Short at turn-on
Fail-safe = 1
Forced Sleep TSD2/SHTV1 = 1
Read&Clear SR3 after wake
Undervoltage
Fail-safe = 1
V1fail = 1(1)
V1 > Vrth
Read Fail-safe bit
Temperature
Tj > TSD2
Fail-safe = 1
TW = 1
TSD1 = 1
TSD2 = 1
Tj < TSD2
Read&Clear SR3
SPI
DI short to GND or VCC
Fail-safe = 1
Valid SPI command
µC (oscillator)
V1
1. if V1 < V1fail (for t > tV1fail)
The fail-safe bit is located in the global status register (Bit 0).
26/102
Doc ID 17639 Rev 4
L99PM62GXP
2.5.2
Detailed description
Multiple failures – entering forced VBAT standby mode
If the fail-safe condition persists and all attempts to return to normal system operation fail,
the L99PM62 enters the forced VBAT standby mode in order to prevent damage to the
system. The forced VBAT standby mode can be terminated by any regular wake-up event.
The root cause of the forced VBAT standby is indicated in the SPI status registers
The forced VBAT standby mode is entered in case of:
Table 6.
●
Multiple watchdog failures: forced sleep WD = 1 (15x watchdog failure)
●
Multiple thermal shutdown 2: forced sleep TSD2/SHTV1 = 1 (7 x TSD2)
●
V1 short at turn-on: forced sleep TSD2/SHTV1 = 1 (V1 < V1fail for t > tV1fail)
Persisting fail safe conditions and exit modes
Failure source
Failure condition
Diagnosis
Exit from fail-safe mode
µC (oscillator)
15 consecutive
watchdog failures
Fail-safe = 1
ForcedSleepWD = 1
Wake-up
TRIG = 1 during LOWi
read & clear SR3
V1
short at turn-on
Fail-safe = 1
ForcedSleepTSD2/SHTV1 = 1
Read&clear SR3 after wake-up
7 times TSD2
Fail-safe = 1
TW = 1
TSD1 = 1
TSD2 = 1
ForcedSleepTSD2/SHTV1 = 1
Read&clear SR3 after wake-up
Temperature
Figure 16. Example: exit fail safe mode from watchdog failure
)DLO6DIH0RGHDFWLYH
:DWFKGRJ
0RGH
ORQJRSHQZLQGRZ
)DLO6DIH0RGHLQDFWLYH
ZLQGRZPRGH
&61
63,
&RPPDQG
ZULWHRSHUDWLRQ
&WUO5HJ :'7LPH
>HJPV@
ZULWHRSHUDWLRQ
&WUO5HJ7ULJ
UHDGRSHUDWLRQ
DQ\YDOLGDGGUHVV
63,
)HHGEDFN
)HHGEDFN
)62
ZULWHRSHUDWLRQEORFNHG
)HHGEDFN
)62
SURYLGHSURSSHUWULJJHU
)HHGEDFN
FKHFN)62
TXLWIDLOVDIHPRGH
$*9
Doc ID 17639 Rev 4
27/102
Detailed description
2.6
L99PM62GXP
Reset output (NRESET)
If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is pulled up by internal pull up resistor to V1 voltage after a reset delay time (trd).
This is necessary for a defined start of the micro controller when the application is switched
on. Since the NRESET output is realized as an open drain output it is also possible to
connect an external NRESET open drain NRESET source to the output. It must be
considered that as soon the NRESET is released from the L99PM62 the Watchdog timing
starts.
A reset pulse is generated in case of:
●
V1 drops below Vrth (configurable by SPI) for t > tUV1
●
Watchdog failure
Note:
An external pull-up resistor (1kΩ) to V1 is recommended in order to ensure ILOAD1 > Icmp
during reset condition
2.7
Operational amplifiers
The operational amplifiers are especially designed to be used for sensing and amplifying the
voltage drop across ground connected shunt resistors. Therefore the input common mode
range includes -0.2 V to 3 V.
The operational amplifiers are designed for -0.2 V to +3 V input voltage swing and rail-to-rail
output voltage range.
All pins (positive, negative and outputs) are available to be able to operate in non-inverting
and inverting mode. Both operational amplifiers are on-chip compensated for stability over
the whole operating range within the defined load impedance.
The operational amplifiers may also be used to setup an additional high current voltage
source with an external pass element. Refer to Section 2.1.3 for a detailed description.
2.8
LIN bus interface
Features
28/102
●
Speed communication up to 20 kbit/s.
●
LIN 2.1 compliant (SAEJ2602 compatible) transceiver.
●
Function range from +40 V to -18 V DC at LIN pin.
●
GND disconnection fail safe at module level.
●
Off mode: does not disturb network.
●
GND shift operation at system level.
●
Micro controller Interface with CMOS compatible I/O pins.
●
Internal pull up resistor.
●
Internal high-side switch to disconnect master pull-up resistor in case of short circuit of
bus signal.
●
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2.
●
Matched output slopes and propagation delay.
Doc ID 17639 Rev 4
L99PM62GXP
Detailed description
In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
Note:
Use of master pull-up switch is optional.
2.8.1
Error handling
The L99PM62GXP provides the following 3 error handling features which are not described
in the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers / micro
controllers to switch the application back to normal operation mode.
At VS > Vpor (i.e. Vs power-on reset threshold), the LIN transceiver is enabled. The LIN
transmitter is disabled in case of the following errors:
●
Dominant TxDL time out
●
LIN permanent recessive
●
Thermal shutdown 1
●
VS over/undervoltage
●
The LIN receiver is not disabled in case of any failure condition.
Dominant TxDL time out
If TXDL is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the
status bit is latched and can be read and optionally cleared by SPI. The transmitter remains
disabled until the status register is cleared. This feature can be disabled via SPI.
Permanent recessive
If TXDL changes to dominant (low) state but RXDL signal does not follow within 40 µs the
transmitter is disabled, the status bit is latched and can be read and optionally cleared by
SPI. The transmitter remains disabled until the status register is cleared.
Permanent dominant
If the bus state is dominant (low) for more than 12 ms a permanent dominant status is
detected. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter is not disabled.
2.8.2
Wake up (from LIN)
In standby mode the L99PM62GXP can receive a wake up from LIN bus. For the wake up
feature the L99PM62GXP logic differentiates two different conditions.
Normal wake up
Normal wake up can occur when the LIN transceiver was set in standby mode while LIN
was in recessive (high) state. A dominant level at LIN for tlinbus, switches the L99PM62GXP
to active mode.
Wake up from short to GND condition
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for tlinbus, switches the L99PM62GXP to active mode.
Note:
A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.
Doc ID 17639 Rev 4
29/102
Detailed description
2.8.3
L99PM62GXP
LIN pull-up
The master node pull-up resistor (1 kΩ) can be connected to VS using the internal LIN_PU
high-side switch. This high-side switch can be controlled by SPI in order to allow
disconnection of the pull-up resistor in case of LIN bus short to GND conditions.
Figure 17. LIN master node configuration using LIN_PU (optional)
9V
/,1
FRQWURO
7 6:
FRQWURO
/,138
N
N
/,1
0DVWHUQRGH
SXOOXS
*QG
$*9
LIN_PU high-side driver characteristics:
2.9
●
Activated by default and can be turned off by SPI command (CR4).
●
Remains active in standby modes.
●
Switch off only in case of over temperature (TSD2 = thermal shutdown #2).
●
No over current protection.
●
Typical RDSon, 10 Ω.
High speed CAN bus transceiver
General requirements
30/102
●
Communication speed up to 1 Mbit/s.
●
ISO 11898-2 and ISO 11898-5 compliant
●
SAE J2284 compliant
●
Function range from -27 V to +40 V DC at CAN pins.
●
GND disconnection fail safe at module level.
●
GND shift operation at system level.
●
Micro controller Interface with CMOS compatible I/O pins.
●
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
●
Matched output slopes and propagation delay
●
Split output pin for stabilizing the recessive bus level
●
Receive-only mode available
Doc ID 17639 Rev 4
L99PM62GXP
Detailed description
In order to further reduce the current consumption in standby mode, the integrated CAN bus
interface offers an ultra low current consumption.
2.9.1
CAN error handling
The L99PM62GXP provides the following 4 error handling features which are not described
in the ISO 11898-2/ISO 11898-5, but are realized in different stand alone CAN
transceivers/micro controllers to switch the application back to normal operation mode.
At VS > Vpor (i.e. VS power-on reset threshold), the CAN transceiver is enabled. It remains
enabled also in case of VS overvoltage and undervoltage conditions.
The CAN transmitter is disabled only in case of the following errors:
●
Dominant TxDC time out
●
CAN permanent recessive
●
RxDC permanent recessive
●
Thermal shutdown 1
The CAN receiver is not disabled in case of any failure condition.
Dominant TxDC time out
If TXDC is in dominant state (low) for t > tdom(TxD) the transmitter is disabled, status bit is
latched and can be read and optionally cleared by SPI. The transmitter remains disabled
until the status register is cleared.
CAN permanent recessive
If TXDC changes to dominant (low) state but CAN bus does not follow for 4 times, the
transmitter is disabled, status bit is latched and can be read and optionally cleared by SPI.
The transmitter remains disabled until the status register is cleared.
CAN permanent dominant
If the bus state is dominant (low) for t > tCAN a permanent dominant status is detected. The
status bit is latched and can be read and optionally cleared by SPI. The transmitter is not
disabled.
RXDC permanent recessive
If RXDC pin is clamped to recessive (high) state, the controller is not able to recognize a bus
dominant state and could start messages at any time, which results in disturbing the overall
bus communication. Therefore, if RXDC does not follow TXDC for 4 times the transmitter is
disabled. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter remains disabled until the status register is cleared.
2.9.2
Wake up (from CAN)
When the L99PM62GXP is in standby mode with CAN wake up option enabled, the CAN
bus traffic is detected. For the wake up feature the L99PM62GXP logic differentiates
different conditions. During V1 Standby mode RXDC output is kept at recessive level.
Independent from the wakeup pattern selected and independent from the previous Standby
mode, the RXDC reflect immediately the bus state after the wakeup. This feature allows
implementation of a ‘partial networking’ functionality controlled by the system
microcontroller.
Doc ID 17639 Rev 4
31/102
Detailed description
L99PM62GXP
Normal pattern wake up
Normal pattern wake up can occur when CAN pattern wake up option is enabled and the
CAN transceiver was set in standby mode while CAN bus was in recessive (high) state or
dominant (low) state. In order to wake up the L99PM62GXP, the following criteria must be
fulfilled:
●
The CAN interface wake-up receiver must receive a series of two consecutive valid
dominant pulses, each of which must be longer than 2 µs
●
The distance between 2 pulses must be longer than 2 µs.
●
The two pulses must occur within a time frame of 1.0 ms
Wake up from short to GND condition
Even if CAN pattern wake up option is enabled, but the CAN transceiver was set in standby
mode after a qualified permanent dominant state, recessive level at CAN, switches the
L99PM62GXP to active mode.
No pattern wake up
If the CAN pattern wake up option is disabled, any transition either dominant (low) state to
recessive (high) state or recessive (high) state to dominant (low) state switches the
L99PM62GXP to active mode (after a filtering time of 2 µs).
Note:
A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.
Figure 18. CAN wake up capabilities
3DWWHUQ:DNHXS
1RSDWWHUQ:DNHXS
PV
!XV
!XV
!XV
!XV
&$15;
67$7(
&$15;
$&7,9(
67$1'%<
$&7,9(
67$7(
$&7,9(
67$1'%<
$&7,9(
6WDQGDUGZDNHXS
6WDQGDUGFDQSDWWHUQZDNHXS
PV
!XV
!XV
!XV
!XV
&$15;
67$7(
&$15;
$&7,9(
67$1'%<
$&7,9(
67$7(
$&7,9(
&$1SDWWHUQZDNHXSZLWKGRPLQDQWEHIRUH6WDQGE\
!SHUPDQQHQWGRPLQDQWILOWHUWLPH
$&7,9(
&$1ZDNHXSZLWKGRPLQDQWEHIRUH6WDQGE\
!SHUPDQQHQW
GRPLQDQWILOWHUWLPH
!XV
&$15;
67$7(
67$1'%<
!XV
&$15;
$&7,9(
67$1'%<
$&7,9(
67$7(
&$1SDWWHUQZDNHXSZLWKSHUPDQHQWGRPLQDQW
$&7,9(
67$1'%<
$&7,9(
&$1ZDNHXSZLWKSHUPDQHQWGRPLQDQW
$*9
Note:
32/102
Pictures above illustrate the wake up behaviour from V1 standby mode. For wake up from
VBAT standby mode an NReset pulse is generated instead of the RXDL (Interrupt) signal.
Doc ID 17639 Rev 4
L99PM62GXP
2.9.3
Detailed description
CAN sleep mode
During active mode it is possible to deactivate the CAN transceiver with a dedicated SPI
command (CR4, CAN_act = 0). The CAN transceiver remains deactivated until it is
activated again. With a deactivated CAN the receiver input termination network is
disconnected from the bus and the CANH, CANL bus lines is driven to GND. The SPLIT
output is also deactivated in this case.
2.9.4
CAN receive only mode
With the CAN_rec_only bit in control register 4 it is possible to disable the CAN transmitter
in active mode. In this mode it is possible to listen to the bus but not sending to it. The
receiver termination network is still activated in this mode.
2.9.5
CAN looping mode
If the CAN_Loop_en bit in control register 4 is set the TXDC input is mapped directly to the
RXDC pin. This mode can be used in combination with the CAN receive only mode, to run
diagnosis for the CAN protocol handler of the micro controller.
2.10
Serial peripheral interface (ST SPI standard)
A 24 bit SPI is used for bi-directional communication with the micro controller.
During active mode, the SPI
●
Triggers the watchdog
●
Controls the modes and status of all L99PM62GXP modules (incl. input and output
drivers)
●
Provides driver output diagnostic
●
Provide L99PM62GXP diagnostic (incl. overtemperature warning, L99PM62GXP
operation status)
The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible
output pins and one input pin is needed to communicate with the device. A fault condition
can be detected by setting CSN to low. If CSN = 0, the DO-pin reflects the global error flag
(fault condition) of the device.
Chip select not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal activates the output driver and a
serial communication can be started. The state during CSN = 0 is called a communication
frame.
If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not block
the signal line for other SPI nodes.
Doc ID 17639 Rev 4
33/102
Detailed description
L99PM62GXP
Serial data in (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI is
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register is transferred to Data
Input Register. The writing to the selected data input register is only enabled if exactly 24
bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame is ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Serial data out (DO)
The data output driver is activated by a logical low level at the CSN input and goes from high
impedance to a low or high level depending on the global error flag (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin transfers the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK shifts the next bit out.
Serial clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the
falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 1MHz.
34/102
Doc ID 17639 Rev 4
L99PM62GXP
Protection and diagnosis
3
Protection and diagnosis
3.1
Power supply fail
Over and under-voltage detection on Vs
3.1.1
VS overvoltage
If the supply voltage Vs reaches the over voltage threshold (VSOV):
●
3.1.2
Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).
CAN is not disabled. Recovery of outputs when the overvoltage condition disappears is
depending on the setting of VLOCKOUT_EN bit in Control Register 4.
–
VLOCKOUT_EN = 1: Outputs are off until read and clear SR3.
–
VLOCKOUT_EN = 0: Outputs switch automatically on when overvoltage condition
disappears.
●
The over voltage bit is set and can be cleared with a ‘Read and Clear’ command. The
overvoltage bit is removed automatically if VLOCKOUT_EN = 0 and the overvoltage
condition disappears.
●
Outputs REL1,2 can be excluded from a shutdown in case of overvoltage by SPI
(LSOVUV_ Shutdown_en in CR4)
Vs undervoltage
If the supply voltage Vs drops below the under voltage threshold voltage (VSUV)
●
Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).
CAN is not disabled. Recovery of outputs when the undervoltage condition disappears
is depending on the setting of VLOCKOUT_EN bit.
VLOCKOUT_EN = 1: Outputs are off until read and clear SR3.
VLOCKOUT_EN = 0: Outputs switch on automatically when undervoltage condition
disappears.
●
The undervoltage bit is set and can be cleared with a ‘Read and Clear’ command. The
undervoltage bit is removed automatically if VLOCKOUT_EN = 0 and the undervoltage
condition disappears
●
Outputs REL1,2 can be excluded from a shutdown in case of undervoltage by SPI
(LSOVUV_shutdown_en in CR4)
Doc ID 17639 Rev 4
35/102
Protection and diagnosis
L99PM62GXP
Figure 19. Over voltage and under voltage protection and diagnosis
$FWLYH
0RGH
6WDQGE\0RGHV
GXULQJF\FOLFVHQVH
9V8QGHUYROWDJH
9V 9VXY
9V2YHUYROWDJH
9V!9VRY
9V 9VRY$1'Ã5HDGDQG&OHDU¶
25
9V 9VRY$1'9ORFNRXW
9V!9VXY$1'Ã5HDGDQG&OHDU¶
25
9V!9VXY$1'9ORFNRXW
9V2YHUYROWDJH
6KXWGRZQ
9V8YHUYROWDJH
6KXWGRZQ
$OORXWSXWV KLJK,PSHGDQFH
H[FHSW5(/RXWSXWVLI
/6BRYXY
$OORXWSXWV KLJK,PSHGDQFH
H[FHSW5(/RXWSXWVLI
/6BRYXY
'LDJQRVLV 29
'LDJQRVLV 89
$*9
36/102
Doc ID 17639 Rev 4
L99PM62GXP
3.2
Protection and diagnosis
Temperature warning and thermal shutdown
Figure 20. Thermal shutdown protection and diagnosis
7M!76'
76'
76'
$OORXWSXWV RII
9 RIIIRUVHF
7!VHF
'LDJQRVLV 76'
$OORXWSXWVH[FHSW9 RII
'LDJQRVLV 76'
[76'
:DNHXSHYHQW
7M!76'
Ã5HDGDQG&OHDU¶
25
3RZHURQUHVHW
9EDWVWE\
3RZHURQUHVHW
$OORXWSXWVLQFO9 RII
7HPSHUDWXUH
:DUQLQJ
'LDJQRVLV 7:
Ã5HDGDQG&OHDU¶
25
3RZHURQUHVHW
7M!7Z
$FWLYH
0RGH
6WDQGE\0RGHV
GXULQJF\FOLFVHQVH
9V!9SRU
3RZHU2Q5HVHW
$OORXWSXWVLQFO9RII
$* 9
Note:
The thermal state machine recovers the same state were it was before entering standby
mode. In case of a TSD2 it enters TSD1 state.
Doc ID 17639 Rev 4
37/102
Protection and diagnosis
3.3
L99PM62GXP
High-side driver outputs
The component provides a total of 4 high-side outputs Out1 to 4, (7 Ω typical at 25°C) to
drive e.g. LED's or hall sensors and 1 high-side output OUT_HS with 1 Ω typical at 25 °C).
The high-side outputs switch off in case of:
●
VS over and undervoltage
●
Overcurrent
●
Overtemperature (TSD1) with pre warning(a)
In case of overload or over temperature (TSD1) condition, the drivers switches off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case over/under voltage condition, the drivers is switched off. The according status bit is
latched and can be read and optionally cleared by SPI. If the Vlockout bit (Control Register
4) is set to ‘1’ the drivers remain off until the status is cleared. If the Vlockout bit is set to ‘0’
the drivers switches on automatically if the error condition disappears.
In case of open-load condition, the according status register is latched. The status can be
read and optionally cleared by SPI. The high-sides are not switched off.
For OUT_HS the auto recovery feature (OUTHSREC bit Control Register 4) can be
enabled. If this bit is set to ‘1’ the driver is automatically restart from a overload condition.
This overload recovery feature is intended for loads which have an initial current higher than
the over current limit of the output (e.g. Inrush current of cold light bulbs). During auto
recovery mode the over current status bit can not be read from SPI.
The device itself can not distinguish between a real overload and a non linear load like a
light bulb. A real overload condition can only be qualified by time. As an example, the micro
controller can switch on light bulbs by setting the over current recovery bit for the first 50ms.
After clearing the recovery bit, the output is automatically disabled if the overload condition
still exists.
In case of a fail safe condition, the high-side drivers are switched off. The control bits are set
to default values. (except OUT3/FSO if it is used as a high-side driver output)
Note:
The maximum voltage and current applied to the high-side outputs is specified in
Section 5.1: Absolute maximum rating. Appropriate external protection may be required in
order to respect these limits under application conditions.
Each high-side driver can be driven whether with a PWM signal or with a internal Timer. See
Table 7.
For more Details please refer to Section 6.2: SPI registers.
Table 7.
PWM configuration for high-side outputs
High-side output
PWM channel
Internal timer
OUT1
PWM 1
Timer 1
OUT2
PWM 2
Timer 2
OUT3
PWM 3
-
a. Except OUT3 when configured as FSO.
38/102
Doc ID 17639 Rev 4
L99PM62GXP
Protection and diagnosis
Table 7.
PWM configuration for high-side outputs (continued)
High-side output
PWM channel
Internal timer
OUT4
PWM 4
Timer 2
OUTHS
PWM 3 / PWM 4
Timer 1 / Timer 2
The PWM 1 / 3 channels start a PWM period with the ON phase, while the PWM 2 / 4
channels start with the OFF phase. In this way it is possible to use the 4 PWM channels in a
phase shifted way.
The Figure 21 shows this feature with a duty cycle of 25% for both PWM channels.
Figure 21. Phase shifted PWM
287
3:0[)
3:03HULRG
287
3:0[)
$*9
3.4
Low-side driver outputs REL1, REL2
The outputs REL1, REL2 (RDSon = 2 Ω typical at 25 °C) are specially designed to drive relay
loads.
The outputs provide an active output zener clamping (45 V typical) feature for the
demagnetization of the relay coil, even though a load dump condition exists.
For fail-safe reasons the relay drivers are linked with the fail safe operation: in case of
entering the fail safe mode, the relay drivers switches off and the SPI control bits are set to
default (i.e. driver is off).
The low-side drivers switch off in case of:
●
VS over and undervoltage
●
Overcurrent
●
Overtemperature with pre warning
In case of overload or overtemperature (TSD1) condition, the drivers switches off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
Doc ID 17639 Rev 4
39/102
Protection and diagnosis
L99PM62GXP
In case VS over/undervoltage condition, the drivers is switched off. The according status bit
is latched and can be read and optionally cleared by SPI. If the Vlockout bit (Control
Register 4) is set to ‘1’ the drivers remain off until the status is cleared. If the Vlockout bit is
set to ‘0’ the drivers is switched on automatically if the error condition disappears.
With the LSOVUV_shutdown_en bit (Control Register 4) the drivers can be excluded from a
switch off in case of VS over/undervoltage. If the bit is set to ‘1’ the driver switches off,
otherwise the drivers remain on.
3.5
SPI diagnosis
Digital diagnosis features are provided by SPI (for details please refer to Section 6.2: SPI
registers.
40/102
●
V1 reset threshold programmable
●
Overtemperature including. pre warning
●
Open-load separately for each output stage except REL1/REL2
●
Overload status separately for each output stage
●
Vs-supply over/under voltage
●
V1 and V2 fail bit
●
V2 output short to GND
●
Status of the WU1 to 3
●
Wake-up sources (CAN, LIN, SPI, Timer, WU1…3)
●
chip reset bit (start from power-on reset)
●
Number of unsuccessful V1 restarts after thermal shutdown
●
Number of sequential watchdog failures
●
LIN diagnosis (permanent recessive/dominant, dominant TxD)
●
CAN diagnosis (permanent recessive/dominant, dominant TxD, recessive RXD)
●
Device State (wake-up from V1 standby or VBAT standby)
●
Forced VBAT standby after WD-fail, forced VBAT standby after overtemperature
●
Watchdog timer state (diagnosis of watchdog)
●
Fail-safe status
●
SPI communication error
Doc ID 17639 Rev 4
L99PM62GXP
4
Typical application
Typical application
Figure 22. Typical application diagram
9EDW
9V
9V
9EDW
9V
9
([WHUQDOORDGV
7HPS3UHZDUQLQJ
6KXWGRZQ
9ROWDJH
5HJXODWRU
Q)
8QGHUYROWDJH
2YHUYROWDJH
6KXWGRZQ
0
/RZ6LGH
9V
9
5(/
2XWSXW&ODPS
9ROWDJH
5HJXODWRU
/RZ6LGH
5(/
2XWSXW&ODPS
Q)
9ROWDJH
0RQLWRU
Nȍ
23
23
23B287
15(6(7
0LFUR
FRQWUROOHU
& $'&
:LQGRZ
:DWFKGRJ
',
'2
&/.
&61
63,
+LJK6LGH
7['/
+LJK6LGH
/,1
/,138
/,1
+LJK6LGH
/,1
+LJK6LGH
9
23
23B287
/2*,&
+LJK6LGH
5['/1,17
23
287B+6
287
287
287)62
5['&
&$1+
+6&$1
HJ/('
+DOO6HQVRU
287
&$1683
7['&
HJ%XOE
/('+DOO
6HQVRU
:DNH8S
,1
:8
:DNH8S
,1
:8
:DNH8S
,1
:8
&\FOLF&RQWDFW
0RQLWRULQJ
([WHUQDO
)DLO6DIH
/RJLF
&$1
&$1/
/,1FRPSOLDQW
6$(-FRPSDWLEOH
3*1'
$*1'
,62 [
DQG6$(-FRPSOLDQW
$*9
Doc ID 17639 Rev 4
41/102
Electrical specifications
L99PM62GXP
5
Electrical specifications
5.1
Absolute maximum rating
Table 8.
Absolute maximum rating
Symbol
VS
Parameter/test condition
Value [DC voltage]
Unit
DC supply voltage / “jump start”
-0.3 to +28
V
Single pulse / tmax < 400 ms “transient load dump”
-0.3 to +40
V
-0.3 to (V1 + 0.3) V
V1 < V S
V
-0.3 to +28
V
-0.3 to V1+0.3
V
-0.3 to VS+0.3
V
V1
Stabilized supply voltage, logic supply
V2
Stabilized supply voltage
VDI VCLK
VDO VRXDL
VNRESET
VRXDC
Logic input / output voltage range
VTXDC, VTXDL, VCSN Multi level inputs
VREL1, VREL2,
Low-side output voltage range
-0.3 to +40
V
VOUT1..4, VOUT_HS
High-side output voltage range
-0.3 to VS+0.3
V
VWU1...3
Wake up input voltage range
-0.3 to VS+0.3
V
VOP1P,VOP1M,
VOP2P, VOP2M,
Opamp1 input voltage range
Opamp2 input voltage range
-0.3 to V1+0.3
V
VOPOUT1,
VOPOUT2
Analog Output voltage range
-0.3 to VS+0.3
V
-20 to +40
V
Current injection into VS related input pins
20
mA
Current injection into VS related outputs
20
mA
-0.3 to +5.25
V
-27 to +40
V
VLIN, VLINPU
IInput
Iout_inj
VCANSUP
VCANH, VCANL,
VSPLIT
Note:
LIN bus I/O voltage range
CAN supply
CAN bus I/O voltage range
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit!
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds,
the current load must be limited to this nominal current.
42/102
Doc ID 17639 Rev 4
L99PM62GXP
5.2
Electrical specifications
ESD protection
Table 9.
ESD protection
Parameter
Value
Unit
+/-2
kV
+/-4
kV
LIN
+/-8(2)
+/-10(3)
+/-6(4)
kV
CAN_H, CAN_L
+/-8(2)
+/-6(4)
kV
All pins(5)
+/-500
V
+/-750
V
+/-200
V
(1)
All pins
All output
Corner
All
pins(2)
pins(5)
pins(6)
1. HBM (human body model, 100 pF, 1.5 kΩ) according to MIL 883C, method 3015.7 or EIA/JESD22A114-A.
2. HBM with all none zapped pins grounded.
3. Indirect ESD test according to IEC 61000-4-2 (150 pF, 330 Ω) and 'Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications' (version 1.1, 2009-12-02).
4. Direct ESD test according to IEC 61000-4-2 (150 pF, 330 Ω) and 'Hardware Requirements for LIN, CAN
and Flexray Interfaces in Automotive Applications' (version 1.1, 2009-12-02); Cbus,LIN = 220 pF.
5. Charged device model.
6. Machine model: C = 200 pF; R = 0 Ω.
5.3
Thermal data
Table 10.
Operating junction temperature
Symbol
Tj
RthjA
Table 11.
Parameter
TSD1 OFF
Thermal resistance junction / ambient
-40 to 150
°C
See Figure 25
°K/W
Temperature warning and thermal shutdown
Parameter
Min.
Typ.
Max.
Unit
Thermal over temperature warning
threshold
Tj(1)
120
130
140
°C
Thermal shutdown junction temperature 1
Tj(1)
130
140
150
°C
Tj(1)
150
160
170
°C
TSD2 OFF
TSD2 ON
Unit
Operating junction temperature
Symbol
TW ON
Value
Thermal shutdown junction temperature 2
Hysteresis
5
°C
TSD12hys
1. Non-overlapping
Doc ID 17639 Rev 4
43/102
Electrical specifications
L99PM62GXP
Figure 23. Thermal data of PowerSSO-36
P a d s o ld e re d
35
30
P ow erS S O -3 6 o n 2 s 2 p
P ow erS S O -3 6 o n 2 s 2 p th. e n h.
ZTH (ºC/W)
25
20
15
10
5
0
0 .0 0 0 1
0 .0 0 1
0 .0 1
0 .1
T im e (s )
44/102
Doc ID 17639 Rev 4
1
10
100
1000
AG00022V1
L99PM62GXP
Electrical specifications
5.4
Package and PCB thermal data
5.4.1
PowerSSO-36 thermal data
Figure 24. PowerSSO-36 PC board
$*9
Note:
Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10% board
double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070 mm (front
and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm,
Cu thickness on vias 0.025 mm).
Doc ID 17639 Rev 4
45/102
Electrical specifications
L99PM62GXP
Figure 25. PowerSSO-36 Thermal Resistance junction to ambient vs PCB copper
area (V1 ON)
57+MDPE
57+MBDPE &:
57+MDPE
3&%&XKHDWVLQNDUHD FPA
$*9
Figure 26. PowerSSO-36 Thermal Impedance junction to ambient vs PCB copper
area (single pulse with V1 ON)
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print
10
1
0.01
0.1
1
Time (s)
10
100
1000
AG00025V1
46/102
Doc ID 17639 Rev 4
L99PM62GXP
Electrical specifications
Figure 27. PowerSSO-36 thermal fitting model (V1 ON)
$*9
Equation 1: pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Table 12.
Thermal parameter
Area/island (cm2)
Footprint
2
8
R1 (°C/W)
2
R2 (°C/W)
8
4
4
R3 (°C/W)
20
15.5
10
R4 (°C/W)
36
29
18
C1 (W.s/°C)
0.01
C2 (W.s/°C)
0.1
0.2
0.2
C3 (W.s/°C)
0.8
1
1.5
C4 (W.s/°C)
2
3
6
Doc ID 17639 Rev 4
47/102
Electrical specifications
L99PM62GXP
5.5
Electrical characteristics
5.5.1
Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin Tj = -40 °C to 130 °C, unless otherwise specified.
Table 13.
Symbol
VSUV
Supply and supply monitoring
Parameter
VS undervoltage threshold
Test condition
Min.
VS increasing / decreasing
5.11
Vhyst_UV VS undervoltage hysteresis
VSOV
VS overvoltage threshold
Vhyst_OV VS overvoltage hysteresis
tovuv_filt
0.0
VS increasing / decreasing
18.5
Hysteresis
0.5
VS over/undervoltage filter time
Typ.
Max.
Unit
5.81
V
0.15
V
22
V
1.5
V
6
12
mA
0.1
1
64*Tosc
Current consumption in active
mode
Vs = 12V
TxD CAN = high
TxD LIN = high
V1 = on, V2 = on
HS/LS driver off
Current consumption in VBAT
standby mode
VS = 12V
Both voltage regulators deactivated,
no wake-up request(1)
HS/LS driver off
8
12
28
µA
VS = 12V
Current consumption in VBAT
Both voltage regulators deactivated,
IV(BAT)CS standby mode with cyclic sense
T = 50 ms, ton = 100 µs no wake-up
enabled
request(1)
70
110
130
µA
VS = 12V
Both voltage regulators deactivated
During standby phase no
wake-up request(1)
70
110
130
µA
VS = 12V
Voltage Regulator V1 active,
(Iv1 < Icmp) no wake-up request(1)
HS/LS driver off
16
51
76
µA
IV(act)
IV(BAT)
Current consumption in VBAT
IV(BAT)CW standby mode with cyclic wake
enabled
I(V1)
Current consumption in
V1-standby mode
1. Conditions for no wake-up request are (all conditions must be met):
2 V < LIN < (VS-2 V)
0.4 V < (CAN_H – CAN_L) < 1,2 V
1 V < VWUth < (VS-2 V)
The current consumption in standby modes with cyclic sense can be calculated using the following formulas:
IV(BAT)CS = IV(BAT) + 55 µA + (2 mA * (tON + 100 µs) / T)
I(V1)CS = IV1 + 55 µA + (2 mA * (tON + 100 µs) / T)
48/102
Doc ID 17639 Rev 4
L99PM62GXP
5.5.2
Electrical specifications
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; all outputs open; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 14.
Oscillator
Symbol
Test condition
Oscillation frequency
FCLK
5.5.3
Parameter
Min.
Typ.
Max.
Unit
0.80
1.0
1.35
MHz
Typ.
Max.
Unit
3.45
4.5
V
3.5
V
Power-on reset (VS)
All outputs open; Tj = -40°C to 130°C, unless otherwise specified.
Table 15.
Power-on reset (Vs)
Symbol
VPOR
VPOR
Parameter
VPOR threshold
VPOR threshold
Test condition
Min.
Vs increasing
Vs
decreasing(1)
2.65
1. This threshold is valid if Vs had already reached 7V previously
5.5.4
Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 16.
Symbol
Voltage regulator V1
Parameter
V1
Output voltage
V1
Output voltage tolerance
Active mode
Vhc1
Output voltage tolerance
active mode, high current
VSTB1
VDP1
ICC1
ICCmax1
Output voltage tolerance
V1-standby mode
Drop-out voltage
Test condition
Min.
Typ.
Max.
5.0
Unit
V
ILOAD1 = 4 mA to 100 mA;
VS = 13.5 V
-2
+2
%
ILOAD1 = 100 mA to 250 mA;
VS = 13.5 V
-3
+3
%
ILOAD1 = 250 mA;
VS = 13.5 V
-5
+5
%
ILOAD1 = 0 µA to 4 mA;
VS = 13.5 V
-2
+4
%
ILOAD1 = 50 mA; VS = 5 V
0.2
0.4
V
ILOAD1 = 100 mA; VS = 4.5 V
0.2
0.5
V
ILOAD1 = 100 mA; VS = 5 V
0.3
0.5
V
ILOAD1 = 150 mA; VS = 4.5 V
0.45
0.6
V
ILOAD1 = 150 mA; VS = 5.0 V
0.45
0.6
V
250
mA
900
mA
Output current in active mode
Max. continuous load current
Short circuit output current
Current limitation
Doc ID 17639 Rev 4
340
600
49/102
Electrical specifications
Table 16.
Symbol
Cload1
tTSD
L99PM62GXP
Voltage regulator V1 (continued)
Parameter
Load capacitor1
Test condition
Ceramic (+/- 20%)
Min.
Typ.
Max.
Unit
(1)
0.22
V1 deactivation time after
thermal shutdown
µF
1
sec
Icmp_ris
Current comp. rising thresh.
Rising current
1.0
2.5
4
mA
Icmp_fal
Current comp. falling threshold
Falling current
0.8
1.95
3.1
mA
Icmp_hys
Current comp. hysteresis
0.5
mA
2
V
V1fail
V1 fail threshold
tV1fail
V1 fail filter time
2
µs
V1 short filter time
4
ms
tV1short
V1 forced
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20 %). Capacitor must be
located close to the regulator output pin.
5.5.5
Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 17.
Symbol
Voltage regulator V2
Parameter
Test condition
Min.
Typ.
Max.
Unit
V2
Output voltage
V2
Output voltage tolerance
active mode
ILOAD2 = 1 mA to 50 mA;
VS = 13.5 V
+/- 3
%
Vhc1
Output voltage tolerance
active mode
ILOAD2 = 50 mA to 80 mA;
VS = 13,5 V
+/- 4
%
V2
Output voltage tolerance
active mode, high current
ILOAD2 = 100 mA; VS = 13.5 V
+/- 6
%
VSTB2
Output voltage tolerance
V1 standby mode
ILOAD2 = 1 mA; VS = 13.5 V
+/-6.5
%
VDP2
Drop-out voltage
ICC2
Output current in active mode
ICCmax2 Short circuit output current
5,0
V
ILOAD2 = 25 mA; VS = 5.25 V
0.3
0.4
V
ILOAD2 = 50 mA; VS = 5.25 V
0.4
0.7
V
100
mA
450
mA
Max. continuous load current
Current limitation
150
280
0.22(1)
Cload
Load capacitor
Ceramic (+/- 20 %)
V2fail
V2 fail threshold
V2 forced
tV2fail
V2 fail filter time
2
µs
V2 short filter time
4
ms
tV2short
µF
2
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20 %). Capacitor must be
located close to the regulator output pin.
50/102
Doc ID 17639 Rev 4
V
L99PM62GXP
5.5.6
Electrical specifications
Reset output
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 4.0 V < VS = 28 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 18.
Reset output
Symbol
5.5.7
Parameter
Test condition
Min.
Typ.
Max.
Unit
VRT1
Reset threshold voltage1
V1 decreasing
3.7
3.9
4.1
V
VRT2
Reset threshold voltage2
V1 decreasing
4.2
4.3
4.45
V
VRT3
Reset threshold voltage3
V1 decreasing
4.25
4.4
4.55
V
VRT4
Reset threshold voltage4
V1
decreasing
4.5
4.60
4.75
V
VRT4
Reset threshold voltage4
V1 increasing
4.7
4.8
4.9
V
0,2
0,4
V
110
150
kΩ
40
µs
VRESET
Reset pin low output voltage V1 > 1 V; IRESET = 5 mA
RRESET
Reset pull up int. resistor
tRR
Reset reaction time
tUV1
V1 under-voltage filter time
Trd
Reset pulse duration
80
ILOAD1 = 1 mA
6
16
1.46
2
µs
2.5
ms
Watchdog
4.5 V < VS < 28 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless otherwise specified, see
Figure 28 and Figure 29.
Table 19.
Symbol
tLW
Watchdog
Parameter
Test condition
Long open window
Min.
Typ.
Max.
Unit
48,75
65
81,25
ms
4.5
ms
TEFW1
Early failure window 1
TLFW1
Late failure window 1
20
TSW1
Safe window 1
7.5
TEFW2
Early failure window 2
TLFW2
Late failure window 2
100
TSW2
Safe window 2
37.5
TEFW3
Early failure window 3
TLFW3
Late failure window 3
200
TSW3
Safe window 3
75
TEFW4
Early failure window 4
TLFW4
Late failure window 4
400
TSW4
Safe window 4
150
Doc ID 17639 Rev 4
ms
12
ms
22.3
ms
ms
60
ms
45
ms
ms
120
ms
90
ms
ms
240
ms
51/102
Electrical specifications
L99PM62GXP
Figure 28. Watchdog timing (long, early, late and safe window)
1RUPDOVWDUWXSRSHUDWLRQDQGWLPHRXWIDLOXUHV
7/: ORQJZLQGRZ
7&: FORVHGZLQGRZ
FRUUHFWWULJJHUWLPLQJ
72: RSHQZLQGRZ
HDUO\WULJJHUWLPLQJ
7:'5 ZDWFKGRJUHVHW
PLVVLQJWULJJHU
7&: 72:
7&: 72:
7&:
7/:
:'
WULJJHU
WULJJHUVLJQDO
7/:
7/:
15(6
2XW
7:'5
QRUPDORSHUDWLRQ
WLPHPV
7:'5
PLVVLQJ
WULJJHU
HDUO\
ZULWH
WLPHPV
0LVVLQJX&WULJJHUVLJQDO
:'
WULJJHU
7/:
7/:
7/:
WLPHPV
15(6
2XW
7:'5
7:'5
7:'5
WLPHPV
$*9
52/102
Doc ID 17639 Rev 4
L99PM62GXP
Electrical specifications
Figure 29. Watchdog early, late and safe windows
76:Q 6DIHZLQGRZ
7():Q (DUO\)DLOXUHZLQGRZ
7/):Q /DWHIDLOXUHZLQGRZ
7/):QBPLQ
76:QBPD[
76:QBPLQ
7():QBPD[
(DUO\
:DWFKGRJ
IDLOXUH
XQGHILQHG
VDIHWULJJHUDUHD
XQGHILQHG
/DWH
ZDWFKGRJ
IDLOXUH
WLPH
$*9
5.5.8
High-side outputs
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 20.
Symbol
Output (OUT_HS)
Parameter
Test condition
Min.
Typ.
Max.
Unit
Static drain source
on-resistance
(IOUT_HS = 150 mA)
Tj = 25 °C
1
2
RDSON
Ω
Tj = 125 °C
1.6
3
Ω
tdON
Switch on delay time
0.2 VS
5
35
60
µs
tdOFF
Switch off delay time
0.8 VS
40
95
150
µs
tSCF
Short circuit filter time
Tested by scan chain
64*TOSC
tdARHS
Auto recovery filter time
Tested by scan chain
400*TOSC
dVOUT/dt
Slew rate
0,18
0,5
0,8
V/µs
IOUT
Short circuit shutdown
current
480
900
1320
mA
IOLD
Open-load detection current
40
80
120
mA
tOLDT
Open-load detection time
IFW (1)
Loss of GND current
(ESD structure)
Tested by scan chain
64*TOSC
100
mA
1. Parameter guaranteed by design
Doc ID 17639 Rev 4
53/102
Electrical specifications
L99PM62GXP
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 21.
Symbol
Parameter
RDSON
Static drain source
on-resistance
(IOUT_HS = 150mA)
5.5.9
Test Condition
Min.
ILOAD = 60 mA @
Tj = +25 °C
Typ.
Max.
Unit
7
13
Ω
IOUT
Short circuit shutdown current 8 V < Vs < 16 V
140
235
350
mA
IOLD
Open-load detection current 1
0.9
2
4.5
mA
Slew rate
0.2
0.5
0.8
V/µs
dVOUT/dt
1.
Outputs (OUT1...4)
tdON
Switch ON delay time
0.2 Vs
5
35
60
µs
tdOFF
Switch OFF delay time
0.8 Vs
30
95
150
µs
tSCF
Short circuit filter time
Tested by scan chain
IFW(1)
Loss of GND current
(ESD structure)
tOLDT
Open-load detection time
64*TOSC
100
Tested by scan chain
mA
64*TOSC
Parameter guaranteed by design
Relay drivers
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 °C to 130 °C, unless
otherwise specified.
Table 22.
Relay drivers
Symbol
RDSON
IOUT
VZ
Parameter
Test condition
DC output resistance
ILOAD = 100 mA @ Tj = +25 °C
Short circuit shutdown current
8 V < Vs < 16 V
250
Output clamp voltage(1)
ILOAD = 100 mA
40
Typ.
Max. Unit
2
3
Ω
375
500
mA
48
V
tONHL
Turn on delay time to 10% VOUT
5
50
100
µs
tOFFLH
Turn off delay time to 90% VOUT
5
50
100
µs
4
V/µs
tSCF
Short circuit filter time
Tested by scan chain
dVOUT/dt Slew Rate
1.
Min.
64*TOSC
0.2
2
The output is capable to switch off relay coils with the impedance of RL = 160Ω; L = 300mH (RL = 220Ω; L = 420mH); at VS = 40V (load
dump condition)
54/102
Doc ID 17639 Rev 4
L99PM62GXP
5.5.10
Electrical specifications
Wake up inputs (WU1... WU3)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 23.
Wake up inputs (WU1... WU3)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VWUthp
Wake-up negative edge threshold
voltage
0.4*Vs
0.45*Vs
0.5*Vs
V
VWUthn
Wake-up positive edge threshold
voltage
0.5*Vs
0.55*Vs
0.6*Vs
V
VHYST
Hysteresis
0.05*Vs
0.1*Vs
0.15*Vs
V
tWU_stat
Static wake filter time
64*TOSC
IWU_stdby
Input current in standby mode
RWU_act
Input resistor to Gnd in active mode
and in standby mode during wake-up
request
tWU_cyc
Cyclic wake filter time
1 V > Vin > (Vs - 2 V)
µs
9
15
28
µA
80
160
300
kΩ
16(1)
µs
1. Blanking time 80 µs or 800 µs.
5.5.11
High speed CAN transceiver(b)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < Vcansup. < 5.2 V; Tjunction = -40 °C to 130 °C, unless otherwise
specified.
Table 24.
CAN communication operating range
Symbol
VSCOM
Parameter
Test condition
Min. Typ. Max. Unit
Supply voltage operating
Active mode, V1 = VCANSUP
range for CAN communication
Table 25.
Symbol
5.5
-
18
V
CAN transmit data input: pin TXDC
Parameter
Test condition
Min.
Typ.
1.35
1.8
VTXDCLOW
Input voltage dominant
Active mode, V1 = 5 V
level
VTXDCHIGH
Input voltage
recessive level
VTXDCHYS
VTXDCHIGH-VTXDCLOW Active mode, V1 = 5 V
0.7
1
RTXDCPU
TXDC pull up resistor
10
20
Active mode, V1 = 5 V
Active mode, V1 = 5 V
2.7
Max.
Unit
V
2.9
V
V
35
kΩ
b. ISO 11898-2 and ISO 11898-5 compliant; SAE J2284 compliant.
Doc ID 17639 Rev 4
55/102
Electrical specifications
Table 26.
L99PM62GXP
CAN receive data output: pin RXDC
Symbol
Parameter
Test condition
Min.
VRXDCLOW
Output voltage dominant level
Active mode, V1 = 5 V, 2 mA
VRXDCHIGH
Output voltage recessive level
Active mode, V1 = 5 V, 2 mA
Table 27.
Max.
Unit
0.2
0.5
V
4.5
V
CAN bus common mode stabilization output termination: pin SPLIT
Symbol
Parameter
Test Condition
VSPLIT,l
Split output voltage, loaded
condition (normal mode)
Active mode;
VTXDC = VTXDCHIGH;
|Isplit| = 500 µA
VSPLIT,u
Split output voltage,
unloaded condition (normal
mode)
Active mode;
VTXDC = VTXDCHIGH; No Load
Split leakage current (low
power mode)
V1-standby mode;
-12 V < VSPLIT < 12 V
ISPLIT
Typ.
Table 28.
Symbol
VCANHdom
VCANLdom
Typ.
Max.
Unit
0.3*
VCANSUP
0.5*
VCANSUP
0.7*
VCANSUP
V
0.5*
VCANSUP
0.55*
VCANSUP
V
5
µA
CAN transmitter and receiver: pins CANH and CANL
Parameter
Test Condition
Min.
CANH voltage level in dominant Active mode;
state
VTXDC = VTXDCLOW;
RL = 60 Ω; RL = 50 Ω
CANL voltage level in dominant
state
Differential output voltage in
VDIFF,domOUT dominant state:
VCANHdom - VCANLdom
VCM
Min.
Driver symmetry:
VCANHdom + 0VCANLdom
Max.
Unit
2.75
4.5
V
Active mode;
VTXDC = VTXDCLOW;
RL = 60 Ω; RL = 50 Ω
0.5
2.25
V
Active mode;
VTXDC = VTXDCLOW;
RL = 60 Ω; RL = 50 Ω
1.5
3
V
Active mode;
VTXDC = VTXDCLOW;
RL = 60 Ω;
CSPLIT = 4.7 pF
Typ.
1.1*
0.9*
V
VCANSUP CANSUP VCANSUP
V
VCANHrec
CANH voltage level in recessive Active mode;
state (normal mode)
VTXDC = VTXDCHIGH;
no load
2
2.5
3
V
VCANLrec
CANL voltage level in recessive Active mode;
state (normal mode)
VTXDC = VTXDCHiGH;
no load
2
2.5
3
V
VCANHrecLP
CANH voltage level in recessive V1 standby mode;
state (low power mode)
VTXDC = VTXDCHIGH;
no load
-0.1
0
0.1
V
VCANLrecLP
CANL voltage level in recessive V1 standby mode;
state (low power mode)
VTXDC = VTXDCHiGH;
no load
-0.1
0
0.1
V
56/102
Doc ID 17639 Rev 4
L99PM62GXP
Table 28.
CAN transmitter and receiver: pins CANH and CANL (continued)
Symbol
VDIFF,recOUT
VDIFF,recOUTL
P
Electrical specifications
Parameter
Test Condition
Min.
Differential output voltage in
recessive state (normal mode):
VCANHrec - VCANLrec
Active mode;
VTXDC = VTXDCHIGH;
no load
Differential output voltage in
recessive state (low power
mode): VCANHrec - VCANLrec
Common mode Bus voltage
VCANHL,CM
Typ.
Max.
Unit
-50
50
mV
V1 standby mode;
VTXDC = VTXDCHIGH;
no load
-50
50
mV
Measured with respect to
the ground of each CAN
node
-12
12
V
IOCANH,dom
CANH output current in
dominant state
Active mode;
VTXDC = VTXDCLOW;
VCANH = 0 V
-160
-75
-45
mA
IOCANL,dom
CANL output current in
dominant state
Active mode;
VTXDC = VTXDCLOW;
VCANL = 5 V
45
75
160
mA
Input leakage current
Unpowered device;
VBUS = 5 V
0
250
µA
Internal resistance
Active mode & V1
standby mode;
VTXDC = VTXDCHIGH;
no load
20
38
kΩ
3
%
75
kΩ
ILeakage
Rin
Internal resistor matching
CANH, CANL
Active mode & V1
standby mode;
VTXDC = VTXDCHIGH;
no load
Rin(CANH) - Rin(CANL)
Rin,matching
Differential internal resistance
Active mode & V1
standby mode;
VTXDC = VTXDCHIGH;
no load
Rin,diff
Cin
27.5
50
60
Internal capacitance
Guaranteed by design
20
pF
Differential internal capacitance
Guaranteed by design
10
pF
Differential receiver threshold
voltage recessive to dominant
state (normal mode)
Active mode
VTHdom
Differential receiver threshold
voltage recessive to dominant
state (low power mode)
V1 standby mode
VTHdomLP
Differential receiver threshold
voltage dominant to recessive
state (normal mode)
Active mode
VTHrec
Differential receiver threshold
voltage dominant to recessive
state (low power mode)
V1 standby mode
VTHrecLP
Cin,diff
Doc ID 17639 Rev 4
0.9
V
1.15
V
0.5
V
0.4
V
57/102
Electrical specifications
Table 29.
Symbol
L99PM62GXP
CAN transceiver timing
Parameter
Test condition
Min.
Typ.
Max.
Unit
tTXpd,hl
Propagation delay TXDC to
RXDC (high to low)
Active mode; 50 % VTXDC to 50 %
VRXDC; CRXDC = 100 pF; RL = 60 Ω
0
255
ns
tTXpd,lh
Propagation delay TXDC to
RXDC (low to high)
Active mode; 50 % VTXDC to 50 %
VRXDC; CRXDC = 100 pF; RL = 60 Ω
0
255
ns
0.5
5
µs
twake
Wake up filter time
tdom(TXDC)
TXDC dominant time-out
700
µs
tCAN
CAN permanent dominant
time-out
700
µs
5.5.12
LIN transceiver(c)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tjunction = -40 °C to 130 °C unless otherwise specified.
Table 30.
LIN transmit data input: pin TXD
Symbol
Parameter
Test condition
Min.
Typ.
VTXDLOW
Input voltage dominant level
Active mode; V1 = 5 V
1,35
1.8
VTXDHIGH Input voltage recessive level
Active mode; V1 = 5 V
VTXDHYS
VTXDHIGH-VTXDLOW
Active mode; V1 = 5 V
0.7
1
RTXDPU
TXD pull up resistor
Active mode; V1 = 5 V
10
20
Min.
Typ. Max. Unit
Table 31.
Table 32.
Symbol
c.
Unit
V
2.7
2.9
V
V
35
kΩ
LIN receive data output: pin RXD
Symbol
Parameter
VRXDLOW
Output voltage dominant level
Active mode;
V1 = 5 V, ILOAD1 = 2 mA
VRXDHIGH
Output voltage recessive
level
Active mode;
V1 = 5 V, ILOAD1 = 2 mA
Test condition
0.2
0.5
4.5
V
V
LIN transmitter and receiver: pin LIN
Parameter
VTHdom
Receiver threshold voltage
recessive to dominant state
VBusdom
Receiver dominant state
Test condition
LIN 2.1 compliant for Baud rates up to 20 kBit/s
SAE J2602 compatible
58/102
Max.
Doc ID 17639 Rev 4
Min.
Typ.
Max.
Unit
0.4*VS
0.45*VS
0.5*VS
V
0.4*VS
V
L99PM62GXP
Table 32.
Electrical specifications
LIN transmitter and receiver: pin LIN (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
0.55*VS
0.6*VS
V
VTHrec
Receiver threshold voltage
dominant to recessive state
0.5*VS
VBusrec
Receiver recessive state
0.6*VS
VTHhys
Receiver threshold hysteresis:
VTHrec -VTHdom
0.07*VS
0.1*VS
0.175*VS
V
VTHcnt
Receiver tolerance center
value: (VTHrec +VTHdom)/2
0.475*VS
0.5*VS
0.525*VS
V
V
VTHwkup
Receiver wakeup threshold
voltage
1.0
1.5
2
V
VTHwkdwn
Receiver wakeup threshold
voltage
VS-3.5
VS-2.5
VS-1.5
V
tlinbus
ILINDomSC
Ibus_PAS_dom
Dominant time for wakeup via
bus
Sleep mode;
edge: rec-dom
Transmitter input current limit in VTXD = VTXDLOW;
dominant state
VLIN = VBATMAX = 18 V
Input leakage current at the
receiver incl. pull-up resistor
Transmitter input current in
Ibus_PAS_rec
recessive state
VTXD = VTXDHIGH;
VLIN = 0 V; VBAT = 12 V(1)
µs
64*TOSC
40
100
180
-1
mA
mA
VTXD = VTXDHIGH;
8 V < VLIN;
VBAT < 18 V; VLIN >= VBAT
in standby modes
20
µA
1
mA
Ibus_NO_GND
Input current if loss of GND at
device
GND = VS;
0 V < VLIN < 18 V;
VBAT = 12 V
Ibus
Input current if loss of VBAT at
device
GND = VS;
0 V < VLIN < 18 V
100
µA
VLINdom
LIN voltage level in dominant
state
Active mode;
VTXD = VTXDLOW;
ILIN = 40 mA
1.2
V
VLINrec
LIN voltage level in recessive
state
Active mode;
VTXD = VTXDHIGH;
ILIN = 10 µA
1
V
RLINup
LIN output pull up resistor
VLIN = 0 V
60
kΩ
-1
0.8*VS
20
40
1. Slave mode.
Doc ID 17639 Rev 4
59/102
Electrical specifications
Table 33.
Symbol
tRXpd
LIN transceiver timing
Parameter
Receiver propagation delay
time
Symmetry of receiver
tRXpd_sym propagation delay time
(rising vs. falling edge)
D1
D2
D3
D4
L99PM62GXP
Test condition
Min.
Typ.
tRXpd = max (tRXpdr, tRXpdf);
tRXpdf = t(0.5 VRXD) - t(0.45 VLIN);
tRXpdr = t(0.5 VRXD) - t(0.55 VLIN);
VS = 12 V; CRXD = 20 pF;
Rbus, = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
tRXpd_sym = tRXpdr - tRXpdf;
VS = 12 V;
Rbus = 1 kΩ, Cbus = 1 nF
Duty cycle 1
THRec(max) = 0.744*VS;
THDom(max) = 0.581*VS;
VS = 7 V to 18 V, tbit = 50 µs;
D1 = tbus_rec(min)/(2xtbit);
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
Duty cycle 2
THRec(min) = 0.284*VS;
THDom(min) = 0.422*VS;
VS = 7.6 to 18 V, tbit = 50 µs;
D2 = tbus_rec(max)/(2xtbit);
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
Duty cycle 3
THRec(max) = 0.778*VS;
THDom(max) = 0.616*VS;
VS = 7 V to 18 V, tbit = 96 µs;
D3 = tbus_rec(min)/(2xtbit);
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
Duty cycle 4
THRec(min) = 0.251*VS;
THDom(min) = 0.389*VS;
VS = 7.6 V to 18 V, tbit = 96 µs;
D4 = tbus_rec(max)/(2xtbit);
Rbus = 1 kΩ, Cbus = 1 nF;
Rbus = 660 Ω, Cbus = 6.8 nF;
Rbus = 500 Ω, Cbus = 10 nF
-2
Max.
Unit
6
µs
2
µs
0.396
0.581
0.417
0.590
tdom(TXDL) TXDL dominant time-out
12
ms
LIN permanent recessive
time-out
40
µs
LIN bus permanent
dominant time-out
12
ms
tLIN
tdom(BUS)
60/102
Doc ID 17639 Rev 4
L99PM62GXP
Electrical specifications
Table 34.
Symbol
LIN pull-up: pin LINPU
Parameter
Test condition
Min.
RDSON ON resistance
Ileak
Typ.
Max.
Unit
10.5
16
Ω
1
µA
Leakage current
Figure 30. LIN transmit, receive timing
W 7;SGI
W 7;SGU
9 7['
WLPH
9 /,1UHF
9 /,1
9 7+UHF
9 7+GRP
9 /,1GRP
WLPH
9 5['
WLPH
W 5;SGI
W 5;SGU
$* 9
5.5.13
Operational amplifier
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; Tj = -40 °C to 130 °C, unless otherwise specified.
Table 35.
Symbol
GBW
Operational amplifier
Parameter
Test condition
GBW product
AVOLDC DC open loop gain
PSRR
Power supply rejection
DC, Vin = 150 mV
Voff
Input offset voltage
VICR
Common mode input range
VOH
Output voltage range high
ILOAD = 1 mA to Gnd
VOL
Output voltage range low
ILim+
Ilim-
Min.
Typ.
Max.
Unit
1
3.5
7.0
MHz
80
dB
80
dB
-5
+5
mV
3
V
VS-0.2
VS
V
ILOAD = 1 mA to VS
0
0.2
V
Output current limitation +
DC
10
15
30
mA
Output current limitation -
DC
-10
15
-30
mA
-0.2
Doc ID 17639 Rev 4
0
61/102
Electrical specifications
Table 35.
L99PM62GXP
Operational amplifier (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
SR+
Slew rate positive
1
4
10
V/µs
SR-
Slew rate negative
-1
-4
-10
V/µs
Note:
The operational amplifier is on-chip stabilized for external capacitive loads CL < 25 pF (all operating
conditions)
5.5.14
SPI
Input: CSN
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.
Input: CSN
Table 36.
Symbol
Input: CSN
Parameter
Test condition
VCSNLOW Input voltage low level
Normal mode, V1 = 5 V
VCSNHIGH Input voltage high level
Normal mode, V1 = 5 V
VCSNHYS VCSNHIGH - VCSNLOW
Normal mode, V1 = 5 V
Normal mode, V1 = 5 V
ICSNPU
CSN pull up resistor
Min.
Typ.
1.35
1.8
Max. Unit
V
2.7
2.9
V
0.6
1.0
1.5
V
10
20
35
kΩ
CLK, DI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.
Table 37.
Symbol
tset
Parameter
Test condition
Min.
Switching from standby to
delay time from standby active mode. Time until
to active mode
output drivers are enabled
after CSN going to high.
Typ.
Max.
Unit
160
300
µs
Vin L
input low level
V1 = 5 V
1.0
2.05
2.5
V
Vin H
input high level
V1 = 5 V
1.5
2.8
3.5
V
Vin Hyst
input hysteresis
V1 = 5 V
0.4
0.75
1.5
V
pull down current at
input
Vin = 1.5 V
5
30
60
µA
I in
62/102
Input CLK, DI
Doc ID 17639 Rev 4
L99PM62GXP
Electrical specifications
Table 37.
Input CLK, DI (continued)
Symbol
Parameter
Test condition
Cin(1)
input capacitance at
input CSN, CLK, DI and 0 V < V1 < 5.3 V
PWM1,2
fCLK
SPI input frequency at
CLK
1.
Min.
Typ.
Max.
Unit
10
15
pF
1
MHz
Value of input capacity is not measured in production test. Parameter guaranteed by design.
DI timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.
Table 38.
DI timing(1)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tCLK
Clock period
V1 = 5 V
1000
-
ns
tCLKH
Clock high time
V1 = 5 V
400
-
ns
tCLKL
Clock low time
V1 = 5 V
400
-
ns
tset CSN
CSN setup time, CSN low
V1 = 5 V
before rising edge of CLK
400
-
ns
tset CLK
CLK setup time, CLK high
V =5V
before rising edge of CSN 1
400
-
ns
tset DI
DI setup time
V1 = 5 V
200
-
ns
thold DI
DI hold time
V1 = 5 V
200
-
ns
tr in
Rise time of input signal
DI, CLK, CSN
V1 = 5 V
-
100
ns
tf in
Fall time of input signal
DI, CLK, CSN
V1 = 5 V
-
100
ns
1. See Figure 32.
DO
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.
Table 39.
Symbol
DO output pin
Parameter
Test condition
VDOL
Output low level
V1 = 5 V, ID = -4 mA
VDOH
output high level
V = 5 V, ID = 4 mA
Doc ID 17639 Rev 4
Min.
4.5
Typ.
Max.
Unit
0.5
V
V
63/102
Electrical specifications
Table 39.
L99PM62GXP
DO output pin (continued)
Symbol
Parameter
Test condition
IDOLK
3-state leakage current
VCSN = V1, 0 V < VDO < V1
CDO 2
3-state input capacitance
VCSN = V1,
0 V < V1 < 5.3 V
Min.
Typ.
-10
10
Max.
Unit
10
µA
15
pF
DO timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.
DO timing(1)
Table 40.
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
tr DO
DO rise time
CL = 100 pF, ILOAD = -1 mA
-
50
100
ns
tf DO
DO fall time
CL = 100 pF, ILOAD = 1 mA
-
50
100
ns
ten DO tri L
DO enable time
from 3-state to low level
CL = 100 pF, ILOAD = 1 mA
pull-up load to V1
-
50
250
ns
tdis DO L tri
DO disable time
from low level to 3-state
CL = 100 pF, ILOAD = 4 mA
pull-up load to V1
-
50
250
ns
ten DO tri H
DO enable time
from 3-state to high level
CL = 100 pF, ILOAD = -1 mA
pull-down load to GND
-
50
250
ns
tdis DO H tri
DO disable time
from high level to 3-state
CL = 100 pF, ILOAD = -4 mA
pull-down load to GND
-
50
250
ns
DO delay time
VDO < 0.3 V1,
VDO > 0.7 V1,
CL = 100 pF
-
50
250
ns
td DO
1. See Figure 33 and Figure 34.
CSN timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to
130 °C, unless otherwise specified.
Table 41.
CSN timing(1)
Symbol
Parameter
Test Condition
tCSN_HI,min
Minimum CSN HI
time, active mode
Transfer of SPI-command to Input
register
6
tCSNfail
CSN low timeout
Tested by scan chain
20
1. See Figure 35.
64/102
Min. Typ. Max. Unit
Doc ID 17639 Rev 4
µs
35
50
ms
L99PM62GXP
Electrical specifications
RXDL/NINT timing
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40 °C to 130 °C, unless otherwise
specified.
Table 42.
5.5.15
RXDL/NINT timing
Symbol
Parameter
Test condition
tInterupt
Interrupt pulse duration
Min. Typ. Max. Unit
Walk-up from V1-standby
—
56
—
µs
Inputs TxD_C and TxD_L for Flash mode
6 V ≤ Vs ≤ 18 V; 4.5 V ≤ V1 ≤ 5.3 V; Tj = -40 °C to 130 °C, voltages are referred to PGND,
all outputs open
Table 43.
Inputs TxD_C and TxD_L for Flash mode
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VFlashL
Input low level (VTXDC/L for
transition into Flash mode)
V1 = 5 V
6.1
7.25
8.4
V
VFlashH
Input high level (VTXDC/L for exit
from Flash mode)
V1 = 5 V
7.4
8.4
9.4
V
Input Voltage Hysteresis
V1 = 5 V
0.6
0.8
1.0
V
VFlashHYS
Figure 31. SPI – transfer timing diagram
&61KLJKWRORZ '2HQDEOHG
&61
WLPH
&/.
;
;
WLPH
', GDWDZLOOEHDFFHSWHGRQWKHULVLQJHGJHRI&/.VLJQDO
',
;
;
&RPPDQG%\WH
'DWD
'2 GDWDZLOOFKDQJHRQWKHIDOOLQJHGJHRI&/.VLJQDO
'2
,QSXW
'DWD
5HJLVWHU
;
;
WLPH
*OREDO6WDWXV%\WH &61ORZWRKLJK DFWXDOGDWDLV
WUDQVIHUHGWRRXWSXWSRZHUVZLWFKHV
*OREDO(UURU
ROGGDWD
WLPH
QHZGDWD
WLPH
$*9
Doc ID 17639 Rev 4
65/102
Electrical specifications
L99PM62GXP
The SPI can be driven by a micro controller with its SPI peripheral running in following
mode:
CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
Figure 32. SPI - input timing
9&&
&61
9&&
WVHW &61
W&/.+
WVHW &/.
9&&
&/.
9&&
WVHW ',
WKROG ',
W&/./
9&&
',
9DOLG
9DOLG
9&&
$*9
66/102
Doc ID 17639 Rev 4
L99PM62GXP
Electrical specifications
Figure 33. SPI output timing (part 1)
7I&/.
7U&/.
9FF
&/.
9FF
9FF
7U'2
9FF
'2
ORZWRKLJK
9FF
7G'2 7I
'2
9FF
'2
KLJKWRORZ
9FF
7I&61
7U&61
9FF
&61
9FF
9FF
7HQ'2BWULB/
7GLV'2B/BWUL
7HQ'2BWULB+
7GLV'2B+BWUL
$*9
Doc ID 17639 Rev 4
67/102
Electrical specifications
L99PM62GXP
Figure 34. SPI output timing (part 2)
& 61 ORZ WR KLJK GDWD IURP VKLIW UHJLVWHU
LV WUDQVIHUUHG WR RXWSXW SRZHU V ZLWFKHV
W U LQ
W I LQ
W &61B+,PLQ
& 61
WG 2))
RXWSXW FXUUHQW
RI D GULYHU
2 1 VWDWH
2) ) VWDWH
W 2))
WG 21
W 21
RXWSXW FXUUHQW
RI D GULYHU
2 )) VWDWH
2 1 VWDWH
$*9
Figure 35. SPI – CSN low to high transition and global status bit access
& 6 1 KLJ K WR OR Z D Q G &/ . V WD\V OR Z VWDWXV LQIRU PDWLR Q RI G DWD ELW ID XOW F R Q GLWLR Q LV WUD QV IHUH G WR ' 2
&61
WLP H
&/.
WLP H
',
WLP H
', G DWD LV Q RW DFF H SWH G
'2
WLP H
' 2 VWDWXV LQIRU P DWLRQ RI GDWD ELW IDXOW F R QGLWLR Q ZLOO VWD\ DV OR QJ DV & 6 1 LV OR Z
$*9
68/102
Doc ID 17639 Rev 4
L99PM62GXP
ST SPI
6
ST SPI
6.1
SPI communication flow
6.1.1
General description
The proposed SPI communication is based on a standard SPI interface structure using CSN
(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)
signal lines.
At device start-up the master reads the register (ROM address 3EH) of the
slave device. This 8-bit register indicates the SPI frame length (24bit) and the availability of
additional features.
Each communication frame consists of an instruction byte which is followed by 2 data bytes.
The data returned on SDO within the same frame always starts with the
register. It provides general status information about the device. It is followed by 2 data
bytes (i. e. ‘In-frame-response’).
For write cycles the register is followed by the previous content of the
addressed register.
For read cycles the register is followed by the content of the addressed
register.
A write command is only accepted as a valid command by the device if the counted number
of clocks is exact 24, otherwise the command is rejected.
Command byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (, , , ) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.
Table 44.
Command byte
MSB
LSB
Op code
OC1
Address
OC0
A5
A4
A3
A2
A1
A0
OCx: operating code
Ax: address
6.1.2
Operating code definition
Table 45.
Operating code definition
OC1
OC0
Meaning
0
0
0
1
Doc ID 17639 Rev 4
69/102
ST SPI
L99PM62GXP
Table 45.
Operating code definition (continued)
OC1
OC0
Meaning
1
0
1
1
The and operations allow access to
the RAM of the device, i. e. to write to control registers or read status information.
A operation addressed to a device specific status register reads
back and subsequently clear this status register.
A operation with address 3FH clears all status registers (including
the Global Status Register). Configuration register is read by this operation.
allows access to the ROM area which contains device related
information such as the product family, product name, silicon version, register width and
availability of a watchdog.
More detailed descriptions of the device information are available in ‘Read Device
Information’.
6.1.3
Global status register(d)
Table 46.
6.1.4
Global status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
OR comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Configuration register
The register is accessible at RAM address 3FH.
For the config register, the 8 bits are located in the low byte (LSB).
The configuration register is implemented for compliance purpose to ST SPI standard.
Table 47.
Configuration register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
WD trigger
: this bit is reserved to serve the watchdog.
d. See Section 6.2 for details.
70/102
Doc ID 17639 Rev 4
L99PM62GXP
ST SPI
Figure 36. Read configuration register(1)
&61
6',
75,*
&RPPDQG
6'2
&RP
*() (UURU
127
&KLS
5HV 76'
25
&RPP
(UU
76' 9 9V )DLO
)DLO )DLO 6DIH
*OREDO6WDWXV
$*9
1. The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the
watchdog trigger bit at D0
Figure 37. Write configuration register(1)
&61
6',
75,*
Q
75,*
Q
&RPPDQG
6'2
&RP
*() (UURU
127
&KLS
5HV 76'
25
&RPP
(UU
76' 9 9V )DLO
)DLO )DLO 6DIH
*OREDO6WDWXV
$*9
1. The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the
watchdog trigger bit at D0
Doc ID 17639 Rev 4
71/102
ST SPI
L99PM62GXP
6.1.5
Address mapping
Table 48.
Address mapping
RAM
adress
Description
Access
ROM
adress
Description
Access
3FH
R/W
3FH
Reserved
N/A
13H
Status register 3
R
3EH
R
12H
Status register 2
R
11H
Status register 1
R
…
Unused
N/A
06H
Control register 6
R/W
03H
N/A
05H
Control register 5
R/W
04H
Control register 4
R/W
02H
R
03H
Control register 3
R/W
02H
Control register 2
R/W
01H
R
01H
Control register 1
R/W
00H
Reserved
R/W
00H
R
The RAM memory area consists of 16 bit registers.
For the device information (ROM memory area) the eight most significant bits of the memory
cell are used. The remaining 8 are zero.
All unused RAM and ROM addresses is read as ‘0’.
Note:
6.1.6
1
The register definition for RAM address 00H is unused. A register value of all 0 must cause
the device to enter a fail-safe state (interpreted as ‘SDI stuck to GND’ failure).
2
ROM address 3FH is unused. An attempt to access this address must be recognized as a
communication error (‘SDI stuck to VCC’ failure) and must cause the device to enter a failsafe state.
Write operation
The write operation starts with a command byte followed by 2, data bytes. The number of
data bytes is specified in the .
Write command format
Table 49.
Write command format: command byte
MSB
LSB
Op Code
0
72/102
Address
0
A5
A4
Doc ID 17639 Rev 4
A3
A2
A1
A0
L99PM62GXP
ST SPI
Table 50.
Write command format: data byte 1
MSB
D15
Table 51.
LSB
D14
D13
D12
D11
D10
D9
D8
Write command format: data byte 2
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
OC0, OC1:operating code (00 for ‘write’ mode)
A0 to A5:address bits
An attempt to write 00H at RAM address 00H is recognized as a failure (SDI stuck to GND).
The device enters a fail-safe state.
6.1.7
Format of data shifted out at SDO during write cycle
Table 52.
Format of data shifted out at SDO during write cycle: global status
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
or comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Table 53.
Format of data shifted out at SDO during write cycle: data byte 1
MSB
D15
Table 54.
Previous content of addressed register
D14
D12
D11
D10
D9
D8
Format of data shifted out at SDO during write cycle: data byte 2
MSB
D7
D13
LSB
Previous content of addressed register
D6
D5
D4
D3
D2
LSB
D1
D0
Failures are indicated by activating the corresponding bit of the register.
The returned data byte(s) represent(s) the previous content of the accessed register.
Doc ID 17639 Rev 4
73/102
ST SPI
L99PM62GXP
Figure 38. Format of data shifted out at SDO during write cycle
&61
6',
$ $ $ $ $ $ ' ' ' ' ' '
&RPPDQG
6'2
&RP
*() (UURU
127
&KLS
5HV 76'
25
&RPP
(UU
' ' ' ' ' ' ' ' ' '
VW 'DWDE\WH
QG 'DWDE\WH
76' 9 9V )DLO
' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
)DLO )DLO 6DIH
VW 'DWDE\WH
*OREDO6WDWXV
QG 'DWDE\WH
SUHYLRXVFRQWHQWRIUHJLVWHU
SUHYLRXVFRQWHQWRIUHJLVWHU
$*9
6.1.8
Read operation
The read operation starts with a command byte followed by 2 data bytes. The number of
data bytes is specified in the . The content of the data bytes is ‘don’t care’.
The content of the addressed register is shifted out at SDO within the same frame (‘in-frame
response’).
Read command format
Table 55.
Read command format: command byte
MSB
LSB
Op Code
0
Table 56.
Address
1
A5
A4
A3
A2
A1
Read command format: data byte 1
MSB
0
Table 57.
LSB
0
0
0
0
0
0
LSB
0
0
0
OC0, OC1:operating code (01 for ‘read’ mode)
74/102
0
Read command format: data byte 2
MSB
0
A0
Doc ID 17639 Rev 4
0
0
0
0
L99PM62GXP
ST SPI
A0 to A5:address bits
6.1.9
Format of data shifted out at SDO during read cycle
Table 58.
Format of data shifted out at SDO during read cycle: global status
register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
or comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Table 59.
Format of data shifted out at SDO during read cycle: data byte 1
MSB
Previous content of addressed register
D15
D14
Table 60.
D13
D12
D11
LSB
D10
D9
D8
Format of data shifted out at SDO during read cycle: data byte 2
MSB
Previous content of addressed register
D7
D6
D5
D4
D3
LSB
D2
D1
D0
Failures are indicated by activating the corresponding bit of the register.
The returned data byte(s) represent(s) the content of the register to be read.
Figure 39. Format of data shifted out at SDO during read cycle
&61
6',
$ $ $ $ $ $
&RPPDQG
6'2
&RP
*() (UURU
127
&KLS
5HV 76'
25
&RPP
(UU
76' 9 9V )DLO
' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
)DLO )DLO 6DIH
*OREDO6WDWXV
VW 'DWDE\WH
QG 'DWDE\WH
$*9
Doc ID 17639 Rev 4
75/102
ST SPI
6.1.10
L99PM62GXP
Read and clear status operation
The ‘Read and Clear Status’ operation starts with a command byte followed 2 data bytes.
The number of data bytes is specified in the . The content of the data bytes
is ‘don’t care’. The content of the addressed status register is transferred to SDO within the
same frame (‘in-frame response’) and is subsequently cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all status registers (incl. the
register). The configuration register is read by this operation.
Read and clear status command format
Table 61.
Read and clear status command format: command byte
MSB
LSB
Op Code
1
Table 62.
Address
01
A5
A4
A3
A2
A1
A0
Read and clear status command format: data byte 1
MSB
0
Table 63.
LSB
0
0
0
0
0
0
0
Read and clear status command format: data byte 2
MSB
0
LSB
0
0
0
0
0
0
0
OC0, OC1:operating code (10 for ‘read and clear status’ mode)
A0 to A5:address bits
Format of data shifted out at SDO during read and clear status operation
Table 64.
Format of data shifted out at SDO during read and clear status: global
status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
or comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Table 65.
Format of data shifted out at SDO during read and clear status:
data byte 1
MSB
D15
76/102
Previous content of addressed register
D14
D13
D12
Doc ID 17639 Rev 4
D11
D10
LSB
D9
D8
L99PM62GXP
ST SPI
Table 66.
Format of data shifted out at SDO during read and clear status:
data byte 2
MSB
Previous content of addressed register
D7
D6
D5
D4
D3
LSB
D2
D1
D0
Failures are indicated by activating the corresponding bit of the register.
The returned data byte(s) represent(s) the content of the register to be read.
Figure 40. Format of data shifted out at SDO during read and clear status operation
&61
6',
$ $ $ $ $ $
&RPPDQG
127
&KLS
6'2
*()
&RP 5HV
(UURU 25
76' 76' 9 9V )DLO
' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
)DLO )DLO 6DIH
&RPP
(UU
*OREDO6WDWXV
VW 'DWDE\WH
QG 'DWDE\WH
&RQWHQWRIDGGUHVVHG6WDWXV5HJLVWHU
&RQWHQWRIDGGUHVVHG6WDWXV5HJLVWHU
$* 9
6.1.11
Read device information
The device information is stored at the ROM addresses defined below and is read using the
respective operating code.
Read device information
Table 67.
Op code
ROM
Device information
OC1
OC0
address
1
1
3FH
Reserved
1
1
3EH
includes frame width and availability of watchdog
1
1
04H to 3DH
1
1
03H
unused
unique product identifier
Doc ID 17639 Rev 4
Value
00
42 Hex
00
4B Hex
77/102
ST SPI
L99PM62GXP
Read device information (continued)
Table 67.
Op code
ROM
Device information
Value
OC1
OC0
address
1
1
02H
unique product identifier
13 Hex
1
1
01H
indicates Design Version
According to
silicon
version
1
1
00H
device family max adress of device information
43 Hex
The (ROM address 00H) indicates the product family and specifies the highest
address which contains product information
Table 68.
ID-header
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
0
1
1
Family Identifier
Highest address containing device information
:01 Hex (BCD)
:03 Hex
Table 69.
Family identifier
Bit 7
Bit 6
Meaning
0
0
VIPower
0
1
BCD
1
0
VIPower hybrid
1
1
Tbd
The (ROM address 02H) and (ROM address 03H)
represents a unique code to identify the product name.
13 Hex
4B Hex
The (ROM address 01H) provides information about the silicon version
according to the table below:
Table 70.
Bit 7
Silicon version identifier
Bit 6
Bit 5
Bit 4
Reserved
78/102
Bit 3
Bit 2
Bit 1
Silicon version
Doc ID 17639 Rev 4
Bit 0
L99PM62GXP
ST SPI
The (ROM address 3EH) provides information about the register width (1,
2, 3 bytes) and the availability of ‘Burst Mode Read’ and watchdog.
Table 71.
SPI-frame-ID
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
0
1
0
BR
WD
X
X
X
32-bit
24-bit
16-bit
BR:burst-mode read (1 = burst-mode read is supported)
WD:watchdog (1 = available, 0 = not available)
32-bit, 24-bit, 16-bit: width of SPI frame (see table below)
:not supported
:available
:24 bit
6.2
SPI registers
6.2.1
Overview
Overview command byte
Table 72.
SPI register: command byte
Read/write
x
Address
x
Table 73.
x
x
x
x
x
SPI register: mode selection
Read/write
Table 74.
x
Mode selection
0
0
Write
0
1
Read
1
0
Read and clear
1
1
Read device info
SPI register: CTRL register selection
CTRL register 1…6
CTRL register selection
0
0
0
0
0
1
CTRL register1
0
0
0
0
1
0
CTRL register2
0
0
0
0
1
1
CTRL register3
0
0
0
1
0
0
CTRL register4
Doc ID 17639 Rev 4
79/102
ST SPI
L99PM62GXP
Table 74.
SPI register: CTRL register selection (continued)
CTRL register 1…6
CTRL register selection
0
0
0
1
0
1
CTRL register5
0
0
0
1
1
0
CTRL register6
Table 75.
SPI register: STAT register selection
STAT register. 1…3
STAT register selection
0
1
0
0
0
1
STAT register1
0
1
0
0
1
0
STAT register2
0
1
0
0
1
1
STAT register3
Overview of control register data bytes
80/102
Doc ID 17639 Rev 4
L99PM62GXP
ST SPI
6.2.2
Control registers
Table 76.
Overview of control registers data bytes
1st data byte
2nd data byte
Control register 1, data
Defaults
0
0
0
0
0
0
0
0
0
0
0
0
Function
OUT
HS
OUT
HS
OUT
4
OUT
4
OUT
HS_EXT
OUT
3
OUT
2
OUT
1
REL
2
REL
1
V2
V2
Group
HS control
Res
0
0
0
Stby
sel
Go
Stby
Trig
LS Output, V2 and mode control
Control register 2, data
Defaults
Function Res
Res
0
0
0
0
0
0
Inp.
Filt 3
Inp.
Filt 3
Inp.
Filt 2
Inp.
Filt 2
Inp.
Filt 1
Inp.
Filt1
Group
0
0
0
0
Input
Input
Input
Res
Pu/Pd 3 Pu/Pd 2 Pu/Pd 1
Wake-up control
Res
1
1
1
WU
EN 3
WU
EN 2
WU
EN 1
Wake-up control
Control register 3, data
Defaults
Function Res
0
0
0
T1
On
T1
Per
T1
Per
Group
Res
0
0
0
T2
On
T2
Per
T2
Per
Res
Res
Timer Settings
0
0
1
1
0
0
WD
time
WD
time
LIN
WU
En
CAN
WU
En
Wake
timer
En
Wake
Timer
Select
Watchdog and cyclic wake up settings
Control register 4, data
Defaults
Function Res
0
ICMP
0
1
OutHS Vlock
Rec
Out
En
En
Group
1
Res
0
LS
V1
OV/UV
Reset
shut
Level
down_en
0
V1
Reset
Level
1
LIN
Pu
En
1
1
Res
Lin
TxD
Tout
En
Control (other)
1
CAN
ACT
0
1
1
0
CAN
Loop
En
CAN
Patt.
wake
En
CAN
split
On
CAN
Rec
Only
0
0
0
Transceiver settings
Control register 5, data
Defaults
Function Res
1
1
1
PWM2 PWM2 PWM2
OffOffOffDC
DC
DC
Group
1
1
PWM2
OffDC
PWM2
OffDC
1
1
0
0
0
0
0
PWM2 PWM2
PWM PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1
OffOffFreq ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC
DC
DC
PWM2 setting
PWM1 setting
Control register 6, data
Defaults
Function Res
Group
1
1
1
PWM4 PWM4 PWM4
Off-DC Off-DC Off-DC
1
1
PWM4
OffDC
PWM4
OffDC
1
1
PWM4 PWM4
Off-DC Off-DC
Res
0
0
PWM3
ONDC
PWM3
ONDC
PWM4 setting
0
0
0
0
0
PWM3 PWM3 PWM3 PWM3 PWM3
ONONONONONDC
DC
DC
DC
DC
PWM3 setting
Doc ID 17639 Rev 4
81/102
ST SPI
L99PM62GXP
Control register 1
Table 77.
Control register 1: command and data bytes
Command byte
Read/write
x
Table 78.
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
0
0
0
0
0
1
Control register 1, data bytes
1st data byte
2nd data byte
Defaults
0
0
0
0
0
0
0
0
0
0
0
0
Function
OUT
HS_2
OUT
HS_1
OUT
4_2
OUT
4_1
OUT
HS_EXT
OUT
3
OUT
2
OUT
1
REL
2
REL
1
V2_2
V2_1
Group
HS control
Table 79.
Name
15
OUTHS
14
12
11
82/102
0
0
Stby
sel
Go
Stby
Trig
LS Output, V2 and mode control
Control register 1, bits
Bit
13
Res
0
OUT4
Comment
Select mode of OUTHS
OUTHS_EXT
OUTHS_2
OUTHS_1
Mode
0
0
0
HS off
0
0
1
HS cyclic on with timer 1
0
1
0
HS controlled by PWM4
0
1
1
HS cyclic on with Timer 2
1
1
0
PWM3
1
x
1
HS on
Select mode of OUT4
OUT4_2
OUT4_1
Mode
0
0
HS off
0
1
HS on
1
0
HS controlled Active and standby mode
by PWM4
1
1
HS cyclic on
with Timer 2
OUTHS_EXT Extended function of OUTHS; see table OUTHS
Doc ID 17639 Rev 4
Active and
standby mode
L99PM62GXP
Table 79.
ST SPI
Control register 1, bits (continued)
Bit
Name
10
OUT3
Comment
Select mode of OUT3
OUT3
9
OUT2
Mode
0
Select FSO
1
Select PWM3
Select mode of OUT2
OUT2
0
1
8
OUT1
Mode
Select PWM2 Active and
Select timer2 standby mode
Select mode of OUT1
OUT1
0
1
7
REL2
Mode
Select PWM1 Active and
Select timer1 standby mode
Select mode of REL2
REL2
6
REL1
Active and
standby mode
Mode
0
REL2 off
Active and
standby mode
1
REL2 on
Active mode
Select mode of REL1
REL1
Mode
0
REL1 off
Active and
standby mode
1
REL1 on
Active mode
Doc ID 17639 Rev 4
83/102
ST SPI
L99PM62GXP
Table 79.
Control register 1, bits (continued)
Bit
Name
5
V2
Comment
4
3
RES
2
STBY_SEL
1
V2_1
0
0
V2 OFF in all modes
0
1
V2 ON in active mode; OFF in V1/VBAT
standby mode
1
0
V2 ON in Active/V1 standby mode; OFF in
VBAT standby mode
1
1
V2 ON in all modes
Reserved
Select standby mode
GO_STBY
0
V2_2
0
VBAT standby mode
1
V1standby mode
Execute standby mode
TRIG
0
No action
1
Execute standby mode
Trigger Bit for Watchdog
Control register 2
Table 80.
Control register 2: command and data bytes
Command byte
Read/write
x
Table 81.
x
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
0
0
0
0
1
0
Control register 2, data bytes
1st data byte
Defaults
Function Res Res
Group
84/102
0
Wu3
Filt_MSB
0
0
0
2nd data byte
0
0
Wu3
WU2
WU2
WU1
WU1
Res
Filt_LSB Filt_MSB Filt_LSB Filt_MSB Filt_LSB
Wakeup control
0
0
WU3
Pu/Pd
WU2
Pu/Pd
0
Wakeup control
Doc ID 17639 Rev 4
1
1
1
WU1
WU3 WU2 WU1
Res
Pu/Pd
EN
EN
EN
L99PM62GXP
Table 82.
ST SPI
Control register 2, bits
Bit
Name
Comment
15
Res
Reserved
14
Res
Reserved
13, 12
WU3_Filt
11, 10
WU2_Filt
MSB
LSB
9, 8
WU1_Filt
0
0
Static, 64 µs
0
1
Enabled with timer 2; 80 µs blank
1
0
Enabled with timer 2; 800 µs blank
1
1
Enabled with timer 1; 800 µs blank
Wakeup filter configuration
7
Res
Reserved
6
WU3_Pu/Pd
5
WU2_Pu/Pd
0
Pull down
4
WU1_Pu/Pd
1
Pull up
3
Res
2
WU3_EN
1
WU2_EN
0
Disable
0
WU1_EN
1
Enable
Pull up or pull down configuration
Reserved
Enable Wake up source
Control register 3
Table 83.
Control register 3: command data bytes
Command byte
Read/write
x
Table 84.
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
0
0
0
0
1
1
Control register 3, data bytes
1st data byte
Defaults
Function
Group
Res
2nd data byte
0
0
0
0
0
0
0
T1
On
T1
Per
MSB
T1
Per
LSB
Res
T2
On
T2
Per
MSB
T2
Per
LSB
Res
Timer Settings
Res
0
0
1
1
0
0
WD
time
MSB
WD
time
LSB
LIN
WU
En
CAN
WU
En
Wake
timer
En
Wake
timer
select
Watchdog and cyclic wake up settings
Doc ID 17639 Rev 4
85/102
ST SPI
Table 85.
L99PM62GXP
Control register 3, bits
Bit
Name
15
RES
14
T1_On
13
T1_Per_MSB
12
T1_Per_LSB
Comment
Reserved
Timer 1 “ON” time selections
0
10 ms
1
20 ms
Timer 1 period selection
MSB
LSB
0
0
1s
0
1
2s
1
0
3s
1
1
4s
Timer 1 is restarted with a valid write command to control register 3
11
Res
10
T2_On
9
T2_Per_MSB
8
T2_Per_LSB
Timer 2 “ON” time selection
0
0.1 ms
1
1 ms
Timer 2 period selection
MSB
LSB
0
0
10 ms
0
1
20 ms
1
0
50 ms
1
1
200 ms
Timer 2 is restarted with a valid write command to control register 3
7
Res
Reserved
6
Res
Reserved
86/102
Doc ID 17639 Rev 4
L99PM62GXP
Table 85.
ST SPI
Control register 3, bits (continued)
Bit
Name
5
WD_time_MSB
4
WD_time_LSB
3
2
1
0
LIN_WU_En
CAN_WU_En
Wake_timer_En
Comment
Trigger window selection
MSB
LSB
0
0
10 ms
0
1
50 ms
1
0
100 ms
1
1
200 ms
Enable LIN as wake up source
0
Disabled
1
Enabled
Enable CAN as wake up source
0
Disabled
1
Enabled
Enable wake up by timer from V1 standby mode (Interrupt) or VBAT standby Mode
(Nreset)
0
Disabled
1
Enabled
Wake_timer_select Timer selection for timer interrupt / wake-up of µC by timer
0
Timer 2
1
Timer 1
Control register 4
Table 86.
Control register 4: command and data bytes
Command byte
Read/Write
x
x
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
0
0
0
1
0
0
Doc ID 17639 Rev 4
87/102
ST SPI
L99PM62GXP
Table 87.
Control register 4, data bytes
1st data byte
Defaults
Function
0
RES
ICMP
0
OutHS
Rec
En
Group
Table 88.
1
Vlock
Out_en
2nd data byte
0
1
RES
LS
OV/UV
shut
down_en
0
V1
Reset
Lev_2
1
Res
Lin
TxD
Tout
En
1
CAN
ACT
0
1
1
0
CAN
Loop
En
CAN
Patt.
wake
En
CAN
split
On
CAN
Rec
only
Control register 4, bits
15
Res
Reserved; must be set to zero
14
Icmp
V1 load current supervision
OUTHS_rec_en
Vlock_out_en
11
Res
10
LS_OV/UV
shut_down_en
88/102
LIN
Pu
En
1
Transceiver settings
Name
12
V1
Reset
Lev_1
1
Control (other)
Bit
13
0
Comment
0
Enabled; Watchdog is disabled in V1 Standby when the
V1loadcurrent < Icmpthreshold
1
Disabled; Watchdog is automatically disabled when V1
standby is entered
Overcurrent Auto recovery mode for OUTHS
0
Disabled
1
Enabled
Voltage lock out: OV/UV status
0
Over/under voltage status recovers automatically when
condition disappears
1
Over/under voltage status is latched until a read and clear
command is performed
Reserved
Shutdown of low-side drivers in case of over-/under voltage
0
No shutdown of low-sides in case of over/under voltage
1
Shutdown low-sides in case of over/under voltage
Doc ID 17639 Rev 4
L99PM62GXP
Table 88.
ST SPI
Control register 4, bits (continued)
Bit
Name
9
V1Reset_level_1
8
V1Reset_level_2
7
LIN_PU_EN
6
Res
5
Lin_TxD_Tout_En
4
CAN_ACT
Comment
Select reset level
V1RSTlev_2
V1RSTlev_1
V1 reset level
0
0
4.6 V
0
1
4.35 V
1
0
4.1 V
1
1
3.8 V
Enable internal Lin pull up
0
No LIN master pull-up
1
LIN master pull-up
Must be written to ‘1’
Enable / disable monitoring via TxD
0
No TxD monitoring
1
TxD monitoring; LIN transmitter is switched off if TXDL is
dominant for t > 12 ms
Activate CAN transceiver
0
CAN transceiver deactivated
1
CAN transceiver activated
Active mode
3
2
1
CAN_Loop_En
Enable looping of CANTX to CANRXD
0
No looping
1
TXDC is looped to RXDC
CAN_Patt_wake_En Enable pattern wake up for CAN
CAN_split_On
0
No pattern wake up
1
Pattern wake up
Enable SPLIT termination for CAN
0
Split termination disabled
1
Split termination enabled
Active mode
Doc ID 17639 Rev 4
89/102
ST SPI
L99PM62GXP
Table 88.
Control register 4, bits (continued)
Bit
Name
Comment
0
CAN_Rec_only
Enable CAN receive only mode
0
CAN in transceiver mode
1
CAN in receive only mode
Active mode
Control register 5
Table 89.
Control register 5: command and data bytes
Command byte
Read/write
x
Table 90.
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
0
0
0
1
0
1
Control register 5, data bytes
1st data byte
Defaults
1
Function Res
1
1
1
2nd data byte
1
1
1
0
0
0
0
0
PWM2 setting
PWM1 setting
Control register 5, bits
Bit
Name
15
RES
14
PWM2_
Off_DC_6
13
PWM2_
Off_DC_5
PWM2
OFF_
DC_6
PWM2
OFF_
DC_5
PWM2
OFF_
DC_4
PWM2
OFF_
DC_3
PWM2
OFF_
DC_2
PWM2
OFF_
DC_1
PWM2
OFF_
DC_0
12
PWM2_
Off_DC_4
1
1
1
1
1
1
1
0%, HS OFF
11
PWM2_
Off_DC_3
10
PWM2_
Off_DC_2
0
0
0
0
0
1
0
98.5%
9
PWM2_
Off_DC_1
0
0
0
0
0
0
1
99.25%
8
PWM2_
Off_DC_0
0
0
0
0
0
0
0
100% HS ON
90/102
0
0
PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2
PWM PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1
OffOffOffOffOffOffOffFreq ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC ON-DC
DC
DC
DC
DC
DC
DC
DC
Group
Table 91.
0
Comment
Reserved; must be set to zero
PWM duty cycle
...
Doc ID 17639 Rev 4
L99PM62GXP
Table 91.
ST SPI
Control register 5, bits (continued)
Bit
Name
7
PWM_
FREQ
Comment
Select PWM frequency
0
128 Hz
1
256 Hz
6
PWM1_
ON_DC_6
5
PWM1_
ON_DC_5
PWM1
ON_
DC_6
PWM1
ON_
DC_5
PWM1
ON_
DC_4
PWM1
ON_
DC_3
PWM1
ON_
DC_2
PWM1
ON_
DC_1
PWM1
ON_
DC_0
4
PWM1_
ON_DC_4
1
1
1
1
1
1
1
100%, HS ON
3
PWM1_
ON_DC_3
2
PWM1_
ON_DC_2
0
0
0
0
0
1
0
1.5%
1
PWM1_
ON_DC_1
0
0
0
0
0
0
1
0.75%
0
PWM1_
ON_DC_0
0
0
0
0
0
0
0
0% HS OFF
PWM duty cycle
...
Control register 6
Table 92.
Control register 6: command and data bytes
Command byte
Read/Write
x
Table 93.
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
0
0
0
1
1
0
Control register 6, data bytes
1st data byte
Defaults
1
1
1
1
1
2nd data byte
1
1
0
0
0
0
0
0
0
PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 PWM4
PWM3 PWM3 PWM3
PWM3 PWM3 PWM3
PWM3
Off_
Off_ Res ON_
ON_
ON_
Function Res Off_
Off_
Off_
Off_
Off_
ON_
ON_
ON_
ON-DC_3
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0
DC_6 DC_5 DC_4
DC_2 DC_1 DC_0
Group
PWM4 setting
PWM3 setting
Doc ID 17639 Rev 4
91/102
ST SPI
Table 94.
L99PM62GXP
Control register 6, bits
Bit
Name
15
RES
14
PWM4_
Off_DC_6
13
PWM4_
Off_DC_5
PWM4
OFF_
DC_6
PWM4
OFF_
DC_5
PWM4
OFF_
DC_4
PWM4
OFF_
DC_3
PWM4
OFF_
DC_2
PWM4
OFF_
DC_1
PWM4
OFF_
DC_0
12
PWM4_
Off_DC_4
1
1
1
1
1
1
1
0%, HS OFF
11
PWM4_
Off_DC_3
10
PWM4_
Off_DC_2
0
0
0
0
0
1
0
98.5%
9
PWM4_
Off_DC_1
0
0
0
0
0
0
1
99.25%
8
PWM4_
Off_DC_0
0
0
0
0
0
0
0
100% HS ON
7
RES
6
PWM3_
ON_DC_6
5
PWM3_
ON_DC_5
PWM3
ON_
DC_6
PWM3
ON_
DC_5
PWM3
ON_
DC_4
PWM3
ON_
DC_3
PWM3
ON_
DC_2
PWM3
ON_
DC_1
PWM3
ON_
DC_0
4
PWM3_
ON_DC_4
1
1
1
1
1
1
1
100%, HS ON
3
PWM3_
ON_DC_3
2
PWM3_
ON_DC_2
0
0
0
0
0
1
0
1.5%
1
PWM3_
ON_DC_1
0
0
0
0
0
0
1
0.75%
0
PWM3_
ON_DC_0
0
0
0
0
0
0
0
0% HS OFF
92/102
Comment
Reserved; must be set to zero
PWM4 duty cycle
...
Reserved; must be set to zero
PWM3 duty cycle
...
Doc ID 17639 Rev 4
L99PM62GXP
ST SPI
6.2.3
Status registers
Table 95.
Overview of status register data bytes
1st data byte
2nd data byte
Status register 1, data
Function
OL
HS
OL
OL
OUT4 OUT3
OL
OL
OUT2 OUT1
Group
UV
V2
fail
V2
short
OV
OC
HS
OC
Out4
OC
Out3
Diagnosis 1
OC
OUT2
OC
Out1
OC
Rel2
OC
Rel1
CAN
perm.
rec.
CAN
CAN
perm.
TxD
dom. perm dom
Diagnosis 2
Status register 2, data
Function
WU3
state
WU2
state
WU3
wake
WU1
state
Group
WU2
wake
WU1
Wake
Wake
CAN
Wake LIN
LIN
LIN
CAN
Wake
TxD
perm.
RxD
Timer perm.
LIN
dom. perm dom. rec. perm rec.
int
Diagnosis 3
Diagnosis 4
Status register 3, data
Function TSD1
TW
Device Device
state
state
Group
V1
V1
V1
restart restart restart
WD
fail
WD
fail
WD
fail
WD
fail
Diagnosis 5
Forced
sleep
WD
Forced
WD
sleep
timer
TSD2
state
SHTV1
WD
timer
state
Diagnosis 6
Global status register
Bit 0
Fail safe(6)
Bit 1
Vs fail(5)
(OV/UV)
Bit 2
V1 Fail
Bit 3
TSD1
Bit 4
TSD2(4)
Bit 5
NOT (chip reset or
comm. error)
i.e. cold start (3)
Bit 6
Communication
error(2)
Bit 7
Global error
flag(1)
Table 96.
V1
fail
Active high/low
High
High
Low
High
High
High
High
High
Default value in
normal mode after correct WD
trigger or after
read & clear on
error flags
0
0
1
0
0
0
0
0
20
Power ON
1
0
0
0
0
0
0
0
80
Power ON
weak battery(7)
1
0
0
0
0
0
1
0
82
Communication
error
1
1
0
0
0
0
0
0
C0
Vs over or
under-voltage
1
0
1
0
0
0
1
0
A2
WD failure
1
0
1
0
0
0
0
1
A1
Doc ID 17639 Rev 4
Hex
value
93/102
ST SPI
L99PM62GXP
Global status register (continued)
Bit 0
Fail safe(6)
Bit 1
Vs fail(5)
(OV/UV)
Bit 2
V1 Fail
Bit 3
TSD1
Bit 4
TSD2(4)
Bit 5
NOT (chip reset or
comm. error)
i.e. cold start (3)
Bit 6
Communication
error(2)
Bit 7
Global error
flag(1)
Table 96.
Hex
value
SPI error (DI
stuck)
1
0
1
0
0
0
0
1
A1
TSD1
1
0
1
0
1
0
0
0
A8
TSD2
1
0
1
1
1
0
0
1
B9
V1 fail
1
0
1
0
0
1
0
0
A4
Other device
failure(8)
1
0
1
0
0
0
0
0
A0
1. The following status bits are reported in the global error flag:
Global status register: Bits 0 - 6
Status register 1: Bits 0 – 10
Status register 3: Bits 2, 3, 15
2. Invalid CLOCK COUNT.
3. Cleared with CLR command on SR3.
4. Cleared with “READ and CLEAR” on SR3 (-> TSD1).
5. Diagnosis bit only, Vs Fail is not a fail-safe event; cleared by read&clear. Bit is automatically cleared at (Vs > VsUV) and.
(Vs < VsOV) if Vlock_out_en = 0.
6. Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure.
7. Slow Vs ramp-up (Vs undervoltage is filtered with 64 µs after Power-on reset).
8. The global error flag is raised due to a failure condition which is not reported in the global status register. The Failure is
reported in the status registers 1 – 3.
Status register 1
Table 97.
Status register 1: command and data bytes
Command byte
Read/write
x
Table 98.
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
x
0
1
0
0
0
1
Status register 1, data bytes
1st data byte
Function
Group
94/102
OL
HS
OL
OUT4
OL
OUT3
OL
OUT2
OL
OUT1
2nd data byte
UV
V2
fail
V2
short
OV
Diagnosis 1
OC
HS
OC
Out4
OC
Out3
OC
OUT2
Diagnosis 2
Doc ID 17639 Rev 4
OC
Out1
OC
Rel2
OC
Rel1
L99PM62GXP
Table 99.
ST SPI
Status register 1, bits
Bit
Name
15
OL_HS
14
OL_OUT4
13
OL_OUT3
12
OL_OUT2
11
OL_OUT1
10
UV
Comment
Information storage
Open-load event occurred
since last read out
Bit is latched until a “read and clear” access
VLOCKOUTEN
(CR4)
Under voltage event on VS
occurred since last read out
9
V2_fail
8
V2_short
7
OV
V2 fail (V2 < 2 V for t> 2 µs)
event occurred since last
readout
0
automatically reset when UV
condition disappears
1
Bit is latched until a “read and clear”
access
Bit is latched until a “Read and clear” access
V2 short (V2 < 2 V for t > 4ms
during start up) event
Bit is latched until a “Read and clear” access
occurred since last readout
VLOCKOUTEN
(CR4)
Over voltage event on VS
occurred since last read out
6
OC_HS
5
OC_OUT4
4
OC_OUT3
3
OC_OUT2
2
OC_OUT1
1
OC_REL2
0
OC_REL1
Information storage
Over current event occurred
since last read out
Information storage
0
automatically reset when OV
condition disappears
1
Bit is latched until a “read and clear”
access
Bit is latched until a “read and clear” access
Doc ID 17639 Rev 4
95/102
ST SPI
L99PM62GXP
Status register 2
Table 100. Status register 2: command and data bytes
Command byte
Read/write
x
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
x
0
1
0
0
1
0
Table 101. Status register 2, data bytes
1st data byte
Function
WU3 WU2 WU1 WU3 WU2
state state state wake wake
Group
2nd data byte
WU1 Wake Wake Wake
Timer
LIN
wake CAN
int
LIN
perm.
dom.
LIN
TxD
perm dom.
Diagnosis 3
LIN
perm.
rec.
CAN
RxD
perm rec.
CAN
perm.
rec.
CAN
perm.
dom.
CAN
TxD
perm dom
Diagnosis 4
Table 102. Status register 2, bits
Bit
Name
Comment
15
WU3_state
14
WU2_state
13
WU1_state
12
WU3_wake
11
WU2_wake
10
WU1_wake
9
WAKE_CAN
8
WAKE_LIN
7
Wake_TIMER_int
6
LIN_perm_DOM
5
LIN_TxD_perm_DOM
TxDL pin is dominant for t > 12 ms;
Transmitter is disabled
4
LIN_perm_REC
LIN bus does not follow TxDL within
40 µs; Transmitter is disabled
3
CAN_RxD_perm_rec
RxDC has not followed TxDC for 4 times;
Transmitter is disabled
2
CAN_perm_REC
CAN has not followed TxDC for 4 times;
Transmitter is disabled
1
CAN_perm_DOM
CAN bus is dominant for t > 700 µs
0
CAN_TxD_perm_DOM
TxDC pin is dominant for t > 700 µs;
Transmitter is disabled
State of WUx input;
Information storage
“Live bits” not clearable
Shows wake up source (‘1’ = wake-up)
96/102
LIN bus is dominant for t > 12 ms
Doc ID 17639 Rev 4
Bits are latched until a “Read and
clear” access
L99PM62GXP
ST SPI
Status register 3
Table 103. Status register 3: command and data bytes
Command byte
Read/write
x
Address
x
0
1
0
0
1
1
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Table 104. Status register 3, data bytes
1st data byte
Function TSD1 TW
2nd data byte
Device Device V1
V1
V1
V1
WD
WD
WD
WD
state_2 state_1 fail restart_2 restart_1 restart_0 fail_3 fail_2 fail_1 fail_0
Group
Diagnosis 5
Forced
sleep
WD
Forced
WD
WD
sleep
timer
timer
TSD2
state_1 state_0
SHTV1
Diagnosis 6
Table 105. Status register 3, bits
Bit
Name
15
TSD1
14
TW
Comment
Information storage
Thermal warning / shutdown1 occurred since last readout
13
Bit is latched until a
“read and clear access”
State from which the device woke up
12
Device_state
11
V1_fail
10
V1_restart_2
9
V1_restart_1
8
V1_restart_0
7
WD_fail_3
6
WD_fail_2
5
WD_fail_1
4
WD_fail_0
State from
which the
device woke
up
Device state_2
Device state_1
0
0
Active
0
1
V1 standby
1
0
VBAT standby
1
1
Flash
Bit is latched until a
“read and clear access”
after a “read and clear
access”, the device
state is updated
after a wake up, device
state is
01: V1 standby
or
10: VBAT standby
V1 fail (V1 < 2 V for t > 2 µs) event occurred since last read out
Bit is latched until a
“read and clear access”
Number of TSD2 events which caused a restart of V1
regulator
(7 TSD2 events forces the device into VBAT standby)
Bits are not clearable;
is cleared automatically
if no additional TSD2
event occurs within 1
min.
Number of missing watchdog triggers
(15 missing watchdog trigger forces the device into VBAT
standby)
Bits are not clearable;
is cleared with a proper
Watchdog trigger
Doc ID 17639 Rev 4
97/102
ST SPI
L99PM62GXP
Table 105. Status register 3, bits (continued)
Bit
Name
Comment
3
Forced_sleep_WD
Device was forced to VBAT standby mode because of multiple
watchdog errors
2
Device was forced to VBAT standby or multiple thermal
Forced_sleep_TSD shutdown events
2_SHTV1
or
a short on V1 during startup.
1
WD_timer_state_1 Status of watchdog counter of selected watchdog timing
0
WD_timer_state_0
WD_timer_state_1 WD_timer_state_0
98/102
Information storage
Counter
0
0
0 – 33%
0
1
33 – 66%
1
1
66 – 100%
Doc ID 17639 Rev 4
Bits are latched until a
read and clear access
Bits are not clearable
L99PM62GXP
Package and packing information
7
Package and packing information
7.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.2
PowerSSO-36 package information
Figure 41. PowerSSO-36 package dimensions
AG00066V1
Doc ID 17639 Rev 4
99/102
Package and packing information
L99PM62GXP
Table 106. PowerSSO-36 mechanical data
Millimeters
Symbol
100/102
Min.
Typ.
Max.
A
-
-
2.45
A2
2.15
-
2.35
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D
10.10
-
10.50
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
-
2.3
-
G
-
-
0.1
G1
-
-
0.06
H
10.1
-
10.5
h
-
-
0.4
k
0°
-
8°
L
0.55
-
0.85
M
-
4.3
-
N
-
-
10 deg
O
-
1.2
-
Q
-
0.8
-
S
-
2.9
-
T
-
3.65
-
U
-
1.0
-
X
4.1
-
4.7
Y
6.5
-
7.1
Doc ID 17639 Rev 4
L99PM62GXP
8
Revision history
Revision history
Table 107. Document revision history
Date
Revision
Change
24-Jan-2011
1
Initial release.
23-Feb-2011
2
Table 11: Temperature warning and thermal shutdown:
– TSD2 OFF: updated minimum and typical values
01-Jun-2011
3
Updated following figures:
– Figure 3: Voltage source with external PNP
– Figure 5: Voltage source with external NPN
19-Sep-2013
4
Updated disclaimer.
Doc ID 17639 Rev 4
101/102
L99PM62GXP
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE
SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)
AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS
OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT
PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS
EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY
DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE
DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
102/102
Doc ID 17639 Rev 4
工商网监
湘ICP备2023018690号
