L99PM72PXP
Advanced power management system IC with embedded LIN and
high speed CAN transceiver supporting CAN Partial Networking
Datasheet production data
Features
■
Two 5 V voltage regulators for microcontroller
and peripheral supply
■
No electrolytic capacitor required on regulator
outputs
*$3*&)7
PowerSSO-36
■
Ultra low quiescent current in standby modes
■
Programmable reset generator for power-on
and undervoltage
Applications
■
Configurable window watchdog and fail safe
output
■
■
LIN 2.1 compliant (SAEJ2602 compatible)
transceiver
■
Advanced high speed CAN transceiver (ISO
11898-2/-5 and SAE J2284 compliant) with
local failure and bus failure diagnosis and
selective wake-up functionality according to
ISO 11898-6
■
Complete 3 channel contact monitoring
interface with programmable cyclic sense
functionality
■
Programmable periodic system wake-up
feature
■
ST SPI interface for mode control and
diagnosis
Description
■
5 fully protected high-side drivers with internal
4-channel PWM generator
■
2 low-side drivers with active Zener clamping
■
4 Internal PWM timers
■
2 operational amplifiers with rail-to-rail outputs
(VS) and low voltage inputs
■
Temperature warning and thermal shutdown
Table 1.
Automotive ECU's such as door zone and body
control modules description
The L99PM72PXP is a power management
system IC providing electronic control units with
enhanced system power supply functionality
including various standby modes as well as LIN
and HS CAN physical communication layers. It
contains two low drop voltage regulators to supply
the system microcontroller and external
peripheral loads such as sensors and provides
enhanced system standby functionality with
programmable local and remote wake up
capability.
In addition, five high-side drivers, two low-side
drivers and two operational amplifiers increase
the system integration level.
The ST standard SPI Interface (3.0) allows control
and diagnosis of the device and enables generic
software development.
Device summary
Order code
Package
PowerSSO-36
September 2013
This is information on a product in full production.
Tube
Tape and reel
L99PM72PXP
L99PM72PXPTR
Doc ID 023553 Rev 3
1/128
www.st.com
1
Contents
L99PM72PXP
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1
2.2
Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.1
Voltage regulator: V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.2
Voltage regulator: V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.1.3
Increased output current capability for voltage regulator V2 . . . . . . . . . 14
2.1.4
Voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.1.5
Voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.1
Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.2
Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.3
SW-Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.4
V1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.5
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.6
VBat_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.7
Wake up from Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.8
Wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.9
Cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.10
Timer interrupt / wake-up of microcontroller by timer . . . . . . . . . . . . . . . 22
2.3
Functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4
Configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4.1
2.5
Fail Safe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.1
Single failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5.2
Multiple failures – entering forced VBat_standby Mode . . . . . . . . . . . . . . . 30
2.6
Reset output (NRESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.7
Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.8
LIN Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.9
2/128
Change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.8.1
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.8.2
Wake up (from LIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.8.3
LIN Pull-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
High speed CAN bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 023553 Rev 3
L99PM72PXP
2.10
3
Contents
2.9.1
CAN transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.9.2
Sequence for enabling selective wakeup . . . . . . . . . . . . . . . . . . . . . . . . 37
2.9.3
CAN error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.9.4
Wake up by CAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.9.5
CAN receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.9.6
CAN looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Serial Peripheral Interface (ST SPI Standard 3.0) . . . . . . . . . . . . . . . . . . 40
Protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1
Power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1.1
VS overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.1.2
VS undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.2
Temperature warning and thermal shut-down . . . . . . . . . . . . . . . . . . . . . 44
3.3
High side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.4
Low side driver outputs REL1, REL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.5
SPI diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4
Typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
5.4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.4.1
5.5
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.1
Supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.5.2
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.5.3
Power-on reset (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.5.4
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.5.5
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.5.6
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.7
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.5.8
High side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.5.9
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.5.10
Wake up inputs (WU1 ... WU3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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Contents
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L99PM72PXP
High speed CAN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.5.12
LIN transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.5.13
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.5.14
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5.15
Inputs TxDC and TxDL for Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . 72
ST SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1
6.2
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5.5.11
SPI communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.1.2
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.3
Global Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.4
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.1.5
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.6
Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.1.7
Format of data shifted out at SDO during Write cycle . . . . . . . . . . . . . . 80
6.1.8
Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.1.9
Format of data shifted out at SDO during Read cycle . . . . . . . . . . . . . . 82
6.1.10
Read and Clear Status Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.1.11
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.2.1
Overview command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.2.2
Overview control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.2.3
Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.2.4
Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.2.5
Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.2.6
Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.2.7
Control Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.2.8
Control Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.2.9
Control Register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.2.10
Control Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2.11
Control Register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.2.12
Control Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2.13
Control Register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.2.14
Control Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.2.15
Control Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.2.16
Control Register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.2.17
Control Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Doc ID 023553 Rev 3
L99PM72PXP
7
8
Contents
6.2.18
Control Register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2.19
Control Register 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.2.20
Control Register 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.2.21
Overview status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.2.22
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2.23
Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.2.24
Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.2.25
Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
6.2.26
Status Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
6.2.27
Status Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.2
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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List of tables
L99PM72PXP
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CAN wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Wake up from Standby Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Fail-Safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Persisting fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PWM configuration for high-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Power-on reset (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Voltage regulator V1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Voltage regulator V2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Output (OUT_HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Outputs (OUT1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAN communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAN transmit data input: pin TxDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
CAN receive data output: pin RxDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
CAN transmitter and receiver: pins CANH and CANL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
CAN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
LIN transmit data input: pin TxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LIN receive data output: pin RxD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LIN transmitter and receiver: pin LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
LIN transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LIN pull-up: pin LINPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Input: CSN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Inputs: CLK, DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
DI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Output: DO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
DO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
CSN timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
RXDL/NINT, RXDC/NINT timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Inputs: TxDC and TxDL for Flash Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Doc ID 023553 Rev 3
L99PM72PXP
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
List of tables
Write command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Write command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Write command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Format of data shifted out at SDO during write cycle: global status register . . . . . . . . . . . 80
Format of data shifted out at SDO during write cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 80
Format of data shifted out at SDO during write cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 80
Read command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Read command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Read command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Format of data shifted out at SDO during read cycle: global status register. . . . . . . . . . . . 82
Format of data shifted out at SDO during read cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 82
Format of data shifted out at SDO during read cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 82
Read and clear status command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read and clear status command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Read and clear status command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Format of data shifted out at SDO during read and clear status: global status register . . . 83
Format of data shifted out at SDO during read and clear status: data byte 1. . . . . . . . . . . 83
Format of data shifted out at SDO during read and clear status: data byte 2. . . . . . . . . . . 84
Read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
ID-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Silicon version identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SPI-frame-ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI register: CTRL register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
SPI register: STAT register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Overview of control register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Control register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Control register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Control register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Control register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Control register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Control register 5, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Control register 6: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Control register 6, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Control register 6, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Control register 7: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Control register 7, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Control register 7, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Control register 8: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Control register 8, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Control register 8, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Doc ID 023553 Rev 3
7/128
List of tables
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
8/128
L99PM72PXP
Control register 9: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Control register 9, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Control register 9, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Control register 10: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Control register 10, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Control register 10, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Control register 11: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Control register 11, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Control register 11, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Control register 12: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control register 12, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control register 12, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control register 13: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control register 13, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control register 13, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control register 14: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control register 14, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control register 14, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Control register 15: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Control register 15, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Control register 15, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Control register 16: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Control register 16, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Control register 16, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Control register 34: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Control register 34, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Control register 34, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Control register 35: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Control register 35, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Control register 35, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Status register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Status register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Status register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Status register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Status register 4, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Status register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Status register 5, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Doc ID 023553 Rev 3
L99PM72PXP
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage source with external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage source with external PNP and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Voltage source with external NPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage source with external NPN and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-down
conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Sequence to enter and exit SW Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Watchdog in FLASH Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Change watchdog timing within long open window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Change watchdog timing within window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General procedure to change watchdog timing out of Fail safe mode . . . . . . . . . . . . . . . . 28
Change watchdog timing out of Fail safe mode (Watchdog failure) . . . . . . . . . . . . . . . . . . 28
Example: exit Fail-Safe mode from Watchdog failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Master node configuration using LIN_PU (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Transceiver state diagram if selective wake-up is disabled (CR16 SW_EN = 0) . . . . . . . . 35
CAN transceiver state diagram if selective wake-up is enabled (CR16 SW_EN = 1). . . . . 36
CAN wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Overvoltage and undervoltage protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Phase shifted PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal data of PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
PowerSSO-36 thermal resistance junction to ambient vs PCB copper area (V1 ON) . . . . 53
PowerSSO-36 thermal impedance junction to ambient vs PCB copper area (single pulse
with V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
PowerSSO-36 thermal fitting model (V1 ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Watchdog timing (long, early, late and safe window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
LIN transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SPI - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SPI output timing (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SPI CSN - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SPI - CSN low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 75
Read configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Write configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Format of data shifted out at SDO during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Format of data shifted out at SDO during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Format of data shifted out at SDO during read and clear status operation . . . . . . . . . . . . 84
PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Doc ID 023553 Rev 3
9/128
Block diagram and pin description
1
L99PM72PXP
Block diagram and pin description
Figure 1.
Block diagram
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Doc ID 023553 Rev 3
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L99PM72PXP
Block diagram and pin description
Table 2.
Pin definitions and functions
Pin
Symbol
1
AGND
2
Function
Analog ground
RxDC -> CAN receive data output
RxDC/NINT NINT -> indicates remote CAN wake-up events in Active Mode (transceiver in
TRX_STBY; CAN_ACT = 0)
3
TxDC
CAN transmit data Input
4
CANH
CAN high level voltage I/O
5
CANL
CAN low level voltage I/O
6
N.C.
7
CANSUP
CAN supply input; to allow external CAN supply from V1 or V2 regulator.
8
NRESET
Nreset output to microcontroller; Internal pull-up of typ. 100 K
(reset state = LOW)
9
V1
Voltage regulator 1 output: 5 V supply e.g. micro controller, CAN transceiver
10
V2
Voltage regulator 2 output: 5 V supply for external loads (IR receiver,
potentiometer, sensors) or CAN transceiver. V2 is protected against reverse
supply.
11
TxDL
12
TBC
LIN transmit data input
RxDL -> LIN receive data output
RxDL/NINT NINT -> indicates local/remote wake-up events except CAN wake-up in Active
Mode provides a programmable timer interrupt signal
13
OP2+
Non inverting input of operational amplifier 2
14
OP2-
Inverting input of operational amplifier 2
15
OP2_OUT
16
DI
SPI: serial data input
17
DO
SPI: serial data output
18
CLK
SPI: serial clock input
19
CSN
SPI: chip select not input
20…22
WU1…3
23
OP1_OUT
24
OP1-
Inverting input of operational amplifier 1
25
OP1+
Non inverting input of operational amplifier 1
26
OUT4
High side driver output (7, typ)
27
Output of operational amplifier 2
Wake-up Inputs 1…3: Input pins for static or cyclic monitoring of external
contacts
Output of operational amplifier 1
Configurable as:
OUT3/FSO – High-side driver output (7, typ)
– Fail safe output pin (default)
28
OUT2
High side driver output (7, typ)
29
OUT1
High side driver output (7, typ)
30
OUT_HS
High side driver (1 , typ)
Doc ID 023553 Rev 3
11/128
Block diagram and pin description
Table 2.
L99PM72PXP
Pin definitions and functions (continued)
Pin
Symbol
31
VS
32
LINPU
33
LIN
34
REL1
Low side driver output (2 typ)
35
REL2
Low side driver output (2 typ)
36
PGND
Power ground (REL1/2, LIN and CAN GND), to be connected to AGND
externally
Figure 2.
Function
Power supply voltage
High side driver output to switch off LIN master pull up resistor
LIN bus line
Pin connection (top view)
AGND
1
36
PGND
RxDC / NINT
2
35
REL2
TxDC
3
34
REL1
CANH
4
33
LIN
CANL
5
32
LINPU
N.C.
6
31
Vs
CANSUP
7
30
OUT_HS
NRESET
8
29
OUT1
V1
9
28
OUT2
PowerSSO-36
V2
10
27
OUT3/FSO
TxDL
11
26
OUT4
RxDL / NINT
12
25
OP1P
OP2P
OP2M
13
24
OP1M
14
23
OPOUT1
OPOUT2
15
22
WU3
DI
16
21
WU2
DO
17
20
WU1
CLK
18
19
CSN
TAB = AGND
12/128
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
2
Detailed description
2.1
Voltage regulators
The L99PM72PXP contains two independent and fully protected low drop voltage
regulators, which are designed for very fast transient response and do not require
electrolytic output capacitors for stability.
The output voltage is stable with ceramic load capacitors 220 nF.
2.1.1
Voltage regulator: V1
The V1 voltage regulator provides 5 V supply voltage and up to 250 mA continuous load
current and is mainly intended for supply of the system microcontroller. The V1 regulator is
embedded in the power management and Fail_safe functionality of the device and operates
according to the selected operating mode.
It can be used to supply the internal HS CAN Transceiver via the CANSUP pin externally. In
case of a short circuit condition on the CAN bus, the output current of the transmitter is
limited to 100 mA and the transceiver is turned off in order to ensure continued supply of the
microcontroller.
In addition the regulator V1 drives the L99PM72PXP internal 5 V loads. The voltage
regulator is protected against overload and overtemperature. An external reverse current
protection has to be provided by the application circuitry to prevent the input capacitor from
being discharged by negative transients or low input voltage. Current limitation of the
regulator ensures fast charge of external bypass capacitors. The output voltage is stable for
ceramic load capacitors 220 nF.
If the device temperature exceeds the TSD1 threshold, all outputs (OUTx, RELx, V2, LIN)
are deactivated except V1. Hence the micro controller has the possibility for interaction or
error logging. In case of exceeding TSD2 threshold (TSD2 > TSD1), also V1 is deactivated
(see Figure 23: Thermal shutdown protection and diagnosis). A timer is started and the
voltage regulator is deactivated for tTSD = 1 sec. During this time, all other wakeup sources
(CAN, LIN, WU1...3 and wake up of µC by timer) are disabled. After 1 sec, the voltage
regulator tries to restart automatically. If the restart fails 7 times, within one minute, without
clearing and thermal shutdown condition still exists, the L99PM72PXP enters the Forced
VBat_standby Mode.
In case of short to GND at "V1" after initial turn on (V1 < 2 V for t > tV1 short) the
L99PM72PXP enters the Forced VBat_standby Mode. Reactivation (wake-up) of the device
can be achieved with signals from CAN, LIN, WU1..3 or periodic wake by timer.
2.1.2
Voltage regulator: V2
The voltage regulator V2 can supply additional 5 V loads (e.g. logic components or the
integrated HS CAN transceiver or external loads such as sensors or potentiometers. The
maximum continuous load current is 100 mA. The regulator is protected against:
●
Overload
●
Overtemperature
●
Short circuit (short to ground and battery supply voltage)
●
Reverse biasing
Doc ID 023553 Rev 3
13/128
Detailed description
2.1.3
L99PM72PXP
Increased output current capability for voltage regulator V2
For applications, which require high output currents, the output current capability of the
regulator can be increased my means of the integrated operational amplifiers and an
external pass transistor.
Figure 3.
Voltage source with external PNP
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Figure 3 shows a possible configuration with a PNP pass element using Voltage Regulator 2
to provide the voltage reference for the regulated output voltage V3.
The VS operating range for this circuit is 5.5 V to 18 V. It is important respect the input
common mode range specified for the operational amplifiers.
The output voltage V3 can be calculated using the following formula (for R3 = R4):
V2 R1 + R2
V 3 = ------- --------------------- V
2
R2
14/128
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
The circuit in Figure 4 provides additional current limitation using an additional PNP
transistor and R6, which allows setting the current limit.
Figure 5.
Voltage source with external NPN
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Figure 5 shows a possible configuration with an NPN pass element using Voltage Regulator
2 to provide the voltage reference for the regulated output voltage V3. This circuit requires
fewer components compared to the configuration in Figure 3 but has a limited VS operating
range (6 V to 18 V).
The output voltage V3 can be calculated using the following formula (for R3 = R4):
V2 R1 + R2
V 3 = ------- --------------------- V
2
R2
The circuit in Figure 6 provides additional current limitation using an additional NPN
transistor and R5 which allows setting the current limit.
Doc ID 023553 Rev 3
15/128
Detailed description
L99PM72PXP
Alternatively, Voltage Regulator 1 can be used to provide the 5 V reference for this topology.
However, the additional current consumption through R3 and R4 has to be considered in
V1_standby Mode.
2.1.4
Voltage regulator failure
The V1 and V2 regulator output voltages are monitored.
In case of a drop below the V1, V2 - fail thresholds (V1,2 < 2 V, typ for t > 2 µs), the V1,2 -fail
bits are latched. The fail bits can be cleared by a dedicated SPI command.
Short to ground detection
If 4 ms after turn on of the regulator the V1,2 voltage is below the V1,2 fail thresholds,
(independent for V1,2), the L99PM72PXP identifies a short circuit condition at the related
regulator output and the regulator are switched off.
In case of V1 short to GND failure the device enters VBat_standby mode automatically. Bits
Forced VBAT TSD2/SHTV1 and V1_fail were set.
In case of a V2 short to GND failure the V2 short and V2 fail bit is set.
If the output voltage of the corresponding regulator once exceeded the V1,2_fail thresholds
the short to ground detection is disabled. If a short to ground condition occurs the regulator
outputs switch of due to Thermal shutdown (V1 at TSD2; V2 at TSD1).
16/128
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
2.1.5
Voltage regulator behavior
Figure 7.
Voltage regulator behaviour and diagnosis during supply voltage ramp-up / rampdown conditions
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Operating modes
The L99PM72PXP can be operated in 4 different operating modes:
●
Active
●
FLASH
●
V1_standby
●
VBat_standby
A cyclic monitoring of wake-up inputs and a periodic interrupt / wake-up by timer is available
in stand-by modes.
2.2.1
Active Mode
All functions are available and the device is controlled by the ST SPI Interface.
2.2.2
Flash Mode
To program the system microcontroller via LIN or HS CAN bus signals, the device can be
operated in LIN Flash Mode or CAN Flash Mode where the internal watchdog is disabled.
Doc ID 023553 Rev 3
17/128
Detailed description
L99PM72PXP
Moreover, in Flash Mode the DO-output is a test output and cannot be used for device
communication. All other device features in Flash Mode are available as in Active Mode.
The CAN-Receiver is enabled in CAN Flash Mode by default; the CAN Transmitter has to be
enabled by setting the CAN_ACT bit to ‘1’.
A transition from Flash Modes to V1_standby or Vbat_standby is not possible.
The modes can be entered by applying an external voltage at the respective pin:
●
VTxDL > Vflash (CAN Flash Mode)
●
VTxDC > Vflash (LIN Flash Mode)
At exit from Flash Modes (VTxD < Vflash) no NReset pulse is generated and the watchdog
starts with a long open window.
Note:
Setting both TxDL and TxDC to high voltage levels (> Vflash) is not allowed Communication
at the respective TxD pin is not possible
2.2.3
SW-Debug Mode
To allow software debugging, the watchdog can be deactivated by setting CR34: WDEN = 0.
Write access to this bit is only possible during CAN Flash Mode in order to prevent
accidental deactivation of the watchdog. After setting the WDEN bit the CAN Flash Mode
can be left (VTxDL < VFlash) and the Watchdog remains deactivated (see Figure 8)
In SW-Debug Mode, the full device functionality is available.
Figure 8.
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2.2.4
V1_standby mode
The transition from Active Mode to V1_standby mode is controlled by SPI.
To supply the micro controller in a low power mode, the voltage regulator 1 (V1) remains
active. In order to reduce the current consumption, the regulator goes in low current mode
as soon as the supply current of the microcontroller goes below the ICMP current threshold.
At this transition, the L99PM72PXP also deactivates the internal watchdog.
Relay outputs, LIN and CAN Transmitters are switched off in V1_standby Mode. High side
outputs and the V2 regulator remain in the configuration programmed prior to the standby
command.
18/128
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
A cyclic supply of external contacts and a synchronized monitoring of the contact state can
be activated and configured by SPI.
In V1_standby mode various wake-up sources can be individually programmed. Each wakeup event puts the device into Active Mode and forces the RxDL/NINT pin to a low level
indicating the wake-up condition to the microcontroller.
After Power ON Reset (POR) all wake up sources are activated by default except the
periodic interrupt / wake timer.
With the interrupt timer the micro controller can be forced from 'stop' to 'run' after a
programmable period. The RxDL/NINT pin is forced low after the timer is elapsed. The
L99PM72PXP enters active mode and is awaiting a valid watchdog trigger.
Both internal timers can be used for this feature.
The interrupt timer (TINT) at pin RxDL/NINT is only available in V1_standby mode.
Note:
Inputs TxDL, TxDC must be at recessive (high) level and CSN must be at high level or at
high impedance in order to achieve minimum standby current in V1_standby Mode.
Inputs DI and CLK must be at GND or at high impedance to achieve minimum standby
current in V1_standby Mode.
2.2.5
Interrupt
The interrupt signal (linked to RxDL/NINT) indicates a wake-up event from V1_standby mode.
In case of a wake-up by Wake-up Inputs, activity on LIN or CAN, SPI access or TimerInterrupt the RxDL/NINT pin is pulled low for t = tinterrupt.
When CAN_ACT = 0 (during V1_standby Mode or Active Mode) a WUP (SW_EN = 0) or a
WUF (SW_EN = 1) generates an interrupt on RxDC/NINT to signalize CAN communication
on the bus to the µC.
In case of a CAN communication timeout an interrupt at RxDC /NINT is generated and the
CAN_TO flag is set.
In case of V1_standby mode and (IV1 > ICMP), the device remains in standby mode, the V1
regulator switches to high current mode and the watchdog starts. No Interrupt signal is
generated.
Table 3.
Operating
mode
CAN wake-up signalization
Event
Wake-up
transition to
active
WUP or WUF(1)
Not applicable
Active
CAN timeout
Status flag
Interrupt
Transceiver
state
Wake_CAN WUP
or
WUP/WUF
RxDC
TRX_STBY
CAN_TO
RxDC
TRX_STBY
WUP or WUF(1)
Yes
Wake_CAN WUP
or
WUP/WUF
RxDL
TRX_STBY
CAN timeout
No
CAN_TO
RxDC
TRX_STBY
V1_standby
Doc ID 023553 Rev 3
19/128
Detailed description
Table 3.
L99PM72PXP
CAN wake-up signalization (continued)
Operating
mode
Event
Wake-up
transition to
active
Status flag
Interrupt
Transceiver
state
WUP or
WUP/WUF(2)
Yes
Wake_CAN
WUP/WUF
Not
applicable
TRX_STBY
CAN timeout
Transition to
TRX_SLEEP
CAN_TO
Vbat_standby
TRX_SLEEP
1. SW_EN = 0:
— wake-up according ISO 11898-5 (WUP)
— Flags: Wake_CAN, WUP
SW_EN = 1:
— wake-up according ISO 11898-6 (WUP)
— Flags: Wake_CAN, WUP, WUF (the WUP flag is set only if the received WUF also contained a WUP)
2. SW_EN = 0:
— wake-up according ISO 11898-5 (on WUP)
— Flags: Wake_CAN, WUP
SW_EN = 1:
— wake-up according ISO 11898-6 (on WUP/WUF combination)
— After the reception of a wake-up pattern (WUP) the CAN Enhanced Voltage Biasing is turned on until a
CAN timeout is detected
— Flags: Wake_CAN, WUP, WUF
2.2.6
VBat_standby mode
The transition from Active Mode to VBat_standby mode is initiated by an SPI command.
In VBat_standby Mode, the V1 voltage regulator, relay outputs, LIN and CAN Transmitters are
switched off. High side Outputs and the V2 Regulator remain in the configuration
programmed prior to the standby command.
In VBat_standby mode the current consumption of the L99PM72PXP is reduced to a minimum
level.
An NReset pulse is generated upon wake-up from Vbat_standby Mode.
Note:
Inputs TXDL, TXDC and CSN must be terminated to GND in Vbat_standby to achieve
minimum standby current.
This can be achieved with the internal ESD protection diodes of the microcontroller
(microcontroller is not supplied in this mode; V1 is pulled to GND).
2.2.7
Wake up from Standby Modes
A wake-up from standby mode switches the device to active mode. This can be initiated by
one or more of the following events:
Table 4.
Wake up from Standby Modes
Wake up source
20/128
Description
LIN bus activity
Can be disabled by SPI
CAN bus activity
Can be disabled by SPI
Selective Wake-up can be configured by SPI
Level change of WU1 - 3
Can be individually configured or disabled by SPI
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L99PM72PXP
Detailed description
Table 4.
Wake up from Standby Modes (continued)
Wake up source
IV1 > ICMP
Description
Device remains in V1_standby mode but watchdog is enabled (If ICMP = 0)
and the V1 regulator goes into High Current Mode (Increased Current
Consumption). No interrupt is generated.
programmable by SPI
– V1_standby Mode: device wakes up and Interrupt signal is generated at
Timer Interrupt /
RxDL/NINT when programmable timeout has elapsed
Wake up of µC by TIMER
– VBat_standby Mode: device wakes up, V1 regulator is turned on and
NReset signal is generated when programmable timeout has elapsed
SPI Access
Always active (except in VBat_standby mode)
Wake up event: CSN is low and first rising edge on CLK
To prevent the system from a deadlock condition (no wake up possible) a configuration
where the periodic timer interrupt and wake up by LIN and HS CAN are disabled, is not
allowed. The default configuration is entered for all wake-up sources in case of such an
invalid setting.
All wake-up events from V1_standby mode (except IV1 > ICMP) are indicated to the
microcontroller by a low-pulse (duration: 56 µs) at RxDL/NINT or RxDC/NINT (see Table 3:
CAN wake-up signalization)
Wake-up from V1_standby by SPI Access might be used to check the interrupt service
handler.
2.2.8
Wake up inputs
The de-bounced digital inputs WU1...WU3 can be used to wake up the L99PM72PXP from
standby modes. These inputs are sensitive to any level transition (positive and negative
edge)
For static contact monitoring, a filter time of 64µs is implemented at WU1-3. The filter is
started when the input voltage passes the specified threshold.
In addition to the continuous sensing (static contact monitoring) at the wake up inputs, a
cyclic sense functionality is implemented. This feature allows periodical activation of the
wake-up inputs to read the status of the external contacts. The periodical activation can be
linked to Timer 1 or Timer 2 (see Section 2.2.9). The input signal is filtered with a filter time
of 16 µs after a programmable delay (80 µs or 800 µs) according to the configured Timer
On-time. A wake-up is processed if the status has changed versus the previous cycle.
The Outputs OUT_HS and OUT1-4 can be used to supply the external contacts with the
timer setting according to the cyclic monitoring of the wake-up inputs.
If the wake-up inputs are configured for cyclic sense mode the input filter timing and input
filter delay (WUx_filt in control register 2) must correspond to the setting of the High Side
Output which supplies the external contact switches (OUTx in control register 0).
In Standby Mode, the inputs WU1-3 are SPI configurable for pull-up or pull-down current
source configuration according to the setup of the external. In active mode the inputs have a
pull down resistor.
In Active Mode, the input status can be read by SPI (Status Register 2). Static sense should
be configured (Control Register 2) before the read operation is started (In cyclic sense
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Detailed description
L99PM72PXP
configuration, the input status is updated according to the cyclic sense timing; therefore,
reading the input status in this mode may not reflect the actual status).
2.2.9
Cyclic contact supply
In V1_standby and VBat_standby modes, any high side driver output (OUT1..4, OUTHS) can be
used to periodically supply external contacts.
The timing is selectable by SPI
Timer 1: period is X s. The on-time is 10 ms resp. 20 ms: with X {1, 2, 3, 4s}
Timer 2: period is X ms. The on-time is 100 µs resp. 1 ms: with X {10, 20, 50, 200 ms}
Timer 1 and Timer 2 are re-started with every valid write command to CR3 (CSN low to high
transition). The timers start with the off-phase.
2.2.10
Timer interrupt / wake-up of microcontroller by timer
During standby modes the cyclic wake up feature, configured via SPI, allows waking up the
µC after a programmable timeout according to timer1 or timer 2.
From V1_standby mode, the L99PM72PXP wakes up (after the selected timer has elapsed)
and sends an interrupt signal (via RxDL/NINT pin) to the µC. The device enters active mode
and the watchdog is started with a long open window. The microcontroller can send the
device back into V1_standby after finishing its tasks.
From Vbat_standby mode, the L99PM72PXP wakes up (after the selected timer has elapsed),
turns on the V1 regulator and provides an NReset signal to the µC. The device enters active
mode and the watchdog is started with a long open window. The microcontroller can send
the device back into Vbat_standby after finishing its tasks.
2.3
Functional overview (truth table)
Table 5.
Functional overview (truth table)
Operating modes
Function
Comments
Active Mode
Voltage regulator, V1
Voltage regulator, V2
VOUT=5V
VOUT=5V
Reset generator
Window watchdog
V1 monitor
Wake up
HS-cyclic supply
Relay driver
22/128
Oscillator
time base
V1_standby
static mode
VBat_standby
static mode
(cyclic sense)
(cyclic sense)
On(1)
On
(2)
On/ Off
On
(2)
/ Off
Off
On
(2)
/ Off
On
On
Off
On
Off (ON: IV1 > ICMPthreshold and
ICMP = 0)
Off
Off
Active(3)
Active(3)
On / Off
On(2) / Off
On(2) / Off
On
Off
Off
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
Table 5.
Functional overview (truth table) (continued)
Operating modes
V1_standby
static mode
VBat_standby
static mode
(cyclic sense)
(cyclic sense)
On
Off
Off
On
Off(4)
Off(4)
On / Off(5)
Off(4)
Off(4)
OUT3/FSO OFF
(6)
OUT3/FSO OFF(6)
OUT3/FSO OFF(6)
Oscillator
On
Off(7)
Off(7)
VS-Monitor
On
(8)
(8)
Function
Comments
Active Mode
Operational amplifiers
LIN
LIN 2.1
HS_CAN
FSO (if configured by
SPI), active by default
Fail safe
output
1. Supply the processor in low current mode.
2. Only active when selected via SPI.
3. Unless disabled by SPI
4. The bus state is internally stored when going to standby mode. A change of bus state leads to a wake-up
after exceeding of internal filter time (if wake-up by LIN or CAN is not disabled by SPI). Selective Wake
functionality if enabled by SPI
5. After power-on, the HS CAN transceiver is in ‘CAN Trx Standby’ Mode. It is activated by SPI command
(CAN_ACT = 1)
6. ON in Failsafe Condition: If Standby mode is entered with active Fail Safe mode, the output remains ON in
Standby mode.
7. ON, if cyclic sense is enabled.
8. Cyclic activation = pulsed ON during cyclic sense
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Detailed description
Figure 9.
L99PM72PXP
Main operating modes
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2.4
Configurable window watchdog
During normal operation, the watchdog monitors the micro controller within a programmable
trigger cycle: (10 ms, 50 ms, 100 ms, 200 ms)
In VBat_standby and Flash program modes, the watchdog circuit is automatically disabled. In
V1_standby mode a wake up by timer is programmable in order to wake up the µC (see
Section 2.2.10). After wake-up, the Watchdog starts with a long open window. After serving
the watchdog, the microcontroller may send the device back to V1_standby mode.
After power-on or Standby mode, the watchdog is started with a long open window (65 ms
nominal). The long open window allows the micro controller to run its own setup and then to
trigger the watchdog via the SPI. The trigger is processed when the CSN input becomes
HIGH after the transmission of the SPI word.
Writing '1' to the watchdog trigger bit terminates the long open window and start the window
watchdog (the timing is programmable by SPI). Subsequently, the micro controller has to
24/128
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer
to Figure 32).
A correct watchdog trigger signal immediately starts the next cycle.
After 8 watchdog failures in sequence, the V1 regulator is switched off for 200 ms. If
subsequently, 7 additional watchdog failures occur, the V1 regulator is completely turned off
and the device goes into VBat_standby mode until a wakeup occurs.
In case of a Watchdog failure, the outputs (RELx, OUTx, V2) are switched off and the device
enters Fail_safe mode (i. e. all control registers are set to default values except the 'OUT3
control bit').
The following diagrams illustrate the Watchdog behavior of the L99PM72PXP. The diagrams
are split into 3 parts. First diagram shows the functional behavior of the watchdog without
any error. The second diagram covers the behavior covering all the error conditions, which
can affect the watchdog behavior. Third diagram shows the transition in and out of FLASH
mode. All 3 diagrams can be overlapped to get all the possible state transitions under all
circumstances. For a better readability, they were split in normal operating, operating with
errors and flash mode.
Figure 10. Watchdog in normal operating mode (no errors)
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Detailed description
L99PM72PXP
Figure 11. Watchdog with error conditions
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2.4.1
Change watchdog timing
There are 4 programmable Watchdog timings available, which represent the nominal trigger
time in window mode. To change the watchdog timing, a new timing has to be written by SPI.
The new timing gets active with the next valid watchdog trigger. The following figures
illustrate the sequence, which is recommended to use, changing the timing within long open
window and within window mode.
26/128
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L99PM72PXP
Detailed description
Figure 13. Change watchdog timing within long open window
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Figure 14. Change watchdog timing within window mode
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If the device is in Fail_safe mode, the Control Registers are locked for writing. To change the
watchdog timing out of Fail_safe mode, first the Fail_safe condition must be solved,
respective confirmed from the microcontroller. Afterwards the new watchdog timing can be
programmed using the sequence from Figure 15. Since the actions to remove, a Fail_safe
condition can differ from the root cause of the fail safe the following diagram shows the
general procedure how to change the watchdog timing out of Fail_safe mode. Figure 16
shows the procedure to change watchdog timing with a previous watchdog failure, since this
is a special Fail_safe scenario.
Doc ID 023553 Rev 3
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Detailed description
L99PM72PXP
Figure 15. General procedure to change watchdog timing out of Fail safe mode
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Figure 16. Change watchdog timing out of Fail safe mode (Watchdog failure)
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2.5
Fail Safe Mode
2.5.1
Single failures
L99PM72PXP enters Fail Safe Mode in case of:
●
Watchdog failure
●
V1 turn on failure
–
●
V1 undervoltage (V1 < VRTH for t > tUV1)
●
Thermal Shutdown TSD2
●
SPI failure
–
28/128
V1 short (V1 < V1fail for t > tV1short)
DI stuck to GND or VCC (SPI frame = ’00 00 00’ or ‘FF FF FF’)
Doc ID 023553 Rev 3
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L99PM72PXP
Detailed description
The Fail Safe functionality is also available in V1_standby Mode. During V1_standby Mode the
Fail Safe Mode is entered in the following cases:
●
V1 undervoltage (V1 < VRTH for t > tUV1)
●
Watchdog failure (if watchdog still running due to IV1 > ICMP)
●
Thermal shutdown TSD2
In Fail Safe Mode the L99PM72PXP returns to a default. The Fail Safe condition is indicated
to the remaining system in the Global Status Register. The conditions during Fails Safe
Mode are:
●
All outputs are turned off
●
All Control Registers are set to default values (except OUT3/FSO configuration)
–
This includes the programmed wake-up-frame. Therefore it is mandatory to
reprogram the wake-up-frame before entering the selective wake-up mode after a
Fail_safe event(a)
●
Write operations to Control Registers are blocked until the Fail Safe condition is cleared
(see Table 6)
●
LIN and HS CAN transmitter, operational amplifiers and SPI remain on
●
Corresponding Failure Bits in Status Registers are set.
●
FSO Bit (Bit 0 Global Status Register) is set
●
OUT3/FSO is activated if configured as Fail Safe Output
If OUT3 is configured as FSO, the internal Fail-Safe Mode can be monitored at OUT3 (High
side driver is turned on in Fail-safe Mode). Self-protection features for OUT3 when
configured as FSO are active (See Section 3.3: High side driver outputs)
OUT3 is configured as Fail Safe Output by default. It can be configured to normal high side
driver operation by SPI. It this case, the configuration remains until VS Power On.
If the Fail Safe Mode was entered it keeps active until the Fail safe condition is removed and
the Fail Safe was read by SPI. Depending on the root cause of the Fail Safe operation, the
actions to exit Fail safe Mode are as shown in the following table.
Table 6.
Fail-Safe conditions and exit modes
Failure source
µC (oscillator)
Failure condition
Diagnosis
Exit from Fail_safe
Mode
Watchdog early
write failure or
expired window
Fail_safe = 1; WDfail = n + 1
Short at turn-on
Fail_safe = 1;
Read & Clear SR3 after
Forced_Sleep_TSD2_SHTV1 = 1 wake
Undervoltage
Fail_safe = 1; V1_fail = 1 (1)
V1
TRIG = 1 during LOWi
and read Fail_safe bit
V1 > VRTH
Read Fail_safe bit
a. Even though it is still possible after a Fail_safe event to enter the selective-wake-up mode, the device wakes
only up with the default values of the configuration register (see Section 6.2.2: Overview control register).
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Detailed description
L99PM72PXP
Table 6.
Fail-Safe conditions and exit modes (continued)
Failure source
Failure condition
Diagnosis
Exit from Fail_safe
Mode
Temperature
Tj > TSD2
Fail_safe = 1; TW = 1; TSD1 = 1;
TSD2 = 1
Tj < TSD2
Read & Clear SR3
SPI
DI short to GND or
VCC
Fail_safe = 1
Valid SPI command
1. If V1 < V1_Fail (for t > tv1fail)
The Fail_safe Bit is located in the Global Status Register (Bit 0)
Figure 17. Example: exit Fail-Safe mode from Watchdog failure
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2.5.2
Multiple failures – entering forced VBat_standby Mode
If the Fail-Safe condition persists and all attempts to return to normal system operation fail,
the L99PM72PXP enters the Forced Vbat_standby Mode in order to prevent damage to the
system. The Forced Vbat_standby Mode can be terminated by any regular wake-up event. The
root cause of the Forced Vbat_standby is indicated in the SPI Status Registers
The forced Vbat_standby Mode is entered in case of:
30/128
●
Multiple watchdog failures: forced sleep WD = 1 (15 x watchdog failure)
●
Multiple thermal shutdown 2: forced sleep TSD2/SHTV1 = 1 (7 x TSD2)
●
V1 short at turn-on: forced sleep TSD2/SHTV1 = 1 (V1 < V1_Fail for t > tv1fail)
Doc ID 023553 Rev 3
L99PM72PXP
Detailed description
Table 7.
Persisting fail safe conditions and exit modes
Failure source Failure condition
µC (oscillator)
V1
Temperature
2.6
Diagnosis
Exit from Fail_safe Mode
Wake-up
TRIG = 1 during LOWi
Read & Clear SR3
15 consecutive
watchdog failures
Fail_safe = 1;
Forced_Sleep_WD = 1
short at turn-on
Fail_safe = 1;
Read & Clear SR3 after
Forced_Sleep_TSD2_SHTV1 = 1 wake-up
7 times TSD2
Fail_safe = 1; TW = 1; TSD1 = 1;
Read & Clear SR3 after
TSD2 = 1;
wake-up
Forced_Sleep_TSD2_SHTV1=1
Reset output (NRESET)
If V1 is turned on and the voltage exceeds the V1 reset threshold, the reset output
“NRESET” is pulled up by internal pull up resistor to V1 voltage after a reset delay time (trd).
This is necessary for a defined start of the micro controller when the application is switched
on. Since the NRESET output is realized as an open drain output it is also possible to
connect an external NRESET open drain NRESET source to the output. As soon as the
NRESET is released by the L99PM72 the Watchdog timing starts with a long open window.
A reset pulse is generated in case of:
2.7
●
V1 drops below VRTH (configurable by SPI) for t > tUV1
●
watchdog failure
●
turn-on of the V1 regulator (VS power-on or wake-up from Vbat_standby mode)
Operational amplifiers
The operational amplifiers are especially designed to be used for sensing and amplifying the
voltage drop across ground connected shunt resistors. Therefore the input common mode
range includes -0.2 V to 3V.
The operational amplifiers are designed for -0.2 V to 3 V input voltage swing and rail-to-rail
output voltage range.
All pins (positive, negative and outputs) are available to be able to operate in non-inverting
and inverting mode. Both operational amplifiers are on-chip compensated for stability over
the whole operating range within the defined load impedance.
The Operational Amplifiers may also be used to setup an additional high current voltage
source with an external pass element. Refer to Section 2.1.3 for a detailed description.
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Detailed description
2.8
L99PM72PXP
LIN Bus Interface
Features:
●
Speed communication up to 20kbit/s.
●
LIN 2.1 compliant (SAEJ2602 compatible) transceiver.
●
GND disconnection fail safe at module level.
●
Off mode: does not disturb network.
●
GND shift operation at system level.
●
Micro controller Interface with CMOS compatible I/O pins.
●
Internal Pull-up resistor
●
Internal High Side Switch to disconnect Master Pull-up resistor in case of short circuit
of bus signal (b)
●
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
●
Matched output slopes and propagation delay
In order to further reduce the current consumption in standby mode, the integrated LIN bus
interface offers an ultra low current consumption.
2.8.1
Error handling
The L99PM72PXP provides the following three error handling features which are not
described in the LIN Spec. V2.1, but are realized in different stand alone LIN transceivers /
micro controllers to switch the application back to normal operation mode.
At VS > VPOR (i.e. VS power-on reset threshold), the LIN transceiver is enabled.
The LIN transmitter is disabled in case of the following errors:
●
Dominant TxDL time out
●
LIN permanent recessive
●
Thermal Shutdown 1
●
VS Over- / Undervoltage
The LIN receiver is not disabled in case of any failure condition.
Dominant TxDL time out
If TXDL is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the
status bit is latched and can be read and optionally cleared by SPI. The transmitter remains
disabled until the status register is cleared. This feature can be disabled via SPI.
Permanent recessive
If TXDL changes to dominant (low) state but RXDL signal does not follow within 40 µs the
transmitter is disabled, the status bit is latched and can be read and optionally cleared by
SPI. The transmitter remains disabled until the status register is cleared.
b. Use of the Master Pull-up switch is optional.
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Detailed description
Permanent dominant
If the bus state is dominant (low) for more than 12 ms a permanent dominant status is
detected. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter is not disabled.
2.8.2
Wake up (from LIN)
In standby mode the L99PM72PXP can receive a wake up from LIN bus. For the wake up
feature the L99PM72PXP logic differentiates two different conditions.
Normal wake up
Normal wake up can occur when the LIN transceiver was set in standby mode while LIN was
in recessive (high) state. A dominant level at LIN for tlinbus, switches the L99PM72PXP to
active mode.
Wake up from short to GND condition
If the LIN transceiver was set in standby mode while LIN was in dominant (low) state,
recessive level at LIN for tlinbus, switchs the L99PM72PXP to active mode.
Note:
A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.
2.8.3
LIN Pull-Up
The master node pull-up resistor (1 k) can be connected to VS using the internal LIN_PU
high side switch. This high side switch can be controlled by SPI in order to allow
disconnection of the pull-up resistor in case of LIN bus short to GND conditions.
Figure 18. Master node configuration using LIN_PU (optional)
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Detailed description
L99PM72PXP
LIN_PU high side driver characteristics:
2.9
●
Activated by default and can be turned off by SPI Command (CR4)
●
remains active in standby modes
●
Switch off only in case of over-temperature (TSD2 = thermal shut down #2)
●
no over current protection.
●
Typical RDS(on), 10
High speed CAN bus transceiver
General requirements:
●
Communication Speed up to 1Mbit/s.
●
ISO 11898-2 and ISO 11898-5 compliant
●
Selective wake-up functionality according to ISO 11898-6
●
Non-selective wake-up functionality according to ISO 11898-5
●
SAE J2284 compliant
●
Function range from -27 V to 40 V DC at CAN pins.
●
GND disconnection fail safe at module level.
●
GND shift operation at system level.
●
Microcontroller Interface with CMOS compatible I/O pins.
●
ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2
●
Matched output slopes and propagation delay
●
Receive-only mode available
For further reducing the current consumption in standby mode, the integrated CAN bus
interface offers an ultra-low current consumption.
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2.9.1
Detailed description
CAN transceiver operating modes
Figure 19. Transceiver state diagram if selective wake-up is disabled (CR16 SW_EN = 0)
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Detailed description
L99PM72PXP
Figure 20. CAN transceiver state diagram if selective wake-up is enabled (CR16 SW_EN = 1)
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TRX Normal Mode
Full functionality of the CAN-Transceiver is available (transmitter and receiver) and the bus
biasing is enabled.
State transitions from 'TRX Normal' mode to 'VBat_standby' and 'V1_standby' are possible. No
interrupt is generated in this mode.
CAN TRX_STBY Mode
The CAN-Transmitter is disabled in this mode and the RxDC-pin is kept at high ('recessive')
level.
If selective wake-up is enabled (SW_EN=1), the receiver, CAN biasing and the reference
oscillator are active. Once a wake up frame (WUF) is detected by the internal CAN frame
detection logic, this wake-up event is indicated to the micro-controller by an interrupt signal
(see Section 2.2.5: Interrupt for more details). A wake-up pattern (WUP) is not required and
does not count as a frame error.
Since a further CAN-timeout cannot be indicated, if the CAN_TO bit has already been set, it
is recommended to clear this bit before entering V1_standby Mode.
If selective wake-up is disabled (SW_EN = 0), the CAN-Receiver is capable to detect a
wake-up pattern (WUP). In V1_standby Mode and Active Mode, a WUP is indicated to the
micro-controller by an interrupt signal (see Section 2.2.5: Interrupt for more details). In this
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Detailed description
mode (SW_EN = 0) the automatic voltage biasing is disabled and the transceiver biasing
works according to ISO 11898-5.
There is no automatic state transition into TRX Normal Mode in case of a detected CAN
wake-up (WUF or WUP). After serving the interrupt the micro controller can initiate a state
transition into TRX Normal Mode by setting the SPI bit CAN_ACT to '1'.
TRX_SLEEP (SW_EN=1)
The CAN and LIN Transceivers are disabled. The CAN selective wakeup reference oscillator
is off, while the receiver is in low power mode.
After the detection of CAN communication (WUP), the transceiver enters
'PN_TRX_selective_sleep' mode, starts the oscillator and decodes the CAN frame.
'TRX_SLEEP' mode is entered automatically after a CAN communication timeout.
PN TRX Selective Sleep (SW_EN=1)
In this mode the CAN frame detection logic is enabled (receiver and reference oscillator
enabled). In case of receiving a wake up frame (WUF) a state transition to 'CAN TRX_STBY'
is done. After the biasing has been switched on, not more than four CAN frames are ignored
before a wake-up frame is recognized and the device wakes up.
If there is no CAN communication and the CAN bus is recessive for longer than tsilence, an
automatic state transition to 'TRX_SLEEP' is done.
In case of a Frame-Detect-Error (SR4, FDERR=1), an automatic wake up is performed and
the selective wakeup feature is disabled (SW_EN=0).
2.9.2
Sequence for enabling selective wakeup
After power-on reset the selective wakeup feature is disabled.
The Configuration Registers 7 to 15 have to be read and verified by the microcontroller in
order to ensure a valid configuration. A read operation to Registers 7 to 15 is required to
allow enabling the selective wake-up feature (set SW_EN=1).
A valid read operation is indicated by the SW_RDxx bits in SR 4. The SW_RDxx bits are
reset to 0 with every WRITE operation.
When all SW_RD bits are set, the SW_EN bit in CR 16 can be set to enable the Selective
Wakeup function. In case the SYSERROR bit in SR 4 is set while Selective Wakeup is
enabled, the Selective Wakeup is automatically disabled. In case SYSERROR is set,
enabling the Selective Wakeup function is prohibited.
2.9.3
CAN error handling
The L99PM72PXP provides the following four error handling features.
After power-on reset (VS > VPOR) the CAN transceiver is disabled. The transceiver is
enabled by setting the CAN_ACT bit in Control Register 4.
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Detailed description
L99PM72PXP
The CAN transmitter is disabled automatically in case of the following errors:
●
Dominant TxDC time out
●
CAN permanent recessive
●
RxDC permanent recessive
●
Thermal shutdown 1
The CAN receiver is not disabled in case of any failure condition.
Dominant TxDC time out
If TXDC is in dominant state (low) for t > tdom(TxD) the transmitter is disabled, status bit is
latched and can be read and optionally cleared by SPI. The transmitter remains disabled
until the status register is cleared.
CAN permanent recessive
If TXDC changes to dominant (low) state but CAN bus does not follow for 4 times, the
transmitter is disabled, status bit is latched and can be read and optionally cleared by SPI.
The transmitter remains disabled until the status register is cleared.
CAN permanent dominant
If the bus state is dominant (low) for t > tCAN a permanent dominant status is detected. The
status bit is latched and can be read and optionally cleared by SPI. The transmitter is not
disabled.
RXDC permanent recessive
If RXDC pin is clamped to recessive (high) state, the controller is not able to recognize a bus
dominant state and could start messages at any time, which results in disturbing the overall
bus communication. Therefore, if RXDC does not follow TXDC for 4 times the transmitter is
disabled. The status bit is latched and can be read and optionally cleared by SPI. The
transmitter remains disabled until the status register is cleared.
2.9.4
Wake up by CAN
The L99PM72PXP supports 2 wakeup modes. The selective wakeup according to ISO
11898-6 or the wakeup by any bus activity according to ISO 11898-2/-5. The wake up
behavior can be configured by SPI (see Chapter 6: ST SPI).
Wake up by CAN pattern (WUP)
The default setting for the wake up behavior after power-on reset is the wake up by regular
communication on the CAN bus. When the CAN transceiver is in a Standby Mode (CAN
TRX_STBY or TRX_SLEEP) the device can be woken up by sending two consecutive
dominant bits separated by a recessive bit.
Normal pattern wake up can occur when CAN pattern wake up option is enabled and the
CAN transceiver was set in Standby Mode (CAN TRX_STBY or TRX_SLEEP) while CAN
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Detailed description
bus was in recessive (high) state or dominant (low) state. In order to wake up the
L99PM72PXP, the following criteria must be fulfilled:
Note:
●
The CAN interface wake-up receiver must receive a series of two consecutive valid
dominant pulses, each of which must be longer than 2 µs
●
The distance between 2 pulses must be longer than 2 µs.
●
The two pulses must occur within a time frame of 1.0 ms
A wake up caused by a message on the bus starts the voltage regulator and the
microcontroller to switch the application back to normal operation mode.
Figure 21. CAN wake up capabilities
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Note:
Pictures above illustrate the wake up behaviour from V1_standby Mode. For wake up from
VBat_standby Mode the NRESET signal (with 2 ms timing) is generated instead of the
RXDL(Interrupt) signal.
Wakeup by CAN Frame (WUF)
Wake from CAN TRX_STBY
If the CAN transceiver is in STBY the CAN frame detection logic is active.
In case of a valid wake up frame the Interrupt on pin RxDC is generated and the WUF flag
for wake up identification is set. There is no automatic state transition from CAN Transceiver
point of view. After serving the interrupt the micro can bring the CAN Transceiver into
TRX_NORMAL by setting CAN_ACT = 1 (CR 4).
Wake up from TRX_SLEEP
If the CAN Transceiver is in TRX_SLEEP mode the CAN frame detection logic is disabled.
The wake up can be done in two steps. To enable the CAN frame detection logic a wake up
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Detailed description
L99PM72PXP
pattern must be sent on the bus. With the detection of the wake up pattern an automatic
state transition to ‘PN_TRX_Selective_Sleep’ state is done. WUP flag is set.
In ‘PN_TRX_Selective_Sleep’ the CAN frame detection logic is enabled. If a valid wake up
frame is detected a state transition to TRX_STBY is done, the WUF flag is set and the micro
is powered up. The remote transition request bit is ignored in wake-up frames. Also masking
of the data length code (DLC) bits is not supported.
After expiration of the frame error counter (FEC), and if the erroneous frame leading to the
FEC-overflow is long enough to contain a CRC-field, a wake up is performed and the
selective wakeup feature is disabled. If the frame is shorter the FEC starts again from 0
without having set the FD_ERR-flag and without wake-up.
The frame-error-counter (FEC) is cleared after each expiration of the time tsilence whenever
the frame detection logic is enabled. Ringing on the dominant-to-recessive edge of the
CAN-Signal is filtered up to 50% of the CAN-Bit-Time.
2.9.5
CAN receive only mode
With the CAN_rec_only bit in Control register 4 it is possible to disable the CAN Transmitter
in active mode. In this mode it is possible to listen to the bus but not sending to it. The
Receiver termination network is still activated in this mode.
2.9.6
CAN looping mode
If the CAN_Loop_en bit in Control register 4 is set the TxDC input is mapped directly to the
RxDC pin. This mode can be used in combination with the CAN Receive only mode, to run
diagnosis for the CAN protocol handler of the micro controller.
2.10
Serial Peripheral Interface (ST SPI Standard 3.0)
A 24 bit SPI is used for bi-directional communication with the micro controller.
During active mode, the SPI
●
triggers the watchdog
●
controls the modes and status of all L99PM72PXP modules (incl. input and output
drivers)
●
provides driver output diagnostic
●
provide L99PM72PXP diagnostic (incl. over temperature warning, L99PM72PXP
operation status)
The SPI can be driven by a micro controller with its SPI peripheral running in
following mode: CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
This device is not limited to micro controller with a built-in SPI. Only three CMOS-compatible
output pins and one input pin are needed to communicate with the device. A fault condition
can be detected by setting CSN to low. If CSN = 0, the DO pin reflects the global error flag
(fault condition) of the device.
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Detailed description
Chip Select Not (CSN)
The input pin is used to select the serial interface of this device. When CSN is high, the
output pin (DO) is in high impedance state. A low signal activates the output driver and a
serial communication can be started. The state during CSN = 0 is called a communication
frame.
If CSN = low for t > tCSNfail the DO output is switched to high impedance in order to not block
the signal line for other SPI nodes.
Serial Data In (DI)
The input pin is used to transfer data serial into the device. The data applied to the DI are
sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register.
At the rising edge of the CSN signal the contents of the shift register is transferred to Data
Input Register. The writing to the selected Data Input Register is only enabled if exactly 24
bits are transmitted within one communication frame (i.e. CSN low). If more or less clock
pulses are counted within one frame the complete frame is ignored. This safety function is
implemented to avoid an activation of the output stages by a wrong communication frame.
Note:
Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel
operation of the SPI bus by controlling the CSN signal of the connected IC's is
recommended.
Serial Data Out (DO)
The data output driver is activated by a logical low level at the CSN input and goes from high
impedance to a low or high level depending on the global error flag (fault condition). The first
rising edge of the CLK input after a high to low transition of the CSN pin transfers the
content of the selected status register into the data out shift register. Each subsequent
falling edge of the CLK shifts the next bit out.
Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the
falling edge of the CLK signal. The SPI can be driven with a CLK Frequency up to 1 MHz.
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Protection and diagnosis
L99PM72PXP
3
Protection and diagnosis
3.1
Power supply fail
Overvoltage and undervoltage detection on VS
3.1.1
VS overvoltage
If the supply voltage VS reaches the over voltage threshold (VSOV):
●
3.1.2
Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).
CAN is not disabled. Recovery of outputs when the overvoltage condition disappears is
depending on the setting of VLOCK_OUT_EN bit in Control Register 4.
–
VLOCK_OUT_EN = 1: Outputs are off until read and clear SR3.
–
VLOCK_OUT_EN = 0: Outputs switch automatically on when overvoltage
condition disappears.
●
The over voltage bit is set and can be cleared with a ‘Read and Clear’ command. The
overvoltage bit is removed automatically if VLOCK_OUT_EN = 0 and the overvoltage
condition disappears.
●
Outputs REL1,2 can be excluded from a shutdown in case of overvoltage by SPI
(LS_OV/UV_shutdown_en in CR4)
VS undervoltage
If the supply voltage VS drops below the under voltage threshold voltage (VSUV)
●
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Outputs OUTx, RELx and LIN are switched to high impedance state (load protection).
CAN is not disabled. Recovery of outputs when the undervoltage condition disappears
is depending on the setting of VLOCK_OUT_EN bit.
–
VLOCK_OUT_EN = 1: Outputs are off until read and clear SR3.
–
VLOCK_OUT_EN = 0: Outputs switch on automatically when undervoltage
condition disappears.
●
The undervoltage bit is set and can be cleared with a ‘Read and Clear’ command. The
undervoltage bit is removed automatically if VLOCK_OUT_EN = 0 and the
undervoltage condition disappears
●
Outputs REL1,2 can be excluded from a shutdown in case of undervoltage by SPI
(LS_OV/UV_shutdown_en in CR4)
Doc ID 023553 Rev 3
L99PM72PXP
Protection and diagnosis
Figure 22. Overvoltage and undervoltage protection and diagnosis
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Protection and diagnosis
3.2
L99PM72PXP
Temperature warning and thermal shut-down
Figure 23. Thermal shutdown protection and diagnosis
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44/128
The Thermal State machine recovers the same state were it was before entering Standby
Mode. In case of a TSD2 it enters TSD1 state.
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L99PM72PXP
3.3
Protection and diagnosis
High side driver outputs
The component provides a total of 4 high side outputs Out1...4, (7 typ. at 25°C) to drive
e.g. LED's or hall sensors and 1 high side output OUT_HS with 1 typ. at 25°C).
●
The high side outputs switch off in case of:
●
VS overvoltage and undervoltage
●
Overcurrent
●
Overtemperature (TSD1) with pre warning(c)
In case of overcurrent or overtemperature (TSD1) condition, the drivers switch off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case overvoltage or undervoltage condition, the drivers are switched off. The according
status bit is latched and can be read and optionally cleared by SPI. If the VLOCK_OUT_EN
bit (Control Register 4) is set to ‘1’ the drivers remain off until the status is cleared. If the
VLOCK_OUT_EN bit is set to ‘0’ the drivers switch on automatically if the error condition
disappears.
In case of open load condition, the according status register is latched. The status can be
read and optionally cleared by SPI. The High sides are not switched off.
For OUT_HS the auto recovery feature (OUTHS_rec_en bit Control Register 4) can be
enabled. If this bit is set to ‘1’ the driver automatically restarts from a overload condition.
This overload recovery feature is intended for loads which have an initial current higher than
the over current limit of the output (e.g. Inrush current of cold light bulbs). During auto
recovery mode the over current status bit can not be read from SPI.
The device itself cannot distinguish between a real overload and a non linear load like a light
bulb. A real overload condition can only be qualified by time. As an example, the micro
controller can switch on light bulbs by setting the over current recovery bit for the first 50 ms.
After clearing the recovery bit, the output is automatically disabled if the overload condition
still exists.
In case of a fail safe condition, the high side drivers are switched off. The control bits are set
to default values. (except OUT3/FSO if it is used as a High Side Driver Output)
Note:
The maximum voltage and current applied to the High Side Outputs is specified in 2.1
‘Absolute Maximum Ratings’. Appropriate external protection may be required in order to
respect these limits under application conditions.
Each high side driver can be driven whether with a PWM signal or with a internal Timer (see
Table 8).
For more details please refer to Section 6.2.3: Control Register 1
Table 8.
c.
PWM configuration for high-side outputs
High side output
PWM channel
Internal timer
OUT1
PWM 1
Timer 1
OUT2
PWM 2
Timer 2
Except OUT3 when configured as FSO
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Protection and diagnosis
Table 8.
L99PM72PXP
PWM configuration for high-side outputs (continued)
High side output
PWM channel
Internal timer
OUT3
PWM 3
-
OUT4
PWM 4
Timer 2
OUTHS
PWM 3 / PWM 4
Timer 1 / Timer 2
The PWM 1/3 channels start a PWM period with the ON phase, while the PWM 2/4
channels start with the OFF phase. In this way it is possible to use the 4 PWM channels in a
phase shifted way. The picture below shows this feature with a duty cycle of 25% for both
PWM channels.
Figure 24. Phase shifted PWM
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3.4
Low side driver outputs REL1, REL2
The outputs REL1, REL2 (RDSon = 2 typ. @25 C) are specially designed to drive relay
loads.
The outputs provide an active output zener clamping (45 V typ.) feature for the
demagnetization of the relay coil, even though a load dump condition exists.
For Fail_safe reasons the relay drivers are linked with the fail safe operation: In case of
entering the Fail Safe Mode, the relay drivers switch off and the SPI control bits are set to
default (i.e. driver is off).
The low side drivers switch off in case of:
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●
VS overvoltage and undervoltage
●
Overcurrent
●
Overtemperature with pre warning
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L99PM72PXP
Protection and diagnosis
In case of overload or overtemperature (TSD1) condition, the drivers switch off. The
according status bit is latched and can be read and optionally cleared by SPI. The drivers
remain off until the status is cleared.
In case VS overvoltage or undervoltage condition, the drivers are switched off. The
according status bit is latched and can be read and optionally cleared by SPI. If the
VLOCK_OUT_EN bit (Control Register 4) is set to ‘1’ the drivers remain off until the status is
cleared. If the VLOCK_OUT_EN bit is set to ‘0’ the drivers are switched on automatically if
the error condition disappears.
With the LS_OV/UV_shutdown_en bit (Control Register 4) the drivers can be excluded from
a switch off in case of VS overvoltage or undervoltage. If the bit is set to ‘1’ the driver
switches off, otherwise the drivers remain on.
3.5
SPI diagnosis
Digital diagnosis features are provided by SPI (for details please refer to Section 6.2: SPI
registers)
●
V1 reset threshold programmable
●
Overtemperature including. pre warning
●
Open load separately for each output stage except REL1/REL2
●
Overload status separately for each output stage
●
VS-supply overvoltage/undervoltage
●
V1 and V2 fail bit
●
V2 output short to GND
●
Status of the WU1...3
●
Wake-up sources (CAN, LIN, SPI, Timer, WU1…3)
●
Chip reset bit (start from power-on reset)
●
Number of unsuccessful V1 restarts after thermal shutdown
●
Number of sequential watchdog failures
●
LIN diagnosis (permanent recessive/dominant, dominant TxD)
●
CAN diagnosis (permanent recessive/dominant, dominant TxD, recessive RXD)
●
Device State (wake-up from V1_standby or Vbat_standby)
●
Forced Vbat_standby after WD-fail, forced Vbat_standby after overtemperature
●
Watchdog timer state (diagnosis of watchdog)
●
Failsafe status
●
SPI communication error
●
Diagnosis of selective wake functionality according to ISO 11898-6
Doc ID 023553 Rev 3
47/128
Typical application
4
L99PM72PXP
Typical application
Figure 25. Typical application diagram
9EDW
9V
9V
9EDW
9V
9
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,62
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("1($'5
1. In case a LIN/CAN conformance test has to be executed on the device, some capacitances have to be
placed on the Fixed-Function-Unit pins:
- 22 nF (low ESR and close to the pin) for all power outputs (OUT_HS, OUT1 … 4, REL1 and REL2) and
also for the wake-up inputs, if they go out of the PCB.
- 47 µF and a 100 nF low ESR capacitance (close to the pin) at the power supply VS.
48/128
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
5
Electrical specifications
5.1
Absolute maximum ratings
All maximum ratings are absolute ratings. Leaving the limitation of any of these values may
cause an irreversible damage of the integrated circuit.
Loss of ground or ground shift with externally grounded loads: ESD structures are
configured for nominal currents only. If external loads are connected to different grounds, the
current load must be limited to this nominal current.
Table 9.
Absolute maximum ratings
Symbol
Value [DC Voltage]
Unit
DC supply voltage / “jump start”
-0.3 to +28
V
Load dump
-0.3 to +40
V
-0.3 to
(V1 + 0.3) V1 < VS
V
-0.3 to +28
V
Logic input / output voltage range
-0.3 to V1 + 0.3
V
VTXDC, VTXDL
Multi Level Inputs
-0.3 to VS + 0.3
V
VREL1, VREL2
Low side output voltage range
-0.3 to +40
V
-0.3 to VS + 0.3
V
VS
Parameter / Test condition
V1
stabilized supply voltage, logic supply
V2
stabilized supply voltage
VDI, VCLK, VDO,
VRXDL, VNRESET,
VRXDC, VCSN
VOUT1..4, VOUT_HS High side output voltage range
VWU1...3
Wake up input voltage range
-0.3 to VS + 0.3
V
VOP1P, VOP1M,
VOP2P, VOP2M,
Opamp1 input voltage range
Opamp2 input voltage range
-0.3 to V1 + 0.3
V
VOPOUT1,
VOPOUT2
Analog output voltage range
-0.3 to VS + 0.3
V
-20 to +40
V
Current injection into VS related input pins
20
mA
Current injection into VS related outputs
20
mA
-0.3 to +5.25
V
-27 to +40
V
-0.3 to VS + 0.3
V
VLIN, VLINPU
IInput
Iout_inj
VCANSUP
VCANH,VCANL
VPin6
LIN bus I/O voltage range
CAN supply
CAN bus I/O voltage range
Not connected
Doc ID 023553 Rev 3
49/128
Electrical specifications
5.2
L99PM72PXP
ESD protection
Table 10.
ESD protection
Parameter
Value
Unit
+/-2
kV
+/-4
kV
LIN
+/-8 (2)
+/-10 (3)
+/-6 (4)
kV
CAN_H, CAN_L
+/-8 (2)
+/-6 (4)
kV
All pins (5)
+/-500
V
Corner pins (5)
+/-750
V
+/-200
V
All pins (1)
All output pins
All pins
(2)
(6)
1. HBM (Human Body Model, C = 100 pF, R = 1.5 k) according to MIL 883C, Method 3015.7 or
EIA/JESD22A114-A.
2. HBM with all none zapped pins grounded.
3. Indirect ESD test according to IEC 61000-4-2 (C = 150 pF, R = 330 ) and ‘Hardware Requirements for
LIN, CAN and Flexray Interfaces in Automotive Applications’ (version 1.1, 2009-12-02).
4. Direct ESD test according to IEC 61000-4-2 (C = 150pF, R = 330 ) and ‘Hardware Requirements for LIN,
CAN and Flexray Interfaces in Automotive Applications’ (version 1.1, 2009-12-02).
5. Charged device model.
6. Machine model: C = 200 pF; R = 0
5.3
Thermal data
Table 11.
Operating junction temperature
Symbol
Tj
Rthj_amb
Table 12.
Parameter
Unit
-40 to 150
°C
See Figure 29
K/W
Operating junction temperature
Thermal resistance junction ambient
Temperature warning and thermal shutdown
Symbol
Parameter
Min.
Typ.
Max.
Unit
Thermal over temperature
warning threshold
Tj (1)
120
130
140
°C
TSD1_OFF
Thermal shut-down junction
temperature 1
Tj (1)
130
140
150
°C
TSD2_OFF
Thermal shut-down junction
temperature 2
Tj (1)
150
160
170
°C
TW_ON
TSD12_hys
Hysteresis
1. Non-overlapping.
50/128
Value
Doc ID 023553 Rev 3
5
°C
L99PM72PXP
Electrical specifications
Figure 26. Thermal data of PowerSSO-36
P a d s o ld e re d
35
30
P ow erS S O -3 6 o n 2 s 2 p
P ow erS S O -3 6 o n 2 s 2 p th. e n h.
ZTH (ºC/W)
25
20
15
10
5
0
0 .0 0 0 1
0 .0 0 1
0 .0 1
0 .1
T im e (s )
Doc ID 023553 Rev 3
1
10
100
1000
AG00022V1
51/128
Electrical specifications
L99PM72PXP
5.4
Package and PCB thermal data
5.4.1
PowerSSO-36 thermal data
Figure 27. PowerSSO-36 PC board
$*9
Note:
52/128
Layout condition of Rth and Zth measurements (board finish thickness 1.6 mm +/- 10% board
double layer, board dimension 129x60, board Material FR4, Cu thickness 0.070 mm (front
and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm,
Cu thickness on vias 0.025 mm).
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
Figure 28. PowerSSO-36 thermal resistance junction to ambient vs PCB copper area
(V1 ON)
57+MDPE
57+MBDPE &:
57+MDPE
3&%&XKHDWVLQNDUHD FPA
$*9
Figure 29. PowerSSO-36 thermal impedance junction to ambient vs PCB copper
area (single pulse with V1 ON)
ZTH (°C/W)
100
Cu=8 cm2
Cu=2 cm2
Cu=foot print
10
1
0.01
0.1
1
Time (s)
10
100
1000
AG00025V1
Doc ID 023553 Rev 3
53/128
Electrical specifications
L99PM72PXP
Figure 30. PowerSSO-36 thermal fitting model (V1 ON)
$*9
Equation 1: pulse calculation formula
Z TH = R TH + Z THtp 1 –
where
= tp T
Table 13.
Thermal parameter
Area/island (cm2)
54/128
Footprint
2
8
R1 (°C/W)
2
R2 (°C/W)
8
4
4
R3 (°C/W)
20
15.5
10
R4 (°C/W)
36
29
18
C1 (W.s/°C)
0.01
C2 (W.s/°C)
0.1
0.2
0.2
C3 (W.s/°C)
0.8
1
1.5
C4 (W.s/°C)
2
3
6
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
5.5
Electrical characteristics
5.5.1
Supply and supply monitoring
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. Tj = -40°C to 130°C, unless otherwise specified.
Table 14.
Supply and supply monitoring
Symbol
VSUV
Parameter
Test condition
VS undervoltage threshold
VS increasing / decreasing
Min.
Typ.
5.81
V
0.15
V
22
V
1.5
V
6
12
mA
8
12
28
µA
Current consumption in
VS = 12 V; both voltage
IV(BAT)CS VBat_standby mode with cyclic regulators deactivated;
sense enabled(1)
T = 50 ms; tON = 100 µs
40
75
125
µA
Current consumption in
VS = 12 V; both voltage
IV(BAT)CW VBat_standby mode with cyclic regulators deactivated
wake enabled(1)
during standby phase
40
75
125
µA
16
51
76
µA
1200
µA
Vhyst_UV VS undervoltage hysteresis
VSOV
VS overvoltage threshold
Vhyst_OV VS overvoltage hysteresis
0.04
VS increasing / decreasing
18.5
hysteresis
0.5
tovuv_filt
VS overvoltage
/undervoltage filter time
IV(act)
Current consumption in
active mode
VS = 12 V; TxDC = high;
TxDL = high; V1 = ON;
V2 = ON; HS/LS Driver OFF
IV(BAT)
Current consumption in
VBat_standby mode(1)
VS = 12V; both voltage
regulators deactivated;
HS/LS driver OFF; no CAN
communication
IV(V1stby)
IV(SW)
Current consumption in
V1_standby mode(1)
Current consumption in
standby mode but selective
wakeup enabled and CAN
communication on the bus
(PN_TRX_selective_Sleep)
5.11
Max. Unit
0.1
1
64*Tosc
VS = 12 V; voltage regulator
V1 active (IV1 < ICMP); HS/LS
driver OFF
VS = 12 V; both voltage
regulators deactivated;
HS/LS driver OFF
(1)
1. Conditions for specified current consumption:
VLIN > (VS - 1.5 V)
(CAN_H – CAN_L) < 0.4 V or (CAN_H – CAN_L) > 1.2 V
VWU < 1 V or VWU > (Vs – 1.5V)
The current consumption in standby modes with cyclic sense can be calculated using the following
formulas:
IV(BAT)CS = IV(BAT) + 55 µA + (2 mA * (tON + 100 µs) / T)
I(V1)CS = IV1 + 55 µA + (2 mA * (tON + 100 µs) / T)
Doc ID 023553 Rev 3
55/128
Electrical specifications
5.5.2
L99PM72PXP
Oscillator
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40°C to 130°C, unless otherwise specified.
Table 15.
Symbol
FCLK
Oscillator
Parameter
Test condition
Oscillation frequency
Min.
Typ.
Max.
Unit
0.80
1.0
1.35
MHz
Typ.
Max.
Unit
3.45
4.5
V
3.5
V
All outputs open; Tj = -40°C to 130°C, unless otherwise specified.
5.5.3
Power-on reset (VS)
Table 16.
Symbol
VPOR
Power-on reset (VS)
Parameter
VPOR threshold
Test condition
Min.
VS increasing
VS
decreasing(1)
2.35
1. This threshold is valid if VS had already reached 7 V previously.
5.5.4
Voltage regulator V1
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40°C to 130°C, unless otherwise specified.
Table 17.
Voltage regulator V1
Symbol
Parameter
Test condition
Min.
Output voltage
V1
Vhc1
VSTB1
VDP1
ICC1
ICCmax1
56/128
Typ.
Max. Unit
5.0
Output voltage tolerance
active mode
Output voltage tolerance;
active mode; high current
Output voltage tolerance
V1_standby mode
Drop-out voltage
V
ILOAD = 4 mA to 100 mA;
VS = 13.5 V
-2
2
%
ILOAD = 100 mA to 250 mA;
VS = 13.5 V
-3
3
%
ILOAD = 250 mA;
VS = 13.5 V
-5
5
%
ILOAD = 0 µA to 4 mA;
VS = 13.5 V
-2
4
%
ILOAD = 50 mA; VS = 5 V
0.2
0.4
V
ILOAD = 100 mA; VS = 4.5 V
0.2
0.5
V
ILOAD = 100 mA; VS = 5 V
0.3
0.5
V
ILOAD = 150 mA; VS = 4.5 V
0.45
0.6
V
ILOAD = 150 mA; VS = 5.0 V
0.45
0.6
V
250
mA
900
mA
Output current in active mode
Max. continuous load
current
Short circuit output current
Current limitation
Doc ID 023553 Rev 3
340
600
L99PM72PXP
Electrical specifications
Table 17.
Symbol
Cload1
tTSD
Voltage regulator V1 (continued)
Parameter
Test condition
Load capacitor 1
Min.
Typ.
Max. Unit
0.22(1)
Ceramic (+/- 20%)
µF
V1 deactivation time after
thermal shutdown
1
sec
ICMP_ris
Current comp. rising threshold Rising current
1.0
2.5
4.0
mA
ICMP_fal
Current comp. falling
threshold
0.8
1.95
3.1
mA
Falling current
ICMP_hys Current comp. hysteresis
0.5
mA
2
V
V1fail
V1 fail threshold
tV1fail
V1 fail filter time
2
µs
V1 short filter time
4
ms
tV1short
V1 forced
1. Nominal capacitor value required for stability of the regulator. Tested with 220nF ceramic (+/- 20%).
Capacitor must be located close to the regulator output pin.
5.5.5
Voltage regulator V2
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 4.5 V < VS < 28 V; Tj = -40°C to 130°C, unless otherwise specified.
Table 18.
Symbol
Voltage regulator V2
Parameter
Test condition
Min.
Typ.
Max.
Unit
V2
Output voltage
V2
Output voltage
ILOAD = 1 mA to 50 mA;
tolerance; active mode VS = 13.5 V
-3
3
%
Vhc1
Output voltage
ILOAD = 50 mA to 80 mA;
tolerance; active mode VS = 13.5 V
-4
4
%
Output voltage
tolerance; active
mode; high current
ILOAD = 100 mA; VS = 13.5 V
-6
6
%
VSTB2
Output voltage
tolerance
V1_standby mode
ILOAD = 1 mA; VS = 13.5 V
-6.5
6.5
%
VDP2
Drop-out voltage
ICC2
Output current in
active mode
Max. continuous load current
Short circuit output
current
Current limitation
150
Cload
Load capacitor
Ceramic (+/- 20%)
0.22(1)
V2fail
V2 fail threshold
V2 forced
V2
ICCmax2
5.0
V
ILOAD = 25 mA; VS = 5.25 V
0.3
0.4
V
ILOAD = 50 mA; VS = 5.25 V
0.4
0.7
V
100
mA
450
mA
Doc ID 023553 Rev 3
280
µF
2
V
57/128
Electrical specifications
Table 18.
Voltage regulator V2 (continued)
Symbol
tV2fail
tV2short
L99PM72PXP
Parameter
Test condition
Min.
Typ.
Max.
Unit
V2 fail filter time
2
µs
V2 short filter time
4
ms
1. Nominal capacitor value required for stability of the regulator. Tested with 220 nF ceramic (+/- 20%).
Capacitor must be located close to the regulator output pin
5.5.6
Reset output
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 4.0 V < VS < 28 V; Tj = -40°C to 130°C, unless otherwise specified.
Table 19.
Reset output
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VRT1
Reset threshold voltage 1
VV1 decreasing
3.7
3.9
4.1
V
VRT2
Reset threshold voltage 2
VV1 decreasing
4.2
4.3
4.45
V
VRT3
Reset threshold voltage 3
VV1 decreasing
4.25
4.4
4.55
V
4.60
4.75
V
Reset threshold voltage 4
VV1 decreasing
4.5
VRT4
VV1 increasing
4.7
4.8
4.9
V
0.2
0.4
V
110
150
k
40
s
VRESET
Reset pin low output
voltage
V1 > 1 V; IRESET = 5 mA
RRESET Reset pull up int. resistor
5.5.7
tRR
Reset reaction time
tUV1
V1 undervoltage filter time
Trd
Reset pulse duration
80
ILOAD = 1 mA
6
s
16
1.46
2.0
2.5
ms
Watchdog
4.5 V < VS < 28 V; 4.8 V < V1 < 5.2 V; Tj = -40°C to 130°C, unless otherwise specified,
see Figure 31 and Figure 32.
Table 20.
Symbol
tLW
58/128
Watchdog
Parameter
Test condition
Long open window
Min.
Typ.
Max.
Unit
48.75
65
81.25
ms
4.5
ms
TEFW1
Early failure window 1
TLFW1
Late failure window 1
20
TSW1
Safe window 1
7.5
TEFW2
Early failure window 2
TLFW2
Late failure window 2
100
TSW2
Safe window 2
37.5
TEFW3
Early failure window 3
Doc ID 023553 Rev 3
ms
12
ms
22.3
ms
ms
60
ms
45
ms
L99PM72PXP
Electrical specifications
Table 20.
Watchdog (continued)
Symbol
Parameter
Test condition
Min.
TLFW3
Late failure window 3
200
TSW3
Safe window 3
75
TEFW4
Early failure window 4
TLFW4
Late failure window 4
400
TSW4
Safe window 4
150
Typ.
Max.
Unit
ms
120
ms
90
ms
ms
240
ms
Figure 31. Watchdog timing (long, early, late and safe window)
.ORMALSTARTUPOPERATIONANDTIMEOUTFAILURES
4,7 LONGWINDOW MS
4#7 CLOSEDWINDOW MS
CORRECTTRIGGERTIMING
4/7 OPENWINDOW MS
47$2 WATCHDOGRESET MS
EARLYTRIGGERTIMING
MISSINGTRIGGER
4#7 4/7
4 #7 4/7
4#7
4,7
7$
TRIGGER
TRIGGERSIGNAL
4,7
4,7
.2%3
/UT
47$2
47$2
NORMALOPERATION
TIMEMS
MISSING
TRIGGER
EARLY
WRITE
TIMEMS
-ISSINGU#TRIGGERSIGNAL
7$
TRIGGER
4,7
4,7
4,7
TIMEMS
.2%3
/UT
47$2
47$2
47$2
TIMEMS
("1($'5
Doc ID 023553 Rev 3
59/128
Electrical specifications
L99PM72PXP
Figure 32. Watchdog early, late and safe windows
437N 3AFEWINDOW
4%&7N %ARLY&AILUREWINDOW
4,&7N ,ATEFAILUREWINDOW
4,&7N?MIN
437N?MAX
437N?MIN
4%&7N?MAX
%ARLY
7ATCHDOG
FAILURE
UNDEFINED SAFETRIGGERAREA
,ATE
WATCHDOG
FAILURE
UNDEFINED
TIME
'!0'#&4
5.5.8
High side outputs
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40°C to 130°C, unless
otherwise specified.
Table 21.
Symbol
Output (OUT_HS)
Parameter
Test condition
Typ.
Max.
Unit
Static drain source onresistance
(IOUT_HS = 150 mA)
Tj = 25°C
1.0
2.0
Tj = 125°C
1.6
3
td(on)
Switch on delay time
0.2 VS
5
35
60
µs
td(off)
Switch off delay time
0.8 VS
40
95
150
µs
tSCF
Short circuit filter time
Tested by scan chain
64 * TOSC
Auto recovery filter time
Tested by scan chain
400 * TOSC
RDS(on)
td_ARHS
dVOUT/dt Slew rate
0.18
0.5
0.8
V/µs
IOUT
Short circuit shut down
current
480
900
1320
mA
IOLD
Open load detection current
40
80
120
mA
tOLDT
Open load detection time
IFW (1)
Loss of GND current (ESD
structure)
Tested by scan chain
1. Parameter guaranteed by design.
60/128
Min.
Doc ID 023553 Rev 3
64 * TOSC
100
mA
L99PM72PXP
Electrical specifications
Table 22.
Outputs (OUT1...4)
Symbol
Parameter
Test condition
Static drain source onRDS(ON) resistance
(IOUT_HS = 150 mA)
Min.
Typ.
Max.
Unit
7
13
140
235
350
mA
0.9
2
4.5
mA
0.2
0.5
0.8
V/µs
ILOAD = 60 mA; Tj = 25°C
IOUT
Short circuit shut down
current
IOLD
Open load detection current
8 V < VS < 16 V
dVOUT/dt Slew rate
td(on)
Switch ON delay time
0.2 VS
5
35
60
µs
td(off)
Switch OFF delay time
0.8 VS
30
95
150
µs
tSCF
Short circuit filter time
Tested by scan chain
IFW (1)
Loss of GND current (ESD
structure)
tOLDT
Open load detection time
64 * TOSC
100
Tested by scan chain
mA
64 * TOSC
1. Parameter guaranteed by design.
5.5.9
Relay drivers
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tj = -40 to 130°C, unless otherwise
specified.
Table 23.
Relay drivers
Symbol
RDS(on)
IOUT
VZ
Parameter
Test condition
Min.
DC output resistance
ILOAD = 100 mA at Tj = 25°C
Short circuit shut
down current
8 V < VS < 16 V
250
ILOAD = 100 mA
40
Output clamp voltage
(1)
Typ.
Max.
Unit
2
3
375
500
mA
48
V
tONHL
Turn on delay time to
10% VOUT
5
50
100
µs
tOFFLH
Turn off delay time to
90% VOUT
5
50
100
µs
tSCF
Short circuit filter time
4
V/µs
Tested by scan chain
dVOUT/dt Slew rate
64*TOSC
0.2
2
1. The output is capable to switch off relay coils with the impedance of RL = 160 ; L = 300 mH (RL = 220 ;
L = 420 mH); at VS = 40 V (Load dump condition)
Doc ID 023553 Rev 3
61/128
Electrical specifications
5.5.10
L99PM72PXP
Wake up inputs (WU1 ... WU3)
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; Tj = -40 to 130°C, unless otherwise specified.
Table 24.
Symbol
Wake-up inputs
Parameter
Test condition
Typ.
Max.
Unit
VWUthp
Wake-up negative edge
threshold voltage
0.4 VS
0.45 VS
0.5 VS
V
VWUthn
Wake-up positive edge
threshold voltage
0.5 VS
0.55 VS
0.6 VS
V
VHYST
Hysteresis
0.05 VS
0.1 VS
0.15 VS
V
tWU_stat
Static wake filter time
IWU_stdby
64 * TOSC
Input current in standby
mode
VWU < 1 V or
VWU > (VS – 1.5 V)
Input resistor to GND in
active mode and in
RWU_act
standby mode during
wake-up input sensing
tWU_cyc
5.5.11
Min.
µs
9
15
28
µA
80
160
300
k
Cyclic wake filter time
16
µs
High speed CAN transceiver(d)
Selective wake functionality according to ISO 11898-6
Table 25.
Symbol
VSCOM
CAN communication operating range
Parameter
Test condition
Supply voltage
operating range for
CAN communication
Active mode, V1 = VCANSUP
Min.
Typ.
Max.
Unit
5.5
—
18
V
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < VCANSUP. < 5.2 V; Tjunction = -40°C to 130°C,
unless otherwise specified. -12 V = (CANH + CANL) / 2 = 12 V.
Table 26.
Symbol
CAN transmit data input: pin TxDC
Parameter
Test condition
Typ.
1.35
1.8
VTXDCLOW Input voltage dominant level
Active mode, V1 = 5 V
VTXDCHIGH Input voltage recessive level
Active mode, V1 = 5 V
VTXDCHYS VTXDCHIGH - VTXDCLOW
Active mode, V1 = 5 V
0.7
1
Active Mode, V1 = 5 V
10
20
RTXDCPU
TxDC pull up resistor
d. ISO 11898-2 and ISO 11898-5 compliant.
SAE J2284 compliant.
62/128
Min.
Doc ID 023553 Rev 3
2.5
Max.
Unit
V
3
V
V
35
k
L99PM72PXP
Electrical specifications
Table 27.
CAN receive data output: pin RxDC
Symbol
Parameter
Test condition
Min.
VRXDCLOW
Output voltage
dominant level
Active mode, V1 = 5 V; 2 mA
VRXDCHIGH
Output voltage
recessive level
Active mode, V1 = 5 V; 2 mA
Table 28.
Typ.
Max.
Unit
0.2
0.5
V
4.5
V
CAN transmitter and receiver: pins CANH and CANL
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VCANHdom
CANH voltage level
in dominant state
Active mode;
VTXDC = VTXDCLOW;
RL = 60 ; RL = 50
2.75
4.5
V
VCANLdom
Active mode;
CANL voltage level in
VTXDC = VTXDCLOW;
dominant state
RL = 60 ; RL = 50
0.5
2.25
V
Differential output
voltage in dominant
state: VCANHdom VCANLdom
1.5
3
V
VDIFF,domOUT
VCM
Active mode;
VTXDC = VTXDCLOW;
RL = 60 ; RL = 50
Active mode;
Driver symmetry:
= VTXDCLOW;
V
VCANHdom+VCANLdom TXDC
RL = 60
1.1 *
0.9 *
V
VCANSUP CANSUP VCANSUP
V
VCANHrec
CANH voltage level
in recessive state
(Normal Mode)
Active mode;
VTXDC = VTXDCHIGH;
No load
2
2.5
3
V
VCANLrec
CANL voltage level in Active mode;
recessive state
VTXDC = VTXDCHiGH;
(Normal Mode)
No load
2
2.5
3
V
VCANHrecLP
CANH voltage level
in recessive state
(Low Power Mode)
V1_standby mode;
VTXDC = VTXDCHIGH;
No load
-0.1
0
0.1
V
VCANLrecLP
CANL voltage level in V1_standby mode;
recessive state (Low VTXDC = VTXDCHiGH;
Power Mode)
No load
-0.1
0
0.1
V
VDIFF,recOUT
Differential output
Active mode;
voltage in recessive
VTXDC = VTXDCHIGH;
state (Normal Mode):
No load
VCANHrec - VCANLrec
-50
50
mV
VDIFF,recOUTLP
Differential output
voltage in recessive
state (Low Power
Mode): VCANHrec VCANLrec
V1_standby mode;
VTXDC = VTXDCHIGH;
No load
-50
50
mV
VCANHL,CM
Common mode Bus
voltage
Measured with
respect to the ground
of each CAN node
-12
12
V
Doc ID 023553 Rev 3
63/128
Electrical specifications
Table 28.
CAN transmitter and receiver: pins CANH and CANL (continued)
Symbol
Min.
Typ.
Max.
Unit
Parameter
Test condition
-160
-75
-45
mA
Active mode;
VTXDC = VTXDCLOW;
VCANL = 5 V
45
75
160
mA
Active mode;
VTXDC = VTXDCLOW;
CANH output current
IOCANH,dom (40V)
VCANH = 40 V;
in dominant state
VCANL = 0 V;
VS = 40 V
0
2
5
mA
Active mode;
VTXDC = VTXDCLOW;
VCANL = 40 V;
VCANH = 0 V;
VS = 40 V
47
75
160
mA
Ileakage,CANH
Unpowered device;
VBUS = 5 V;
– Vcansupply connect
Input leakage current
0 to GND
– Vcansupply connect
47 k to GND(1)
-10
—
10
µA
Ileakage,CANL
Unpowered device;
VBUS = 5 V;
– Vcansupply connect
Input leakage current
0 to GND
– Vcansupply connect
47 k to GND(1)
-10
—
10
µA
Internal resistance
Active mode &
V1- standby mode;
VTXDC = VTXDCHIGH;
No load
20
27.5
38
k
Internal Resistor
matching
CANH,CANL
Active mode &
V1_standby mode;
VTXDC = VTXDCHIGH;
No load;
Rin(CANH) – Rin(CANL)
3
%
Differential internal
resistance
Active mode &
V1_standby mode;
VTXDC = VTXDCHIGH;
No load
60
75
k
Internal capacitance
Guaranteed by
design
20
40
pF
Differential internal
capacitance
Guaranteed by
design
10
20
pF
IOCANH,dom (0V)
Active mode;
CANH output current
VTXDC = VTXDCLOW;
in dominant state
VCANH = 0 V
IOCANL,dom (5V)
CANL output current
in dominant state
IOCANL,dom (40V)
Rin
Rin,matching
Rin,diff
Cin
Cin,diff
64/128
L99PM72PXP
CANL output current
in dominant state
Doc ID 023553 Rev 3
50
L99PM72PXP
Electrical specifications
Table 28.
CAN transmitter and receiver: pins CANH and CANL (continued)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTHdom
Differential receiver
threshold voltage
recessive to
dominant state
(Normal Mode)
Active mode
0.9
V
VTHdomLP
Differential receiver
threshold voltage
recessive to
dominant state (Low
Power Mode)
V1_standby mode
1.15
V
VTHrec
Differential receiver
threshold voltage
dominant to
recessive state
(Normal Mode)
Active mode
0.5
V
VTHrecLP
Differential receiver
threshold voltage
dominant to
recessive state (Low
Power Mode)
V1_standby mode
0.4
V
1. Guaranteed by design.
Table 29.
Symbol
CAN transceiver timing
Parameter
Test condition
Min.
Typ.
Max.
Unit
tTXpd,hl
Propagation delay
Active mode; RL = 120 ;
TxDC to RxDC (high to CL = 100 pF; CRXDC = 15 pF;
low)
fTXDC = 250 kHz
255
ns
tTXpd,lh
Propagation delay
TxDC to RxDC (low to
high)
Active mode; RL = 120 ;
CL = 100 pF; CRXDC = 15 pF;
fTXDC = 250 kHz
255
ns
5
µs
5
ms
tfilter
tdom(TxDC)
tCAN
tsilence
tBIAS
tV1swon
Wake up filter time
0.5
TxDC dominant timeout
Tested by scan and oscillator
0.8
CAN permanent
dominant time-out
2
700
CAN timeout
600
RL = 60 ; CL = 100 pF;
CGND = 100 pF
Bias reaction time
V1 switch-on time after
reception of a valid
WUF in VBat-standby
Mode
Doc ID 023553 Rev 3
700
µs
1200
ms
200
µs
50
µs
65/128
Electrical specifications
5.5.12
L99PM72PXP
LIN transceiver(e)
The voltages are referred to GND and currents are assumed positive, when the current flows into the
pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; Tjunction = -40°C to 130°C, unless otherwise specified.
Table 30.
LIN transmit data input: pin TxD
Symbol
Parameter
Test condition
VTXDLOW
Input voltage dominant level
Active mode; V1 = 5 V
VTXDHIGH Input voltage recessive level
Active mode; V1 = 5 V
Typ.
1,35
1.8
2.5
Max.
Unit
V
3
V
VTXDHYS
VTXDHIGH - VTXDLOW
Active mode; V1 = 5 V
0.7
1
RTXDPU
TXD pull up resistor
Active Mode; V1 = 5 V
10
20
35
k
Min.
Typ.
Max.
Unit
0.2
0.5
V
Table 31.
Symbol
V
LIN receive data output: pin RxD
Parameter
Test condition
VRXDLOW
Output voltage dominant
level
Active mode; V1 = 5 V; 2 mA
VRXDHIGH
Output voltage recessive
level
Active mode; V1 = 5 V; 2 mA
Table 32.
4.5
V
LIN transmitter and receiver: pin LIN
Symbol
Parameter
VTHdom
Receiver threshold
voltage recessive
to dominant state
0.4 VS 0.45 VS 0.5 VS
V
VBusdom
Receiver dominant
state
0.4 VS
V
VTHrec
Receiver threshold
voltage dominant
to recessive state
0.5 *
VS
0.6 *
VS
V
VBusrec
Receiver recessive
state
0.6 VS
VTHhys
Receiver threshold
hysteresis: VTHrec VTHdom
0.07 *
VS
0.1 *
VS
0.175 *
VS
V
VTHcnt
Receiver tolerance
center value:
(VTHrec +VTHdom)/2
0.475 *
VS
0.5 *
VS
0.525 *
VS
V
1.0
1.5
2
V
VTHwkup
Test condition
Receiver wakeup
threshold voltage
e. LIN 2.1 compliant for Baud rates up to 20 kBit/s.
SAE J2602 compatible.
66/128
Min.
Doc ID 023553 Rev 3
Min.
Typ.
0.55 *
VS
Max.
Unit
V
L99PM72PXP
Electrical specifications
Table 32.
LIN transmitter and receiver: pin LIN (continued)
Symbol
Parameter
Test condition
Min.
VTHwkdwn
Receiver wakeup
threshold voltage
tlinbus
Dominant time for
wakeup via bus
Sleep mode; Edge: rec-dom
ILINDomSC
Transmitter input
current limit in
dominant state
VTXD = VTXDLOW;
VLIN = VBATMAX = 18 V
40
Input leakage
current at the
Ibus_PAS_dom
receiver incl. pullup resistor
VTXD = VTXDHIGH; VLIN = 0 V;
VBAT = 12 V(1)
-1
Transmitter input
Ibus_PAS_rec current in
recessive state
In stanby Modes;
VTXD = VTXDHIGH; VLIN > 8 V;
VBAT < 18 V; VLIN VBAT
Typ.
Max.
Unit
VS - 3.5 VS - 2.5 VS - 1.5
V
64 *
TOSC
µs
100
180
mA
mA
20
µA
1
mA
Ibus_NO_GND
Input current if loss GND = VS; 0 V < VLIN < 18 V;
of GND at Device VBAT = 12 V
Ibus
Input current if loss
GND = VS; 0 V < VLIN < 18 V
of VBAT at Device
100
µA
VLINdom
LIN voltage level in Active mode;
dominant state
VTXD = VTXDLOW; ILIN = 40 mA
1.2
V
VLINrec
LIN voltage level in Active mode;
recessive state
VTXD = VTXDHIGH; ILIN = 10 µA
1
V
RLINup
LIN output pull up
resistor
60
k
90
pF
Max.
Unit
6
µs
2
µs
CLIN
VLIN = 0 V
-1
0.8 *
VS
20
40
LIN input
capacitance
1. Slave mode.
Table 33.
Symbol
tRXpd
tRXpd_sym
LIN transceiver timing
Parameter
Receiver
propagation delay
time
Test condition
Min.
tRXpd = max(tRXpdr,tRXpdf);
tRXpdf = t(0.5 VRXD) - t(0.45 VLIN);
tRXpdr = t(0.5 VRXD) - t(0.55 VLIN);
VS = 12 V; CRXD = 20 pF;
Rbus = 1 k; Cbus = 1 nF;
Rbus = 660 ; Cbus = 6.8 nF;
Rbus = 500 ; Cbus = 10 nF
Symmetry of
=t
-t
;
t
receiver propagation RXpd_sym RXpdr RXpdf
VS = 12 V; Rbus = 1 k;
delay time (rising vs.
Cbus = 1 nF; CRXD = 20 pF
falling edge)
Doc ID 023553 Rev 3
-2
Typ.
67/128
Electrical specifications
Table 33.
Symbol
D1
D2
D3
D4
LIN transceiver timing (continued)
Parameter
Test condition
Duty Cycle 1
THRec(max) = 0.744 * VS;
THDom(max) = 0.581 * VS;
VS = 7 V to 18 V; tbit = 50 µs;
D1 = tbus_rec(min) / (2 * tbit);
Rbus = 1 k; Cbus = 1 nF;
Rbus = 660 ; Cbus = 6.8 nF;
Rbus = 500 ; Cbus = 10 nF
Duty Cycle 2
THRec(min) = 0.422 * VS;
THDom(min) = 0.284 * VS;
VS = 7.6 V to 18 V; tbit = 50us;
D2 = tbus_rec(max) / (2 * tbit);
Rbus = 1 k; Cbus = 1 nF;
Rbus = 660 ; Cbus = 6.8 nF;
Rbus = 500 ; Cbus = 10 nF
Duty Cycle 3
THRec(max) = 0.778 * VS;
THDom(max) = 0.616 * VS;
VS = 7 V to 18 V; tbit = 96 µs;
D3 = tbus_rec(min) / (2 * tbit);
Rbus = 1 k; Cbus = 1 nF;
Rbus = 660 ; Cbus = 6.8 nF;
Rbus = 500 ; Cbus = 10 nF
Duty Cycle 4
THRec(min) = 0.389 * VS;
THDom(min) = 0.251 * VS;
VS = 7.6 V to 18 V; tbit = 96 µs;
D4 = tbus_rec(max) / (2 * tbit);
Rbus = 1 k; Cbus = 1 nF;
Rbus = 660 ; Cbus = 6.8 nF;
Rbus = 500 ; Cbus = 10 nF
Min.
Typ.
Max.
Unit
0.396
0.581
0.417
0.590
TXDL dominant
time-out
12
ms
tLIN
LIN permanent
recessive time-out
40
µs
Tdom(bus)
LIN Bus permanent
dominant time-out
12
ms
tdom(TXDL)
Table 34.
Symbol
RDS(on)
Ileak
68/128
L99PM72PXP
LIN pull-up: pin LINPU
Parameter
Test condition
Min.
Typ.
Max.
Unit
ON resistance
—
10.5
16
Leakage current
—
1
µA
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
Figure 33. LIN transmit, receive timing
W 7;SGI
W 7;SGU
9 7['
WLPH
9 /,1UHF
9 /,1
9 7+UHF
9 7+GRP
9 /,1GRP
WLPH
9 5['
WLPH
W 5;SGI
W 5;SGU
$* 9
5.5.13
Operational amplifier
The voltages are referred to GND and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; Tj = -40°C to 130°C, unless otherwise specified.
Table 35.
Symbol
GBW
AVOLDC
PSRR
Note:
Operational amplifier
Parameter
Min.
Typ.
Max.
Unit
GBW product
1
3.5
7.0
MHz
DC open loop gain
80
dB
80
dB
Power supply rejection
Test condition
DC, VIN = 150 mV
Voff
Input offset voltage
-5
+5
mV
VICR
Common mode input range
3
V
VOH
Output voltage range high
ILOAD = 1 mA to GND
VS - 0.2
VS
V
VOL
Output voltage range low
ILOAD = 1 mA to VS
0
0.2
V
ILim+
Output current limitation +
DC
10
15
30
mA
Ilim-
Output current limitation -
DC
-10
-15
-30
mA
SR+
Slew rate positive
1
4
10
V/µs
SR-
Slew rate negative
-1
-4
-10
V/µs
-0.2
0
The operational amplifier is on-chip stabilized for external capacitive loads CL < 25pF (all
operating conditions)
Doc ID 023553 Rev 3
69/128
Electrical specifications
5.5.14
L99PM72PXP
SPI
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin.
6 V < VS < 18 V; 4.5 V < V1 < 5.3 V; all outputs open; Tj = -40°C to 130°C, unless otherwise
specified.
Table 36.
Symbol
Input: CSN
Parameter
Test condition
VCSNLOW
Input voltage low level
Normal mode, V1 = 5 V
VCSNHIGH
Input voltage high level
Normal mode, V1 = 5 V
VCSNHYS
VCSNHIGH - VCSNLOW
Normal mode, V1 = 5 V
ICSNPU
CSN pull up resistor
Normal mode, V1 = 5 V
Table 37.
Symbol
Min.
Typ.
1.35
1.8
Max.
Unit
V
2
2.9
V
0.6
1.0
1.5
V
10
20
35
k
Typ.
Max.
Unit
160
300
µs
Inputs: CLK, DI
Parameter
Test condition
Min.
Delay time from
standby to active
mode
Switching from standby to active
mode. Time until output drivers
are enabled after CSN going to
high.
VIN L
Input low level
V1 = 5 V
1.35
2.05
2.75
V
VIN H
Input high level
V1 = 5 V
1.9
2.8
3.7
V
VIN Hyst
Input hysteresis
V1 = 5 V
0.4
0.75
1.5
V
Pull down current
at input
VIN = 1.5 V
5
30
60
µA
10
15
pF
1
MHz
Max.
Unit
tset
I in
Cin (1)
fCLK
Input capacitance
at input CSN, CLK, 0 V < V1 < 5.3 V
DI and PWM1,2
SPI input
frequency at CLK
1. Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 38.
Symbol
Parameter
Test condition
Min.
Typ.
tCLK
clock period
V1 = 5 V
1000
—
ns
tCLKH
clock high time
V1 = 5 V
400
—
ns
tCLKL
clock low time
V1 = 5 V
400
—
ns
tset CSN
CSN setup time, CSN low before
V1 = 5 V
rising edge of CLK
400
—
ns
tset CLK
CLK setup time, CLK high
before rising edge of CSN
V1 = 5 V
400
—
ns
DI setup time
V1 = 5 V
200
—
ns
tset DI
70/128
DI timing(1)
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
Table 38.
Symbol
thold DI
DI timing(1) (continued)
Parameter
Test condition
DI hold time
V1 = 5 V
Min.
Typ.
200
—
Max.
Unit
ns
tr in
rise time of input signal DI, CLK,
V1 = 5 V
CSN
—
100
ns
tf in
fall time of input signal DI, CLK,
CSN
—
100
ns
Typ.
Max.
Unit
0.5
V
V1 = 5 V
1. See Figure 35: SPI input timing.
Table 39.
Symbol
1.
Output: DO
Parameter
Test condition
Min.
VDOL
output low level
V1 = 5 V; ID = -4 mA
VDOH
output high level
V = 5 V; ID = 4 mA
4.5
IDOLK
tristate leakage current
VCSN = V1; 0 V < VDO < V1
-10
CDO
tristate input capacitance
VCSN = V1;
0 V < V1 < 5.3 V(1)
V
10
10
µA
15
pF
Value of input capacity is not measured in production test. Parameter guaranteed by design.
Table 40.
Symbol
DO timing(1)
Parameter
Test condition
Min.
Typ.
Max.
Unit
tr DO
DO rise time
CL = 100 pF; ILOAD = -1 mA
—
50
100
ns
tf DO
DO fall time
CL = 100 pF; ILOAD = 1 mA
—
50
100
ns
ten DO tri L
DO enable time from CL = 100 pF; ILOAD = 1 mA;
tristate to low level
pull-up load to V1
—
50
250
ns
tdis DO L tri
DO disable time from CL = 100 pF; ILOAD = 4 mA;
low level to tristate
pull-up load to V1
—
50
250
ns
ten DO tri H
DO enable time from CL = 100 pF; ILOAD = -1 mA;
tristate to high level pull-down load to GND
—
50
250
ns
tdis DO H tri
DO disable time from CL = 100 pF; ILOAD = -4 mA;
high level to tristate
pull-down load to GND
—
50
250
ns
VDO < 0.3 V1; VDO > 0.7 V1;
CL = 100 pF
—
50
250
ns
Typ.
Max.
Unit
td DO
DO delay time
1. See Figure 36: SPI output timing (part 1).
Table 41.
Symbol
CSN timing(1)
Parameter
tCSN_HI,min
Minimum CSN HI
time, active mode
tCSNfail
CSN low timeout
Test condition
Transfer of SPI-command to
Input Register
Min.
6
20
µs
35
50
ms
1. See Figure 37: SPI CSN - output timing.
Doc ID 023553 Rev 3
71/128
Electrical specifications
L99PM72PXP
The voltages are referred to ground and currents are assumed positive, when the current
flows into the pin. 6 V < VS < 18 V; 4.8 V < V1 < 5.2 V; all outputs open; Tj = -40°C to 130°C,
unless otherwise specified
Table 42.
5.5.15
RXDL/NINT, RXDC/NINT timing
Symbol
Parameter
Test condition
tInterupt
Interrupt pulse duration
Min.
Typ.
Max.
Unit
—
56
—
µs
Inputs TxDC and TxDL for Flash Mode
6 V VS 18 V; 4.5 V V1 5.3 V; Tj = -40°C to 130°C; voltages are referred to PGND, all
outputs open
Table 43.
Inputs: TxDC and TxDL for Flash Mode
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VflashL
Input low level (VTXDC/L for
exit from Flash Mode)
V1 = 5 V
7.1
8.4
9.0
V
VflashH
Input high level (VTXDC/L for
transition into Flash Mode)
V1 = 5 V
8.3
9.4
10.0
V
Input voltage hysteresis
V1 = 5 V
0.8
1.0
1.2
V
VflashHYS
Figure 34. SPI - transfer timing diagram
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The SPI can be driven by a micro controller with its SPI peripheral running in following
mode: CPOL = 0 and CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and
output data is changed from the high to low transition of CLK.
72/128
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
Figure 35. SPI input timing
9&&
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$*9
Doc ID 023553 Rev 3
73/128
Electrical specifications
L99PM72PXP
Figure 36. SPI output timing (part 1)
7I&/.
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74/128
Doc ID 023553 Rev 3
L99PM72PXP
Electrical specifications
Figure 37. SPI CSN - output timing
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Figure 38. SPI - CSN low to high transition and global status bit access
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Doc ID 023553 Rev 3
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ST SPI
L99PM72PXP
6
ST SPI
6.1
SPI communication flow
6.1.1
General description
The SPI communication is based on a standard SPI interface structure using CSN (Chip
Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock) signal
lines.
At device start-up the master reads the register (ROM address 3EH) of the
slave device. This 8-bit register indicates the SPI frame length (24bit) and the availability of
additional features.
Each communication frame consists of an instruction byte which is followed by two data
bytes.
The data returned on SDO within the same frame always starts with the
register. It provides general status information about the device. It is followed by two data
bytes (i. e. ‘In-frame-response’).
For Write cycles the register is followed by the previous content of the
addressed register.
For Read cycles the register is followed by the content of the addressed
register.
A Write command is only accepted as a valid command by the device if the counted number
of clocks is exact 24, otherwise the command is rejected.
Command Byte
Each communication frame starts with a command byte. It consists of an operating code
which specifies the type of operation (, , , ) and a 6 bit address. If less than 6 address bits are required, the remaining bits
are unused but are reserved.
Table 44.
Command Byte
MSB
LSB
Op Code
OC1
OC0
Address
A5
A4
OCx: Operating Code
Ax: Address
76/128
Doc ID 023553 Rev 3
A3
A2
A1
A0
L99PM72PXP
6.1.2
ST SPI
Operating code definition
Table 45.
Operating code definition
OC1
OC0
Meaning
0
0
0
1
1
0
1
1
The and operations allow access to
the RAM of the device, i. e. to write to control registers or read status information.
A operation addressed to a device specific status register reads
back and subsequently clear this status register.
A operation with address 3FH clears all status registers (including
the Global Status Register). Configuration Register is read by this operation.
allows access to the ROM area which contains device related
information such as the product family, product name, silicon version, register width and
availability of a watchdog.
More detailed descriptions of the Device Information are available in ‘Read Device
Information’.
6.1.3
Global Status Register
Table 46.
6.1.4
Global status register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Global error
flag (GEF)
Comm
error
Not (chip reset
OR comm error)
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Configuration register(f)
The register is accessible at RAM address 3FH.
For the Config Register, the 8 bits are located in the low byte (LSB).
The Configuration Register is implemented for compliance purpose to ST SPI Standard.
Table 47.
Configuration register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
WD trigger
: This Bit is reserved to serve the watchdog.
f.
See Section 6.2 for details.
Doc ID 023553 Rev 3
77/128
ST SPI
L99PM72PXP
Figure 39. Read configuration register
&61
6',
75,*
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1. The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the
watchdog trigger bit at D0.
Figure 40. Write configuration register
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1. The configuration register is implemented for compliance with ST standard SPI 3.0 and contains only the
watchdog trigger bit at D0.
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Doc ID 023553 Rev 3
L99PM72PXP
6.1.5
ST SPI
Address mapping
Table 48.
Address mapping
RAM
Address
Description
Access
ROM
Address
Description
Access
3FH
R/W
3FH
Reserved
N/A
…
…
…
3EH
R
13H
Status Register 3
R
12H
Status Register 2
R
11H
Status Register 1
R
…
…
…
…
Unused
N/A
06H
Control Register 6
R/W
05H
Control Register 5
R/W
04H
Control Register 4
R/W
03H
Control Register 3
R/W
03H
R
02H
Control Register 2
R/W
02H
R
01H
Control Register 1
R/W
01H
R
00H
Reserved
R/W
00H
R
The RAM memory area consists of 16 bit registers.
For the device information (ROM memory area) the eight most significant bits of the memory
cell are used. The remaining 8 are zero.
All unused RAM and ROM addresses are read as ‘0’.
Note:
The register definition for RAM address 00H is unused. A register value of all 0 must cause
the device to enter a Fail-Safe state (interpreted as ‘SDI stuck to GND’ failure).
Note:
ROM address 3FH is unused. An attempt to access this address must be recognized as a
communication error (‘SDI stuck to VCC’ failure) and must cause the device to enter a
Fail-Safe state.
6.1.6
Write operation
The write operation starts with a Command Byte followed by 2, data bytes. The number of
data bytes is specified in the .
Write command format
Table 49.
Write command format: command byte
MSB
LSB
Op Code
0
Address
0
A5
A4
Doc ID 023553 Rev 3
A3
A2
A1
A0
79/128
ST SPI
L99PM72PXP
Table 50.
Write command format: data byte 1
MSB
D15
Table 51.
LSB
D14
D13
D12
D11
D10
D9
D8
Write command format: data byte 2
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
OC0, OC1: operating code (00 for ‘write’ mode)
A0 to A5: address bits
An attempt to write 00H at RAM address 00H is recognized as a failure (SDI stuck to GND).
The device enters a Fail-Safe state.
6.1.7
Format of data shifted out at SDO during Write cycle
Table 52.
Bit 7
Format of data shifted out at SDO during write cycle: global status
register
Bit 6
Bit 5
Global error Communication Not (chip reset
flag (GEF)
error
or comm error)
Table 53.
Table 54.
Bit 2
Bit 1
Bit 0
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Previous content of addressed register
D14
D13
D12
D11
D10
LSB
D9
D8
Format of data shifted out at SDO during write cycle: data byte 2
MSB
D7
Bit 3
Format of data shifted out at SDO during write cycle: data byte 1
MSB
D15
Bit 4
Previous content of addressed register
D6
D5
D4
D3
D2
LSB
D1
D0
Failures are indicated by activating the corresponding bit of the register.
The returned data byte(s) represent(s) the previous content of the accessed register
80/128
Doc ID 023553 Rev 3
L99PM72PXP
ST SPI
Figure 41. Format of data shifted out at SDO during write cycle
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6',
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6.1.8
Read operation
Table 55.
Read command format: command byte
MSB
LSB
Op Code
0
Table 56.
Address
1
A5
A4
A3
A2
A1
Read command format: data byte 1
MSB
0
Table 57.
LSB
0
0
0
0
0
0
0
Read command format: data byte 2
MSB
0
A0
LSB
0
0
0
0
0
0
0
OC0, OC1: operating code (01 for ‘read’ mode)
A0 to A5: Address Bits
Doc ID 023553 Rev 3
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ST SPI
6.1.9
L99PM72PXP
Format of data shifted out at SDO during Read cycle
Table 58.
Format of data shifted out at SDO during read cycle: global status
register
Bit 7
Bit 6
Global error
flag (GEF)
Table 59.
Bit 5
Communication Not (chip reset
error
OR comm error)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Format of data shifted out at SDO during read cycle: data byte 1
MSB
Previous content of addressed register
D15
D14
Table 60.
D13
D12
D11
LSB
D10
D9
D8
Format of data shifted out at SDO during read cycle: data byte 2
MSB
Previous content of addressed register
D7
D6
D5
D4
D3
LSB
D2
D1
D0
Failures are indicated by activating the corresponding bit of the register.
The returned data byte(s) represent(s) the content of the register to be read.
Figure 42. Format of data shifted out at SDO during read cycle
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82/128
Doc ID 023553 Rev 3
L99PM72PXP
6.1.10
ST SPI
Read and Clear Status Operation
The ‘Read and Clear Status’ operation starts with a Command Byte followed 2 data bytes.
The number of data bytes is specified in the . The content of the data bytes
is ‘don’t care’. The content of the addressed Status Register is transferred to SDO within the
same frame (‘in-frame response’) and is subsequently cleared.
A ‘Read and Clear Status’ operation with address 3FH clears all Status registers (incl. the
register). The Configuration Register is read by this operation.
Table 61.
Read and clear status command format: command byte
MSB
LSB
Op Code
1
Table 62.
Address
0
A5
A4
A3
A2
A1
A0
Read and clear status command format: data byte 1
MSB
0
Table 63.
LSB
0
0
0
0
0
0
0
Read and clear status command format: data byte 2
MSB
0
LSB
0
0
0
0
0
0
0
OC0, OC1: operating code (10 for ‘read and clear status’ mode)
A0 to A5: address bits
Format of data shifted out at SDO during ‘Read and Clear Status’ operation
Table 64.
Format of data shifted out at SDO during read and clear status: global
status register
Bit 7
Global error
flag (GEF)
Table 65.
Bit 6
Communication Not (chip reset OR
error
comm error)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TSD2
TSD1
V1 Fail
VS Fail
(OV/UV)
Fail
safe
Format of data shifted out at SDO during read and clear status:
data byte 1
MSB
D15
Bit 5
Previous content of addressed register
D14
D13
D12
Doc ID 023553 Rev 3
D11
D10
LSB
D9
D8
83/128
ST SPI
L99PM72PXP
Table 66.
Format of data shifted out at SDO during read and clear status:
data byte 2
MSB
Previous content of addressed register
D7
D6
D5
D4
D3
LSB
D2
D1
D0
Failures are indicated by activating the corresponding bit of the register.
The returned data byte(s) represent(s) the content of the register to be read.
Figure 43. Format of data shifted out at SDO during read and clear status operation
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6.1.11
Read device information
The device information is stored at the ROM addresses defined below and is read using the
respective operating code.
Read device information
Table 67.
Op Code
ROM address
84/128
Device information
OC1
OC0
1
1
3FH
Reserved
1
1
3EH
Includes frame width and availability of watchdog
1
1
04H to 3DH
1
1
1
1
Value
00
42 Hex
unused
00
03H
Unique product identifier
27h
02H
Unique product identifier
4Bh
Doc ID 023553 Rev 3
L99PM72PXP
ST SPI
Read device information (continued)
Table 67.
Op Code
ROM address
Device information
Value
OC1
OC0
1
1
01H
Indicates Design Version
1
1
00H
Device family max address of device information
According to
silicon version
43 Hex
The (ROM address 00H) indicates the product family and specifies the highest
address which contains product information
Table 68.
ID-header
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
0
1
1
Family Identifier
Highest address containing device information
: 01 Hex (BCD)
: 03 Hex
Table 69.
Family identifier
Bit 7
Bit 6
Meaning
0
0
VIPower
0
1
BCD
1
0
VIPower hybrid
1
1
TBD
The (ROM address 02H) and (ROM address 03H)
represents a unique code to identify the product name.
: 4BHex
: 27 Hex
The (ROM address 01H) provides information about the silicon version
according to the table below:
Table 70.
Bit 7
Silicon version identifier
Bit 6
Bit 5
Bit 4
Reserved
Bit 3
Bit 2
Bit 1
Bit 0
Silicon version
The (ROM address 3EH) provides information about the register width (1,
2, 3 bytes) and the availability of ‘Burst Mode Read’ and watchdog.
Doc ID 023553 Rev 3
85/128
ST SPI
L99PM72PXP
Table 71.
SPI-frame-ID
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
0
0
0
0
1
0
BR
WD
X
X
X
32-bit
24-bit
16-bit
BR: Burst-Mode read (1 = Burst-Mode read is supported)
WD: Watchdog (1 = available, 0 = not available)
32-, 24-, 16-bit: width of SPI frame
: not supported
: available
: 24 bit
6.2
SPI registers
6.2.1
Overview command byte
Table 72.
SPI register: command byte
Read/write
x
Address
x
Table 73.
x
x
x
x
Mode selection
0
0
Write
0
1
Read
1
0
Read and clear
1
1
Read device info
SPI register: CTRL register selection
CTRL register 1…6
86/128
x
SPI register: mode selection
Read/write
Table 74.
x
CTRL register selection
0
0
0
0
0
1
CTRL register1
0
0
0
0
1
0
CTRL register2
0
0
0
0
1
1
CTRL register3
0
0
0
1
0
0
CTRL register4
0
0
0
1
0
1
CTRL register5
0
0
0
1
1
0
CTRL register6
0
0
0
1
1
1
CTRL register7
0
0
1
0
0
0
CTRL register8
Doc ID 023553 Rev 3
L99PM72PXP
ST SPI
Table 74.
SPI register: CTRL register selection (continued)
CTRL register 1…6
CTRL register selection
0
0
1
0
0
1
CTRL Register9
0
0
1
0
1
0
CTRL Register10
0
0
1
0
1
1
CTRL Register11
0
0
1
1
0
0
CTRL Register12
0
0
1
1
0
1
CTRL Register13
0
0
1
1
1
0
CTRL Register14
0
0
1
1
1
1
CTRL Register15
0
1
0
0
0
0
CTRL Register16
1
0
0
0
1
0
CTRL Register34
1
0
0
0
1
1
CTRL Register35
1
1
1
1
1
1
Configuration Register
Table 75.
SPI register: STAT register selection
STAT register. 1…3
STAT register selection
0
1
0
0
0
1
STAT register1
0
1
0
0
1
0
STAT register2
0
1
0
0
1
1
STAT register3
0
1
0
1
0
0
STAT Register4
0
1
0
1
0
1
STAT Register5
6.2.2
Overview control register
Table 76.
Overview of control register data bytes
1st data byte
2nd data byte
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
OUTHS
OUTHS
OUT4
OUT4
OUTHS_EXT
OUT3
OUT2
OUT1
REL2
REL1
V2
V2
Parity
Stby sel
Go Stby
Control register 1, data
Trig
Group
HS control
LS Output, V2 and mode control
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87/128
Group
88/128
1
Function
1
0
0
Function
CAN_ACT
CAN_Loop_En
0
Function
0
Timer Settings
PWM2 setting
Doc ID 023553 Rev 3
Control (other)
WU2_Filt
WU1_Filt
WU1_Filt
Reserved
WU3_Pu/Pd
WU2_Pu/Pd
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
Reserved
0
0
WU1_Pu/Pd
WU1_EN
WU2_Filt
0
Wake Time Sel
Reserved
WU2_EN
Control register 3, data
Wake Timer En
Wake-up control
WU3_EN
0
PWM1 setting
0
0
Reserved
CAN_Rec_Only
Wake-up control
CAN WU En
0
LIN WU En
0
WD_time_LSB
0
WD_time_MSB
0
0
0
0
0
0
PWM1_ON_DC_0
1
Lin TxD Tout En
0
PWM1_ON_DC_1
1
Reserved
0
T2_Per_LSB
0
PWM1_ON_DC_2
0
LIN Pu En
0
T2_Per_MSB
0
PWM1_ON_DC_3
0
V1Reset_Level
0
T2_On
0
WU3_Filt
1st data byte
PWM1_ON_DC_4
Group
PWM1_ON_DC_5
1
V1Reset_Level
Group
PWM1_ON_DC_6
0
LS OV/UV
shutdown_en
0
Reserved
Group
PWM Freq
1
Reserved
0
T1_Per_LSB
WU3_Filt
Reserved
0
PWM2_OFF_DC_0
0
VLOCK_OUT_EN
0
T1_Per_MSB
0
PWM2_OFF_DC_1
0
OUTHS_rec_en
0
T1_On
Function
0
PWM2_OFF_DC_2
1
PWM2_OFF_DC_5
0
ICMP
Default
Reserved
Default
PWM2_OFF_DC_3
0
PWM2_OFF_DC_6
Default
Reserved
Table 76.
PWM2_OFF_DC_4
Default
Reserved
ST SPI
L99PM72PXP
Overview of control register data bytes (continued)
2nd data byte
Control register 2, data
Watchdog and cyclic wake up settings
Control register 4, data
0
Transceiver settings
Control register 5, data
L99PM72PXP
Table 76.
ST SPI
Overview of control register data bytes (continued)
1st data byte
2nd data byte
PWM3_ON_DC_5
0
0
0
PWM3_ON_DC_0
PWM3_ON_DC_6
0
PWM3_ON_DC_1
Reserved
0
PWM3_ON_DC_2
0
PWM3_ON_DC_3
0
PWM3_ON_DC_4
0
0
0
0
0
0
0
0
0
0
0
EXT_ID_6
1
EXT_ID_7
1
PWM4_OFF_DC_0
PWM4_OFF_DC_5
1
EXT_ID_8
PWM4_OFF_DC_6
Group
1
PWM4_OFF_DC_1
Function
1
EXT_ID_9
1
PWM4_OFF_DC_2
1
PWM4_OFF_DC_3
0
PWM4_OFF_DC_4
Default
Reserved
Control register 6, data
PWM4 setting
PWM3 setting
EXT_ID_12
EXT_ID_11
EXT_ID_10
EXT_ID_0
EXT_ID_13
EXT_ID_1
EXT_ID_14
Group
EXT_ID_2
Function
EXT_ID_3
0
EXT_ID_4
0
EXT_ID_5
0
0
0
0
0
0
0
0
0
0
0
ID_4
0
ID_5
0
ID_6
0
ID_7
Default
EXT_ID_15
Control register 7, data
Selective Wakeup Settings
ID_0
EXT_ID_17
EXT_ID_16
0
0
0
0
0
0
DLC_2
DLC_1
DLC_0
Group
ID_1
0
DLC_3
0
ID_2
Reserved
0
CAN_IDE
0
ID_3
Function
0
ID_8
0
ID_9
Default
ID_10
Control register 8, data
0
0
0
0
0
Selective Wakeup Settings
Control register 9, data
Default
0
0
0
0
0
Function
0
0
0
0
0
Reserved
Group
Selective Wakeup Settings
Control register 10, data
Default
Function
Group
0
0
0
0
0
0
0
0
0
0
Data Byte 2
0
Data Byte 1
Selective Wakeup Settings
Doc ID 023553 Rev 3
89/128
ST SPI
Table 76.
L99PM72PXP
Overview of control register data bytes (continued)
1st data byte
2nd data byte
Control register 11, data
Default
0
0
0
Function
0
0
0
0
0
0
0
0
Data Byte 4
0
0
0
0
0
0
0
0
0
0
0
Data Byte 3
Group
Selective Wakeup Settings
Control register 12, data
Default
0
0
0
Function
0
0
0
0
0
0
0
0
Data Byte 6
0
0
Data Byte 5
Group
Selective Wakeup Settings
Control register 13, data
Default
0
0
0
Function
0
0
0
0
0
0
0
0
Data Byte 8
0
0
Data Byte 7
Group
Selective Wakeup Settings
0
0
0
EXT_ID_
Mask_0
0
EXT_ID_
Mask_1
EXT_ID_
Mask_10
0
EXT_ID_
Mask_2
EXT_ID_
Mask_11
0
EXT_ID_
Mask_3
EXT_ID_
Mask_12
0
EXT_ID_
Mask_4
EXT_ID_
Mask_13
0
EXT_ID_
Mask_5
EXT_ID_
Mask_14
Group
0
EXT_ID_
Mask_6
Function
0
0
0
0
0
0
0
0
0
0
0
ID_Mask_4
0
EXT_ID_
Mask_7
0
ID_Mask_5
0
EXT_ID_
Mask_8
0
ID_Mask_6
0
EXT_ID_
Mask_9
0
ID_Mask_7
Default
EXT_ID_
Mask_15
Control register 14, data
Selective Wakeup Settings
ID_Mask_3
ID_Mask_2
ID_Mask_1
ID_Mask_0
EXT_ID_
Mask_17
EXT_ID_
Mask_16
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
Function
Reserved
Samp 2
Samp 1
Samp 0
Reserved
ID_Mask_8
0
CR16_10
ID_Mask_9
Defaults
CR16_11
0
CR16_12
0
CR16_13
0
CR16_14
0
CR16_20
0
CR16_21
0
CR16_30
Defaults
ID_Mask_10
Control register 15, data
Function
Reserved
Group
Selective Wakeup Settings
Group
90/128
Selective Wakeup Settings
Doc ID 023553 Rev 3
BR1 BR2
SW_EN
Control register 16, data
L99PM72PXP
Table 76.
ST SPI
Overview of control register data bytes (continued)
1st data byte
2nd data byte
0
Function
0
0
0
0
0
0
0
0
1
0
1
1
0
1
1
0
0
0
0
0
0
0
WD_EN
0
CR35_10
0
CR35_20
0
CR35_21
0
CR35_22
0
CR35_23
0
CR35_24
Defaults
CR35_25
Control register 34, data
Reserved
Control Register 35, data
Defaults
0
0
0
0
0
Function
0
0
0
0
Reserved
Configuration Register, data
0
0
0
0
0
0
0
Function
Note:
0
0
0
TRIG
Defaults
Reserved
Reserved bit must be kept at their default values.
Writing to other register address is not allowed
Control Register 1
Table 77.
Control register 1: command and data bytes
Command byte
Read/write
x
Table 78.
x
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
0
0
0
0
0
1
Control register 1, data bytes
Defaults
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Function
OUT4_2
OUT4_1
OUTHS_EXT
OUT3
OUT2
OUT1
REL2
REL1
V2_2
V2_1
Parity
STBY_SEL
GO_STBY
2nd data byte
OUTHS_1
1st data byte
OUTHS_2
6.2.3
Trig
Group
HS control
Doc ID 023553 Rev 3
LS Output, V2 and mode control
91/128
ST SPI
L99PM72PXP
Table 79.
Control register 1, bits
Bit
Name
15
OUTHS
14
13
Comment
Select mode of OUTHS
OUTHS_EXT OUTHS_2
OUT4
12
OUTHS_1
Mode
0
0
0
HS off
0
0
1
HS cyclic on with timer
1
0
1
0
0
1
1
1
1
0
PWM3
1
x
1
HS on
HS controlled by PWM4 Active and
standby
HS cyclic on with Timer mode
2
Select mode of OUT4
OUT4_2
OUT4_1
Mode
0
0
HS off
0
1
HS on
1
0
HS
controlled
by PWM4
1
1
HS cyclic
on with
Timer 2
Active and standby
mode
11 OUTHS_EXT Extended function of OUTHS; see OUTHS
10
OUT3
Select mode of OUT3
OUT3
92/128
Mode
0
Select
FSO
1
Select
PWM3
Active and
standby
mode
Doc ID 023553 Rev 3
L99PM72PXP
ST SPI
Table 79.
Control register 1, bits (continued)
Bit
Name
9
OUT2
Comment
Select mode of OUT2
OUT2
8
OUT1
Mode
0
Select
PWM2
1
Select
timer2
Select mode of OUT1
OUT1
7
REL2
Mode
0
Select
PWM1
1
Select
timer1
REL1
Active and
standby
mode
Select mode of REL2
REL2
6
Active and
standby
mode
Mode
0
REL2 off
Active and
standby
mode
1
REL2 on
Active
mode
Select mode of REL1
REL1
Mode
0
REL1 off
Active and
standby
mode
1
REL1 on
Active
mode
Doc ID 023553 Rev 3
93/128
ST SPI
L99PM72PXP
Table 79.
Control register 1, bits (continued)
Bit
Name
5
V2
4
3
Parity
Comment
V2_2
V2_1
0
0
V2 OFF in all modes
0
1
V2 ON in active mode; OFF in
V1/VBat_standby mode
1
0
V2 ON in Active/V1_standby mode;
OFF in VBat_standby mode
1
1
V2 ON in all modes
The Stby_sel and Go_stby bits are protected by a parity check
The bits Stby_sel, Go_stby and Parity must represent an even number of '1',
otherwise the command is ignored and the Communication Error bit is set in the
Global Status Register. Following are the valid settings
2
1
0
94/128
STBY_SEL
GO_STBY
TRIG
Parity
STBY_SE
L
GO_STBY
0
1
1
Go to V1_standby
1
0
1
Go to VBat_standby
0
0
0
No transition to standby
1
1
0
No transition to standby
Select standby mode
0
VBat_standby mode
1
V1_standby mode
Execute standby mode
0
No action
1
Execute standby mode
Trigger Bit for Watchdog
Doc ID 023553 Rev 3
Command
L99PM72PXP
Control Register 2
Table 80.
Control register 2: command and data bytes
Command byte
Read/write
x
0
0
0
0
1
Data, 8bit
Data, 8 bit
0
Control register 2, data bytes
Group
0
0
0
0
0
0
0
0
WU1_Filt_MSB
WU1_Filt_LSB
Reserved
WU3_Pu/Pd
WU2_Pu/Pd
WU1_Pu/Pd
Wakeup control
Table 82.
1
1
Wakeup control
Control register 2, bits
Bit
Name
15
Reserved
Must be kept at default
14
Reserved
Must be kept at default
13, 12
WU3_Filt
Wakeup filter configuration
11, 10
WU2_Filt
MSB
LSB
9, 8
WU1_Filt
0
0
Static, 64 µs
0
1
Enabled with timer 2; 80 µs blank
1
0
Enabled with timer 2; 800 µs blank
1
1
Enabled with timer 1; 800 µs blank
7
1
WU1_EN
0
WU2_EN
0
WU2_Filt_LSB
0
WU2_Filt_MSB
Function
0
WU3_Filt_LSB
Defaults
2nd data byte
WU3_Filt_MSB
1st data byte
WU3_EN
Table 81.
2nd data byte
Reserved
x
1st data byte
Address
Reserved
6.2.4
ST SPI
Reserved
Comment
Must be kept at default
6
WU3_Pu/Pd Pull up or pull down configuration
5
WU2_Pu/Pd
0
Pull down
4
WU1_Pu/Pd
1
Pull up
3
Reserved
Must be kept at default
2
WU3_EN
Enable Wake up source
1
WU2_EN
0
Disable
0
WU1_EN
1
Enable
Doc ID 023553 Rev 3
95/128
ST SPI
Control Register 3
Table 83.
Control register 3: command and data bytes
Command byte
Read/write
Data, 8bit
Data, 8 bit
Address
x
0
0
0
0
1
1
Control register 3, data bytes
0
0
0
0
0
0
Function
T1_Per_MSB
T1_Per_LSB
Reserved
T2_On
T2_Per_MSB
T2_Per_LSB
Group
Timer Settings
Table 85.
0
0
Reserved
0
0
1
1
0
0
Wake_timer_select
0
Wake_timer_en
0
CAN_WU_En
Defaults
T1_On
2nd data byte
Reserved
1st data byte
LIN_WU_En
Table 84.
2nd data byte
WD_time_LSB
x
1st data byte
WD_time_MSB
6.2.5
L99PM72PXP
Watchdog and cyclic wake up settings
Control register 3, bits
Bit
Name
15
Reserved
14
T1_On
13
T1_Per_MSB
12
T1_Per_LSB
Comment
Must be kept at default
Timer 1 “ON” time selections
0
10 ms
1
20 ms
Timer 1 period selection
MSB
LSB
0
0
1s
0
1
2s
1
0
3s
1
1
4s
Timer 1 is restarted with a valid write command to control register 3
96/128
11
Reserved
10
T2_On
Must be kept at default
Timer 2 “ON” time selection
0
0.1 ms
1
1 ms
Doc ID 023553 Rev 3
L99PM72PXP
ST SPI
Table 85.
Control register 3, bits (continued)
Bit
Name
9
T2_Per_MSB
8
T2_Per_LSB
Comment
Timer 2 period selection
MSB
LSB
0
0
10 ms
0
1
20 ms
1
0
50 ms
1
1
200 ms
Timer 2 is restarted with a valid write command to control register 3
7
Reserved
Must be kept at default
6
Reserved
Must be kept at default
5
WD_time_MSB
4
WD_time_LSB
3
2
1
0
LIN_WU_En
CAN_WU_En
Wake_timer_En
Trigger window selection
MSB
LSB
0
0
10 ms
0
1
50 ms
1
0
100 ms
1
1
200 ms
Enable LIN as wake up source
0
Disabled
1
Enabled
Enable CAN as wake up source
0
Disabled
1
Enabled
Enable wake up by timer from V1_standby mode (Interrupt) or VBat_standby
Mode (Nreset)
0
Disabled
1
Enabled
Wake_timer_select Timer selection for timer interrupt / wake-up of µC by timer
0
Timer 2
1
Timer 1
Doc ID 023553 Rev 3
97/128
ST SPI
Control Register 4
Table 86.
Control register 4: command and data bytes
Command byte
Read/write
x
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
Table 87.
1st data byte
0
0
0
1
0
0
Control register 4, data bytes
Defaults
0
0
0
1
0
1
0
0
1
1
1
0
0
Function
ICMP
OUTHS_rec_en
VLOCK_OUT_EN
Reserved
LS_OV/UV_shutdown_en
V1Reset_level_2
V1Reset_level_1
LIN_PU_EN
Reserved
Lin_TxD_Tout_En
CAN_ACT
CAN_Loop_En
2nd data byte
Reserved
1st data byte
Group
Control (other)
Table 88.
0
Reserved
Transceiver settings
Control register 4, bits
Bit
Name
15
Reserved
14
ICMP
13
0
OUTHS_rec_en
Comment
Must be kept at default
V1 load current supervision
0
Enabled; Watchdog is disabled in V1 Standby when
the V1loadcurrent < Icmpthreshold
1
Disabled; Watchdog is automatically disabled when
V1 standby is entered
Overcurrent Auto recovery mode for OUTHS
0
Disabled
1
Enabled
12 VLOCK_OUT_EN Voltage lock out: OV/UV status
11
98/128
Reserved
0
Overvoltage/undervoltage status recovers
automatically when condition disappears
1
Overvoltage/undervoltage status is latched until a
read and clear command is performed
Must be kept at default
Doc ID 023553 Rev 3
0
CAN_Rec_only
6.2.6
L99PM72PXP
L99PM72PXP
ST SPI
Table 88.
Control register 4, bits (continued)
Bit
Name
10
LS_OV/UV
shutdown_en
Comment
Shutdown of low-side drivers in case of overvoltage/undervoltage
0
No shutdown of low-sides in case of
overvoltage/undervoltage
1
Shutdown low-sides in case of
overvoltage/undervoltage
9
V1Reset_level_1 Select reset level
8
V1Reset_level_2
V1Reset_level_
V1Reset_level_1
2
7
6
5
4
LIN_PU_EN
Reserved
V1 reset level
0
0
4.6 V
0
1
4.35 V
1
0
4.1 V
1
1
3.8 V
Enable internal LIN pull up
0
No LIN master pull-up
1
LIN master pull-up
Must be kept at default
Lin_TxD_Tout_En Enable / disable monitoring via TxD
CAN_ACT
0
No TxD monitoring
1
TxD monitoring; LIN transmitter is switched off if
TXDL is dominant for t > 12 ms
Activate CAN transceiver
Controls the CAN transceiver mode transition between 'CAN Trx Standby'
Mode and 'Trx Normal' mode.
The bit CAN_ACT is automatically reset to '0' when the device enters
V1_standby Mode or VBat_standby Mode.
0
CAN Trx Standby Mode
1
Trx Normal Mode
See Section 2.9.1 for details.
Doc ID 023553 Rev 3
99/128
ST SPI
L99PM72PXP
Table 88.
Control register 4, bits (continued)
Bit
Name
Comment
3
CAN_Loop_En
Enable looping of CANTX to CANRXD
0
No looping
1
TXDC is looped to RXDC
2
Reserved
Must be kept at default
1
Reserved
Must be kept at default
0
CAN_Rec_only
Enable CAN receive only mode
0
CAN in transceiver mode
1
CAN in receive only mode
Active mode
Control Register 5
Table 89.
Control register 5: command and data bytes
Command byte
Read/write
Data, 8bit
Data, 8 bit
Address
0
0
0
1
0
1
Control register 5, data bytes
100/128
0
0
0
PWM1_ON_DC_5
PWM2 setting
Doc ID 023553 Rev 3
0
0
0
0
0
PWM1_ON_DC_0
1
PWM1_ON_DC_1
1
PWM1_ON_DC_6
PWM2_OFF_DC_5
1
PWM_Freq
PWM2_OFF_DC_6
Group
1
PWM2_OFF_DC_0
Function
1
PWM2_OFF_DC_1
1
PWM2_OFF_DC_2
1
PWM2_OFF_DC_3
0
2nd data byte
PWM2_OFF_DC_4
Defaults
Reserved
1st data byte
PWM1_ON_DC_2
Table 90.
x
2nd data byte
PWM1_ON_DC_3
x
1st data byte
PWM1_ON_DC_4
6.2.7
PWM1 setting
L99PM72PXP
ST SPI
Table 91.
Control register 5, bits
Bit
Name
15
Reserved
Comment
Must be kept at default
14
PWM2_
PWM2 duty cycle
OFF_DC_6
13
PWM2_
OFF_DC_5
12
PWM2_
OFF_DC_4
11
PWM2_
OFF_DC_3
10
PWM2_
OFF_DC_2
0
0
0
0
9
PWM2_
OFF_DC_1
0
0
0
8
PWM2_
OFF_DC_0
0
0
0
7
PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 PWM2
OFF_ OFF_ OFF_ OFF_ OFF_ OFF_ OFF_
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0
1
1
1
1
1
PWM2 duty
cycle
1
1
0%, HS OFF
0
1
0
98.5%
0
0
0
1
99.25%
0
0
0
0
100% HS ON
...
PWM_FREQ Select PWM frequency
0
128 Hz
1
256 Hz
6
PWM1_
ON_DC_6
PWM1 duty cycle
5
PWM1_
ON_DC_5
PWM1 PWM1 PWM1 PWM1 PWM1 PWM1 PWM1
ON_
ON_
ON_
ON_
ON_
ON_
ON_
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0
4
PWM1_
ON_DC_4
3
PWM1_
ON_DC_3
2
PWM1_
ON_DC_2
0
0
0
0
1
PWM1_
ON_DC_1
0
0
0
0
PWM1_
ON_DC_0
0
0
0
1
1
1
1
1
PWM1 duty
cycle
1
1
100%, HS ON
0
1
0
1.5%
0
0
0
1
0.75%
0
0
0
0
0% HS OFF
...
Doc ID 023553 Rev 3
101/128
ST SPI
Control Register 6
Table 92.
Control register 6: command and data bytes
Command byte
Read/write
Data, 8bit
Data, 8 bit
Address
x
0
0
0
1
1
0
Control register 6, data bytes
Group
Table 94.
102/128
PWM4 setting
0
0
0
0
0
PWM3 setting
Control register 6, bits
Bit
Name
15
Reserved
Comment
Must be kept at default
14
PWM4_
PWM4 duty cycle
OFF_DC_6
13
PWM4 PWM4 PWM4 PWM4 PWM4 PWM4 PWM4
PWM4_
OFF_ OFF_ OFF_ OFF_ OFF_ OFF_ OFF_
OFF_DC_5
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0
12
PWM4_
OFF_DC_4
11
PWM4_
OFF_DC_3
10
PWM4_
OFF_DC_2
0
0
0
0
9
PWM4_
OFF_DC_1
0
0
0
8
PWM4_
OFF_DC_0
0
0
0
7
Reserved
1
1
1
1
1
PWM4 duty
cycle
1
1
0%, HS OFF
0
1
0
98.5%
0
0
0
1
99.25%
0
0
0
0
100% HS ON
...
Must be kept at default
Doc ID 023553 Rev 3
0
PWM3_ON_DC_0
Reserved
0
PWM3_ON_DC_1
0
PWM3_ON_DC_6
1
PWM4_OFF_DC_0
1
PWM4_OFF_DC_1
1
PWM4_OFF_DC_2
1
PWM4_OFF_DC_3
1
PWM4_OFF_DC_4
1
PWM4_OFF_DC_5
1
PWM4_OFF_DC_6
Function
0
Reserved
Defaults
2nd data byte
PWM3_ON_DC_2
1st data byte
PWM3_ON_DC_3
Table 93.
2nd data byte
PWM3_ON_DC_4
x
1st data byte
PWM3_ON_DC_5
6.2.8
L99PM72PXP
L99PM72PXP
ST SPI
Table 94.
Bit
Control register 6, bits (continued)
Name
Comment
6
PWM3_
PWM3 duty cycle
ON_DC_6
5
PWM3_
ON_DC_5
4
PWM3_
ON_DC_4
3
PWM3_
ON_DC_3
2
PWM3_
ON_DC_2
0
0
0
0
1
PWM3_
ON_DC_1
0
0
0
0
PWM3_
ON_DC_0
0
0
0
PWM3 PWM3 PWM3 PWM3 PWM3 PWM3 PWM3
ON_
ON_
ON_
ON_
ON_
ON_
ON_
DC_6 DC_5 DC_4 DC_3 DC_2 DC_1 DC_0
1
1
1
1
1
PWM3 duty
cycle
1
1
100%, HS ON
0
1
0
1.5%
0
0
0
1
0.75%
0
0
0
0
0% HS OFF
...
Doc ID 023553 Rev 3
103/128
ST SPI
6.2.9
L99PM72PXP
Control Register 7
Table 95.
Control register 7: command and data bytes
Command byte
Read/write
x
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
Table 96.
1st data byte
0
0
0
1
1
1
Control register 7, data bytes
EXT_ID_12
EXT_ID_11
EXT_ID_10
0
0
0
0
0
0
EXT_ID_0
EXT_ID_13
0
Selective Wakeup Settings
Table 97.
104/128
0
EXT_ID_1
EXT_ID_14
Group
0
EXT_ID_2
Function
0
EXT_ID_3
0
EXT_ID_4
0
EXT_ID_5
0
EXT_ID_6
0
EXT_ID_7
0
EXT_ID_8
0
2nd data byte
EXT_ID_9
Defaults
EXT_ID_15
1st data byte
Control register 7, bits
Bit
Name
15
EXT_ID_15
14
EXT_ID_14
13
EXT_ID_13
12
EXT_ID_12
11
EXT_ID_11
10
EXT_ID_10
9
EXT_ID_9
8
EXT_ID_8
7
EXT_ID_7
6
EXT_ID_6
5
EXT_ID_5
4
EXT_ID_4
3
EXT_ID_3
2
EXT_ID_2
1
EXT_ID_1
0
EXT_ID_0
Comment
Extended CAN Identifier
Definition of which Extended CAN Identifier will wake up
To run matching on Extended CAN Identifier also CAN IDE (Control Register 9
must be set)
Doc ID 023553 Rev 3
L99PM72PXP
Control Register 8
Table 98.
Control register 8: command and data bytes
Command byte
Read/write
x
x
Table 99.
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
0
0
1
0
0
0
Control register 8, data bytes
Group
0
0
0
0
0
0
0
0
ID_0
EXT_ID_17
EXT_ID_16
0
ID_1
0
ID_2
0
ID_3
0
ID_4
Reserved
0
ID_5
0
ID_6
0
2nd data byte
ID_7
Function
0
ID_8
Defaults
ID_9
1st data byte
ID_10
6.2.10
ST SPI
Selective Wakeup Settings
Table 100. Control register 8, bits
Bit
Name
15
Reserved
14
Reserved
13
Reserved
12
ID_10
11
ID_9
10
ID_8
9
ID_7
8
ID_6
7
ID_5
6
ID_4
5
ID_3
4
ID_2
3
ID_1
2
ID_0
1
0
Comment
Must be kept at default
Standard CAN Identifier
Definition of which Standard CAN Identifier will wake up
EXT_ID_17 Extended CAN Identifier
Definition of which Extended CAN Identifier will wake up
EXT_ID_16 To run matching on Extended CAN Identifier also CAN IDE (Control Register 9
must be set)
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ST SPI
6.2.11
L99PM72PXP
Control Register 9
Table 101. Control register 9: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
0
0
1
0
0
1
Table 102. Control register 9, data bytes
0
0
Function
0
0
0
0
0
Reserved
Group
0
0
0
0
0
0
DLC_0
0
DLC_1
0
DLC_2
0
DLC_3
Defaults
2nd data byte
CAN_IDE
1st data byte
Selective Wakeup Settings
Table 103. Control register 9, bits
106/128
Bit
Name
15
Reserved
14
Reserved
13
Reserved
12
Reserved
11
Reserved
10
Reserved
9
Reserved
8
Reserved
7
Reserved
6
Reserved
5
Reserved
4
CAN_IDE
3
DLC_3
2
DLC_2
1
DLC_1
0
DLC_0
Comment
Must be kept at default
CAN IDE bit
1
CAN Identifier Matching based on CAN Extended Message
Format
0
CAN Identifier matching based on CAN Standard Message
Format
Data Length Code
Defines the amount of Data Bytes used for the data matching.
Possible values up to 8 Byte according to CAN message format
Doc ID 023553 Rev 3
L99PM72PXP
6.2.12
ST SPI
Control Register 10
Table 104. Control register 10: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
0
0
1
0
1
0
Table 105. Control register 10, data bytes
1st data byte
Defaults
0
0
0
0
Function
0
2nd data byte
0
0
0
0
0
0
Data Byte2
0
0
0
0
0
Data Byte1
Group
Selective Wakeup Settings
Table 106. Control register 10, bits
Bit
6.2.13
Name
Comment
15 - 8
Data Byte2 Data field for data matching
7-0
Data Byte1 Data field for data matching
Control Register 11
Table 107. Control register 11: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
0
0
1
0
1
1
Table 108. Control register 11, data bytes
1st data byte
Defaults
0
Function
0
0
0
0
0
2nd data byte
0
0
0
0
Data Byte4
Group
0
0
0
0
0
0
Data Byte3
Selective Wakeup Settings
Table 109. Control register 11, bits
Bit
Name
Comment
15 - 8
Data Byte4 Data field for data matching
7-0
Data Byte3 Data field for data matching
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ST SPI
6.2.14
L99PM72PXP
Control Register 12
Table 110. Control register 12: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
0
0
1
1
0
0
Table 111. Control register 12, data bytes
1st data byte
Defaults
0
0
0
0
Function
0
2nd data byte
0
0
0
0
0
0
Data Byte6
0
0
0
0
0
Data Byte5
Group
Selective Wakeup Settings
Table 112. Control register 12, bits
Bit
6.2.15
Name
Comment
15 - 8
Data Byte6 Data field for data matching
7-0
Data Byte5 Data field for data matching
Control Register 13
Table 113. Control register 13: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
0
0
1
1
0
1
Table 114. Control register 13, data bytes
1st data byte
Defaults
0
Function
0
0
0
0
0
2nd data byte
0
0
0
0
Data Byte8
Group
108/128
0
0
Data Byte7
Selective Wakeup Settings
Table 115. Control register 13, bits
Bit
0
Name
Comment
15 - 8
Data Byte8 Data field for data matching
7-0
Data Byte7 Data field for data matching
Doc ID 023553 Rev 3
0
0
0
L99PM72PXP
Control Register 14
Table 116. Control register 14: command and data bytes
Command byte
Read/write
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
x
0
0
1
1
1
0
Table 117. Control register 14, data bytes
EXT_ID_MSK_11
EXT_ID_MSK_10
0
0
0
0
0
0
0
EXT_ID_MSK_0
EXT_ID_MSK_12
0
EXT_ID_MSK_1
EXT_ID_MSK_13
Group
0
EXT_ID_MSK_2
Function
0
EXT_ID_MSK_3
0
EXT_ID_MSK_4
0
EXT_ID_MSK_5
0
EXT_ID_MSK_6
0
EXT_ID_MSK_7
0
EXT_ID_MSK_8
0
2nd data byte
EXT_ID_MSK_9
Defaults
EXT_ID_MSK_14
1st data byte
EXT_ID_MSK_15
6.2.16
ST SPI
Selective Wakeup Settings
Table 118. Control register 14, bits
Bit
Name
Comment
15
EXT_ID_MSK_15
Masking Bits for Extended CAN Identifier
14
EXT_ID_MSK_14
1
Extended CAN Identifier Bit is ignored for matching
13
EXT_ID_MSK_13
0
Extended CAN Identifier Bit is matched
12
EXT_ID_MSK_12
11
EXT_ID_MSK_11
To run matching on Extended CAN Identifier also CAN_IDE (Control
Register 9 must be set)
10
EXT_ID_MSK_10
9
EXT_ID_MSK_9
8
EXT_ID_MSK_8
7
EXT_ID_MSK_7
6
EXT_ID_MSK_6
5
EXT_ID_MSK_5
4
EXT_ID_MSK_4
3
EXT_ID_MSK_3
2
EXT_ID_MSK_2
1
EXT_ID_MSK_1
0
EXT_ID_MSK_0
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ST SPI
6.2.17
L99PM72PXP
Control Register 15
Table 119. Control register 15: command and data bytes
Command byte
Read/write
x
1st data byte
2nd data byte
Data, 8bit
Data, 8 bit
Address
x
0
0
1
1
1
1
Table 120. Control register 15, data bytes
Group
0
0
0
0
0
0
0
0
0
0
ID_MSK_3
ID_MSK_2
ID_MSK_1
ID_MSK_0
EXT_ID_MSK_17
EXT_ID_MSK_16
0
ID_MSK_4
0
ID_MSK_5
Reserved
0
ID_MSK_6
0
2nd data byte
ID_MSK_7
0
ID_MSK_8
Function
0
ID_MSK_9
Defaults
ID_MSK_10
1st data byte
Selective Wakeup Settings
Table 121. Control register 15, bits
Bit
Name
Comment
15
Reserved
14
Reserved
13
Reserved
12
ID_MSK_10
11
ID_MSK_9
1
Standard CAN Identifier Bit is ignored for matching
10
ID_MSK_8
0
Standard CAN Identifier Bit is matched
9
ID_MSK_7
8
ID_MSK_6
7
ID_MSK_5
6
ID_MSK_4
5
ID_MSK_3
4
ID_MSK_2
3
ID_MSK_1
2
ID_MSK_0
1
EXT_ID_MSK_17
0
EXT_ID_MSK_16
Must be kept at default
Masking Bits for Standard CAN Identifier
Masking Bits for Extended CAN Identifier
1
Extended CAN Identifier Bit is ignored for matching
0
Extended CAN Identifier Bit is matched
To run matching on Extended CAN Identifier also CAN_IDE (Control
Register 9 must be set)
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L99PM72PXP
Control Register 16
Table 122. Control register 16: command and data bytes
Command byte
Read/write
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
x
0
1
0
0
0
0
Table 123. Control register 16, data bytes
CR16_13
CR16_12
0
0
0
0
0
0
0
SW_EN
CR16_14
0
BR_0
CR16_20
Group
0
BR_1
Function
0
Reserved
0
Sample_0
0
Sample_1
0
Sample_2
0
Reserved
0
CR16_10
0
2nd data byte
CR16_11
Defaults
CR16_21
1st data byte
CR16_30
6.2.18
ST SPI
Selective Wakeup Settings
Table 124. Control register 16, bits
Bit
15
Name
Comment
(1)
CR16_30
14
CR16_21
13
CR16_20
12
CR16_14
11
CR16_13
10
CR16_12
9
CR16_11
8
CR16_10
7
Reserved
Must be kept at default
6
Sample_2
Sample point
5
Sample_1
Sample_2 Sample_1 Sample_0
4
Sample_0
0
0
0
71.5 %
0
0
1
73.5 %
0
1
0
75.5 %
0
1
1
77.5 %
1
0
0
79.5 %
1
0
1
81.5 % (Optimum sample point(2))
1
1
0
83.5 %
1
1
1
85.5 %
Must be kept at default
Doc ID 023553 Rev 3
Sample point
111/128
ST SPI
L99PM72PXP
Table 124. Control register 16, bits (continued)
Bit
Name
3
Reserved
2
BR_1
1
BR_0
0
SW_EN
Comment
Must be kept at default
CAN baud rate
BR_1
BR_0
Baud rate
0
0
500 kBaud
0
1
250 kBaud
1
1
125 kBaud
Selective Wakeup Enable
0
No selective wakeup
1
Selective wakeup enabled
See Section 2.9.2
1. Changing the default configuration of CR16 (bits 1 to 15) is only possible when selective wake is disabled
(SW_EN = 0). Setting SW_EN = 0 is always possible. Setting SW_EN = 1 must follow the procedure as
described in Section 2.9.2.
2. The sampling point bits [6:4] have to be programmed to “101” (81.5%) before enabling the selective wakeup feature.
112/128
Doc ID 023553 Rev 3
L99PM72PXP
Control Register 34
Table 125. Control register 34: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
1
0
0
0
1
0
Table 126. Control register 34, data bytes
1st data byte
Defaults
0
0
0
0
0
0
2nd data byte
0
Function
0
0
0
Reserved
Group
0
0
0
0
0
1
WD_EN
6.2.19
ST SPI
Selective Wakeup Settings
Table 127. Control register 34, bits
Bit
Name
15
Reserved
14
Reserved
13
Reserved
12
Reserved
11
Reserved
10
Reserved
9
Reserved
8
Reserved
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
Reserved
0
WD_EN
Comment
Must be kept at default
Watchdog enabled bit
0
Watchdog disabled
1
Watchdog enabled
Writing to this bit is only possible during CAN Flash Mode (VTxDL > VFlash).
See Section 2.2.2: Flash Mode.
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ST SPI
6.2.20
L99PM72PXP
Control Register 35
Table 128. Control register 35: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Data, 8 bit
Data, 8 bit
Address
1
0
0
0
1
1
Table 129. Control register 35, data bytes
0
0
0
Reserved
Group
0
0
1
1
0
1
1
0
CR35_10
0
CR35_20
0
CR35_21
0
CR35_22
Function
0
CR35_23
0
CR35_24
Defaults
2nd data byte
CR35_25
1st data byte
Selective Wakeup Settings
Table 130. Control register 35, bits
Bit
Name
15
Reserved
14
Reserved
13
Reserved
12
Reserved
11
Reserved
10
Reserved
9
Reserved
8
Reserved
7
Reserved
6
CR35_25
5
CR35_24
4
CR35_23
3
CR35_22
2
CR35_21
1
CR35_20
0
CR35_10
Comment
Must be kept at default
Must be kept at default
114/128
Must be kept at default
Doc ID 023553 Rev 3
Function
Group
Reserved
OSC_FAIL
FECNT_0
Diagnosis 9
Doc ID 023553 Rev 3
Diagnosis 5
Diagnosis 7
Reserved
FD_ERR
WD_timer_state
WD_timer_state
Forced_sleep_WD
CAN_silent
Status register 4, data
Forced_sleep_
TSD2_SHTV1
Diagnosis 6
WUF
WUP
Diagnosis 3
CAN_TxD_
perm_dom
CAN_perm_dom
CAN_perm_rec
CAN_RxD_
perm_rec
LIN_perm_rec
LIN_TxD_perm_dom
Diagnosis 1
WD_fail
WD_fail
LIN_perm_dom
Wake_Timer_int
Wake_LIN
Wake_CAN
WU1_Wake
OL_OUT1
OL_OUT2
V2_short
V2_fail
OC_REL1
OC_REL2
OC_OUT1
OC_OUT2
OC_OUT3
OC_OUT4
OC_HS
1st data byte
CAN_TO
TX_SYNC
WD_fail
WD_fail
V1_restart
V1_restart
V1_restart
WU2_wake
WU3_wake
OL_OUT3
OV
SYS_ERR
SWRD_7
SWR_D 8
SWRD_9
SWRD_10
V1_fail
Device_state
WU1_state
OL_OUT4
OL_HS
UV
FECNT_1
FECNT_2
SWRD_11
Group
SWRD_12
Group
FECNT_3
Group
Device_state
WU2_state
Group
FECNT_4
Function
TW
SWRD_13
Function
SWRD_14
Function
WU3_state
Function
TSD1
6.2.21
SWRD_15
L99PM72PXP
ST SPI
Overview status register
Table 131. Overview of status register data bytes
2nd data byte
Status register 1, data
Diagnosis 2
Status register 2, data
Diagnosis 4
Status register 3, data
Diagnosis 8
Status register 5, data
Osc_Mon
Diagnosis 10
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ST SPI
6.2.22
L99PM72PXP
Global status register
The Global Error Flag is set once the watchdog failure counter (SR3) is unequal to 0
(see also Section 2.5: Fail Safe Mode).
Table 132. Global status register
Fail safe(6)
Bit 0
VS Fail
(OV/UV) (5)
Bit 1
V1 Fail
Bit 2
TSD1
Bit 3
TSD2(4)
Bit 4
NOT (chip reset
or comm error)(3)
Bit 5
Communication
error (2)
Bit 6
Global error flag (1)
Bit 7
Active high/low
High
High
Low
High
High
High
High
High
Default value in Normal Mode - after
correct WD trigger or after Read & Clear
on Error Flags
0
0
1
0
0
0
0
0
20
Power ON
1
0
0
0
0
0
0
0
80
1
0
0
0
0
0
1
0
82
Communication error
1
1
0
0
0
0
0
0
C0
VS overvoltage or undervoltage
1
0
1
0
0
0
1
0
A2
WD failure
1
0
1
0
0
0
0
1
A1
SPI Error (DI Stuck)
1
0
1
0
0
0
0
1
A1
TSD1
1
0
1
0
1
0
0
0
A8
TSD2
1
0
1
1
1
0
0
1
B9
1
0
1
0
0
1
0
0
A4
1
0
1
0
0
0
0
0
A0
Power ON weak battery
(7)
V1 Fail
Other Device Failure
(8)
Hex
value
1. The following Status Bits are reported in the Global Error Flag:
Global Status Register: Bits 6-0
Status Register 1: Bits 10-0
Status Register 3: Bits 15, 11, 7-2
2. Communication Error: invalid number of CLOCK cycles during CSN low or failed parity check on standby command.
3. Cleared with CLR command on SR3.
4. Cleared with “READ and CLEAR” on SR3 (-> TSD1)
5. Diagnosis bit only, VS Fail is not a Fail-Safe event; cleared by Read&Clear. Bit is automatically cleared at (VS > VSUV) and
(VS < VSOV) if Vlock_out_en = 0
6. Cleared with a valid WD trigger (WD fail) or by clearing the corresponding status register related to failure
7. Slow VS ramp-up (VS undervoltage is filtered with 64µs after power-on reset)
8. The Global Error Flag is raised due to a failure condition which is not reported in the Global Status Register. The Failure is
reported in the Status Registers 1-5
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L99PM72PXP
Status Register 1
Table 133. Status register 1: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
0
1
0
0
0
1
Table 134. Control register 1, data bytes
Group
Diagnosis 1
OC_REL1
OC_REL2
OC_OUT1
OC_OUT2
OC_OUT3
OC_OUT4
OV
OC_HS
V2_short
UV
2nd data byte
V2_fail
OL_OUT1
OL_OUT2
OL_OUT3
Function
OL_OUT4
1st data byte
OL_HS
6.2.23
ST SPI
Diagnosis 2
Table 135. Status register 1, bits
Bit
Name
15
OL_HS
Comment
Information storage
14 OL_OUT4
13 OL_OUT3
Open-load event occurred
since last read out
Bit is latched until a “read and clear” access
12 OL_OUT2
11 OL_OUT1
10
UV
VLOCKOUTEN
(CR4)
Under voltage event on VS
occurred since last read out
Information storage
0
automatically reset when UV
condition disappears
1
Bit is latched until a “read and
clear” access
9
V2_fail
V2 fail (V2 < 2 V for t> 2 µs)
event occurred since last
Bit is latched until a “Read and clear” access
readout
8
V2_short
V2 short (V2 < 2 V for t >
4ms during start up) event Bit is latched until a “Read and clear” access
occurred since last readout
Doc ID 023553 Rev 3
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ST SPI
L99PM72PXP
Table 135. Status register 1, bits (continued)
Bit
Name
7
OV
Comment
Information storage
VLOCKOUTEN
(CR4)
Over voltage event on VS
occurred since last read out
118/128
6
OC_HS
5
OC_OUT4
4
OC_OUT3
3
OC_OUT2
2
OC_OUT1
1
OC_REL2
0
OC_REL1
Information storage
0
automatically reset when OV
condition disappears
1
Bit is latched until a “read and
clear” access
Over current event
Bit is latched until a “read and clear” access
occurred since last read out
Doc ID 023553 Rev 3
L99PM72PXP
Status Register 2
Table 136. Status register 2: command and data bytes
Command byte
Read/write
x
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
x
0
1
0
0
1
0
Table 137. Control register 2, data bytes
Group
Diagnosis 3
CAN_TxD_perm_dom
CAN_perm_dom
CAN_perm_rec
CAN_RxD_perm_rec
LIN_perm_rec
LIN_TxD_perm_dom
LIN_perm_dom
Wake_Timer_int
Wake_LIN
2nd data byte
Wake_CAN
WU1_wake
WU2_wake
WU3_wake
WU1_state
Function
WU2_state
1st data byte
WU3_state
6.2.24
ST SPI
Diagnosis 4
Table 138. Status register 2, bits
Bit
Name
15
WU3_state
14
WU2_state
13
WU1_state
12
WU3_wake
11
WU2_wake
10
WU1_wake
9
WAKE_CAN
8
WAKE_LIN
7
Wake_TIMER_int
Comment
Information storage
State of WUx input;
“Live bits” not clearable
Shows wake up source (‘1’ = wake-up)
Bits are latched until a “Read
and clear” access
Doc ID 023553 Rev 3
119/128
ST SPI
L99PM72PXP
Table 138. Status register 2, bits (continued)
6.2.25
Bit
Name
Comment
Information storage
6
LIN_perm_DOM
5
LIN_TxD_perm_DOM
TxDL pin is dominant for t > 12 ms;
Transmitter is disabled
4
LIN_perm_REC
LIN bus does not follow TxDL within
40 µs; Transmitter is disabled
3
CAN_RxD_perm_rec
2
CAN_perm_REC
CAN has not followed TxDC for 4 times;
Transmitter is disabled
1
CAN_perm_DOM
CAN bus is dominant for t > 700 µs
0
CAN_TxD_perm_DOM
TxDC pin is dominant for t > 700 µs;
Transmitter is disabled
LIN bus is dominant for t > 12 ms
Bits are latched until a “Read
and clear” access
RxDC has not followed TxDC for 4
times; Transmitter is disabled
Status Register 3
Table 139. Status register 3: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
0
1
0
0
1
1
Table 140. Control register 3, data bytes
Group
Diagnosis 5
WD_timer_state_0
WD_timer_state_1
Forced_sleep_TSD2_SHTV1
Forced_sleep_WD
WD_fail_0
WD_fail_1
WD_fail_2
WD_fail_3
V1_restart_0
2nd data byte
V1_restart_1
V1_restart_2
V1_fail
Device_state_0
TW
Device_state_1
Function
TSD1
1st data byte
Diagnosis 6
Table 141. Status register 3, bits
120/128
Bit
Name
15
TSD1
14
TW
Comment
Thermal warning / shutdown1 occurred since last
readout
Doc ID 023553 Rev 3
Information
storage
Bit is latched until a
“read and clear
access”
L99PM72PXP
ST SPI
Table 141. Status register 3, bits (continued)
Bit
Name
13
Information
storage
Comment
State from which the device woke up
12
Device_state
State from
which the
device woke
up
Device state_2
Device state_1
0
0
Active
0
1
V1_standby
1
0
VBat_standby
1
1
Flash
Bit is latched until a
V1 fail (V1 < 2 V for t > 2 µs) event occurred since last
“read and clear
read out
access”
11
V1_fail
10
V1_restart_2
9
V1_restart_1
8
V1_restart_0
7
WD_fail_3
6
WD_fail_2
5
WD_fail_1
4
WD_fail_0
3
Forced_sleep_WD
Device was forced to VBat_standby mode because of
multiple watchdog errors
2
Forced_sleep_
TSD2_SHTV1
Device was forced to VBat_standby or multiple thermal
shutdown events or a short on V1 during startup.
1
0
Bit is latched until a
“read and clear
access” after a
“read and clear
access”, the device
state is updated.
After a wake up,
device state is:
01: V1_standby
or
10: VBat_standby
Bits are not
clearable; is cleared
Number of TSD2 events which caused a restart of V1
automatically if no
regulator (7 TSD2 events forces the device into
additional TSD2
VBat_standby)
event occurs within
1 min.
Number of missing watchdog triggers (15 missing
watchdog trigger forces the device into VBat_standby)
Bits are not
clearable; is cleared
with a proper
Watchdog trigger
Bits are latched until
a read and clear
access
WD_timer_state_1 Status of watchdog counter of selected watchdog
WD_timer_state_0 timing
WD_timer_state WD_timer_state
_1
_0
Counter
0
0
0 – 33%
0
1
33 – 66%
1
1
66 – 100%
Doc ID 023553 Rev 3
Bits are not
clearable
121/128
ST SPI
6.2.26
L99PM72PXP
Status Register 4
Table 142. Status register 4: command and data bytes
Command byte
Read/write
x
x
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
0
1
0
1
0
0
Table 143. Control register 4, data bytes
Group
Diagnosis 5
FD_ERR
CAN_ silent
WUF
WUP
CAN_TO
TX_ SYNC
SYS_ERR
SWRD_7
SWRD_8
2nd data byte
SWRD_9
SWRD_10
SWRD_11
SWRD_12
SWRD_13
SWRD_14
Function
SWRD_15
1st data byte
Diagnosis 6
Table 144. Status register 4, bits
Bit
Name
15
SWRD_15
14
SWRD_14
13
9
SWRD_13 Status flag for Read operation to Selective Wakeup
SWRD_12 relevant Registers
0: Read not done
SWRD_11
1: Read done
SWRD_10 See also Section 2.10: Serial Peripheral Interface (ST
SWRD_9 SPI Standard 3.0)
8
SWRD_8
7
SWRD_7
6
This bit is a logical OR combination of
NOT(SWRD_x) OR OSC_Fail OR FD_ERR
SYS_ERR The selective wake feature cannot be enabled
(SW_EN = 1) if SYS_ERR = 1
In case of a SYS_ERR the selective wake-up feature is
disabled (SW_EN = 0)
Live bit be updated
while the change of
SWRD_x, OSC_Fail
and FD_ERR.
If SWRD_x are all 1,
OSC_Fail is 0 and
FD_ERR is 0, this bit is
0, otherwise this bit is 1.
5
Status flag for Synchronous Reference oscillator of the
Transceiver. Indicates that the last received frame was
TX_SYNC decoded correctly
0: Not synchron
1: Synchron
Live bit updated after
each sent CAN frame
12
11
10
122/128
Comment
Doc ID 023553 Rev 3
Information storage
Automatically cleared
by a write
L99PM72PXP
ST SPI
Table 144. Status register 4, bits (continued)
Bit
Name
Comment
Information storage
CAN timeout, bit is set if there is no communication on
the bus for longer than tsilence
Vbat_standby Mode: CAN_TO indicates that there was a
transition from PN_TRX_selective_sleep to TRX_SLEEP Bit is latched until a
read and clear access
During TRX_STBY Mode (CAN_ACT = 0, Active Mode
and V1_standby Mode) this bit indicates a CAN
communication timeout. An interrupt on RxDC/NINT is
generated in this case.
4
CAN_TO
3
WUP
Wake up flag for Remote Wake up pattern
Bit is latched until a
read and clear access
2
WUF
Wake up flag for Remote Wake up Frame
Bit is latched until a
read and clear access
1
0
Online monitoring bit to see if there is silence on the bus
for longer than tsilence.
Auto cleared and set
CAN_Silent This flag shows the actual status of the CAN bus
(activity/silence). A microcontroller in Stop Mode may
check this flag periodically
FD_ERR
Frame Detect Error.
This bit is set at overflow of the Frame Error Counter
(FECNT) in SR5
In case of a Frame Detect Error, the device will wake up
from PN_Trx_selective_sleep
Doc ID 023553 Rev 3
Bit is latched until a
read and clear access
123/128
ST SPI
6.2.27
L99PM72PXP
Status Register 5
Table 145. Status register 5: command and data bytes
Command byte
Read/write
x
1st data byte
2nd data byte
Bit
Bit
Data, 8bit
Data, 8 bit
Address
x
0
1
0
1
0
1
Table 146. Control register 5, data bytes
Group
Diagnosis 5
Osc_mon
Osc_mon
Osc_mon
Osc_mon
Reserved
Osc_mon
OSC_FAIL
FECNT_0
2nd data byte
FECNT_1
FECNT_2
Reserved
FECNT_3
Function
FECNT_4
1st data byte
Diagnosis 6
Table 147. Status register 5, bits
Bit
Name
Comment
15
Reserved
14
Reserved
13
Reserved
12
FECNT_4
11
FECNT_3
10
FECNT_2
9
FECNT_1
8
FECNT_0
7
OSC_FAIL OSC Failure Flag (used device internally)
6
Reserved
5
Reserved
4-0
Osc_mon
Information storage
Must be kept at default
Frame Detect Error Counter
This counter is increased by 1 in case a frame was
not received/decoded correctly (CRC error, stuff-bit
error, form error).
Live bit updated after
The counter is decreased by 1 with every frame which each sent CAN frame
is decoded correctly
If FECNT = 31, the next erroneous frame will wakeup the device, set FDERR = 1 and reset FECNTx = 0
Bit is latched until a read
and clear access
Must be kept at default
124/128
Monitoring of internal oscillator (used internally)
Doc ID 023553 Rev 3
Live bit updated after
each sent CAN frame
L99PM72PXP
Package information
7
Package information
7.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.2
PowerSSO-36 mechanical data
Figure 44. PowerSSO-36 package dimensions
AG00066V1
Doc ID 023553 Rev 3
125/128
Package information
L99PM72PXP
Table 148. PowerSSO-36 mechanical data
Millimeters
Symbol
126/128
Min.
Typ.
Max.
A
-
-
2.45
A2
2.15
-
2.35
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D
10.10
-
10.50
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
-
2.3
-
G
-
-
0.1
G1
-
-
0.06
H
10.1
-
10.5
h
-
-
0.4
k
0°
-
8°
L
0.55
-
0.85
M
-
4.3
-
N
-
-
10 deg
O
-
1.2
-
Q
-
0.8
-
S
-
2.9
-
T
-
3.65
-
U
-
1.0
-
X
4.1
-
4.7
Y
6.5
-
7.1
Doc ID 023553 Rev 3
L99PM72PXP
8
Revision history
Revision history
Table 149. Document revision history
Date
Revision
Changes
16-Nov-2012
1
Initial release.
01-Feb-2013
2
Updated Section 2.2.2: Flash Mode and Section : Wake up from
TRX_SLEEP
Table 32: LIN transmitter and receiver: pin LIN:
– CLIN: added row
Table 33: LIN transceiver timing
– D2, D4: updated test condition
Table 123: Control register 16, data bytes:
– Sample_0, Sample_1, Sample_2: updated default values
Table 147: Status register 5, bits:
– OSC_FAIL: updated information storage
19-Sep-2013
3
Updated Disclaimer.
Doc ID 023553 Rev 3
127/128
L99PM72PXP
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