L99SD01-E

L99SD01-E Integrated solenoid driver for automotive applications Datasheet - production data Description The L99SD01-E is a device intended for driving inductive loads such as Compressed Natural Gas (CNG) injectors. The inputs are CMOS-compatible. The diagnostic outputs CLAMP_FLAG and FAULT provide an indication of demagnetization mode and fault conditions, respectively. *$3*&)7 PowerSSO-36 Features • Automotive qualified • Excitation switch S1 = 60 mΩ • Recirculation switch S2 = 60 mΩ • CMOS compatible inputs • Load current up to 14 A • Integrated clamp structure – Switch S1 clamp voltage = 45 V (minimum) • Current sense amplifier with internal sense resistor The integrated standard serial interface (I2C) allows to digitally set peak and hold current values and other injection parameters. It also provides detailed diagnostic information. The device should work with pre-programmed peak and hold current values when values are not set by external micro. All injection parameters can be changed during operating conditions and taken into account at the first injection rising edge after the end of communication. Diagnostic information is available in case of overcurrent, overtemperature, overvoltage and open-load. • S1 switch PWM operation above 10 KHz • I2C standard interface for mode control and enhanced diagnostic • Diagnostic output: – Open drain fault detection – Flag of clamp activation at the end of injection cycle • Input for voltage monitoring and feedback • Thermal shutdown and warning • Overcurrent shutdown and diagnostic • Undervoltage and overvoltage detection Table 1. Device summary • Open-load detection Order codes Package PowerSSO-36 December 2014 This is information on a product in full production. DocID022573 Rev 5 Tube Tape and reel L99SD01-E L99SD01TR-E 1/46 www.st.com Contents L99SD01-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Injection cycle description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Phase 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Phase 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 Phase 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Phase 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 Phase 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 I2C protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 2/46 4.1 SDA and SCL signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 Acknowledge (ACK) and Not Acknowledge (NACK) . . . . . . . . . . . . . . . . 19 4.6 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.9 Registers Addresses and Fault register . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.7 Register G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.8 Register H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.9 Fault register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID022573 Rev 5 L99SD01-E 6 Contents Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 OTP (One Time Programmable Memory) . . . . . . . . . . . . . . . . . . . . . . . 38 8 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.1 10 11 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Package and packing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.2 PowerSSO-36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DocID022573 Rev 5 3/46 3 List of tables L99SD01-E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. 4/46 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Diagnostic fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Registers addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 VBATT supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power switches S1 – S2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 S1 switching (excitation path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Switching (recirculating path) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 VDDL undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Input: SYNC_INJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Input: PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Inputs: E0, E1, E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IN_SIGNAL VOLTAGE MONITOR, CHECK_SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Differential current sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Current sense comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8-bit digital to analog converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 S1 protections and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Application registers range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 IPEAK, IHOLD (-40 °C < Tj < 150 °C, unless otherwise specified). . . . . . . . . . . . . . . . . . . 34 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I2C-bus SDA, SCL I/O stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I2C-bus SDA, SCL bus lines characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 16 bit OTP modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DocID022573 Rev 5 L99SD01-E List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Load configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Registers (default values) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 FSM (state machine) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Short to battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Soft short to battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Open-load diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Connection of I2C-devices to I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 START and STOP conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data transfer on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Complete data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 The first byte after the START procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 WRITE command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current READ command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Random READ command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Fault Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Definition of timing on the I²C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . . 41 PowerSSO-36 thermal impedance junction ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thermal fitting model of a HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 DocID022573 Rev 5 5/46 5 6/46 DocID022573 Rev 5 FAULT PWM SYNC_INJ E0 E1 E2 SDA SCL MAINT_IPK BG Ref 4usec filter CMD_S1 TERMICA CLAMP_FLAG DPOLY VBE from Power - POR ov uv BLANKING TIME 10usec window OC will be treated by logic only during Ipeak –> "01" OL_detect SGND D2AMUX REF REF_OC=FS_DAC_REF COMP + - - + - + REF_OL=1/4*REF 01 => IPEAK 10 => IHOLD 11 => IHOLDTEMP clamp CMD_S2 CMD_S1 VDDL(5V) C3V3 PWMoff FSM-REGISTERS-OTP ot ANALOG CONTROL X1/2 BATT CTANK LOW OFFSET PREAMP - A0 + LOW SIDE DRIVER CLAMP CLAMP FLOATING DRIVER CHARGE PUMP KGND KSENSE CPUMP2 CPUMP1 PGND REC S1 S2 OUT 1 CHECK_SIGNAL IN_SIGNAL + ENABLE Block diagram and pin description L99SD01-E Block diagram and pin description Figure 1. Block diagram L99SD01-E Block diagram and pin description Table 2. Pin description Pin number Pin name 1 OTP_15V 2 IN_SIGNAL 3 Description Power supply for OTP test purposes. Not connected. This pin is used to acquire (through an external resistor) the signal coming from the Main ECU The voltage on the “IN_SIGNAL” pin is compared with VBATT/2: CHECK_SIGNAL IF IN_SIGNAL > Vbatt/2 then CHECK_SIGNAL = H IF IN_SIGNAL 8 V Table 23. Charge pump Symbol Parameter Test conditions Typ Max Unit VBATT +7 VBATT +9 VBATT + 13 V VCP Charge pump output voltage(1) CPUMP1 External charge pump capacitor 4.7 nF CPUMP2 External charge pump capacitor 4.7 nF CTANK External charge pump capacitor for S2 driver peak current 100 nF ICP = 200 µA ICP1 Charge pump output current positive VBATT + 7 V < VCTAK < VBATT + 13 V test mode 15 27 34 mA ICP2 Charge pump output current negative VBATT + 7 V < VCTAK < VBATT + 13 V test mode -140 -100 -55 mA 1. Guaranteed by design using suggested external network: CPUMP1, CPUMP2: 4.7 nF - 50 V ceramic capacitors; CTANK: 100 nF - 50 V ceramic capacitor; Charge pump diodes: BAT41 type 34/46 Min DocID022573 Rev 5 L99SD01-E Electrical specification Table 24. I2C-bus SDA, SCL I/O stages Symbol Parameter Test conditions Min Typ Max Unit — 0.3 * VC3V3 V VIL Low level input voltage VIH High level input voltage 0.7 * VC3V3 — V VHYS Hysteresis of Schmitt trigger inputs 0.05 * VC3V3 — V VOL Low level output voltage ISINK = 3 mA IOL Low level output current VOL = 0.4 V tOFF Output fall time from VIHmim to VILmax — 250 ns tSP Pulse width of spikes that must be suppressed by the input filter — 50 ns — 10 µA — 10 pF Max Unit Ii Input current Ci I/O pin capacitance 0.1 * VDDL < VI < 0.9 * VDDL — 3 0.4 — -10 V mA Table 25. I2C-bus SDA, SCL bus lines characteristics Symbol Parameter Test conditions Min Typ All values are referred to VIH(min) (0.3 * VDDL) and VIL(max) (0.7 * VDDL). See also Figure 20. fSCL SCL clock frequency — tHD;STA Hold time (repeated) START condition tLOW tHIGH After this period the first clock pulse is generated 100 kHz 4.0 — µs LOW period of the SCL clock 4.7 — µs HIGH period of the SCL clock 4.0 — µs tSU;STA Set-up time for a repeated START condition 4.7 — µs tHD;DAT Data hold time(1) 300(2) — tSU;DAT Data set-up time 250 — (3) ns ns tr Rise time of both SDA and SCL signals — 1000 ns tf Fall time of both SDA and SCL signals — 300 ns tSU;STO tBUF Set-up time for a STOP condition 4.0 — µs Bus free time between a STOP and START condition 4.7 — µs DocID022573 Rev 5 35/46 45 Electrical specification L99SD01-E Table 25. I2C-bus SDA, SCL bus lines characteristics Symbol Parameter Cb Test conditions Min Typ Max Unit Capacitive load for each bus line — 400 pF tVD;DAT Data valid time(4) — 3.45(3) µs tVD;ACK Data valid acknowledge time(5) — 3.45(3) µs VnL Noise margin at the LOW level For each connected device (including hysteresis) 0.1 * VDDL — V VnH Noise margin at the HIGH level For each connected device (including hysteresis) 0.2 * VDDL — V 1. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge. 2. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 3. The maximum tHD;DAT could be 3.45 us, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. 4. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse) 5. tVD;ACK = time for acknowledgment signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse) Figure 20. Definition of timing on the I²C-bus 36/46 DocID022573 Rev 5 L99SD01-E Electrical specification Table 26. Electrical transient requirements (part 1) ISO 7637-2: 2004(E) Test levels(1) Number of pulses or test times Burst cycle/pulse repetition time Delays and impedance Test Pulse III IV 1 -75 V -100 V 5000 pulses 0.5 s 5s 2 ms, 10 Ω 2a +37 V +50 V 5000 pulses 0.2 s 5s 50 μs, 2 Ω 3a -100 V -150 V 1h 90 ms 100 ms 0.1 μs, 50 Ω 3b +75 V +100 V 1h 90 ms 100 ms 0.1 μs, 50 Ω 4 -6 V -7 V 1 pulse 100 ms, 0.01 Ω 5b(2) +65 V +87 V 1 pulse 400 ms, 2 Ω 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to OUT. Table 27. Electrical transient requirements (part 2) Test level results(1) ISO 7637-2: 2004(E) test pulse III IV 1 C E 2a C C 3a C C 3b C C 4 C C 5b (2) C C 1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to OUT. Table 28. Electrical transient requirements (part 3) Class Contents C All functions of the device are performed as designed after exposure to disturbance. E One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the DocID022573 Rev 5 37/46 45 OTP (One Time Programmable Memory) 7 L99SD01-E OTP (One Time Programmable Memory) L99SD01-E provides two 16 bit OTP modules for internal parameter trimming. Default application parameters are hard coded into the device. OTP use is reserved to ST and other access will be hardware forbidden. Table 29. 16 bit OTP modules Bit 15 OTP_0 OTP_1 38/46 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Osc trimming Reference slope Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Current reference trimming Blanking DocID022573 Rev 5 Bit 4 Bit 3 Bit 2 Bit 1 Bandgap trimming IHOLD current trimming Bit 0 L99SD01-E 8 Application schematic Application schematic Figure 21. Application schematic OUT Gas Injector REC PGND REC PGND REC PGND REC PGND TEST_OUT2 SGND TEST_OUT1 BATT Module Battery TEST_OUT3 TEST 4.7nF CPUMP1 100nF ENABLE 4.7nF CPUMP2 SYNC_INJ 10uF 5V CTANK PWM VDDL FAULT C3V3 SCL SGND SDA 5V 5V 5V xxuF To mC xxuF SGND/VDDL E0 CLAMP_FLAG SGND/VDDL E1 MAINT_IPK SGND/VDDL E2 CHECK_SIGNAL SGND 5V IN_SIGNAL OTP_0V OTP_15V DocID022573 Rev 5 39/46 45 Package and PCB thermal data L99SD01-E 9 Package and PCB thermal data 9.1 PowerSSO-36 thermal data Figure 22. PowerSSO-36 PC board GAPGCFT01130 1. Board finish thickness 1.6 mm +/- 10%; Board double layer; Board dimension 129 mm x 60 mm; Board Material FR4; Cu thickness 0.070 mm; Thermal vias separation 1.2 mm; Thermal via diameter 0.3 mm +/-0.08 mm; Cu thickness on vias 0.025 mm; Footprint dimension 4.1 mm x 6.5 mm. 40/46 DocID022573 Rev 5 L99SD01-E Package and PCB thermal data Figure 23. Rthj-amb vs PCB copper area in open box free air condition 57+MDPE  57+MDPE              ("1($'5 Figure 24. PowerSSO-36 thermal impedance junction ambient =7+ƒ&:  &X FP &X FP &X IRRWSULQW         7LPHV ("1($'5 DocID022573 Rev 5 41/46 45 Package and PCB thermal data L99SD01-E Figure 25. Thermal fitting model of a HSD in PowerSSO-36 ("1($'5 Table 30. Thermal parameters Area/island 42/46 (cm2) FP 2 8 R1 = R7 (°C/W) 0.8 R2 = R8 (°C/W) 1.2 R3 (°C/W) 5 R4 (°C/W) 8 R5 (°C/W) 18 15 10 R6 (°C/W) 27 23 14 C1 = C7 (W·s/°C) 0.0005 C2 = C8 (W·s/°C) 0.002 C3 (W·s/°C) 0.03 C4 (W·s/°C) 0.5 C5 (W·s/°C) 1 1.5 3 C6 (W·s/°C) 3 5 9 DocID022573 Rev 5 L99SD01-E Package and packing Information 10 Package and packing Information 10.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10.2 PowerSSO-36 package information Figure 26. PowerSSO-36 package dimensions AG00066V1 Table 31. PowerSSO-36 mechanical data Millimeters Symbol Min Typ. Max A 2.15 2.47 A2 2.15 2.40 a1 0 0.1 b 0.18 0.36 DocID022573 Rev 5 43/46 45 Package and packing Information L99SD01-E Table 31. PowerSSO-36 mechanical data Millimeters Symbol Min Typ. Max c 0.23 0.32 D(1) 10.10 10.50 E 7.4 7.6 e 0.5 e3 8.5 F 2.3 G 0.1 G1 0.06 H 10.1 10.5 h 0.4 k 0° 8° L 0.55 0.90 M 4.3 N 10° O 1.2 Q 0.8 S 2.9 T 3.65 U 1 X 4.1 4.7 Y 6.5 7.1 1. “D” and “E“ do not include mold Flash or protrusions. Mold Flash or protrusion shall not exceed 0.15 mm per side (0.006”). 44/46 DocID022573 Rev 5 L99SD01-E 11 Revision history Revision history Table 32. Document revision history Date Revision Changes 05-Dec-2011 1 Initial release 12-Sep-2013 2 Table 2: Pin description: – SCL: updated description Updated Section 4.1: SDA and SCL signals Added Chapter 5: Register description Table 5: Absolute maximum rating: – ILOAD, IR(LOAD): updated value – EC: deleted rows – EAS, EREP1, EREP2: added rows Updated Table 6: Thermal data Table 18: Current sense comparator: – VIOFF_PWMCOMP: updated min value Table 20: S1 protections and diagnostic: – IOL: added test condition and values Table 22: IPEAK, IHOLD (-40 °C < Tj < 150 °C, unless otherwise specified): – IPEAK, IHOLD: added test condition and values Table 23: Charge pump: – added note – ICP1, ICP2: added rows Table 24: I2C-bus SDA, SCL I/O stages: – IOL: removed test condition – tOFF: updated parameter, removed test condition and min value Table 25: I2C-bus SDA, SCL bus lines characteristics: – fSCL, tHD;STA, tLOW, tHIGH, tSU;STA, tHD;DAT, tSU;DAT, tr, tf, tSU;STO, tBUF, Cb, tVD;DAT, tVD;ACK: updated values Added Table 26: Electrical transient requirements (part 1), Table 27: Electrical transient requirements (part 2) and Table 28: Electrical transient requirements (part 3) Added Chapter 9: Package and PCB thermal data 18-Sep-2013 3 Updated disclaimer. 11-Apr-2014 4 Updated document title. 18-Dec-2014 5 Updated document title, Features and Description. DocID022573 Rev 5 45/46 45 L99SD01-E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved 46/46 DocID022573 Rev 5