LD39080PT25-R

LD39080 Ultra low drop BiCMOS voltage regulator Datasheet - production data Applications  Microprocessor power supply  DSP power supply  Post regulators for switching suppliers  High efficiency linear regulator Description PPAK The LD39080 is a fast, ultra low drop linear regulator which operates from 2.5 V to 6 V input supply. Features  0.8 A guaranteed output current  Ultra low-dropout voltage (150 mV typ. @ 0.8 A load, 20 mV typ. @150 mA load) A wide range of output options is available. The low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessors and memory applications. The device is developed on the BiCMOS process which allows the low quiescent current operation regardless of the output load current.  Very low quiescent current (1 mA typ. @ 0.8 A load, 1 µA max.@ 25 °C in off mode)  Logic-controlled electronic shutdown  Current and thermal internal limit  1.5% output voltage tolerance @ 25 °C Table 1. Device summary PPAK (tape and reel) Output voltage LD39080PT-R ADJ from 1.22 to 5.0 V  ADJ output voltage: 1.22 V to 5.0 V  Temperature range: - 40 to 125 °C  Fast dynamic response to line and load changes  Stable with ceramic capacitor  Available in PPAK August 2017 This is information on a product in full production. DocID13158 Rev 3 1/18 www.st.com Contents LD39080 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.1 External capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 DocID13158 Rev 3 LD39080 1 Diagram Diagram Figure 1. Block diagram (*) Not present on ADJ version. DocID13158 Rev 3 3/18 18 Pin configuration 2 LD39080 Pin configuration Figure 2. Pin connections (top view) PPAK Table 2. Pin description 4/18 Pin Symbol Note 5 ADJ 2 VI LDO input voltage: VI from 2.5 V to 6 V, CI=1 µF not farther than 1 cm from input pin 4 VO LDO output voltage pins, with minimum CO = 2.2 µF needed for stability (refer to CO vs ESR stability chart) 1 VINH Inhibit input voltage: on mode when VINH  2 V, off mode when VINH  0.3 V (do not leave it floating, not internally pulled down/up) 3 GND Common ground Error amplifier input pin for VO from 1.22 to 5.0 V DocID13158 Rev 3 LD39080 3 Typical application circuits Typical application circuits (CI and CO capacitors have to be placed as closer as possible to the IC pin). Figure 3. LD39080 adjustable version VO = VREF (1 + R1/R2) Note: Set R2 as closer as possible to 4.7 K Figure 4. Timing diagram DocID13158 Rev 3 5/18 18 Maximum ratings 4 LD39080 Maximum ratings Table 3. Absolute maximum ratings Symbol Value Unit -0.3 to 6.5 V Inhibit input voltage -0.3 to VI +0.3 (6.5 V max.) V DC output voltage -0.3 to VI +0.3 (6.5 V max.) V VADJ ADJ pin voltage -0.3 to VI +0.3 (6.5 V max.) V IO Output current Internally limited mA PD Power dissipation Internally limited mW VI VINH VO Note: Parameter DC input voltage TSTG Storage temperature range -50 to 150 °C TOP Operating junction temperature range -40 to 125 °C Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Table 4. Thermal data Symbol 6/18 Parameter RthJA Thermal resistance junction-ambient RthJC Thermal resistance junction-case DocID13158 Rev 3 Value Unit 100 °C/W 8 °C/W LD39080 5 Electrical characteristics Electrical characteristics TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = 2 V, unless otherwise specified. Table 5. Electrical characteristics Symbol VI Parameter Conditions Operating input voltage VI = VO+1 V, ILOAD = 10 mA to 0.8 A VO VREF VO Output voltage tolerance IQ Max. Unit 2.5 6 V -1.5 1.5 -3 3 Reference voltage Typ. % of VO(NOM) 1.22 V VI = VO+1 V to 6 V 0.04 % Output voltage line regulation VI = VO+1 V to 6 V, TJ = -40 to 125 °C 0.1 Output voltage load VO/ILOAD regulation VDROP VI = VO+1 V to 6 V, ILOAD = 10 mA to 0.8 A TJ = -40 to 125 °C Min. Dropout voltage (VI - VO) 0.2 ILOAD = 10 mA to 0.8 A 0.06 ILOAD = 10 mA to 0.8 A, TJ = -40 to 125 °C 0.2 0.4 ILOAD = 150 mA, TJ=-40 to 125 °C 20 40 ILOAD = 0.8 A, TJ = -40 to 125 °C 150 300 1 2.5 % %/A mV Quiescent current: on mode ILOAD = 10 mA to 0.8 A, VINH = 2 V TJ = -40 to 125 °C Quiescent current: off mode VINH = 0.3 V 1 VINH = 0.3 V, TJ = -40 to 125 °C 5 mA µA Short-circuit protection ISC Short-circuit protection RL = 0 1.6 Inhibit threshold low Inhibit threshold high VI = 2.5 to 6 V off TJ = -40 to 125 °C TD-OFF Current limit ILOAD = 0.8 A, VO = 3.3 V 15 TD-ON Current limit ILOAD = 0.8 A, VO = 3.3 V 15 Inhibit input current (1) VI = 6 V, VINH = 0 to 6 V 0.1 A Inhibit Input VINH IINH 0.3 V 2 µs 1 µA AC parameters SVR Supply voltage rejection VI = 4.5  1 V, VO = 3.3 V, ILOAD = 10 mA, f = 120 Hz 65 f = 1 kHz 55 dB DocID13158 Rev 3 7/18 18 Electrical characteristics LD39080 Table 5. Electrical characteristics (continued) Symbol eN TSHDN Parameter Conditions Output noise voltage BW = 10 Hz to 100 kHz, CO = 2.2 µF, VO = 2.5 V Typ. 100 Thermal shutdown off 170 Hysteresis 10 Max. Unit µVRMS °C 1. Guaranteed by design. 8/18 Min. DocID13158 Rev 3 LD39080 6 Typical performance characteristics Typical performance characteristics TJ = 25 °C, VI = VO+1 V, CI = 1 µF, CO = 2.2 µF, ILOAD = 10 mA, VINH = VI, unless otherwise specified. Figure 5. Output voltage vs temperature Figure 6. Dropout voltage vs temperature Figure 7. Dropout voltage vs output current Figure 8. Quiescent current vs output current DocID13158 Rev 3 9/18 18 Typical performance characteristics LD39080 Figure 9. Quiescent current vs supply voltage Figure 10. Off-state current vs temperature Figure 11. Quiescent current vs temperature Figure 12. Short-circuit current vs temperature Figure 13. Output voltage vs input voltage Figure 14. Supply voltage rejection vs temperature 10/18 DocID13158 Rev 3 LD39080 Typical performance characteristics Figure 15. Stability region vs CO and ESR (at 100 kHz) Figure 16. Stability region vs CO and low ESR (at 100 kHz) Figure 17. Load transient Figure 18. Line transient DocID13158 Rev 3 11/18 18 Application notes 7 Application notes 7.1 External capacitor LD39080 The LD39080 requires external capacitors to assure the stability. These capacitors have to meet the requirements of minimum capacitance and equivalent series resistance (see Figure 16 Figure 17). The input/output capacitors cannot be farther than 1 cm from the relative pins and have to be connected directly to the input/output ground pins using traces without any current flowing through them. Ceramic or electrolytic capacitors can be used. 7.2 Input capacitor An input capacitor, whose minimum value is 1 µF, is required (the amount of capacitance can be increased without any limit). This capacitor cannot be farther than 1 cm from the input pin of the device and has to return to clean analog ground. Ceramic, tantalum or film capacitors can be used. 7.3 Output capacitor Ceramic or tantalum capacitors can be used but the output capacitor has to meet the requirements of minimum capacitance and ESR (equivalent series resistance) value. A minimum capacitance of 2.2 µF is a good choice to guarantee the stability of the regulator. Anyway, other CO values can be used as per Figure 16 Figure 17, where the allowable ESR range is seen as a function of the output capacitance. The curve represents the stability region over the full temperature and IO range. 7.4 Thermal note The output capacitor has to maintain its ESR in the stable region over the operating temperature range to assure the stability. Besides, capacitor tolerance and temperature variation have to be taken into account to assure the minimum amount of capacitance all time. 7.5 Inhibit input operation The inhibit pin can be used to turn off the regulator when pulled down, therefore by reducing the current consumption below 1 µA. When the inhibit feature is not used, this pin has to be tied to VI to turn on the regulator output all the time. To assure the right operation, the signal source, used to drive the inhibit pin, has to swing above and below the specified thresholds listed in Section 5: Electrical characteristics (VIH VIL). The inhibit pin must not be left floating because it is not internally pulled down/up. 12/18 DocID13158 Rev 3 LD39080 8 Package mechanical data Package mechanical data Figure 19. PPAK drawings 0078180_F DocID13158 Rev 3 13/18 18 Package mechanical data LD39080 Table 6. PPAK mechanical data mm Dim. Min. Max. A 2.2 2.4 A1 0.9 1.1 A2 0.03 0.23 B 0.4 0.6 B2 5.2 5.4 C 0.45 0.6 C2 0.48 0.6 D 6 6.2 D1 E 5.1 6.4 E1 6.6 4.7 e 1.27 G 4.9 5.25 G1 2.38 2.7 H 9.35 10.1 L2 0.8 L4 0.6 L5 1 L6 1 1 2.8 R V2 14/18 Typ. 0.20 0° DocID13158 Rev 3 8° LD39080 9 Packaging mechanical data Packaging mechanical data Figure 20. PPAK tape 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DocID13158 Rev 3 15/18 18 Packaging mechanical data LD39080 Figure 21. PPAK reel T REEL DIMENSIONS 40mm min. Access hole At slot location B D C N A Full radius G measured at hub Tape slot in core for tape start 25 mm min. width AM08851v2 Table 7. PPAK tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 16/18 Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID13158 Rev 3 18.4 22.4 LD39080 10 Revision history Revision history Table 8. Document revision history Date Revision Changes 26-Jan-2007 1 Initial release. 25-Mar-2014 2 Updated features in cover page, Section 5: Electrical characteristics, Section 6: Typical performance characteristics, Section 7: Application notes, Section 8: Package mechanical data. Added Section 9: Packaging mechanical data. Minor text changes. 01-Aug-2017 3 Updated Table 1: Device summary on the cover page. DocID13158 Rev 3 17/18 18 LD39080 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 18/18 DocID13158 Rev 3