LD39100XX12

LD39100XX LD39100XX12, LD39100XX25 1 A, low quiescent current, low noise voltage regulator Preliminary data Features ■ ■ ■ Input voltage from 1.5 to 5.5 V Ultra low dropout voltage (200 mV typ. at 1 A load) Very low quiescent current (20 µA typ. at no load, 200 µA typ. at 1 A load, 1 µA max in off mode) Very low noise with no bypass capacitor (30 µVRMS at VOUT = 0.8 V) Output voltage tolerance: ± 2.0 % @ 25 °C 1 A guaranteed output current Wide range of output voltages available on request: 0.8 V to 4.5 V with 100 mV step and adjustable from 0.8 V Logic-controlled electronic shutdown Stabilized with ceramic capacitors COUT = 1 µF Internal current and thermal limit DFN6 (3 x 3 mm) package Temperature range: - 40 °C to 125 °C An enable logic control function puts the LD39100xx in shutdown mode, allowing a total current consumption lower than 1 µA. The device also includes short-circuit constant current limiting and thermal protection. Typical applications are printers, personal digital assistants (PDAs), cordless phones and consumer applications. DFN6 (3 x 3 mm) ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The LD39100xx provides 1 A maximum current from an input voltage ranging from 1.5 V to 5.5 V with a typical dropout voltage of 200 mV. The deveice is stable due to the use of ceramic capacitors on the input and output. The ultra low drop-voltage, low quiescent current and low noise features make it suitable for low power battery powered applications. Power supply rejection is 65 dB at low frequencies and starts to roll off at 10 kHz. Table 1. Device summary Part numbers LD39100XX LD39100XX12 LD39100XX25 Order codes LD39100PUR LD39100PU12R LD39100PU25R Output voltages Adj. from 0.8 V 1.2 V 2.5 V April 2010 Doc ID 15676 Rev 2 1/24 www.st.com 24 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents LD39100XX, LD39100XX12, LD39100XX25 Contents 1 2 3 4 5 6 Circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 6.2 6.3 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power Good function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Different output voltage versions of the LD39100xx available on request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 2/24 Doc ID 15676 Rev 2 LD39100XX, LD39100XX12, LD39100XX25 Circuit schematics 1 Figure 1. Circuit schematics Schematic diagram for the LD39100PU IN Power-good signal IN PG BandGap reference OpAmp Current Current limit Thermal protection OUT ADJ EN Internal enable GND Figure 2. Schematic diagram for the LD39100PUxx IN Power-good signal IN PG BandGap reference OpAmp Current Current limit Thermal protection R1 NC OUT EN Internal enable R2 GND Doc ID 15676 Rev 2 3/24 Pin configuration LD39100XX, LD39100XX12, LD39100XX25 2 Figure 3. Pin configuration Pin connection (top view) EN VIN NC VOUT EN VIN ADJ VOUT GND PG GND PG LD39100PUxx LD39100PU Table 2. Symbol Pin description Pin n° Function LD39100PU LD39100PUxx 1 2 3 4 6 5 EXP pad Enable pin logic input: Low = shutdown, High = active Common ground Power Good Output voltage Adjust pin Input voltage of the LDO Not connected Exposed pad must be connected to GND 1 2 3 4 5 6 - EN GND PG VOUT ADJ VIN NC GND 4/24 Doc ID 15676 Rev 2 LD39100XX, LD39100XX12, LD39100XX25 Maximum ratings 3 Table 3. Symbol VIN VOUT EN PG ADJ IOUT PD TSTG TOP Maximum ratings Absolute maximum ratings Parameter DC input voltage DC output voltage Enable pin Power Good pin Adjust pin Output current Power dissipation Storage temperature range Operating junction temperature range Value -0.3 to 7 -0.3 to VIN + 0.3 (7 V max) -0.3 to VIN + 0.3 (7 V max) -0.3 to 7 4 Internally limited Internally limited - 65 to 150 - 40 to 125 °C °C Unit V V V V V Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Thermal data Parameter Thermal resistance junction-ambient Thermal resistance junction-case Value 55 10 Unit °C/W °C/W Table 4. Symbol RthJA RthJC Table 5. Symbol ESD ESD performance Parameter ESD protection voltage MM 0.4 kV Test conditions HBM Value 4 Unit kV Doc ID 15676 Rev 2 5/24 Electrical characteristics LD39100XX, LD39100XX12, LD39100XX25 4 Electrical characteristics TJ = 25 °C, VIN = 1.8 V, CIN = COUT = 1 µF, IOUT = 100 mA, VEN = VIN, unless otherwise specified. Table 6. Symbol VIN VADJ IADJ ΔVOUT ΔVOUT ΔVOUT ΔVOUT Electrical characteristics for the LD39100PU Parameter Operating input voltage VADJ accuracy Adjust pin current Static line regulation Transient line regulation (1) Static load regulation Transient load regulation (1) VOUT+1 V ≤ VIN ≤ 5.5 V, IOUT=100mA ΔVIN=500mV, IOUT=100mA, tR=5µs ΔVIN=500mV, IOUT=100mA, tF=5µs IOUT=10mA to 1A IOUT=10mA to 1A, tR=5µs IOUT=1A to 10mA, tF=5µs IOUT=1A, VO fixed to 1.5V 40°C