LDLN025PU275R

LDLN025 Datasheet 250 mA ultra low noise LDO Features DFN4-1x1 Flip-Chip4 SOT23-5L • Ultra low output noise: 6.5 μVRMS • • • • Operating input voltage range: 1.5 V to 5.5 V Output current up to 250 mA Very low quiescent current: 12 μA at no-load Controlled Iq in dropout condition • • • • • • • • • • Very low-dropout voltage: 250 mV at 250 mA Very high PSRR: 80 dB@100 Hz, 60 dB @ 100 kHz Output voltage accuracy: 2% across line, load and temperature Output voltage versions: from 1 V to 5 V, with 50 mV step Logic-controlled electronic shutdown Output discharge feature Internal soft-start Overcurrent and thermal protections Temperature range: from -40 °C to +125 °C Packages: Flip-Chip4, DFN4-1x1, SOT23-5L Applications Maturity status link LDLN025 • • • • Smartphones/tablets Image sensors Instrumentation VCO and RF modules Description The LDLN025 is a 250 mA low-dropout voltage regulator, able to work with an input voltage range from 1.5 V to 5.5 V. The typical dropout voltage at 250 mA load is 120 mV. The very low quiescent current, which is just 12 μA at no-load, extends battery-life of applications requiring very long standby time. Thanks to its ultra low noise value and high PSRR, the LDLN025 provides a very clean output, suitable for ultra-sensitive loads. It is stable with ceramic capacitors. The enable logic control function puts the device into shutdown mode allowing a total current consumption lower than 1 μA. The device also includes short-circuit and thermal protection. Typical applications are noise sensitive loads such as ADC, VCO in mobile phones and tablets, wireless LAN devices. The LDLN025 is designed to keep the quiescent current under control and at a low value also during dropout operation, extending the operating time of battery-powered devices. Several small package options are available. DS11756 - Rev 8 - June 2021 For further information contact your local STMicroelectronics sales office. www.st.com LDLN025 Block diagram 1 Block diagram Figure 1. Block diagram VIN VOUT Bia s ge ne ra tor EN Ena ble The rma l prote ction Ba ndga p re fe re nce GND AMG280620171000MT DS11756 - Rev 8 page 2/27 LDLN025 Pin configuration 2 Pin configuration Figure 2. Pin configuration Table 1. Pin description Symbol DFN4-1x1 Flip-Chip4 SOT23-5L VIN 4 A1 1 LDO Supply voltage VOUT 1 A2 5 LDO Output voltage GND 2 B2 2 Ground 3 Enable input: set VEN = high to turn on the device; VEN = low to turn off the device EN 3 B1 Description This pin is internally pulled down via 1 MΩ resistor DS11756 - Rev 8 NC - - 4 Not internally connected: can be connected to GND Exposed pad Exposed pad - - Must be connected to GND page 3/27 LDLN025 Typical application diagram 3 Typical application diagram Figure 3. Typical application diagram VIN VI ON OFF EN LDLN025 C In 1µF VOUT VO GND C Out 1µF AMG010720161412MT DS11756 - Rev 8 page 4/27 LDLN025 Maximum ratings 4 Maximum ratings Table 2. Absolute maximum ratings Symbol VIN Parameter Input supply voltage Value Unit -0.3 to 7 V VOUT Output voltage -0.3 to VIN +0.3 V IOUT Output current Internally limited A EN Enable pin voltage -0.3 to VIN +0.3 V PD Power dissipation Internally limited W ESD Charge device model ±1000 Human body model ±2000 V TJ-OP Operating junction temperature -40 to 125 °C TJ-MAX Maximum junction temperature 150 °C -55 to 150 °C TSTG Storage temperature Table 3. Thermal data Symbol Rthja DS11756 - Rev 8 Parameter Thermal resistance, junction-toambient DFN4-1x1 Flip-Chip4 SOT23-5L Unit 220 210 200 °C/W page 5/27 LDLN025 Electrical characteristics 5 Electrical characteristics (TJ = 25 °C, VIN = VOUT(nom) + 1 V or 1.5 V, whichever is greater; VEN = 1.2 V; CIN = 1 μF; COUT = 1 μF; IOUT = 1 mA) Table 4. Electrical characteristics Symbol Parameter VIN Operating input voltage range Test conditions Min. Typ. Max. Unit 1.5 5.5 V -2.0 +2.0 VOUT + 1 V < VIN < 5.5 V, (1) 1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V, VOUT Output voltage accuracy (Flip-Chip package) -40 °C < TJ < 125 °C % VOUT + 1 V < VIN < 5.5 V,(1) 1 mA < IOUT < 0.25 A, VOUT < 1.8 V, -3.0 +3.0 -2.0 +2.0 -40 °C < TJ < 125 °C VOUT + 1 V < VIN < 5.5 V,(1) 1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V, VOUT Output voltage accuracy (DFN and SOT23 packages) -40 °C < TJ < 125 °C % VOUT + 1 V < VIN < 5.5 V,(1) 1 mA < IOUT < 0.25 A, VOUT < 1.8 V, -4.0 +4.0 -40 °C < TJ < 125 °C ∆VOUT/ ∆VIN Static line regulation Line transient (2) VOUT + 1 V < VIN < 5.5 V(1) 0.02 -40 °C < TJ < 125 °C ∆VIN = +/- 0.6 V, trise = tfall = 30 μs -1 1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V ∆VOUT/ ∆IOUT ∆VOUT VDROP eN SVR DS11756 - Rev 8 Static load regulation 0.002 0.007 1 mA < IOUT < 0.25 A, VOUT ˂ 1.8 V ∆IOUT = 1 mA to 250 mA and back, trise = tfall = 10 μs Overshoot on startup(2) Percentage of VOUT(nom) Dropout voltage(3) Output noise voltage (2) Supply voltage rejection(2) +1 -40 °C < TJ < 125 °C, VOUT ≥ 1.8 V Load transient(2) %/V 0.06 20 -40 mV %/mA mV +40 mV 5 % IOUT = 0.25 A, -40 °C < TJ < 125 °C (Flip-Chip4) 200 mV IOUT = 0.25 A, -40 °C < TJ < 125 °C (DFN4-1x1) 250 IOUT = 0.1 A 50 IOUT = 0.25 A 120 f = 10 Hz to 100 kHz; IOUT = 1 mA 10 f = 10 Hz to 100 kHz; IOUT = 250 mA 6.5 f = 100 Hz; IOUT = 20 mA 80 f = 1 kHz; IOUT = 20 mA 80 f = 10 kHz; IOUT = 20 mA 75 µVRMS dB page 6/27 LDLN025 Electrical characteristics Symbol Parameter Test conditions SVR Supply voltage rejection(2) f = 100 kHz; IOUT = 20 mA 60 IOUT = 0 A 12 IQ Quiescent current(4) Min. Typ. IOUT = 0 A; -40 °C < TJ < 125 °C 250 IOUT = 0.25 A; -40 °C < TJ < 125 °C VEN = 0 V ISC Short-circuit current VOUT = 0 V RLOW Output discharge resistance VEN = 0 V VIL, enable input logic low VEN VIH, enable input logic high IEN Enable pin input current tON TSHDN 425 0.2 250 Unit dB 25 IOUT = 0.25 A Shutdown current Max. 1 µA µA µA 500 mA 230 Ω 0.4 VOUT + 1 V < VIN < 5.5 V -40 °C < TJ < 125 °C(1) V 1.2 VIN = VEN = 5.5 V 5.5 VIN = 5.5 V; VEN = 0 V 0.001 Turn-on time(2) From VEN > VIH to VOUT = 95 % of VOUT(nom) 80 Thermal shutdown(2) IOUT > 1 mA 160 Hysteresis µA 150 µs °C 20 1. VIN = VOUT + 1 V or 1.5 V, whichever is greater. Not applicable for 5 V output voltage versions. 2. Guaranteed by design. 3. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. 4. The quiescent current is defined as IIN-IOUT and does not include the EN pin current. Table 5. Recommended input and output capacitors Symbol CIN DS11756 - Rev 8 Parameter Input capacitance COUT Output capacitance ESR Output/input capacitance Test conditions Stability Min. Typ. 0.7 1 0.7 1 5 Max. 10 500 Unit μF mΩ page 7/27 LDLN025 Typical characteristics 6 Typical characteristics (The following plots are referred to LDLN025J2925R in the typical application circuit and, unless otherwise noted, at TA = 25 °C). Figure 4. Output voltage vs. temperature (VIN = 3.925 V) Figure 5. Output voltage vs. temperature (VIN = 5.5 V) VIN = VOUT + 1 V, EN = 2 V, IOUT = from 0 to 250 mA, CIN = 1 μF , COUT = 1 μF VIN = 5.5 V; IOUT = from 0 to 250 mA, CIN = 1 μF, COUT = 1 μF 3 3 NO LOAD 2.98 IOUT 1mA IOUT 10mA IOUT 250mA 2.94 Output vo ltag e [V] Output vo ltag e [V] 2.96 2.92 2.9 2.88 2.86 2.98 NO LOAD 2.96 IOUT 1mA 2.94 IOUT 250mA 2.92 2.9 2.88 2.86 2.84 2.84 2.82 2.82 2.8 IOUT 10mA 2.8 -75 -50 -25 0 25 50 75 100 125 150 -75 -50 -25 Te mpe rature [°C] 0 25 50 75 AMG010720161030MT 125 150 AMG010720161031MT Figure 7. Line regulation vs. temperature Figure 6. Load regulation vs. temperature VIN = from 3.925 to 5.5 V, IOUT = 1 mA, CIN = 1 μF , COUT = 1 μF VIN = VOUT + 1 V; IOUT = from 1 mA to 0.25 A, CIN = 1 μF , COUT = 1 μF 0.500 0.020 0.400 Line re g ulatio n [%/V] 0.015 Lo ad re g ulatio n [%/mA] 100 Te mpe rature [°C] 0.010 0.005 0.000 -0.005 -0.010 0.300 0.200 0.100 0.000 -0.100 -0.200 -0.300 -0.015 -0.400 -0.020 -0.500 -75 -50 -25 0 25 50 75 100 125 150 Te mpe rature [°C] -50 -25 0 25 50 75 100 125 150 Te mpe rature [°C] AMG010720161032MT DS11756 - Rev 8 -75 AMG010720161033MT page 8/27 LDLN025 Typical characteristics Figure 8. Quiescent current vs. temperature (IOUT = 0 mA) Figure 9. Quiescent current vs. temperature (IOUT = 250 mA) VIN = VOUT + 1 V, VEN = 1.2 V, IOUT = 0 A, CIN = 1 μF , COUT = 1 μF VIN = VOUT + 1 V, VEN = 1.2 V, IOUT = 250 mA, CIN = 1 μF , COUT = 1 μF 24 400 22 375 350 18 Quiescent current [μA] Quiescent current [µA] 20 16 14 12 10 8 6 4 325 300 275 250 225 200 175 150 2 125 0 -75 -50 -25 0 25 50 75 100 125 100 150 -75 Te mpe rature [°C] -50 -25 25 50 75 100 125 150 AMG010720161035MT Figure 11. Off-state current vs. temperature Figure 10. GND current vs. input voltage VIN = VOUT + 1 V, IOUT = 0 A, CIN = 1 μF , COUT = 1 μF VIN = EN = from 0 to 6 V, IOUT = 0 A, CIN = 1 μF , COUT = 1 μF 26 24 22 20 18 16 14 12 10 8 6 4 2 0 10 Quiescent current [µA] GND current [μA] 0 Te mpe rature [°C] AMG010720161034MT 8 6 4 2 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 Input voltage [V] -75 -50 -25 0 25 50 75 100 125 150 Te mpe rature [°C] AMG010720161036MT Figure 12. Quiescent current vs. output current AMG010720161037MT Figure 13. Quiescent current vs. output current (zoom) VEN = 1.2 V, IOUT = from 0 to 250 mA, CIN = 1 μF , COUT = 1 μF Quiescent current [μA] 300 275 VIN=5.5V 250 VIN=3.9V 225 200 175 150 125 100 75 50 25 0 0 25 50 75 100 125 150 175 200 225 250 275 Output current [mA] AMG010720161038MT DS11756 - Rev 8 page 9/27 LDLN025 Typical characteristics Figure 15. Dropout voltage vs. load current Figure 14. Dropout voltage vs. temperature VOUT = 2.8 V, CIN = 1 μF , COUT = 1 μF VOUT = 2.8 V, IOUT = 0.25 A, CIN = 1 μF , COUT = 1 μF 0.18 0.25 0.225 DFN4 DFN4 0.14 0.175 VDROP [V] Dropout voltage [V] 0.2 Flip-Chip 0.16 Flip-Chip 0.15 0.125 0.1 0.12 0.1 0.08 0.06 0.075 0.05 0.04 0.025 0.02 0 0 -75 -50 -25 0 25 50 75 100 125 150 0 0.05 0.1 0.15 0.2 0.25 0.3 Output current [A] Te mpe rature [°C] AMG010720161040MT AMG010720161041MT Figure 17. Short circuit current vs. dropout voltage Figure 16. Output voltage vs. input voltage VIN = VEN = from 0 to 5.5 V, VOUT = 2.75 V, IOUT = 250 mA, CIN = 1 μF , COUT = 1 μF 700 3 600 500 2 1.5 ISC [mA] Output vo ltag e [V] 2.5 125°C 85°C 55°C 25°C 0°C -25°C -40°C 1 0.5 400 300 200 100 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 AMG010720161042MT ESR [Ω] Enable threshold [V] 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 25 50 75 100 125 150 Te mpe rature [°C] Ins ta bility Re gion 0.1 S tability Re g io n 0.3 0.47 1 4.7 10 22 100 COUT [μF] AMG010720161044MT DS11756 - Rev 8 3 2.75 2.5 2.25 2 1.75 1.5 1.25 1 0.75 0.5 0.25 0 Not Te s te d Re gion VIH Not Te s te d Re gion VIL 0.9 0 6.5 VIN = VOUT + Vdrop(max) to 5.5 V, IOUT = from 1 mA to 250 mA, T= 25 °C, CIN = 1 μF 1 -25 6 Figure 19. Stability region vs. COUT and ESR VIN = 3.925 V, IOUT = 1 mA, CIN = 1 μF , COUT = 1 μF -50 5.5 AMG010720161043MT Figure 18. Enable threshold vs. temperature -75 5 Drop voltage [V] Input voltage [V] AMG010720161045MT page 10/27 LDLN025 Typical characteristics Figure 21. PSRR vs. frequency (VOUT = 1.8 V) Figure 20. PSRR vs. frequency (VOUT = 2.75 V) 80 80 60 60 SVR [dB] 100 S VR [dB] 100 1mA 20mA 50mA 100mA 150mA 200mA 250mA 40 20 0 1.0E+01 1.0E+02 10mA 40 20mA 50mA 100mA 20 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 f [Hz] 250mA 0 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 f [Hz] VIN = 3.75 V + Vripple, VOUT = 2.75 V, no CIN, COUT = 1 μF, VEN = 1.2 V VIN = 2.5 V + Vripple, VOUT = 1.8 V, no CIN, COUT = 1 µF, VEN = 1.2 V AMG010720161046MT Figure 22. PSRR vs. frequency (VOUT = 5 V) Figure 23. Noise density 10 100 0mA 1mA 10mA 100mA 1 Vn [uV/S QRT(Hz)] SVR [dB] 80 60 10mA 40 0.1 20mA 50mA 0.01 100mA 20 250mA 0 1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07 0.001 1.0E+01 1.0E+03 1.0E+04 1.0E+05 f [Hz] f [Hz] VIN = 3.75 V, VOUT = 2.75 V, CIN = COUT = 1 μF VIN = 5 V + Vripple, VOUT = 5 V, no CIN, COUT = 1 µF, VEN = 1.2 V Figure 24. Line transient (IOUT = 1 mA) 1.0E+02 AMG010720161047MT Figure 25. Line transient (IOUT = 250 mA) VIN VIN VOUT VVOUT OUT VIN VIN = from 3.4 V to 4.4 V, IOUT = 1 mA, tr = 10 μs, CIN = COUT = 1 μF (X7R) AMG010720161048MT DS11756 - Rev 8 VIN = from 3.4 V to 4.4 V, IOUT = 250 mA, tr = 10 μs, CIN = COUT = 1 μF (X7R) AMG010720161049MT page 11/27 LDLN025 Typical characteristics Figure 27. Inrush current Figure 26. Load transient VOUT VEN VIN V VIN IN VOUT IOUT IIN VOUT IOUT = from 0 mA to 250 mA, tr = 10 μs, CIN = COUT = 1 μF (X7R) VIN = 4 V, IOUT = 0 mA, CIN = COUT = 1 μF (X7R) AMG010720161050MT Figure 28. Enable transient (IOUT = 0 mA) AMG180720161000MT Figure 29. Enable transient (IOUT = 250 mA) VVOUT IN VVOUT VEN VEN IN VOUT VOUT VIN VIN VIN = 3.925 V, VEN = from 0 V to 3.925 V, IOUT = 0 mA, tr = 1 μs, CIN = COUT = 1 μF (X7R) AMG010720161052MT DS11756 - Rev 8 VIN = 3.925 V, VEN = from 0 V to 3.925 V, IO = 250 mA, tr = 1 μs, CIN = COUT = 1 μF (X7R) AMG010720161053MT page 12/27 LDLN025 Package information 7 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 7.1 Flip-Chip4 package information Figure 30. Flip-Chip4 package outline 8387748 option F DS11756 - Rev 8 page 13/27 LDLN025 Flip-Chip4 package information Table 6. Flip-Chip4 mechanical data Dim. mm Min. Typ. Max. A 0.375 0.410 0.445 A1 0.145 0.160 0.175 0.230 0.250 0.270 b 0.189 0.210 0.231 D 0.598 0.628 0.658 A2 (1) D1 E 0.350 0.598 0.628 E1 0.350 SD 0.175 SE 0.175 f 0.139 ccc 0.075 0.658 1. Including back coating. Figure 31. Flip-Chip4 recommended footprint DS11756 - Rev 8 page 14/27 LDLN025 Flip-Chip4_160304-47_carrier_tape 7.2 Flip-Chip4_160304-47_carrier_tape Figure 32. Flip-Chip4 carrier tape DS11756 - Rev 8 page 15/27 LDLN025 DFN4-1x1 package info 7.3 DFN4-1x1 package info Figure 33. DFN4-1x1 package outline DS11756 - Rev 8 page 16/27 LDLN025 DFN4-1x1 package info Table 7. DFN4-1x1 package mechanical data Dim. mm Min. Typ. Max. A 0.34 0.37 0.40 A1 0.00 0.02 0.05 A3 0.127 REF. b 0.17 0.22 0.27 D 0.95 1.00 1.05 E 0.95 1.00 1.05 e 0.65 BSC D2 0.43 0.48 0.53 E2 0.43 0.48 0.53 K 0.15 L 0.20 0.25 0.30 N 4 ND 2 Figure 34. DFN4-1x1 recommended footprint DS11756 - Rev 8 page 17/27 LDLN025 DFN4_1x1x0.38_pitch_4mm_carrier_tape 7.4 DFN4_1x1x0.38_pitch_4mm_carrier_tape Figure 35. DFN4 (1x1x0.38 pitch 4 mm) carrier tape DS11756 - Rev 8 page 18/27 LDLN025 SOT23-5L mechanical data 7.5 SOT23-5L mechanical data Figure 36. SOT23-5L package outline 7049676_k Table 8. SOT23-5L package mechanical data Dim. DS11756 - Rev 8 mm Min. Typ. Max. A 0.90 1.45 A1 0 0.15 A2 0.90 1.30 b 0.30 0.50 c 0.09 0.20 D 2.95 E 1.60 e 0.95 H 2.80 L 0.30 0.60 θ 0° 8° page 19/27 LDLN025 SOT23-5L mechanical data Figure 37. SOT23-5L recommended footprint Note: DS11756 - Rev 8 Dimensions are in mm page 20/27 LDLN025 Ordering information 8 Ordering information Table 9. Order code Order code Package Output voltage (V) Marking LDLN025PU12R 1.2 12 LDLN025PU18R 1.8 18 LDLN025PU25R 2.5 25 LDLN025PU275R 2.75 2Z 2.8 28 2.9 29 LDLN025PU30R 3.0 30 LDLN025PU32R 3.2 32 LDLN025PU33R 3.3 33 LDLN025PU50R 5.0 50 LDLN025J12R 1.2 M LDLN025J18R 1.8 E LDLN025J25R 2.5 H LDLN025J28R 2.8 I LDLN025J29R 2.9 S 2.925 K 3.0 G LDLN025J32R 3.2 N LDLN025J33R 3.3 F LDLN025J50R 5.0 P LDLN025M12R 1.2 LN12 LDLN025M15R 1.5 LN15 LDLN025M18R 1.8 LN18 LDLN025PU28R LDLN025PU29R LDLN025J2925R LDLN025J30R DFN4-1x1 Flip-Chip4 (1) LDLN025M25R 2.5 LN25 2.8 LN28 LDLN025M30R 3.0 LN30 LDLN025M33R 3.3 LN33 LDLN025M45R 4.5 LN45 LDLN025M28R SOT23-5L Packing Tape and reel 1. Part number in development. Contact our sales office. DS11756 - Rev 8 page 21/27 LDLN025 Marking information 8.1 Marking information Figure 38. Flip-Chip marking composition (marking view) # A2 B2 A1 B1 AMG260720161100MT Note: DS11756 - Rev 8 the symbol # indicates the marking digit, as per Table 9. Order code. page 22/27 LDLN025 Revision history Table 10. Document revision history Date Revision 03-Aug-2016 1 01-Sep-2016 2 24-Oct-2016 3 17-Nov-2016 4 Changes First release. Updated Table 8: “Order code”. Minor text changes. Updated Table 2: "Absolute maximum ratings". Minor text changes. Updated Section 9: “Ordering information”. Minor text changes. Added SOT23-5L package. Modified silhouette, features, Figure 1: "Block diagram", Section 2: "Pin configuration" and Table 4: 12-Jul-2017 5 "Electrical characteristics". Added Section 7.5: "SOT23-5L package information". Updated Table 9: "Order code". Minor text changes. Added Figure 21. PSRR vs. frequency (VOUT = 1.8 V), Figure 22. PSRR vs. frequency (VOUT = 5 V), new order codes 09-Oct-2018 6 08-May-2019 7 Added footnote on A2 parameter in Table 6. Flip-Chip4 mechanical data.. 16-Jul-2021 8 Update Figure 33. DFN4-1x1 package outline and Table 7. DFN4-1x1 package mechanical data LDLN025PU12R and LDLN025J29R in Table 9. Order code. DS11756 - Rev 8 page 23/27 LDLN025 Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 5 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 8 7.1 Flip-Chip4 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Flip-Chip4 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 DFN4-1x1 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 DFN4-1x1 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.5 SOT23-5L package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 8.1 Marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 DS11756 - Rev 8 page 24/27 LDLN025 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Pin description. . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . Recommended input and output capacitors . Flip-Chip4 mechanical data . . . . . . . . . . . . DFN4-1x1 package mechanical data . . . . . SOT23-5L package mechanical data . . . . . Order code . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . DS11756 - Rev 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 . 5 . 5 . 6 . 7 14 17 19 21 23 page 25/27 LDLN025 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. DS11756 - Rev 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . Typical application diagram . . . . . . . . . . . . . . . . . Output voltage vs. temperature (VIN = 3.925 V). . . . Output voltage vs. temperature (VIN = 5.5 V) . . . . . Load regulation vs. temperature . . . . . . . . . . . . . . Line regulation vs. temperature. . . . . . . . . . . . . . . Quiescent current vs. temperature (IOUT = 0 mA) . . Quiescent current vs. temperature (IOUT = 250 mA). GND current vs. input voltage . . . . . . . . . . . . . . . . Off-state current vs. temperature. . . . . . . . . . . . . . Quiescent current vs. output current . . . . . . . . . . . Quiescent current vs. output current (zoom) . . . . . . Dropout voltage vs. temperature . . . . . . . . . . . . . . Dropout voltage vs. load current . . . . . . . . . . . . . . Output voltage vs. input voltage . . . . . . . . . . . . . . Short circuit current vs. dropout voltage . . . . . . . . . Enable threshold vs. temperature . . . . . . . . . . . . . Stability region vs. COUT and ESR. . . . . . . . . . . . . PSRR vs. frequency (VOUT = 2.75 V). . . . . . . . . . . PSRR vs. frequency (VOUT = 1.8 V) . . . . . . . . . . . PSRR vs. frequency (VOUT = 5 V) . . . . . . . . . . . . . Noise density . . . . . . . . . . . . . . . . . . . . . . . . . . . Line transient (IOUT = 1 mA) . . . . . . . . . . . . . . . . . Line transient (IOUT = 250 mA) . . . . . . . . . . . . . . . Load transient . . . . . . . . . . . . . . . . . . . . . . . . . . Inrush current . . . . . . . . . . . . . . . . . . . . . . . . . . . Enable transient (IOUT = 0 mA) . . . . . . . . . . . . . . . Enable transient (IOUT = 250 mA) . . . . . . . . . . . . . Flip-Chip4 package outline . . . . . . . . . . . . . . . . . . Flip-Chip4 recommended footprint . . . . . . . . . . . . Flip-Chip4 carrier tape . . . . . . . . . . . . . . . . . . . . . DFN4-1x1 package outline . . . . . . . . . . . . . . . . . . DFN4-1x1 recommended footprint. . . . . . . . . . . . . DFN4 (1x1x0.38 pitch 4 mm) carrier tape . . . . . . . . SOT23-5L package outline. . . . . . . . . . . . . . . . . . SOT23-5L recommended footprint . . . . . . . . . . . . Flip-Chip marking composition (marking view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 4 . 8 . 8 . 8 . 8 . 9 . 9 . 9 . 9 . 9 . 9 10 10 10 10 10 10 11 11 11 11 11 11 12 12 12 12 13 14 15 16 17 18 19 20 22 page 26/27 LDLN025 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2021 STMicroelectronics – All rights reserved DS11756 - Rev 8 page 27/27