LED1642GWXTTR

LED1642GW 16 channel LED driver with error detection current gain control and 12/16-bit PWM brightness control Datasheet - production data Applications • Full color/monochrome large displays • LED signage QSOP-24 TSSOP24 Description The LED1642GW is a monolithic, low voltage, low current power 16-bit shift register designed for LED panel displays. The LED1642GW guarantees 20 V output driving capability allowing the user to connect several LEDs in series. In the output stage, sixteen regulated current sources provide from 3 mA to 40 mA constant current to drive the LEDs. The current is programmed through an external resistor and can be adjusted by a 7-bit current gain register in two subranges. The brightness can be adjusted separately for each channel through 12/16-bit grayscale control. TSSOP24 (exposed pad) Features • 16 constant current output channels • Output current: from 3 mA to 40 mA • Current programmable through external resistor • 7-bit global current gain adjustment in two ranges • 12/16-bit PWM grayscale brightness control • Programmable output turn-on/off time • Error detection mode (both open and shortedLED) • Programmable shorted-LED detection thresholds • Auto power saving/auto-wakeup • Selectable SDO synchronization on the CLK falling edge • Gradual output delay (selectable) • Supply voltage: 3 V to 5.5 V • Thermal shutdown and overtemperature alert Programmable turn-on and turn-off time (four different values available) improves the low noise generation performance of the system. Open/short error detection mode is available in the LED1642GW. The auto power-shutdown and auto power-on features (selectable) allow the device to save power without external intervention. Thermal management includes an overtemperature data alert and output thermal shutdown (170 °C). The high clock frequency is up to 30 MHz and it makes the device suitable for high data rate transmission. A selectable gradual output delay reduces the inrush current, whereas the selectable SDO synchronization feature works when the device is used in daisy-chain configuration. The supply voltage range is between 3 V and 5.5 V. • 30 MHz 4-wires interface • 20 V current generator rated voltage November 2015 This is information on a product in full production. DocID024395 Rev 6 1/42 www.st.com Contents LED1642GW Contents 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Simplified internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 Equivalent circuits of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 Gain control (from CFG 0 to 5) and current ranges (CFG- 6) . . . . . . . . . 19 8.2 Error detection mode (CFG-7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 Error detection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 Auto-wakeup/auto power shutdown (CFG-10) . . . . . . . . . . . . . . . . . . . . . 24 8.5 Programmable turn-on/turn-off time (CFG-11/12) . . . . . . . . . . . . . . . . . . 24 8.6 SDO delay (CFG-13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.7 Gradual output delay (CFG-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.8 PWM counter setting and brightness register (CFG-15) . . . . . . . . . . . . . 27 9 Thermal flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 Dropout voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2/42 DocID024395 Rev 6 LED1642GW 11 Contents Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11.1 QSOP-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11.2 QFN-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11.3 TSSOP24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.4 TSSOP24 exposed pad package information . . . . . . . . . . . . . . . . . . . . . 37 11.5 TSSOP24 and TSSOP24 exposed pad packing information . . . . . . . . . . 39 12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID024395 Rev 6 3/42 42 List of tables LED1642GW List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. 4/42 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Programmable TON/TOFF (output rise and fall time). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Digital key summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Example of current ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Gain steps for the current range selected by REXT = 11 kW . . . . . . . . . . . . . . . . . . . . . . . 20 Diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Minimum dropout voltage for some current values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 QSOP-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 QFN-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 TSSOP24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP24 exposed pad mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data. . . . . . . . . . . . . . . 39 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID024395 Rev 6 LED1642GW List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. TSSOP24, TSSOP24EP, QSOP-24 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 QFN-24 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Typical chip-to-chip accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing for clock, serial in, serial out, latch enable and outputs. . . . . . . . . . . . . . . . . . . . . . 14 LED1642GW simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Input and output equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Digital keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Channel data and write switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Channel current vs. gain register value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Error detection action sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Error detection power-on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Configuration register reading sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration register reading sequence (zoom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Configuration register reading sequence - SDO delay actives . . . . . . . . . . . . . . . . . . . . . . 23 Configuration register reading sequence - SDO delay actives (zoom) . . . . . . . . . . . . . . . . 23 Output TON (current rise time) CFG -12 = CFG - 11 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output TOFF (current fall time) CFG - 2 = CFG - 11 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output TON (current rise time) CFG -12 = CFG - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output TOFF (current fall time) CFG -12 = CFG - 11 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SDO delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Gradual output delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PWCLK counter and comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Brightness register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal flag status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Typical channel dropout voltage vs. output current (VDD = 3.3 V). . . . . . . . . . . . . . . . . . . 30 QSOP-24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 QFN-24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TSSOP24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP24 exposed pad outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TSSOP24 and TSSOP24 exposed pad tape and reel outline . . . . . . . . . . . . . . . . . . . . . . 39 DocID024395 Rev 6 5/42 42 Pin description 1 LED1642GW Pin description Figure 1. TSSOP24, TSSOP24EP, QSOP-24 pinout GND VDD SDI R-EXT CLK SDO LE PWCLK OUT0 OUT15 OUT1 OUT14 OUT2 OUT13 OUT3 OUT12 OUT4 OUT11 OUT5 OUT10 OUT6 OUT9 OUT7 OUT8 AM13686v1 SDO R-EXT VDD GND SDI CLK Figure 2. QFN-24 pinout LE 1 24 23 22 21 20 19 18 OUT0 2 17 OUT15 PWCLK OUT12 6 13 10 11 12 OUT11 OUT4 7 8 9 OUT10 5 OUT3 OUT8 OUT13 14 OUT9 15 OUT7 16 4 OUT5 3 OUT2 OUT6 OUT1 OUT14 AM13687V1 Table 1. Pin description 6/42 TSSOP24 TSSOP24EP QSOP-24 QFN-24 Symbol 1 22 GND Ground terminal 2 23 SDI Serial data input terminal 3 24 CLK Clock input terminal 4 1 LE Latch input terminal 5-20 2-17 OUT0-OUT15 21 18 PWCLK Name and function Output terminals Clock input for PWM counter DocID024395 Rev 6 LED1642GW Absolute maximum ratings Table 1. Pin description (continued) 2 TSSOP24 TSSOP24EP QSOP-24 QFN-24 Symbol 22 19 SDO 23 20 R-EXT 24 21 VDD Name and function Serial data output terminal Terminal for external resistor for constant current programming Supply voltage terminal Absolute maximum ratings Stressing the device above the ratings listed in the Table 2 may cause the device permanent damage. Operating under conditions above those indicated in the operating section is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the device reliability. Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDD Supply voltage 0 to 7 V VOUT Output voltage -0.5 to 20 V IOUT Output current 50 mA Vi Input voltage -0.4 to VDD +0.4 V IGND GND terminal current 1400 mA ESD Electrostatic discharge protection HBM human body model ±2 kV DocID024395 Rev 6 7/42 42 Thermal characteristics 3 LED1642GW Thermal characteristics Table 3. Thermal characteristics Symbol Parameter Value Ta Operative free-air temperature range(1) -40 to +85 TOPR Operative junction temperature range -40 to +125 TSTG Storage ambient temperature range -55 to +150 QFN-24(2) Thermal resistance junction-ambient TSSOP24EP °C 30 TSSOP24 Rthj-amb Unit 85 °C/W (2) 37.5 QSOP-24 72 1. This data must be considered in adequate power dissipation conditions, the junction temperature must be maintained below 125 °C. 2. The exposed pad should be soldered directly to the PCB to get the thermal benefits. The exposed pad can be attached to a metal land electrically isolated or connected to ground. 4 Electrical characteristics VDD = 3.3 V, Tj = 25 °C, unless otherwise specified. Table 4. Electrical characteristics Symbol Parameter VDD Supply voltage VOUT Output voltage VIH Conditions VOH IOleak Out 0 - out 15 Input voltage Hyuvlo 8/42 Max. Unit 5.5 - - 19 0.7 x VDD - VDD GND - 0.3 x VDD Serial data output voltage (SDO) VDD= 3 to 5.5 V I = +/- 1 mA - - 0.4 VDD -0.4 - - Output leakage current VOUT = 19 V, all outputs OFF - - 0.5 2.7 2.9 UVLO threshold (rising) Vuvlo Typ. 3 VIL VOL Min. V µA V UVLO threshold (falling) 2.2 UVLO hysteresis 2.3 400 DocID024395 Rev 6 mV LED1642GW Electrical characteristics Table 4. Electrical characteristics (continued) Symbol Parameter Conditions Min. Typ. Max. VOUT = 0.1 V; (IOUT = 3 mA) REXT = 11 kΩ CFG-0…CFG-5= “000000” CFG-6 = “0” - - ±4 VOUT = 0.5 V; (IOUT = 20 mA) REXT = 11 kΩ CFG-0…CFG-5 = “011010” CFG-6 = “1” - - ±3 VOUT = 0.8 V; (IOUT = 36 mA) REXT = 11 kΩ CFG-0…CFG-5 = “111111” CFG-6 = “1” - - ±3 Output current precision device-to-device (all outputs ON)(1) VOUT = 0.5 V; (IOUT = 20 mA) REXT=1 1 kΩ CFG-0…CFG-5 = “011010” CFG-6 = “1” - - ±6 Output current vs. output voltage regulation (3) VOUT from 1 V to 3 V; (IOUT = 36 mA) REXT = 11 kΩ CFG-0…CFG-5 = “111111” CFG-6 = “1” - ±0.1 - %/dVDD Output current vs. supply voltage regulation(4) VDD from 3 V to 5.5 V VOUT = 0.8 V; (IOUT = 36 mA) REXT = 11 kΩ CFG-0…CFG-5 = “111111” CFG-6 = “1” Rup ∆IOL1 ∆IOL2 Output current precision channel-to-channel (all outputs ON)(1)(2) ∆IOL3 ∆IOL2a %/dVOUT % % %/V - ±1 - Pull-up resistor for PWCLK pin 400 500 600 Rdw Pull-down resistor for LE pin 400 500 600 REXT External current setup resistance IDD(OFF1) Supply current (OFF) IDD(ON1) Unit KΩ 100 REXT = 11 kΩ OUT 0 to 15 = OFF CFG = default - REXT = 11 kΩ; IOUT = 20 mA OUT 0 to 15 = ON CFG-0…CFG-5 = “011010” CFG-6 = “1” - 8 REXT = 11 kΩ; IOUT = 36 mA OUT 0 to 15 = ON CFG-0…CFG-5 = “111111” CFG-6 = “1” - 10 - 6 mA Supply current (ON) IDD(ON2) DocID024395 Rev 6 9/42 42 Electrical characteristics LED1642GW Table 4. Electrical characteristics (continued) Symbol Parameter Conditions Min. Typ. Max. Unit IDD (auto OFF) Supply current (auto OFF) REXT= 11 kΩ; OUT 0 to 15 = OFF CFG-0…CFG-5 = “111111” CFG-6 = “1” - 200 500 µA Tflg Thermal flag Tsd Tsd-hy Thermal shutdown 150 (5) 170 Thermal shutdown hysteresis(5) °C 15 20 35 40 1. Tested with just one output loaded. 2. ((Ioutn - Ioutavg1-15)/ Ioutavg1-15) x 100. 3. Δ (% / V ) = ( Ioutn @ Voutn = 3. 0 V ) − (Ioutn @ Voutn = 1 .0 V ) 100 × ( Ioutn @ Voutn = 1 .0 V ) 3 −1 4. Δ (% / V ) = ( Ioutn @ V dd = 5. 5 V ) − ( Ioutn @ Vdd = 3 . 0 V ) 100 × ( Ioutn @ V dd = 3 . 0 V ) 5.5 − 3 5. Not tested, guaranteed by design. Figure 3. Typical chip-to-chip accuracy VDD=3.3/5 V; T=25 °C 4 Chip-to-chip (%) 3.5 3 2.5 2 1.5 1 0.5 0 0 5 10 15 20 25 30 IOUT (mA) AM13688V1 10/42 DocID024395 Rev 6 LED1642GW Electrical characteristics Figure 4. Typical application schematic LED common rail voltage + Cled ….. Supply voltage VDD OUT0 OUT15 OUT1 SDI CLK Cin LED1642GW LE Data loaded through serial interface PWCLK R-EXT SDO Data output GND Current setting resistor AM13689V1 DocID024395 Rev 6 11/42 42 Switching characteristics 5 LED1642GW Switching characteristics VDD = 3.3 V, Tj = 25 °C, unless otherwise specified. Table 5. Switching characteristics(1) Symbol Parameter Conditions Min. Typ. Max. fclk Clock frequency Cascade operation - - 30 fpwclk PWclock frequency - - 30 tr(SDO) SDO rise time - 5 - tf(SDO) SDO fall time - 5 - - 200 - 8 15 25 - 100 - 8 15 25 20 - - 20 - - 20 - - Unit MHz tPLHLE LE - OUTn(2) tPLH CLK - SDO CFG-13 = ‘0’ tPHLLE LE - OUTn(2) tPHL CLK - SDO CFG-13 = ‘0’ tw(CLK) CLK tW(PWCLK) PWCLK tw(L) LE tgr-d Gradual delay ch-to-ch tsu(L) Setup time for LE th(L) REXT= 11 kΩ; IOUT = 20 mA VOUT = 0.8 V VIH = VDD; VIL = GND RL = 3.3 KΩ; CL = 10 pF CFG-0…CFG-5 = “011010” CFG-6 = “1” Propagation delay time (“L to “H”) Propagation delay time (“H” to “L”) Pulse width REXT = 11 kΩ; IOUT = 20 mA VOUT = 0.8 V VIH = VDD; VIL = GND RL = 50 Ω; CL = 10 pF CFG-0…CFG-5 = “011010” CFG-6 = “1” ns 10 5 - - Hold time for LE 5 - - tsu(D) Setup time for SDI 5 - - th(D) Hold time for SDI 10 - - tclkr(3) Maximum CLK rise time - - 5 (3) Maximum CLK fall time - - 5 - - 10 % - - 1 µs tclkf µs Iout-ov Output current turn-on overshoot tn-err Normal error detection minimum output ON time 12/42 VOUT = 0.6 to 3 V CL = 10 pF; IOUT = 3 to 36 mA DocID024395 Rev 6 LED1642GW Switching characteristics Table 5. Switching characteristics(1) Symbol Parameter Conditions Min. Typ. Max. Unit tshutdown Auto power shutdown time (auto OFF) From LE falling edge to REXT voltage reference at -10% - 100 - ns twakeup Auto-wakeup From LE falling edge to REXT voltage reference at 90% - 3 - µs 1. Not tested in production. All table limits are guaranteed by design. 2. CFG -11= 0 and CFG -12 = 0 (output tr = 30 ns; output tf = 20 ns); CFG-14=1 (no output gradual delay). 3. If devices are connected in cascade and tclkr or tclkf is large, it may be critical to achieve the timing required for data transfer between two cascaded devices. Table 6. Programmable TON/TOFF (output rise and fall time) Configuration bits (CFG-12 - CFG-11) 0-0 0-1 1-0 1-1 Typ. (20% to 80%) Conditions Unit Turn-on Turn-off 30 ns 20 ns 100 ns 40 ns 140 ns 80 ns 180 ns 150 ns REXT = 11 kΩ; IOUT = 20 mA VOUT = 0.8 V VIH= VDD; VIL= GND RL = 50 Ω; CL=10pF CFG-0...CFG-5=“011010” CFG-6 = “1” DocID024395 Rev 6 ns 13/42 42 Switching characteristics LED1642GW Figure 5. Timing for clock, serial in, serial out, latch enable and outputs tpLHLE, tpHLLE AM13690V1 The correct sampling of the data depends on the stability of the data at SDI on the rising edge of the clock signal and it is assured by a proper data setup and hold time (tSU(D) and th(D)), as shown in Figure 5. The same figure shows the propagation delay from CLK to SDO (tPLH/tPHL). Figure 5 describes also the minimum duration of CLK, LE pulses (tW(CLK)) and tW(L) respectively and the propagation delay from LE to OUTn (tPLHLE and tPHLLE) in the hypothesis that all channels have already been enabled by PWM counter. 14/42 DocID024395 Rev 6 LED1642GW 6 Simplified internal block diagram Simplified internal block diagram Figure 6. LED1642GW simplified block diagram SDO SDI CLK LE Control Logic & Data Registers PWCLK OUT0 PWM counter OUT1 VDD GND UVLO & POR Error detection Channel driver Timing control Turn ON/OFF Gradual delay ………… R-EXT Current gain adjustment 16 output channels Thermal shutdown Configuration register Current Ref. OUT2 OUT14 OUT15 AM13691V1 6.1 Equivalent circuits of inputs and outputs LE and PWCLK input terminals have pull-down and pull-up connection respectively. CLK and SDI must be connected to the external circuit to fix the logic level. Figure 7. Input and output equivalent circuits PWCLK terminal LE terminal CLK, SDI terminal SDO terminal AM13692V1 DocID024395 Rev 6 15/42 42 Digital blocks 7 LED1642GW Digital blocks The data input arrives through the serial Interface at each CLK rising edge. The LE signal is used to latch the loaded data and also to address data loading to the appropriate register, thermal flag reading and error detection. The access to the different registers or functions of the device (configuration register, brightness register or current gain, error detection, etc.) is achieved by using different digital keys, defined as a number of CLK pulses during which the LE signal is asserted. The available digital keys are listed in Table 7 and Figure 8. A typical channel data input is shown in Figure 9. Table 7. Digital key summary Number # CLK rising edge when the LE is “1” 16/42 Command description 1 1–2 Write switch (to turn on/off output channels) 2 3–4 Brightness data latch 3 5–6 Brightness global latch 4 7 Write configuration register 5 8 Read configuration register 6 9 Start open error detection mode 7 10 Start short error detection mode 8 11 Start combined error detection mode 9 12 End error detection mode 10 13 Thermal error reading 11 14 Reserved 12 15 Reserved DocID024395 Rev 6 LED1642GW Digital blocks Figure 8. Digital keys CLK LE Write switch LE Data latch LE Global latch LE Write CR LE Read CR LE Start open error detection LE Start short error detection LE Start combined detection LE End error detection LE Thermal error reading AM13693V1 Figure 9. Channel data and write switch SDI 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 CLK LE 16-bit data AM13694V1 DocID024395 Rev 6 17/42 42 Configuration register 8 LED1642GW Configuration register The configuration register is used to enable or disable some device features, to program some parameters and to change other settings. The access to this register (read or write) is managed to find a description for each bit as described in Table 8. The default value of the configuration register (when the device is switched on or after a reset) is "0" for all bits. To change anything in the configuration register, a 16-bit digital word must be sent (CFG - 0 represents LSB, CFG -15 the MSB). Table 8. Configuration register Bit Definition R/W Description Default CFG-0 0 CFG-1 0 CFG-2 CFG-3 Current gain adjustment R/W 6-bit DAC allows adjusting the device output current in 64 steps for each range (defined by CFG-6) 0 0 CFG-4 0 CFG-5 0 CFG-6 Current range R/W ”0” low current range “1” high current range 0 CFG-7 Error detection mode R/W “0” normal mode “1” reserved mode 0 CFG-8 Shorted-LED detection thresholds CFG-9 CFG-10 R/W Auto OFF shutdown R/W R/W Output turnon/off time CFG-12 18/42 CFG-8 Th. volt. 0 0 1.8 V 0 1 2.5 V 1 0 3V 1 1 3.5 V R/W CFG-11 CFG-13 Programmable output shorted-LED detection thresholds CFG-9 0 “0” device always ON ”1” auto power shutdown active (auto OFF) Programmable output rise and fall time (20% to 80%) 0 CFG-12 CFG-11 Turn-on Turn-off 0 0 30 ns 20 ns 0 1 100 ns 40 ns 1 0 140 ns 80 ns 1 1 180 ns 150 ns R/W SDO delay R/W 0 0 0 If “0” no delay is present on SDO If “1” the data are shifted out and they are synchronized with the falling edge of the CLK signal DocID024395 Rev 6 0 LED1642GW Configuration register Table 8. Configuration register (continued) Bit Definition R/W CFG-14 Gradual output delay R/W “0” a progressive delay is applied to output (10 ns per channel) ”1” no delay is applied to output 0 CFG-15 12/16 PWM counter R/W “0” to select 16-bit brightness register (65536 grayscale rightness steps). “1” to select 12-bit brightness register (4096 grayscale brightness steps) 0 8.1 Description Default Gain control (from CFG 0 to 5) and current ranges (CFG- 6) The LED current can be programmed using an external resistor connected to GND from REXT pin and can be fixed using the dedicated bits of the configuration register (from CFG 0 to CFG - 5 bits define the gain, while CFG - 6 bit defines the current range within the which the gain can be adjusted). The device can regulate the current up to 36 mA and down to 0.5 mA. The accuracy of the LED current depends on the selected range and it is guaranteed in the ranges indicated in the static electrical characteristics only (see Table 3 and 9). When the device is switched on, the selected current range and the resistor connected to the REXT pin fix the default LED current: I OL _ default = VREF ⋅K REXT Where VREF=1.23 V is the voltage of the REXT pin and K is the mirroring current ratio, whose value depends on the selected current range: • K = 28 with low current range selected (CFG - 6 = "0") • K = 80 with high current range selected (CFG - 6 = "1") The relation between the programmed current and the current gain settings is the following: I OL = ( I OL _ default + G ⋅ ΔI ste p ) where G is the current gain value (decimal value) defined by the dedicated bits of the current gain register. The current gain is managed by 6-bits of the configuration register (CFG - 0 to CFG - 5, CFG - 0 is LSB and CFG - 5 is MSB) and can be adjusted within two ranges (selectable through the bit CFG - 6) over 64 steps. The width of each step depends on the default current (Iol_default) as well as the selected REXT. Finally, each step is as follows: DocID024395 Rev 6 19/42 42 Configuration register LED1642GW Δ I ste p = I O L _ d e fa u lt 21 The Table 9 shows an example of the current setting with an external resistance (REXT) = 11 KΩ: Table 9. Example of current ranges REXT [KΩ] CFG-6 CFG-0 to CFG-5 LED current(1) [mA] Accuracy 11 0 000000 3.1 mA ± 4% ch-to-ch 11 0 111111 12.5 mA 11 1 000000 8.9 mA 11 1 011010 20 mA Low range High range 1. ± 3% ch-to-ch The indicated values may be slightly different on the current device. The Table 10 shows an example of current setting and gain control with REXT = 11 kΩ, see also Figure 10. Table 10. Gain steps for the current range selected by REXT = 11 kΩ CFG-6 CFG(0 to 5) LED current (1) [mA] 0 000000 3.131 0 000001 3.280 … … … 0 111111 12.524 1 000000 8.945 1 000001 9.371 … … … 1 111111 35.78 Low range High range 1. The indicated values may be slightly different on the current device. The external programming resistance must be connected as close as possible to the related device pins (REXT and GND) to reduce as minimum as possible the routing length and prevent reference noise injection and electromagnetic interferences. Moreover, a direct connection to the device GND pin reduces the possible output current variation when the total device ground current changes (load effect). 20/42 DocID024395 Rev 6 LED1642GW Configuration register Figure 10. Channel current vs. gain register value IOUT vs. gain (R = range selection, REXT = 11 K or 18 K) 40.0 11 K R=0 35.0 11 K R=1 IOUT (mA) 30.0 18 K R=0 18 K R=1 25.0 20.0 15.0 10.0 5.0 0.0 0 5 10 15 20 25 30 35 40 45 50 Gain register decimal value 8.2 55 60 65 70 AM13695V1 Error detection mode (CFG-7) Stopping the normal activity of the display and turning on all driver channels allows the error detection to be performed and failed LED or display defects to be checked. The error detection is active when the CFG -7 bit of the configuration register is "0". The diagnostics is performed as shown in Figure 11: • The LED has to be selected turning on the relative channel on the switch register (powering on or off the output channels); the brightness register value for this channel cannot be zero. • The normal error detection has to be selected in the configuration register (CFG-7= "0"). The appropriate digital key to choose the type of detection (open, short or combined) must be sent (see Table 7). • After the error detection starts, the channel under testing has to be turned on at least 1 μs (the LED is at the nominal current). Please note that, the output power-on depends on PWCLK signal and in several applications this signal is not synchronized with the serial interface clock (CLK pin). Therefore, to be sure that, between the detection start and the detection end, the output power-on is 1 μs and moreover, that last power-on, in the interval, starts at least 0.5 μs before the detection end pattern (see Figure 12), it is suggested that the error detection should be performed just after the device startup (brightness counter reset) with all channels ON, before applying PWCLK signal. • The result of the detection ("0" indicates a fault condition) is shifted out SDO, in 16 clock pulses after the "detection end command" is provided, first output bit represents channel 15 (error data can be read in a way similar to configuration register data reading as shown on Figure 13, 14, 15 and 16). Please note that (with SDO delay off) output 15 detection result will be available just after 1st clock pulse rising edge, so it can be sampled on the rising edge of second clock pulse. In the same way output 0 detection result will be available just after 16th clock pulse rising edge, so it can be sampled on the rising edge of 17th CLK pulse. DocID024395 Rev 6 21/42 42 Configuration register LED1642GW Figure 11. Error detection action sequence Normal detection sequence Select LED to be turned on and checked in switch register data; brightness for selected channels cannot be zero. Select normal error detection mode on CFG register (bit 7 = “0”) Send open, short or combined error detection start command by LE digital keys Turn on LED by PWCLK pulses for at least 1 µs Send error detection end command by LE digital key Read error detection result on SDO in 16 clock pulses after detection end command AM13696V1 Figure 12. Error detection power-on timing x0000 < BRT < xFFFF Output Current 1us 0.5us Det. Start Det. End SPI pattern It must contain 1us output power ON AM13697V1 22/42 DocID024395 Rev 6 LED1642GW Configuration register Figure 13. Configuration register reading sequence C1=CLK C2=SDI C3=LE C4=SDO C1=CLK C2=SDI C3=LE C4=SDO First CLK pulse after CFG Reg reading command CFG Reg programming CFG Reg reading command Figure 14. Configuration register reading sequence (zoom) CFG Reg data CFG Reg data First CLK pulse after CFG Reg reading command Figure 15. Configuration register reading sequence - SDO delay actives C1=CLK C2=SDI C3=LE C4=SDO Sync. change C1=CLK C2=SDI C3=LE C4=SDO First CLK pulse after CFG Reg reading command CFG Reg programming CFG Reg reading command Figure 16. Configuration register reading sequence - SDO delay actives (zoom) CFG Reg data CFG13=1 CFG Reg data First CLK pulse after CFG Reg reading command DocID024395 Rev 6 23/42 42 Configuration register 8.3 LED1642GW Error detection conditions During the error detection phases for each channel, the following checks have to be performed: – The output current in open detection mode (digital key: 9 CLK rising edges when LE is "1") – The output voltage in short detection (digital key: 10 CLK rising edges when LE is "1") – Both parameters (output voltage and current) in combined error detection mode (digital key: 11 CLK rising edges when LE is "1"). The thresholds for the error diagnostics are listed in Table 11: Table 11. Diagnostic thresholds Open detection Short detection 8.4 Combined mode Error detection modes Thresholds (V) Checked malfunction CFG-9 Open line or output short to GND x Short on LED or short to V-LED CFG-8 Min. Typ. Max. x - IOUT ≤ 0.5 x IOUT programmed - 0 0 1.15 VOUT ≥ 1.8 2.05 0 1 2.25 VOUT ≥ 2.5 2.75 1 0 2.75 VOUT ≥ 3.0 3.25 1 1 3.25 VOUT ≥ 3.5 3.80 Auto-wakeup/auto power shutdown (CFG-10) This feature reduces the power consumption when all outputs are OFF. It is active when the CFG -10 bit of configuration register is "1". The auto power shutdown (auto OFF) starts when the data latched is "0" for all channels, and device is active again (wakeup) at the first latched data string including at least one bit = "1" (at least one channel ON). Timings for shutdown and wakeup are present in the dynamics feature table. While the auto power shutdown is active, the device ignores any other command except the channel power-on. 8.5 Programmable turn-on/turn-off time (CFG-11/12) The device gives the possibility to program the turn-on and turn-off time of the current generators. Four different values can be selected using CFG -12 and CFG-11 bits of the configuration register (see Table 8) to fit the application requirements: 30/20 ns (00), 100/40 ns (01), 140/80 ns (10) and 180/150 ns (11). The selected value refers to TON (current rise time) and TOFF (current fall time). 24/42 DocID024395 Rev 6 LED1642GW Configuration register Figure 17. Output TON (current rise time) CFG - Figure 18. Output TOFF (current fall time) CFG 12 = CFG - 11 = 0 2 = CFG - 11 = 0 AM13698V1 AM13699V1 Figure 19. Output TON (current rise time) CFG - Figure 20. Output TOFF (current fall time) CFG 12 = CFG - 11 = 1 12 = CFG - 11 = 1 AM13700V1 8.6 AM13701V1 SDO delay (CFG-13) Usually in SDO terminal, data are shifted out the rising edge of CLK signal (with a propagation delay of about 15 ns - signal (a) in Figure 21). The device has the possibility to shift data out the falling edge of the CLK signal (with few ns of propagation delay - signal (b) in Figure 21). This feature is active when CFG -13 bit of the configuration register is "1". Default setting for this bit is "0" hence the SDO delay is not activated by default. This feature is particularly useful when some devices are connected in daisy chain configuration with mismatched propagation delays, between CLK and SDO data path (board routing). DocID024395 Rev 6 25/42 42 Configuration register LED1642GW Figure 21. SDO delay (a) (b) (a) Data shifted out of the SDO with the device propagation delay (b) Data shifted out of the SDO by the falling edge of the CLK AM13702V1 8.7 Gradual output delay (CFG-14) The gradual output delay consists of turning on gradually the current generators avoiding to turn on all channels at the same time. When PWM counter enables the device channels, the outputs can be turned on simultaneously or with a progressive delay. Thanks to configuration register CFG -14 bit, the user can decide to put a delay among outputs (10 ns from each channel to the next one, around 150 ns between first and last channel). The typical output timing is shown in Figure 22. This feature prevents the inrush current and reduces the bypass capacitor value. 26/42 DocID024395 Rev 6 LED1642GW Configuration register Figure 22. Gradual output delay AM13703V1 8.8 PWM counter setting and brightness register (CFG-15) The brightness of each channel can be adjusted through a 12/16-bit PWM grayscale brightness control according to the PWM counter selection (configuration register CFG -15 bit). Brightness data is loaded by the SDI pin in a 16-bit shift register. Once 16-bit has been loaded (first input bit of brightness word is MSB, 16th bit is LSB), the digital word is moved to the corresponding temporary buffer (first word is the brightness of channel 15, the last one is for channel 0) using the appropriate key shown in Table 7 ("data latch"). One "data latch" key must follow each 16-bit brightness word except the last one. When the last brightness word is loaded (channel 0 brightness data), the key indicated as "global latch" in Table 7 must be used. This action moves the word from the shift register to the temporary buffer through the OUT0 and, at the same time, transfers all data of the 16 temporary buffers (16 x16-bit string) to the corresponding brightness registers (see also Figure 28). The PWM signals are generated by comparing the content of the brightness registers to a 16-bit or 12-bit counter, according to the CFG-15 bit status. The counter's clock source is provided to the PWCLK pin. In case of selection of 12-bit PWM counter, the four most significant bits of each brightness data word are ignored. However, each of sixteen brightness data words must be 16-bit long.The brightness register default value is "0", unless this value is changed, the LED brightness is minimum. Figure 27 shows this function in the schematic. PWCLK must be a square wave signal, duty cycle is not important but the minimum width has to be above 20 ns, max. frequency has to be 30 MHz (pay attention the minimum output ON time). Just after the device startup (brightness counter reset), before applying PWCLK signal, all channels are in power-on condition if the brightness register values are not zeroed. DocID024395 Rev 6 27/42 42 Configuration register LED1642GW Figure 23. PWCLK counter and comparator AM13704V1 Figure 24. Brightness register setting SDI 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 CLK LE Data latch 16-bit Data Word BRT15 BRT13 BRT14 BRT03 BRT02 BRT01 BRT00 256-bit brightness data stream MSB SDI 0F LSB 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 CLK LE Global latch AM13705V1 28/42 DocID024395 Rev 6 LED1642GW 9 Thermal flag Thermal flag The device has a thermal control logic providing a flag status when the internal temperature exceeds 150 °C (if temperature increases over 170 °C a thermal shutdown protects the device). This status can be read running the digital key "thermal error reading", holding the LE high for 13 CLK rising edges (see Figure 25). If thermal alert is asserted, a 16-bit string = "1" is sent by SDO. The error data is uploaded into EDR register and this error notification is ready to be streamed through SDO to next 16 CLK rising edges. Hence, thermal flag status can be: Device temperature SDO under 150 °C “0000 0000 0000 0000” over 150 °C “1111 1111 1111 1111” Figure 25. Thermal flag status 13 Clock pulses with LE asserted Previous data Thermal Flag Status AM13706V1 DocID024395 Rev 6 29/42 42 Dropout voltage 10 LED1642GW Dropout voltage In order to correctly regulate the channel current, a minimum output voltage (VDROP) across each current generator must be guaranteed. The Figure 26 and Table 12 show the minimum VDROP related to the regulated current; these measurements have been recorded with just one output ON. When more than one output is active the drop voltage increases. At 36 mA per channel, the minimum output voltage must be increased about 200 mV. A VDROP, lower than the minimum recommended, implies the regulation of a current lower than the expected one. However an excess of VDROP increases the power dissipation. Figure 26. Typical channel dropout voltage vs. output current (VDD = 3.3 V) Drop vs. IOUT @ VDD = 3.3 V, T= 25°C (only one channel ON) 1200 VDROP [mV] 1000 800 600 400 200 0 0 5 10 15 20 25 30 35 40 45 50 55 IOUT [mA] AM13707V1 Table 12. Minimum dropout voltage for some current values 30/42 Output current [mA] Minimum VDROP @ VDD = 3.3 V [mV] 3 70 9 180 12 250 20 410 36 730 40 820 45 955 50 1070 DocID024395 Rev 6 LED1642GW 11 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID024395 Rev 6 31/42 42 Package information 11.1 LED1642GW QSOP-24 package information Figure 27. QSOP-24 package outline 32/42 DocID024395 Rev 6 LED1642GW Package information Table 13. QSOP-24 mechanical data mm Dim. Min. Typ. Max. A 1.54 1.62 1.73 A1 0.1 0.15 0.25 A2 1.47 b 0.31 0.2 c 0.254 0.17 D 8.56 8.66 8.76 E 5.8 6 6.2 E1 3.8 3.91 4.01 e 0.635 L 0.4 0.635 0.89 h 0.25 0.33 0.41 < 8° 0° DocID024395 Rev 6 33/42 42 Package information 11.2 LED1642GW QFN-24 package information Figure 28. QFN-24 package outline 34/42 DocID024395 Rev 6 LED1642GW Package information Table 14. QFN-24 mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0 0.02 0.05 A3 0.20 b 0.18 0.25 0.30 D 3.85 4.00 4.15 D2 2.00 2.15 2.25 E 3.85 4.00 4.15 E2 2.00 2.15 2.25 e L 0.50 0.30 DocID024395 Rev 6 0.40 0.50 35/42 42 Package information 11.3 LED1642GW TSSOP24 package information Figure 29. TSSOP24 package outline Table 15. TSSOP24 mechanical data mm Dim. Min. Typ. A A1 1.1 0.05 A2 0.15 0.9 b 0.19 0.30 c 0.09 0.20 D 7.7 7.9 E 4.3 4.5 e 36/42 Max. 0.65 BSC H 6.25 6.5 K 0° 8° L 0.50 0.70 DocID024395 Rev 6 LED1642GW 11.4 Package information TSSOP24 exposed pad package information Figure 30. TSSOP24 exposed pad outline DocID024395 Rev 6 37/42 42 Package information LED1642GW Table 16. TSSOP24 exposed pad mechanical data mm Dim. Min. Max. A 1.20 A1 0.15 A2 0.80 b 0.19 0.30 c 0.09 0.20 D 7.70 7.80 7.90 D1 4.80 5.00 5.20 E 6.20 6.40 6.60 E1 4.30 4.40 4.50 E2 3.00 3.20 3.40 e L k 1.00 1.05 0.65 0.45 L1 0.60 0.75 1.00 0 aaa 38/42 Typ. 8 0.10 DocID024395 Rev 6 LED1642GW 11.5 Package information TSSOP24 and TSSOP24 exposed pad packing information Figure 31. TSSOP24 and TSSOP24 exposed pad tape and reel outline Table 17. TSSOP24 and TSSOP24 exposed pad tape and reel mechanical data mm Dim. Min. A Typ. Max. - 330 13.2 C 12.8 - D 20.2 - N 60 - T - 22.4 Ao 6.8 - 7 Bo 8.2 - 8.4 Ko 1.7 - 1.9 Po 3.9 - 4.1 P 11.9 - 12.1 DocID024395 Rev 6 39/42 42 Ordering information 12 LED1642GW Ordering information Table 18. Ordering information 40/42 Order code Package Packing LED1642GWPTR QSOP-24 2500 parts per reel LED1642GWQTR QFN-24 4000 parts per reel LED1642GWTTR TSSOP24 2500 parts per reel LED1642GWXTTR TSSOP24 exposed pad 2500 parts per reel DocID024395 Rev 6 LED1642GW 13 Revision history Revision history Table 19. Document revision history Date Revision 03-May-2013 1 Initial release. 2 Updated Table 2: Absolute maximum ratings, Figure 10: Channel current vs. gain register value and Section 8.2: Error detection mode (CFG-7). Added Figure 13, 14, 15 and 16. Minor text changes. 19-Aug-2013 3 Updated the Title, the Features and the Description. Modified Table 4: Electrical characteristics, Updated Table 9: Example of current ranges, Table 10: Gain steps for the current range selected by REXT = 11 kW, Section 8.2: Error detection mode (CFG-7), Section 8.8: PWM counter setting and brightness register (CFG-15). 18-Mar-2014 4 Added footnote 1 in Table 5: Switching characteristics and footnote 5 in Table 4: Electrical characteristics. 16-Jun-2014 5 Updated Table 16: TSSOP24 exposed pad mechanical data. Minor text changes. 16-Nov-2015 6 Modified footnote 2 in Table 3: Thermal characteristics. Minor text changes. 06-Jun-2013 Changes DocID024395 Rev 6 41/42 42 LED1642GW IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 42/42 DocID024395 Rev 6