LIS2DE12
MEMS digital output motion sensor:
ultra-low-power high-performance 3-axis "femto" accelerometer
Datasheet - production data
Description
The LIS2DE12 is an ultra-low-power highperformance three-axis linear accelerometer
belonging to the “femto” family with digital I2C/SPI
serial interface standard output.
The LIS2DE12 has user-selectable full scales of
2g/±4g/8g/16g and is capable of measuring
accelerations with output data rates from 1 Hz to
5.3 kHz.
/*$ [[PP
Features
Wide supply voltage, 1.71 V to 3.6 V
Independent IO supply (1.8 V) and supply
voltage compatible
Ultra-low power consumption down to 2 μA
2g/±4g/8g/16g selectable full scales
I2C/SPI digital output interface
8-bit data output
2 independent programmable interrupt
generators for free-fall and motion detection
6D/4D orientation detection
The self-test capability allows the user to check
the functionality of the sensor in the final
application.
The device may be configured to generate
interrupt signals by detecting two independent
inertial wake-up/free-fall events as well as by the
position of the device itself.
The LIS2DE12 is available in a small thin plastic
land grid array package (LGA) and is guaranteed
to operate over an extended temperature range
from -40 °C to +85 °C.
“Sleep-to-wake” and “return-to-sleep” functions
Free-fall detection
Motion detection
Embedded temperature sensor
Embedded FIFO
Table 1. Device summary
Order code
Temp.
range [C]
Package
Packaging
LIS2DE12TR
-40 to +85
LGA-12
Tape and
reel
ECOPACK®, RoHS and “Green” compliant
Applications
Motion-activated functions
Display orientation
Shake control
Pedometer
Gaming and virtual reality input devices
Impact recognition and logging
January 2017
This is information on a product in full production.
DocID027326 Rev 2
1/51
www.st.com
Contents
LIS2DE12
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5
3
3.2
I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2
Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2
Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.3
6D / 4D orientation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.4
Sleep-to-wake and Return-to-sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
IC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.7
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Digital main blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
2/51
2.4.2
3.3
4.1
5
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Terminology and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
4
2.4.1
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID027326 Rev 2
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Contents
5.1.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3
Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4
Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.5
Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.1
6.2
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.1
SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.2
SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.3
SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.1
STATUS_REG_AUX (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.2
OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . 32
8.3
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.4
CTRL_REG0 (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.5
TEMP_CFG_REG (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.6
CTRL_REG1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.7
CTRL_REG2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.8
CTRL_REG3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.9
CTRL_REG4 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.10
CTRL_REG5 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.11
CTRL_REG6 (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.12
REFERENCE (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.13
STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.14
FIFO_READ_START (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
8.15
OUT_X_H (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.16
OUT_Y_H (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.17
OUT_Z_H (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.18
FIFO_CTRL_REG (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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10
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LIS2DE12
8.19
FIFO_SRC_REG (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.20
INT1_CFG (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.21
INT1_SRC (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.22
INT1_THS (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.23
INT1_DURATION (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.24
INT2_CFG (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.25
INT2_SRC (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.26
INT2_THS (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.27
INT2_DURATION (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.28
CLICK_CFG (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.29
CLICK_SRC (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.30
CLICK_THS (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.31
TIME_LIMIT (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.32
TIME_LATENCY (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.33
TIME_WINDOW (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.34
ACT_THS (3Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.35
ACT_DUR (3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1
LGA-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2
LGA-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DocID027326 Rev 2
LIS2DE12
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Internal pull-up values (typ.) for SDO/SA0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal pin status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
I2C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SAD+read/write patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 25
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 25
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STATUS_REG_AUX register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STATUS_REG_AUX description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CTRL_REG0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
CTRL_REG0 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
TEMP_CFG_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
TEMP_CFG_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CTRL_REG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CTRL_REG1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CTRL_REG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CTRL_REG2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Low-power mode - high-pass filter cutoff frequency [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CTRL_REG3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CTRL_REG3 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CTRL_REG4 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Self-test mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CTRL_REG5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CTRL_REG5 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CTRL_REG6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CTRL_REG6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
REFERENCE register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
REFERENCE description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STATUS_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
FIFO_READ_START register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID027326 Rev 2
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List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
6/51
LIS2DE12
FIFO_CTRL_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FIFO_CTRL_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
FIFO_SRC_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FIFO_SRC_REG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
INT1_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
INT1_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
INT1_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
INT1_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
INT2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
INT2_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
INT2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
INT2_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
INT2_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
INT2_THS description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
INT2_DURATION register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
INT2_DURATION description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CLICK_CFG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CLICK_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
CLICK_SRC register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CLICK_SRC description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CLICK_THS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
CLICK_THS register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TIME_LIMIT register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TIME_LIMIT description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
TIME_LATENCY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TIME_LATENCY description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TIME_WINDOW register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
TIME_WINDOW description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACT_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACT_THS description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACT_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ACT_DUR description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reel dimensions for carrier tape of LGA-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DocID027326 Rev 2
LIS2DE12
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LIS2DE12 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LGA-12: package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Carrier tape information for LGA-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
LGA-12 package orientation in carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Reel information for carrier tape of LGA-12 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DocID027326 Rev 2
7/51
51
Block diagram and pin description
LIS2DE12
1
Block diagram and pin description
1.1
Block diagram
Figure 1. Block diagram
X+
CHARGE
AMPLIFIER
Y+
Z+
a
CS
A/D
CONVERTER
MUX
I2C
CONTROL
LOGIC
SCL/SPC
SDA/SDI/SDO
SPI
Z-
SDO/SA0
YX-
SELF TEST
TRIMMING
CIRCUITS
Temperature
Sensor
CONTROL LOGIC
&
INTERRUPT GEN.
32 Level
FIFO
CLOCK
INT 1
INT 2
AM10218V2
1.2
Pin description
12
12
11
4 CS
8/51
4
6
5
5
(BOTTOM VIEW)
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
DocID027326 Rev 2
SCL/SPC
SDA/SDI/SDO
(BOTTOM VIEW)
(TOP VIEW)
1
1 CSSCL/SPC
7
Y
Pin 1 indicator
SDO/SA0
SDO/SA0
Vdd 8
7
GND
X
14
INT1
RES
INT2
RES
Vdd
RES
GND
GND
1
10
11
GND
Vdd_IO
Vdd_IO
RES
INT 1
RES
Z
INT 2
RES
Figure 2. Pin connections
SDA/SDI/SDO
LIS2DE12
Block diagram and pin description
Table 2. Pin description
Pin#
Name
1
SCL
SPC
Function
I2C serial clock (SCL)
SPI serial port clock (SPC)
SPI enable
2
CS
I2C/SPI mode selection:
1: SPI idle mode / I2C communication enabled
0: SPI communication mode / I2C disabled
3(1)
SDO
SA0
SPI serial data output (SDO)
I2C less significant bit of the device address (SA0)
4
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
5
Res
Connect to GND
6
GND
0 V supply
7
GND
0 V supply
8
GND
0 V supply
9
Vdd
Power supply
10
Vdd_IO
11
INT2
Interrupt pin 2
12
INT1
Interrupt pin 1
Power supply for I/O pins
1. SDO/SA0 pin is internally pulled up. Refer to Table 3 for the internal pull-up values (typ).
Table 3. Internal pull-up values (typ.) for SDO/SA0 pin
Resistor value for SDO/SA0 pin
Vdd_IO
Typ. (kΩ)
1.7 V
54.4
1.8 V
49.2
2.5 V
30.4
3.6 V
20.4
DocID027326 Rev 2
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51
Mechanical and electrical specifications
LIS2DE12
2
Mechanical and electrical specifications
2.1
Mechanical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a)
Table 4. Mechanical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.(1)
Max.
Unit
FS bits set to 00
±2.0
FS bits set to 01
±4.0
FS bits set to 10
±8.0
FS bits set to 11
±16.0
FS bits set to 00
Normal mode
15.6
FS bits set to 01
Normal mode
31.2
FS bits set to 10
Normal mode
62.5
FS bits set to 11
Normal mode
187.5
TCSo
Sensitivity change vs.
FS bits set to 00
temperature
±0.05
%/°C
TyOff
Typical zero-g level
offset accuracy(3)
FS bits set to 00
±100
mg
TCOff
Zero-g level change
vs. temperature
Max delta from 25 °C
±0.5
mg/°C
FS
So
Vst
Top
Measurement range(2)
Sensitivity
g
mg/digit
FS bits set to 00
X-axis; Normal mode
4
90
LSb
FS bits set to 00
Self-test
output change(4) (5) (6) Y-axis; Normal mode
4
90
LSb
FS bits set to 00
Z-axis; Normal mode
4
90
LSb
-40
+85
°C
Operating
temperature range
1. Typical specifications are not guaranteed.
2. Verified by wafer level test and measurement of initial offset and sensitivity.
3. Typical zero-g level offset value after factory calibration test at socket level.
4. The sign of “Self-test output change” is defined by the ST bits in CTRL_REG4 (23h), for all axes.
5. “Self-test output change” is defined as the absolute value of:
OUTPUT[LSb](Self test enabled) - OUTPUT[LSb](Self test disabled). 1LSb =15.6 g at 8-bit representation, ±2 g full scale
6. After enabling the ST bit, correct data is obtained after two samples, normal mode.
a. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.
10/51
DocID027326 Rev 2
LIS2DE12
2.2
Mechanical and electrical specifications
Temperature sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(b)
Table 5. Temperature sensor characteristics
Symbol
Parameter
TSDr
Temperature sensor output change vs. temperature
TODR
Temperature refresh rate
Top
Min.
Operating temperature range
Typ.(1)
Max.
Unit
1
digit/°C(2)
ODR(3)
Hz
-40
+85
°C
1. Typical specifications are not guaranteed.
2. 8-bit resolution.
3. Refer to Table 30.
2.3
Electrical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(c)
Table 6. Electrical characteristics
Symbol
Vdd
Vdd_IO
Parameter
Test conditions
Supply voltage
I/O pins supply
voltage(2)
IddLP
Current consumption
in normal mode
IddPdn
Current consumption
in power-down mode
VIH
Digital high-level input voltage
VIL
Digital low-level input voltage
VOH
High-level output voltage
VOL
Low-level output voltage
Top
Operating temperature range
Min.
Typ.(1)
Max.
Unit
1.71
2.5
3.6
V
Vdd+0.1
V
1.71
50 Hz ODR
6
μA
0.5
μA
0.8*Vdd_IO
V
0.2*Vdd_IO
0.9*Vdd_IO
-40
V
V
0.1*Vdd_IO
V
+85
°C
1. Typical specification are not guaranteed.
2. It is possible to remove Vdd maintaining Vdd_IO without blocking the communication busses, in this condition the
measurement chain is powered off.
b. The product is factory calibrated at 2.5 V. Temperature sensor operation is guaranteed in the range 2 V - 3.6 V.
c. The product is factory calibrated at 2.5 V. The operational power supply range is from 1.71 V to 3.6 V.
DocID027326 Rev 2
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51
Mechanical and electrical specifications
LIS2DE12
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 7. SPI slave timing values
Value (1)
Symbol
Parameter
Unit
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
20
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
SDO output disable time
Max
100
ns
10
MHz
ns
50
5
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production.
Figure 3. SPI slave timing diagram
CS
(1)
(1)
tc(SPC)
tsu(CS)
SPC
(1)
(1)
tsu(SI)
SDI
(1)
th(SI)
LSB IN
MSB IN
tv(SO)
SDO
th(CS)
(1)
tdis(SO)
th(SO)
MSB OUT
(1)
LSB OUT
1. When no communication is ongoing, data on SDO is driven by internal pull-up resistors.
Note:
12/51
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output
ports.
DocID027326 Rev 2
(1)
LIS2DE12
Mechanical and electrical specifications
I2C - inter-IC control interface
2.4.2
Subject to general operating conditions for Vdd and top.
Table 8. I2C slave timing values
Symbol
f(SCL)
I2C standard mode (1)
Parameter
SCL clock frequency
I2C fast mode (1)
Min
Max
Min
Max
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
tw(SP:SR)
Bus free time between STOP
and START condition
3.45
Unit
kHz
μs
ns
0
0.9
μs
μs
1. Data based on standard I2C protocol requirement, not tested in production.
Figure 4. I2C slave timing diagram
REPEATED
START
START
tsu(SR)
START
tw(SP:SR)
SDA
tsu(SDA)
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
Note:
tw(SCLL)
tw(SCLH)
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
DocID027326 Rev 2
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51
Mechanical and electrical specifications
2.5
LIS2DE12
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 9. Absolute maximum ratings
Symbol
Vdd
Vdd_IO
Vin
Note:
Ratings
Maximum value
Unit
Supply voltage
-0.3 to 4.8
V
Supply voltage on I/O pins
-0.3 to 4.8
V
-0.3 to Vdd_IO +0.3
V
Input voltage on any control pin
(CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
APOW
Acceleration (any axis, powered, Vdd = 2.5 V)
AUNP
Acceleration (any axis, unpowered)
3000 g for 0.5 ms
10000 g for 0.2 ms
3000 g for 0.5 ms
10000 g for 0.2 ms
TOP
Operating temperature range
-40 to +85
°C
TSTG
Storage temperature range
-40 to +125
°C
ESD
Electrostatic discharge protection (HBM)
2
kV
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.
14/51
DocID027326 Rev 2
LIS2DE12
Terminology and functionality
3
Terminology and functionality
3.1
Terminology
3.1.1
Sensitivity
Sensitivity describes the gain of the sensor and can be determined by applying 1 g
acceleration to it. As the sensor can measure DC accelerations, this can be done easily by
pointing the axis of interest towards the center of the Earth, noting the output value, rotating
the sensor by 180 degrees (pointing to the sky) and noting the output value again. By doing
so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the
smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This
value changes very little over temperature and time. The sensitivity tolerance describes the
range of sensitivities of a large population of sensors.
3.1.2
Zero-g level
The zero-g level offset (TyOff) describes the deviation of an actual output signal from the
ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal
surface will measure 0 g for the X-axis and 0 g for the Y-axis whereas the Z-axis will
measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content
of OUT registers 00h, data expressed as two’s complement number). A deviation from the
ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to
the MEMS sensor and therefore the offset can slightly change after mounting the sensor on
a printed circuit board or exposing it to extensive mechanical stress. Offset changes little
over temperature, see Table 4 “Zero-g level change vs. temperature” (TCOff). The zero-g
level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a
population of sensors.
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51
Terminology and functionality
3.2
Functionality
3.2.1
Normal mode
LIS2DE12
The LIS2DE12 provides a normal operating mode (see table below).
Table 10. Normal mode
Operating mode
So @ ±2g
BW [Hz]
Turn-on time
[ms]
[mg/digit]
ODR/2
1
16
Normal mode
Table 11. Current consumption
ODR [Hz]
3.2.2
Normal mode [μA]
1
2
10
3
25
4
50
6
100
10
200
18
400
36
1620
100
5376
185
Self-test
The self-test allows the user to check the sensor functionality without moving it. When the
self-test is enabled, an actuation force is applied to the sensor, simulating a definite input
acceleration. In this case the sensor outputs will exhibit a change in their DC levels which
are related to the selected full scale through the device sensitivity. When the self-test is
activated, the device output level is given by the algebraic sum of the signals produced by
the acceleration acting on the sensor and by the electrostatic test-force. If the output signals
change within the amplitude specified inside Table 4, then the sensor is working properly
and the parameters of the interface chip are within the defined specifications.
3.2.3
6D / 4D orientation detection
The LIS2DE12 provides the capability to detect the orientation of the device in space,
enabling easy implementation of energy-saving procedures and automatic image rotation
for mobile devices.
The 4D detection is a subset of the 6D function especially defined to be implemented in
mobile devices for portrait and landscape computation. In 4D configuration, the Z-axis
position detection is disabled.
16/51
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LIS2DE12
3.2.4
Terminology and functionality
Sleep-to-wake and Return-to-sleep
The LIS2DE12 can be programmed to automatically switch to low-ODR mode upon
recognition of a determined event.
Once the event condition is over, the device returns back to the preset ODR.
To enable this function the desired threshold value must be stored inside the ACT_THS
(3Eh) register while the duration value is written inside the ACT_DUR (3Fh) register.
When the acceleration falls below the threshold value for a period of time longer than the
duration value, the device ODR automatically switches to 10 Hz ODR.
During this condition, the ODR[3:0] bits inside CTRL_REG1 (20h) are not considered.
As soon as the acceleration rises above threshold, the module restores the operating mode
and ODRs as determined by the CTRL_REG1 (20h) register setting.
3.3
Sensing element
A proprietary process is used to create a surface micromachined accelerometer. The
technology processes suspended silicon structures which are attached to the substrate in a
few points called anchors and are free to move in the direction of the sensed acceleration.
To be compatible with traditional packaging techniques, a cap is placed on top of the
sensing element to avoid blocking the moving parts during the molding phase of the plastic
encapsulation.
When an acceleration is applied to the sensor, the proof mass displaces from its nominal
position, causing an imbalance in the capacitive half-bridge. This imbalance is measured
using charge integration in response to a voltage pulse applied to the capacitor.
At steady state the nominal value of the capacitors are a few pF and when an acceleration is
applied, the maximum variation of the capacitive load is in the fF range.
3.4
IC interface
The complete measurement chain is composed of a low-noise capacitive amplifier which
converts the capacitive unbalance of the MEMS sensor into an analog voltage that will be
available to the user through an analog-to-digital converter.
The acceleration data may be accessed through an I2C/SPI interface, thus making the
device particularly suitable for direct interfacing with a microcontroller.
The LIS2DE12 features a data-ready signal (DRDY) which indicates when a new set of
measured acceleration data is available, thus simplifying data synchronization in the digital
system that uses the device.
The LIS2DE12 may also be configured to generate an inertial wake-up and free-fall interrupt
signal according to a programmed acceleration event along the enabled axes. Both free-fall
and wake-up can be available simultaneously on two different pins.
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Terminology and functionality
3.5
LIS2DE12
Factory calibration
The IC interface is factory calibrated for sensitivity (So) and zero-g level (TyOff).
The trim values are stored inside the device in non-volatile memory. Any time the device is
turned on, these values are downloaded into the registers to be used during active
operation. This allows using the device without further calibration.
3.6
FIFO
The LIS2DE12 contains a 10-bit, 32-level FIFO. Buffered output allows the following
operation modes: FIFO, Stream, Stream-to-FIFO and FIFO bypass. When FIFO bypass
mode is activated, FIFO is not operating and remains empty. In FIFO mode, measurement
data from acceleration detection on the x, y, and z-axes are stored in the FIFO buffer.
3.7
Temperature sensor
In order to enable the internal temperature sensor, bits TEMP_EN[1:0] in register
TEMP_CFG_REG (1Fh) and the BDU bit in CTRL_REG4 (23h) have to be set.
The temperature is available in OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh) stored as two’s
complement data, left-justified.
Refer to Table 5: Temperature sensor characteristics for the conversion factor.
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Application hints
Figure 5. LIS2DE12 electrical connections
Vdd_IO
100nF
SCL/SPC
1
INT 2
INT 1
Vdd
12
10μF
11
10
CS
SDO/SA0
GND
4
5
6
7
100nF
GND
GND
SDA/SDI/SDO
Vdd_IO
Vdd
RES
4
Application hints
GND
Digital signal from/to signal controller. Signal levels are defined by proper selection of Vdd_IO
The device core is supplied through the Vdd line while the I/O pads are supplied through the
Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10 μF aluminum) should
be placed as near as possible to pin 9 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper
behavior of the IC (refer to Figure 5). It is possible to remove Vdd while maintaining Vdd_IO
without blocking the communication bus, in this condition the measurement chain is
powered off.
The functionality of the device and the measured acceleration data is selectable and
accessible through the I2C or SPI interfaces. When using the I2C, CS must be tied high.
The functions, the threshold and the timing of the two interrupt pins (INT1 and INT2) can be
completely programmed by the user through the I2C/SPI interface.
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Application hints
LIS2DE12
Table 12. Internal pin status
Pin#
1
Name
SCL
SPC
Function
Pin status
2
I C serial clock (SCL)
SPI serial port clock (SPC)
Default: input high impedance
SPI enable
2
CS
I2C/SPI mode selection:
1: SPI idle mode / I2C communication enabled
Default: input high impedance
0: SPI communication mode / I2C disabled
3
SDO
SA0
SPI serial data output (SDO)
Default: input with internal pull-up(1)
I2C less significant bit of the device address (SA0)
4
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
5
Res
Connect to GND
6
GND
0 V supply
7
GND
0 V supply
8
GND
0 V supply
9
Vdd
Power supply
10
Vdd_IO
11
INT2
Interrupt pin 2
Default: push-pull output forced to GND
12
INT1
Interrupt pin 1
Default: push-pull output forced to GND
Default: (SDA) input high impedance
Power supply for I/O pins
1. In order to disable the internal pull-up on the SDO/SA0 pin, write 90h in CTRL_REG0 (1Eh).
4.1
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com.
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Digital main blocks
5
Digital main blocks
5.1
FIFO
The LIS2DE12 embeds a 32-level FIFO for each of the three output channels, X, Y and Z.
This allows consistent power saving for the system, since the host processor does not need
to continuously poll data from the sensor, but it can wake up only when needed and burst
the significant data out from the FIFO.
In order to enable the FIFO buffer, the FIFO_EN bit in CTRL_REG5 (24h) must be set to ‘1’.
This buffer can work according to the following different modes: Bypass mode, FIFO mode,
Stream mode and Stream-to-FIFO mode. Each mode is selected by the FM [1:0] bits in
FIFO_CTRL_REG (2Eh). Programmable FIFO watermark level, FIFO empty or FIFO
overrun events can be enabled to generate dedicated interrupts on the INT1 pin
(configuration through CTRL_REG3 (22h)).
In the FIFO_SRC_REG (2Fh) register the EMPTY bit is equal to ‘1’ when all FIFO samples
are ready and FIFO is empty.
In the FIFO_SRC_REG (2Fh) register the WTM bit goes to ‘1’ if new data is written in the
buffer and FIFO_SRC_REG (2Fh) (FSS [4:0]) is greater than or equal to FIFO_CTRL_REG
(2Eh) (FTH [4:0]). FIFO_SRC_REG (2Fh) (WTM) goes to ‘0’ if reading an X, Y, Z data slot
from FIFO and FIFO_SRC_REG (2Fh) (FSS [4:0]) is less than or equal to
FIFO_CTRL_REG (2Eh) (FTH [4:0]).
In the FIFO_SRC_REG (2Fh) register the OVRN_FIFO bit is equal to ‘1’ if the FIFO slot is
overwritten.
5.1.1
Bypass mode
In Bypass mode the FIFO is not operational and for this reason it remains empty. For each
channel only the first address is used. The remaining FIFO levels are empty.
Bypass mode must be used in order to reset the FIFO buffer when a different mode is
operating (i.e. FIFO mode).
5.1.2
FIFO mode
In FIFO mode, the buffer continues filling data from the X, Y and Z accelerometer channels
until it is full (a set of 32 samples stored). When the FIFO is full, it stops collecting data from
the input channels and the FIFO content remains unchanged.
An overrun interrupt can be enabled, I1_OVERRUN = '1' in the CTRL_REG3 (22h) register,
in order to be raised when the FIFO stops collecting data. When the overrun interrupt
occurs, the first data has been overwritten and the FIFO stops collecting data from the input
channels.
After the last read it is necessary to transit from Bypass mode in order to reset the FIFO
content. After this reset command, it is possible to restart FIFO mode just by selecting the
FIFO mode configuration (FM[1:0] bits) in register FIFO_CTRL_REG (2Eh).
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Digital main blocks
5.1.3
LIS2DE12
Stream mode
In Stream mode the FIFO continues filling data from the X, Y, and Z accelerometer channels
until the buffer is full (a set of 32 samples stored) at which point the FIFO buffer index
restarts from the beginning and older data is replaced by the current data. The oldest values
continue to be overwritten until a read operation frees the FIFO slots.
An overrun interrupt can be enabled, I1_OVERRUN = '1' in the CTRL_REG3 (22h) register,
in order to read the entire contents of the FIFO at once. If, in the application, it is mandatory
not to lose data and it is not possible to read at least one sample for each axis within one
ODR period, a watermark interrupt can be enabled in order to read partially the FIFO and
leave memory slots free for incoming data.
Setting the FTH [4:0] bit in the FIFO_CTRL_REG (2Eh) register to an N value, the number
of X, Y and Z data samples that should be read at the rise of the watermark interrupt is up to
(N+1).
5.1.4
Stream-to-FIFO mode
In Stream-to-FIFO mode, data from the X, Y and Z accelerometer channels are collected in
a combination of Stream mode and FIFO mode. The FIFO buffer starts operating in Stream
mode and switches to FIFO mode when the selected interrupt occurs.
The FIFO operating mode changes according to the INT1 pin value if the TR bit is set to ‘0’
in the FIFO_CTRL_REG (2Eh) register or the INT2 pin value if the TR bit is set to‘1’ in the
FIFO_CTRL_REG (2Eh) register.
When the interrupt pin is selected and the interrupt event is configured on the corresponding
pin, the FIFO operates in Stream mode if the pin value is equal to ‘0’ and it operates in FIFO
mode if the pin value is equal to ‘1’. Switching modes is dynamically performed according to
the pin value.
Stream-to-FIFO can be used in order to analyze the sampling history that generates an
interrupt. The standard operation is to read the contents of FIFO when the FIFO mode is
triggered and the FIFO buffer is full and stopped.
5.1.5
Retrieving data from FIFO
FIFO data is read from OUT_X_H (29h), OUT_Y_H (2Bh) and OUT_Z_H (2Dh). When the
FIFO is in Stream, Stream-to-FIFO or FIFO mode, a read operation starts from
FIFO_READ_START (28h), performs a 6-byte read and provides the data stored in the
FIFO by reading OUT_X_H (29h), OUT_Y_H (2Bh) and OUT_Z_H (2Dh). Each time data is
read from the FIFO, the oldest X, Y and Z data are placed in the OUT_X_H (29h),
OUT_Y_H (2Bh) and OUT_Z_H (2Dh) registers and both single-read and read-burst
operations can be used.
The address to be read is automatically updated by the device and it rolls back to 0x28
when register 0x2D is reached. In order to read all FIFO levels in a multiple byte read,192
bytes (6 output registers of 32 levels) have to be read.
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6
Digital interfaces
Digital interfaces
The registers embedded inside the LIS2DE12 may be accessed through both the I2C and
SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire
interface mode.
The serial interfaces are mapped to the same pads. To select/exploit the I2C interface, the
CS line must be tied high (i.e. connected to Vdd_IO).
Table 13. Serial interface pin description
Pin name
CS
6.1
Pin description
SPI enable
I2C/SPI mode selection:
1: SPI idle mode / I2C communication enabled
0: SPI communication mode / I2C disabled
SCL
SPC
I2C serial clock (SCL)
SPI serial port clock (SPC)
SDA
SDI
SDO
I2C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
SA0
SDO
I2C less significant bit of the device address (SA0)
SPI serial data output (SDO)
I2C serial interface
The LIS2DE12 I2C is a bus slave. The I2C is employed to write data into registers whose
content can also be read back.
The relevant I2C terminology is given in the table below.
Table 14. I2C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving data to/from
the interface. Both the lines must be connected to Vdd_IO through an external pull-up
resistor. When the bus is free, both the lines are high.
The I2C interface is compliant with fast mode (400 kHz) I2C standards as well as with
normal mode.
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Digital interfaces
6.1.1
LIS2DE12
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After
this has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a start condition with its address. If they match, the device considers itself addressed
by the master.
The Slave ADdress (SAD) associated to the LIS2DE12 is 001100xb. The SDO/SA0 pad can
be used to modify the less significant bit of the device address. If the SA0 pad is connected
to the voltage supply, LSb is ‘1’ (address 0011001b), else if the SA0 pad is connected to
ground, the LSb value is ‘0’ (address 0011000b). This solution permits to connect and
address two different accelerometers to the same I2C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line LOW so that it
remains stable low during the HIGH period of the acknowledge clock pulse. A receiver
which has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LIS2DE12 behaves like a slave device and the following
protocol must be adhered to. After the start condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSb represent the actual register address while the MSb enables address auto increment.
If the MSb of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/writes.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write)
the master will transmit to the slave with direction unchanged. Table 15 explains how the
SAD+read/write bit pattern is composed, listing all the possible configurations.
Table 15. SAD+read/write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
001100
0
1
00110001 (31h)
Write
001100
0
0
00110000 (30h)
Read
001100
1
1
00110011 (33h)
Write
001100
1
0
00110010 (32h)
Table 16. Transfer when master is writing one byte to slave
Master
Slave
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ST
SAD + W
SUB
SAK
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DATA
SAK
SP
SAK
LIS2DE12
Digital interfaces
Table 17. Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
Slave
SAK
DATA
DATA
SAK
SP
SAK
SAK
Table 18. Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
Slave
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Table 19. Transfer when master is receiving (reading) multiple bytes of data from slave
Master
Slave
ST
SAD+W
SUB
SAK
SR SAD+R
SAK
MAK
SAK DATA
MAK
DATA
NMAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL low to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A low-to-high transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of the first register to be read.
In the presented communication format MAK is Master acknowledge and NMAK is No
Master Acknowledge.
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Digital interfaces
6.2
LIS2DE12
SPI bus interface
The LIS2DE12 SPI is a bus slave. The SPI allows writing to and reading from the registers
of the device.
The serial interface interacts with the application using 4 wires: CS, SPC, SDI and SDO.
Figure 6. Read and write protocol
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CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of
the transmission and goes back high at the end. SPC is the serial port clock and it is
controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and
SDO are respectively the serial port data input and output. These lines are driven at the
falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in
multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling
edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge
of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the
rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)
from the device is read. In the latter case, the chip will drive SDO at the start of bit 8.
bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands.
When 1, the address is auto incremented in multiple read/write commands.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the
MS bit is ‘0’, the address used to read/write data remains the same for every block. When
the MS bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
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6.2.1
Digital interfaces
SPI read
Figure 7. SPI read protocol
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The SPI read command is performed with 16 clock pulses. A multiple byte read command is
performed by adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in
multiple reads.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb
first).
bit 16-... : data DO(...-8). Further data in multiple byte reads.
Figure 8. Multiple byte SPI read protocol (2-byte example)
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Digital interfaces
6.2.2
LIS2DE12
SPI write
Figure 9. SPI write protocol
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The SPI write command is performed with 16 clock pulses. A multiple byte write command
is performed by adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in
multiple writes.
bit 2 -7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb
first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 10. Multiple byte SPI write protocol (2-byte example)
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6.2.3
Digital interfaces
SPI read in 3-wire mode
3-wire mode is entered by setting the SIM bit (SPI serial interface mode selection) to ‘1’ in
CTRL_REG4 (23h).
Figure 11. SPI read protocol in 3-wire mode
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The SPI read command is performed with 16 clock pulses.
bit 0: READ bit. The value is 1.
bit 1: MS bit. When 0, does not increment the address; when 1, increments the address in
multiple reads.
bit 2-7: address AD(5:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
The multiple read command is also available in 3-wire mode.
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Register mapping
7
LIS2DE12
Register mapping
The table given below provides a list of the 8-bit registers embedded in the device and the
corresponding addresses.
Table 20. Register address map
Register address
Name
Type
Default
Hex
Reserved
-
00 - 06
STATUS_REG_AUX
r
07
Reserved
-
08-0B
OUT_TEMP_L
r
0C
000 1100
Output
OUT_TEMP_H
r
0D
000 1101
Output
Reserved
-
0E
000 1110
WHO_AM_I
r
0F
000 1111
Reserved
-
10 - 1D
CTRL_REG0
rw
1E
001 1110
00010000
TEMP_CFG_REG
rw
1F
001 1111
00000000
CTRL_REG1
rw
20
010 0000
00000111
CTRL_REG2
rw
21
010 0001
00000000
CTRL_REG3
rw
22
010 0010
00000000
CTRL_REG4
rw
23
010 0011
00000000
CTRL_REG5
rw
24
010 0100
00000000
CTRL_REG6
rw
25
010 0101
00000000
REFERENCE
rw
26
010 0110
00000000
STATUS_REG
r
27
010 0111
Output
FIFO_READ_START
r
28
00101000
00000000
OUT_X_H
r
29
010 1001
Output
Reserved
r
2A
OUT_Y_H
r
2B
Reserved
r
2C
OUT_Z_H
r
2D
010 1101
Output
FIFO_CTRL_REG
rw
2E
010 1110
00000000
FIFO_SRC_REG
r
2F
010 1111
Output
INT1_CFG
rw
30
011 0000
00000000
INT1_SRC
r
31
011 0001
Output
INT1_THS
rw
32
011 0010
00000000
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Comment
Binary
Reserved
000 0111
Output
Reserved
Reserved
00110011
Reserved
Reserved
010 1011
Output
Reserved
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LIS2DE12
Register mapping
Table 20. Register address map (continued)
Register address
Name
Type
Default
Hex
Binary
INT1_DURATION
rw
33
011 0011
00000000
INT2_CFG
rw
34
011 0100
00000000
INT2_SRC
r
35
011 0101
Output
INT2_THS
rw
36
011 0110
00000000
INT2_DURATION
rw
37
011 0111
00000000
CLICK_CFG
rw
38
011 1000
00000000
CLICK_SRC
r
39
011 1001
Output
CLICK_THS
rw
3A
011 1010
00000000
TIME_LIMIT
rw
3B
011 1011
00000000
TIME_LATENCY
rw
3C
011 1100
00000000
TIME_WINDOW
rw
3D
011 1101
00000000
ACT_THS
rw
3E
011 1110
00000000
ACT_DUR
rw
3F
011 1111
00000000
Comment
Registers marked as Reserved or not listed in the table above must not be changed. Writing
to those registers may cause permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibration values. Their content is automatically restored when the device is
powered up.
The boot procedure is complete within 5 milliseconds after device power-up.
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Register description
LIS2DE12
8
Register description
8.1
STATUS_REG_AUX (07h)
Table 21. STATUS_REG_AUX register
--
TOR
--
--
--
TDA
--
--
Table 22. STATUS_REG_AUX description
8.2
TOR
Temperature data overrun. Default value: 0
(0: no overrun has occurred;
1: new temperature data has overwritten the previous data)
TDA
Temperature new data available. Default value: 0
(0: new temperature data is not yet available;
1: new temperature data is available)
OUT_TEMP_L (0Ch), OUT_TEMP_H (0Dh)
Temperature sensor data. Refer to Section 3.7: Temperature sensor for details on how to
enable and read the temperature sensor output data.
8.3
WHO_AM_I (0Fh)
Table 23. WHO_AM_I register
0
0
1
1
0
0
1
1
Device identification register.
8.4
CTRL_REG0 (1Eh)
Table 24. CTRL_REG0 register
SDO_PU_DISC
0(1)
0(1)
1(2)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to 0 for correct operation of the device.
2. This bit must be set to 1 for correct operation of the device.
Table 25. CTRL_REG0 description
Disconnect SDO/SA0 pull-up. Default value: 00010000
SDO_PU_DISC (0: pull-up connected to SDO/SA0 pin;
1: pull-up disconnected to SDO/SA0 pin)
Note:
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Leave bits 0 through 6 at the default value in order to ensure correct operation of the device.
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8.5
Register description
TEMP_CFG_REG (1Fh)
Table 26. TEMP_CFG_REG register
TEMP_EN1 TEMP_EN0
0
0
0
0
0
0
Yen
Xen
Table 27. TEMP_CFG_REG description
TEMP_EN[1:0]
8.6
Temperature sensor (T) enable. Default value: 00
(00: T disabled; 11: T enabled)
CTRL_REG1 (20h)
Table 28. CTRL_REG1 register
ODR3
ODR2
ODR1
ODR0
LPen
Zen
Table 29. CTRL_REG1 description
ODR[3:0]
Data rate selection. Default value: 0000
(0000: power-down mode; others: refer to Table 30)
LPen
This bit must be set to '1' for the correct operation of the device. Default value: 0
Zen
Z-axis enable. Default value: 1
(0: Z-axis disabled; 1: Z-axis enabled)
Yen
Y-axis enable. Default value: 1
(0: Y-axis disabled; 1: Y-axis enabled)
Xen
X-axis enable. Default value: 1
(0: X-axis disabled; 1: X-axis enabled)
ODR[3:0] is used to set the power mode and ODR selection. The following table indicates
the frequency for each available combination of ODR[3:0].
Table 30. Data rate configuration
ODR3
ODR2
ODR1
ODR0
Power mode selection
0
0
0
0
Power-down mode
0
0
0
1
Normal mode (1 Hz)
0
0
1
0
Normal mode (10 Hz)
0
0
1
1
Normal mode (25 Hz)
0
1
0
0
Normal mode (50 Hz)
0
1
0
1
Normal mode (100 Hz)
0
1
1
0
Normal mode (200 Hz)
0
1
1
1
Normal mode (400 Hz)
1
0
0
0
Normal mode (1.620 kHz)
1
0
0
1
Normal mode (5.376 kHz)
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51
Register description
8.7
LIS2DE12
CTRL_REG2 (21h)
Table 31. CTRL_REG2 register
HPM1
HPM0
HPCF2
HPCF1
FDS
HPCLICK
HP_IA2
HP_IA1
Table 32. CTRL_REG2 description
HPM[1:0]
High-pass filter mode selection. Default value: 00
Refer to Table 33 for filter mode configuration
HPCF[2:1]
High-pass filter cutoff frequency selection. Refer to Table 34 for HP filter mode
configuration.
FDS
Filtered data selection. Default value: 0
(0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO)
HPCLICK
High-pass filter enabled for CLICK function.
(0: filter bypassed; 1: filter enabled)
HP_IA2
High-pass filter enabled for AOI function on Interrupt 2.
(0: filter bypassed; 1: filter enabled)
HP_IA1
High-pass filter enabled for AOI function on Interrupt 1.
(0: filter bypassed; 1: filter enabled)
Table 33. High-pass filter mode configuration
HPM1
HPM0
High-pass filter mode
0
0
Normal mode (reset by reading REFERENCE (26h) register)
0
1
Reference signal for filtering
1
0
Normal mode
1
1
Autoreset on interrupt event
Table 34. Low-power mode - high-pass filter cutoff frequency [Hz]
HPCF[2:1]
ft [Hz]
@ 1 Hz
ODR
ft [Hz]
@ 10 Hz
ODR
ft [Hz]
@ 25 Hz
ODR
00
0.02
0.2
0.5
1
2
4
8
32
100
01
0.008
0.08
0.2
0.5
1
2
4
16
50
10
0.004
0.04
0.1
0.2
0.5
1
2
8
25
11
0.002
0.02
0.05
0.1
0.2
0.5
1
4
12
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ft [Hz]
ft [Hz]
ft [Hz]
ft [Hz]
ft [Hz]
ft [Hz]
@ 50 Hz @ 100 Hz @ 200 Hz @ 400 Hz @ 1.6 kHz @ 5 kHz
ODR
ODR
ODR
ODR
ODR
ODR
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8.8
Register description
CTRL_REG3 (22h)
Table 35. CTRL_REG3 register
I1_CLICK
I1_IA1
I1_IA2
0(1)
I1_ZYXDA
I1_WTM
I1_OVERRUN
--
1. This bit must be set to ‘0’ for correct operation of the device.
Table 36. CTRL_REG3 description
8.9
I1_CLICK
CLICK interrupt on INT1 pin. Default value: 0
(0: disable; 1: enable)
I1_IA1
IA1 interrupt on INT1 pin. Default value: 0
(0: disable; 1: enable)
I1_IA2
IA2 interrupt on INT1 pin. Default value: 0
(0: disable; 1: enable)
I1_ZYXDA
ZYXDA interrupt on INT1 pin. Default value: 0
(0: disable; 1: enable)
I1_WTM
FIFO watermark interrupt on INT1 pin. Default value: 0
(0: disable; 1: enable)
I1_OVERRUN
FIFO overrun interrupt on INT1 pin. Default value: 0
(0: disable; 1: enable)
CTRL_REG4 (23h)
Table 37. CTRL_REG4 register
0(1)
BDU
FS1
0(1)
FS0
ST1
ST0
SIM
1. This bit must be set to ‘0’ for correct operation of the device.
Table 38. CTRL_REG4 description
BDU
Block data update. Default value: 0
(0: continuous update; 1: output registers not updated until MSB and LSB
have been read)
FS[1:0]
Full-scale selection. Default value: 00
(00: ±2g; 01: ±4g; 10: ±8g; 11: ±16g)
ST[1:0]
Self-test enable. Default value: 00
(00: self-test disabled; other: see Table 39)
SIM
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface).
Table 39. Self-test mode configuration
ST1
ST0
Self-test mode
0
0
Normal mode
0
1
Self-test 0
1
0
Self-test 1
1
1
-
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51
Register description
8.10
LIS2DE12
CTRL_REG5 (24h)
Table 40. CTRL_REG5 register
BOOT
FIFO_EN
0(1)
0(1)
LIR_INT1
D4D_INT1
LIR_INT2
D4D_INT2
1. This bit must be set to 0 for correct operation of the device.
Table 41. CTRL_REG5 description
8.11
BOOT
Reboot memory content. Default value: 0
(0: normal mode; 1: reboot memory content)
FIFO_EN
FIFO enable. Default value: 0
(0: FIFO disabled; 1: FIFO enabled)
LIR_INT1
Latch interrupt request on INT1_SRC (31h), with INT1_SRC (31h) register cleared
by reading INT1_SRC (31h) itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
D4D_INT1
4D enable: 4D detection is enabled on INT1 pin when 6D bit on INT1_CFG (30h) is
set to 1.
LIR_INT2
Latch interrupt request on INT2_SRC (35h) register, with INT2_SRC (35h) register
cleared by reading INT2_SRC (35h) itself. Default value: 0.
(0: interrupt request not latched; 1: interrupt request latched)
D4D_INT2
4D enable: 4D detection is enabled on INT2 pin when 6D bit on INT2_CFG (34h) is
set to 1.
CTRL_REG6 (25h)
Table 42. CTRL_REG6 register
I2_CLICK
I2_IA1
I2_IA2
I2_BOOT
I2_ACT
0(1)
INT_POLARITY 0(1)
1. This bit must be set to 0 for correct operation of the device.
Table 43. CTRL_REG6 description
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I2_CLICK
Click interrupt on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
I2_IA1
Enable interrupt 1 function on INT2 pin. Default value: 0
(0: function disabled; 1: function enabled)
I2_IA2
Enable interrupt 2 function on INT2 pin. Default value: 0
(0: function disabled; 1: function enabled)
I2_BOOT
Enable boot on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
I2_ACT
Enable activity interrupt on INT2 pin. Default value: 0
(0: disabled; 1: enabled)
INT_POLARITY
INT1 and INT2 pin polarity. Default value: 0
(0: active-high; 1: active-low)
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8.12
Register description
REFERENCE (26h)
Table 44. REFERENCE register
Ref7
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
Table 45. REFERENCE description
Ref [7:0]
8.13
Reference value for interrupt generation. Default value: 0
STATUS_REG (27h)
Table 46. STATUS_REG register
ZYXOR
ZOR
YOR
XOR
ZYXDA
ZDA
YDA
XDA
Table 47. STATUS_REG description
8.14
ZYXOR
X-, Y- and Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: a new set of data has overwritten the previous set)
ZOR
Z-axis data overrun. Default value: 0
(0: no overrun has occurred; 1: new data for the Z-axis has overwritten the previous data)
YOR
Y-axis data overrun. Default value: 0
(0: no overrun has occurred;
1: new data for the Y-axis has overwritten the previous data)
XOR
X-axis data overrun. Default value: 0
(0: no overrun has occurred;
1: new data for the X-axis has overwritten the previous data)
ZYXDA
X-, Y- and Z-axis new data available. Default value: 0
(0: a new set of data is not yet available; 1: a new set of data is available)
ZDA
Z-axis new data available. Default value: 0
(0: new data for the Z-axis is not yet available;
1: new data for the Z-axis is available)
YDA
Y-axis new data available. Default value: 0
(0: new data for the Y-axis is not yet available;
1: new data for the Y-axis is available)
FIFO_READ_START (28h)
Acceleration data, refer to Section 5.1.5: Retrieving data from FIFO.
Table 48. FIFO_READ_START register
0
0
0
0
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0
0
0
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51
Register description
8.15
LIS2DE12
OUT_X_H (29h)
X-axis acceleration data. The value is expressed as two’s complement left-justified.
Please refer to Section 3.2.1: Normal mode.
8.16
OUT_Y_H (2Bh)
Y-axis acceleration data. The value is expressed as two’s complement left-justified.
Please refer to Section 3.2.1: Normal mode.
8.17
OUT_Z_H (2Dh)
Z-axis acceleration data. The value is expressed as two’s complement left-justified.
Please refer to Section 3.2.1: Normal mode.
8.18
FIFO_CTRL_REG (2Eh)
Table 49. FIFO_CTRL_REG register
FM1
FM0
TR
FTH4
FTH3
FTH2
Table 50. FIFO_CTRL_REG description
FM[1:0]
FIFO mode selection. Default value: 00 (see Table 51)
TR
Trigger selection. Default value: 0
0: trigger event allows triggering signal on INT1
1: trigger event allows triggering signal on INT2
FTH[4:0]
Default value: 00000
Table 51. FIFO mode configuration
FM1
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FM0
FIFO mode
0
0
Bypass mode
0
1
FIFO mode
1
0
Stream mode
1
1
Stream-to-FIFO mode
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FTH1
FTH0
LIS2DE12
8.19
Register description
FIFO_SRC_REG (2Fh)
Table 52. FIFO_SRC_REG register
WTM
OVRN_FIFO
EMPTY
FSS4
FSS3
FSS2
FSS1
FSS0
Table 53. FIFO_SRC_REG description
8.20
WTM
WTM bit is set high when FIFO content exceeds watermark level
OVRN_FIFO
OVRN bit is set high when FIFO buffer is full; this means that the FIFO buffer
contains 32 unread samples. At the following ODR a new sample set replaces the
oldest FIFO value. The OVRN bit is set to 0 when the first sample set has been
read
EMPTY
EMPTY flag is set high when all FIFO samples have been read and FIFO is empty
FSS [4:0]
FSS [4:0] field always contains the current number of unread samples stored in the
FIFO buffer. When FIFO is enabled, this value increases at ODR frequency until
the buffer is full, whereas, it decreases every time one sample set is retrieved from
FIFO
INT1_CFG (30h)
Table 54. INT1_CFG register
AOI
6D
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Table 55. INT1_CFG description
AOI
And/Or combination of interrupt events. Default value: 0. Refer to Table 56
6D
6-direction detection function enabled. Default value: 0. Refer to Table 56
ZHIE
Enable interrupt generation on Z high event or on direction recognition. Default
value: 0 (0: disable interrupt request;1: enable interrupt request)
ZLIE
Enable interrupt generation on Z low event or on direction recognition. Default value:
0 (0: disable interrupt request;1: enable interrupt request)
YHIE
Enable interrupt generation on Y high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
YLIE
Enable interrupt generation on Y low event or on direction recognition. Default value:
0 (0: disable interrupt request; 1: enable interrupt request.)
XHIE
Enable interrupt generation on X high event or on direction recognition. Default
value: 0 (0: disable interrupt request; 1: enable interrupt request.)
XLIE
Enable interrupt generation on X low event or on direction recognition. Default value:
0 (0: disable interrupt request; 1: enable interrupt request.)
The content of this register is loaded at boot.
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51
Register description
LIS2DE12
A write operation to this address is possible only after system boot.
Table 56. Interrupt mode
AOI
6D
Interrupt mode
0
0
OR combination of interrupt events
0
1
6-direction movement recognition
1
0
AND combination of interrupt events
1
1
6-direction position recognition
The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation
moves from an unknown zone to a known zone. The interrupt signal remains for a duration
ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is
inside a known zone. The interrupt signal remains while the orientation is inside the zone.
8.21
INT1_SRC (31h)
Table 57. INT1_SRC register
0
IA
ZH
ZL
YH
YL
XH
XL
Table 58. INT1_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 1 source register. Read-only register.
Reading at this address clears the INT1_SRC (31h) IA bit (and the interrupt signal on the
INT1 pin) and allows the refresh of data in the INT1_SRC (31h) register if the latched option
was chosen.
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8.22
Register description
INT1_THS (32h)
Table 59. INT1_THS register
0(1)
THS6
THS5
THS4
THS3
THS2
THS1
THS0
D1
D0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 60. INT1_THS description
THS[6:0]
8.23
Interrupt 1 threshold. Default value: 000 0000
1 LSb = 16 mg @ FS = ±2 g
1 LSb = 32 mg @ FS = ±4 g
1 LSb = 62 mg @ FS = ±8 g
1 LSb = 186 mg @ FS = ±16 g
INT1_DURATION (33h)
Table 61. INT1_DURATION register
0(1)
D6
D5
D4
D3
D2
1. This bit must be set to ‘0’ for correct operation of the device.
Table 62. INT1_DURATION description
D[6:0]
Duration value. Default value: 000 0000
1 LSb = 1/ODR
The D[6:0] bits set the minimum duration of the Interrupt 2 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
Duration time is measured in N/ODR, where N is the content of the duration register.
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51
Register description
8.24
LIS2DE12
INT2_CFG (34h)
Table 63. INT2_CFG register
AOI
6D
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Table 64. INT2_CFG description
AOI
AND/OR combination of interrupt events. Default value: 0
(see Table 65)
6D
6-direction detection function enabled. Default value: 0. Refer to Table 65.
ZHIE
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
ZLIE
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
YHIE
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
YLIE
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value lower than preset threshold)
The content of this register is loaded at boot.
A write operation to this address is possible only after system boot.
Table 65. Interrupt mode
AOI
6D
Interrupt mode
0
0
OR combination of interrupt events
0
1
6-direction movement recognition
1
0
AND combination of interrupt events
1
1
6-direction position recognition
The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation
moves from an unknown zone to a known zone. The interrupt signal remains for a duration
ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is
inside a known zone. The interrupt signal remains while the orientation is inside the zone.
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8.25
Register description
INT2_SRC (35h)
Table 66. INT2_SRC register
0
IA
ZH
ZL
YH
YL
XH
XL
Table 67. INT2_SRC description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read-only register.
Reading at this address clears the INT2_SRC (35h) IA bit (and the interrupt signal on the
INT2 pin) and allows the refresh of data in the INT2_SRC (35h) register if the latched option
was chosen.
8.26
INT2_THS (36h)
Table 68. INT2_THS register
0
(1)
THS6
THS5
THS4
THS3
THS2
THS1
THS0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 69. INT2_THS description
Interrupt 2 threshold. Default value: 000 0000
THS[6:0]
1 LSb = 16 mg @ FS = ±2 g
1 LSb = 32 mg @ FS = ±4 g
1 LSb = 62 mg @ FS = ±8 g
1 LSb = 186 mg @ FS = ±16 g
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51
Register description
8.27
LIS2DE12
INT2_DURATION (37h)
Table 70. INT2_DURATION register
0
(1)
D6
D5
D4
D3
D2
D1
D0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 71. INT2_DURATION description
Duration value. Default value: 000 0000
1 LSb = 1/ODR(1)
D[6:0]
1. Duration time is measured in N/ODR, where N is the content of the duration register.
The D[6:0] bits set the minimum duration of the Interrupt 2 event to be recognized. Duration
time steps and maximum values depend on the ODR chosen.
8.28
CLICK_CFG (38h)
Table 72. CLICK_CFG register
0(1)
0(1)
ZD
ZS
YD
YS
XD
XS
1. This bit must be set to ‘0’ for correct operation of the device.
Table 73. CLICK_CFG description
44/51
ZD
Enable interrupt double-click on Z-axis. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
ZS
Enable interrupt single-click on Z-axis. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
YD
Enable interrupt double-click on Y-axis. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
YS
Enable interrupt single-click on Y-axis. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XD
Enable interrupt double-click on X-axis. Default value: 0
(0: disable interrupt request;
1: enable interrupt request on measured accel. value higher than preset threshold)
XS
Enable interrupt single-click on X-axis. Default value: 0
(0: disable interrupt request; 1
: enable interrupt request on measured accel. value higher than preset threshold)
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8.29
Register description
CLICK_SRC (39h)
Table 74. CLICK_SRC register
0
IA
DClick
SClick
Sign
Z
Y
X
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one or more interrupts have been generated)
DClick
Double-click enable. Default value: 0 (0: double-click detection disabled,
1: double-click detection enabled)
SClick
Single-click enable. Default value: 0 (0: single-click detection disabled, 1: single-click
detection enabled)
Sign
Click sign. 0: positive detection, 1: negative detection
Z
Z click detection. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Y
Y click detection. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
X
X click detection. Default value: 0
(0: no interrupt, 1: X high event has occurred)
Table 75. CLICK_SRC description
8.30
CLICK_THS (3Ah)
Table 76. CLICK_THS register
LIR_Click
Ths6
Ths5
Ths4
Ths3
Ths2
Ths1
Ths0
Table 77. CLICK_THS register description
8.31
LIR_Click
If the LIR_Click bit is not set, the interrupt is kept high for the duration of the
latency window.
If the LIR_Click bit is set, the interrupt is kept high until the CLICK_SRC (39h)
register is read.
Ths[6:0]
Click threshold. Default value: 000 0000
TIME_LIMIT (3Bh)
Table 78. TIME_LIMIT register
0(1)
TLI6
TLI5
TLI4
TLI3
TLI2
TLI1
TLI0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 79. TIME_LIMIT description
TLI[6:0]
Click time limit. Default value: 000 0000
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51
Register description
8.32
LIS2DE12
TIME_LATENCY (3Ch)
Table 80. TIME_LATENCY register
TLA7
TLA6
TLA5
TLA4
TLA3
TLA2
TLA1
TLA0
TW1
TW0
Acth1
Acth0
Table 81. TIME_LATENCY description
TLA[7:0]
8.33
Click time latency. Default value: 0000 0000
TIME_WINDOW (3Dh)
Table 82. TIME_WINDOW register
TW7
TW6
TW5
TW4
TW3
TW2
Table 83. TIME_WINDOW description
TW[7:0]
8.34
Click time window
ACT_THS (3Eh)
Table 84. ACT_THS register
0(1)
Acth6
Acth5
Acth4
Acth3
Acth2
1. This bit must be set to ‘0’ for correct operation of the device.
Table 85. ACT_THS description
Acth[6:0]
8.35
Sleep-to-wake, return-to-sleep activation threshold in low-power mode
1 LSb = 16 mg @ FS = ±2 g
1 LSb = 32 mg @ FS = ±4 g
1 LSb = 62 mg @ FS = ±8 g
1 LSb = 186 mg @ FS = ±16 g
ACT_DUR (3Fh)
Table 86. ACT_DUR register
ActD7
ActD6
ActD5
ActD4
ActD3
ActD2
Table 87. ACT_DUR description
ActD[7:0]
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Sleep-to-wake, return-to-sleep duration.
1 LSb = (8*1[LSb]+1)/ODR
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ActD1
ActD0
LIS2DE12
9
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
9.1
LGA-12 package information
Figure 12. LGA-12: package outline and mechanical data
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Package information
9.2
LIS2DE12
LGA-12 packing information
Figure 13. Carrier tape information for LGA-12 package
Figure 14. LGA-12 package orientation in carrier tape
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LIS2DE12
Package information
Figure 15. Reel information for carrier tape of LGA-12 package
7
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Table 88. Reel dimensions for carrier tape of LGA-12 package
Reel dimensions (mm)
A (max)
330
B (min)
1.5
C
13 ±0.25
D (min)
20.2
N (min)
60
G
12.4 +2/-0
T (max)
18.4
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Revision history
10
LIS2DE12
Revision history
Table 89. Document revision history
Date
Revision
27-May-2015
1
Initial release
2
Updated Table 2: Pin description
Added Table 3: Internal pull-up values (typ.) for SDO/SA0 pin
Updated self-test output change in Table 4
Updated APOW and AUNP in Table 9: Absolute maximum ratings
Added Table 12: Internal pin status
Updated Section 3.2.4: Sleep-to-wake and Return-to-sleep
Updated Section 3.7: Temperature sensor
Updated Section 5.1.5: Retrieving data from FIFO
Updated Section 8: Register description
Added Section 9.2: LGA-12 packing information
Minor textual updates
27-Jan-2017
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Changes
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acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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