LNBH221PD

LNBH221 Dual LNB supply and control IC with step-up converter and I²C interface Features ■ All the features are the same for both section ■ Complete and independent interface between LNBS and relevant I²C bus ■ Built-in DC-DC controller for single 12 V supply operation and high efficiency (typ. 93 % @ 500 mA) ■ LNB output current guaranteed up to 500 mA ■ Both compliant with EUTELSAT and direct output voltage specification accurate built-in 22 kHz tone oscillator suits widely accepted standards ■ Fast oscillator start-up facilitates DiSEqC™ encoding ■ Built-in 22 kHz tone detector supports bidirectional DiSEqC™ 2.0 ■ Semi low-drop post regulator and high efficiency step-up PWM for low power loss: Typ. 0.56 W @ 125 mA ■ Two output pins suitable to by-pass the output R-L filter and avoid any tone distortion (R-L filter as per DiSEqC 2.0 specs, see Figure 4 on page 8) ■ Overload and over-temperature internal protections ■ Overload and over-temperature I²C diagnostic bits ■ LNB short circuit SOA protection with I²C diagnostic bit PowerSO-36 ) s t( c u d o r P e et assembled in PowerSO-36, specifically designed to provide the power 13/18 V, and the 22 kHz tone signalling for two independent LNB down converters or to a multiswitch box that could be independently powered and set. In this application field, it offers a complete solution with extremely low component count, low power dissipation together with simple design and I²C standard interfacing. l o bs O ) s ( t c u d o r eP t e ol s b O ■ +/- 4 kV ESD tolerant on input/output power pins Description Intended for analog and digital dual satellite STB receivers/sat-TV, sets/PC cards, the LNBH221 is a voltage regulator and interface IC, April 2009 Doc ID 9913 Rev 6 1/27 www.st.com 27 Contents LNBH221 Contents 1 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Typical application circuits for each section: A and B . . . . . . . . . . . . . 7 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 I²C bus interface (one for each section) . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ) s t( c u d o r P e t section) . . . . . . . . . . . 13 LNBH221 software description (same for lboth e o s b O ) s ( t c u d o r P e t oleElectrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 7 5.1 s b O 5.6 Transmission without acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Received data (I²C bus read mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.5 Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 Thermal design notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 Typical performance characteristics (of each section) . . . . . . . . . . . . 19 10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/27 Doc ID 9913 Rev 6 LNBH221 Diagram 1 Diagram Figure 1. Block diagram Gate LNBH221- section A Sense Step-up Controller VoTX Vup Vcc Byp SDA SCL VoRX Preregul.+ U.V.lockout +P.ON res. Linear Post-reg +Modulator +Protections V Select I²C Diagn. Enable ADDR TEN 22KHz Oscill. DSQIN Tone Detector DSQOUT Step-up Controller SDA SCL Linear Post-reg +Modulator +Protections l o bs V Select I²C TEN ) s t( c du EXTM Diagn. Enable ADDR DSQIN P e et VoRX Preregul.+ U.V.lockout +P.ON res. ) s t( c u d o r VoTX Vup Byp DETIN LNBH221- section B Gate Sense Vcc EXTM -O 22KHz Oscill. Tone Detector DETIN DSQOUT o r eP t e ol s b O Doc ID 9913 Rev 6 3/27 Maximum ratings LNBH221 2 Maximum ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VCC DC input voltage -0.3 to 16 V VUP DC input voltage -0.3 to 25 V DC output pin voltage -0.3 to 25 V Internally limited mA VOTX/RX IO Output current VI Logic input voltage (SDA, SCL, DSQIN) -0.3 to 7 V Detector input signal amplitude -0.3 to 2 VPP VOH Logic high output voltage (DSQOUT) -0.3 to 7 V IGATE Gate current ± 400 mA Current sense voltage -0.3 to 1 Address pin voltage -0.3 to 7 VDETIN VSENSE VADDRESS TSTG TJ Storage temperature range -40 to 150 ) s t( Operating junction temperature range -40 to 125 °C V c u d o r V °C P e et Note: Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 2. Thermal data Symbol RthJC -O Parameter ) s t( c du Thermal resistance junction-case l o bs o r eP t e ol s b O 4/27 Doc ID 9913 Rev 6 Value Unit 2 °C/W LNBH221 Pin configuration 3 Pin configuration Figure 2. Pin configurations (top view) ) s t( c u d o r Table 3. Pin description Symbol VCC l o bs Name P e et Function A B 8 V to 15 V supply. A 220 µF bypass capacitor to GND with a 470 nF (ceramic) in parallel is recommended. 8 26 External MOS switch gate connection of the step-up converter. 7 25 ) s t( c du Supply input -O Pin number Sect: GATE External switch gate SENSE Current sense (input) Current Sense comparator input. Connected to current sensing resistor. 6 24 Step-up voltage Input of the linear post-regulator. The voltage on this pin is monitored by the internal step-up controller to keep a minimum dropout across the linear pass transistor. 9 27 Output port during 22 RX Output to the LNB in DiSEqC 2.0 application. See truth table kHz Tone RX for voltage selections and description on page 4. 28 10 SDA Serial data Bidirectional data from/to I²C bus. 2 20 SCL Serial clock Clock from I²C bus. 3 21 DSQIN DiSEqC input When the TEN bit of the system register is LOW, this pin will accept the DiSEqC code from the main μcontroller. Each section of the LNBH221 will use this code to modulate the internally generated 22 kHz carrier. Set to GND this pin if not used. 4 22 DETIN Detector in 22 kHz tone detector input. Must be AC coupled to the DiSEqC bus. 35 17 VUP o r eP t e ol VORX s b O Doc ID 9913 Rev 6 5/27 Pin configuration Table 3. LNBH221 Pin description Symbol Name Pin number Sect: Function A B Open drain output of the tone detector to the main microcontroller for DiSEqC data decoding. It is LOW when tone is detected on the DETIN. 5 23 External modulation External modulation input. Needs DC decoupling to the AC source. If not used, can be left open. 31 13 GND Ground 1, 14, 1, 14, 18, 18, Circuit ground. It is internally connected to the die frame for heat 19, 19, dissipation. 32, 32, 36 36 BYP Bypass capacitor pin Needed for internal pre regulator filtering. VOTX Output port during 22 Output of the linear post regulator/modulator to the LNB. See kHz tone TX truth table for voltage selections. GND Ground To be connected to ground. Address setting Four I²C bus addresses available by setting the address pin level voltage. DSQOUT DiSEqC output EXTM ADDR l o bs O ) s ( t c u d o r eP t e ol s b O 6/27 Doc ID 9913 Rev 6 34 ) s t( 30 c u d o r P e et 16 12 29 11 33 15 LNBH221 Typical application circuits for each section: A and B 4 Typical application circuits for each section: A and B Figure 3. Application circuit for DiSEqC 1.x and output current up to 500 mA D1 1N4001 Axial Ferrite Bead Filter F1 suggested part number: MURATA BL01RN1-A62 Panasonic EXCELS A35 IC1 F1 Vup C9 220µF C2 220µF IC2 STS4DNFS30L VoRX C3 470nF Ceramic Set TTX=1 to LNB Gate VoTX LNBH221 Sense L1=22µH Rsc 0.1 Ω C5 10nF Section A and B C4 470nF Ceramic c u d o r Byp C5 470nF C1 220µF P e et SDA EXTM SCL Address DSQIN DSQOUT Tone Enable ) s t( (**) DETIN Vcc Vin 12V D2 BAT43 l o bs GND 0