LNBH23L
LNB supply and control IC with step-up and I²C interface
Features
■
Complete interface between LNB and I²C bus
■
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @ 0.5
A)
■
Selectable output current limit by external
resistor
■
Compliant with main satellite receivers output
voltage specification
■
Auxiliary modulation input (EXTM pin)
facilitates DiSEqC™ 1.X encoding
■
Accurate built-in 22 kHz tone generator suits
widely accepted standards
■
Low-drop post regulator and high efficiency
step-up PWM with integrated power NMOS
allow low power losses
■
Overload and over-temperature internal
protections with I²C diagnostic bits
■
LNB short circuit dynamic protection
■
± 4 kV ESD tolerant on output power pins
Applications
■
STB satellite receivers
■
TV satellite receivers
■
PC card satellite receivers
Table 1.
QFN32 (5 x 5 mm)
(Exposed pad)
Description
Intended for analog and digital satellite receivers,
the LNBH23L is a monolithic voltage regulator
and interface IC, assembled in QFN32 5 x 5
specifically designed to provide the 13 / 18 V
power supply and the 22 kHz tone signalling to
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count, low power dissipation together
with simple design and I²C standard interfacing.
Device summary
Order code
Package
Packaging
LNBH23LQTR
QFN32 (5 x 5 mm) Exposed pad
Tape and reel
November 2010
Doc ID 15335 Rev 4
1/25
www.st.com
25
Contents
LNBH23L
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
DiSEqC™ 1.X implementation by EXTM pin . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
DiSEqC™ 1.X implementation with VOTX and EXTM pin connection . . . . 5
2.4
PDC optional circuit for DiSEQC™ 1.X applications using VOTX
signal on to EXTM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5
I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8
Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 6
2.9
Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
2/25
6.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LNBH23L software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2
System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.3
Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4
Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17
Doc ID 15335 Rev 4
LNBH23L
Contents
7.5
Power-on I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6
Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7
DiSEqC™ implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Doc ID 15335 Rev 4
3/25
Block diagram
LNBH23L
1
Block diagram
Figure 1.
Block diagram
ISEL
TTX
ADDR SDA SCL
VCC Byp VCC-L
Rsense
Controller
PWM
LX
Preregulator
+U.V.lockout
+
+P.ON reset
EN
VSEL
P-GND
VSEL
TTX
VOUT Control
Vup
EN
I²C interface
TEN
Linear Post-reg
+Protections
+Diagnostics
VoRX
I²C OLF and OTF
Diagnostics
FB
VoTX
22kHz
Oscill.
TTX
EXTM
Pull Down
Controller
DSQIN
LNBH23L
A-GND
4/25
Doc ID 15335 Rev 4
PDC
LNBH23L
2
Application information
Application information
This IC has a built-in DC-DC step-up converter that, from a single source from 8 V to 15 V,
generates the voltages (VUP) that let the linear post-regulator to work at a minimum
dissipated power of 0.55 W typ. @ 500 mA load (the linear post-regulator drop voltage is
internally kept at VUP - VOUT = 1.1 V typ.). An under voltage lockout circuit will disable the
whole circuit when the supplied VCC drops below a fixed threshold (6.7 V typically).
Note:
In this document the VOUT is intended as the voltage present at the linear post-regulator
output (VoRX pin).
2.1
DiSEqC™ data encoding
The internal 22 kHz tone generator is factory trimmed in accordance to the standards, and
can be selected by I²C interface TTX bit (or TTX pin) and activated by a dedicated pin
(DSQIN) that allows immediate DiSEqC™ data encoding, or through TEN I²C bit in case the
22 kHz presence is requested in continuous mode. In stand-by condition (EN bit LOW) The
TTX function must be disabled setting TTX to LOW. Besides the internal 22 kHz tone
generator, the auxiliary modulation pin (EXTM) can be driven by an external 22 kHz source
and in this case TTX must be set to low.
2.2
DiSEqC™ 1.X implementation by EXTM pin
In order to improve design flexibility and reduce the total application cost, an analogic
modulation input pin is available (EXTM) to generate the 22 kHz tone superimposed to the
VoRX DC output voltage. An appropriate DC blocking capacitor must be used to couple the
modulating signal source to the EXTM pin. If the EXTM solution is used the output R-L filter
can be removed (see Figure 5) saving the external components cost. If this configuration is
used keep TTX set to low.
The pin EXTM modulates the VoRX voltage through the series decoupling capacitor, so that:
VoRX(AC) = VEXTM(AC) x GEXTM
Where VoRX(AC) and VEXTM(AC) are, respectively, the peak to peak voltage on the VoRX and
EXTM pins while GEXTM is the voltage gain from EXTM to VoRX.
2.3
DiSEqC™ 1.X implementation with VOTX and EXTM pin
connection
If an external 22 kHz tone source is not available, it is possible to use the internal 22 kHz
tone generator signal available through the VoTX pin to drive the EXTM pin. The VoTX pin
internal circuit must be preventively set ON by setting the TTX function to High. This can be
controlled both through the TTX pin or by I²C bit. By this way the VoTX 22 kHz signal will be
superimposed to the VoRX DC voltage to generate the LNB output 22 kHz tone (see
Figure 3). After TTX is set to High the internal 22 kHz tone generator available through the
VoTX pin can be activated during the 22 kHz transmission either by DSQIN pin or by the TEN
bit.The DSQIN internal circuit activates the 22 kHz tone on the VoTX output with 0.5 cycles ±
25 µs delay from the TTL signal presence on the DSQIN pin, and it stops with 1 cycles ± 25
µs delay after the TTL signal is expired. As soon as the tone transmission is expired, the
Doc ID 15335 Rev 4
5/25
Application information
LNBH23L
VoTX internal circuits must be disabled by setting the TTX to LOW. The 13 / 18 V power
supply will be always provided to the LNB from the VoRX pin.
2.4
PDC optional circuit for DiSEQC™ 1.X applications using
VOTX signal on to EXTM pin
In some applications, at light output current (< 50 mA) having heavy LNB output capacitive
load, the 22 kHz tone can be distorted. In this case it is possible to add the "Optional"
external components shown in the typical application circuits (see Figure 4) connected
between VoRX and PDC pin. This optional circuit acts as an active pull-down discharging the
output capacitance only when the internal 22 kHz tone is activated. This optional circuit is
not needed in standard applications having IOUT > 50 mA and capacitive load up to 250 nF.
2.5
I²C interface
The main functions of the IC are controlled via I²C bus by writing 6 bits on the system
register (SR 8 bits in write mode). On the same register there are 5 bits that can be read
back (SR 8 bits in read mode) to provide the diagnostic flags of two internal monitoring
functions (OTF, OLF) and three output voltage register status (EN, VSEL, LLC) received by
the IC (see below diagnostic functions section). In read mode there are 3 Test bits (test 1 - 2
- 3) that must be disregarded from the MCU. While, in write mode, 2 test bits (test 4 - 5) must
be always set LOW.
2.6
Output voltage selection
When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the VSEL bit (voltage SELect). Additionally, the LNBH23L is provided
with the LLC I²C bit that increases the selected voltage value to compensate possible
voltage drop along the output line. The LNBH23L is also compliant to the USA LNB power
supply standards. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must
be set LOW (if the TTX pin is not used it can be left floating or to GND but the TTX bit must
be set LOW during the stand-by condition).
2.7
Diagnostic and protection functions
The LNBH23L has two diagnostic internal functions provided via I²C bus by reading 2 bits on
the system register (SR bits in read mode). the diagnostic bits are, in normal operation (no
failure detected), set to LOW. The diagnostic bits are dedicated to the over-temperature and
over-load protections status (OTF and OLF).
2.8
Over-current and short circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short circuit condition,
the device is provided with a dynamic short circuit protection. It is possible to set the short
circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C SR. When the PCL (pulsed current limiting) bit is set lo LOW, the over current
protection circuit works dynamically: as soon as an overload is detected, the output is shut-
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Doc ID 15335 Rev 4
LNBH23L
Application information
down for a time TOFF, typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the
system register is set to "1". After this time has elapsed, the output is resumed for a time
TON = 1/10 TOFF = 90 ms (typ.). At the end of TON, if the overload is still detected, the
protection circuit will cycle again through TOFF and TON. At the end of a full TON in which no
overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to
LOW. Typical TON + TOFF time is 990ms and an internal timer determines it. This dynamic
operation can greatly reduce the power dissipation in short circuit condition, still ensuring
excellent power-on start-up in most conditions. However, there could be some cases in
which a highly capacitive load on the output may cause a difficult start-up when the dynamic
protection is chosen. This can be solved by initiating any power start-up in static mode (PCL
= 1) and, then, switching to the dynamic mode (PCL = 0) after a chosen amount of time
depending on the output capacitance. When in static mode, the diagnostic OLF bit goes to
"1" when the current clamp limit is reached and returns LOW when the overload condition is
cleared.
2.9
Thermal protection and diagnostic
The LNBH23L is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the
diagnostic OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to
LOW when the junction is cooled down to 135 °C (typ.)
2.10
Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
ISEL pin. The resistor value defines the output current limit by the equation:
IMAX (A) = 10000 / RSEL
where RSEL is the resistor connected between ISEL and GND. The highest selectable current
limit threshold shall be 0.65 A typ with RSEL = 15 kΩ. The above equation defines the typical
threshold value.
Note:
External components are needed to comply DiSEqC™ bus hardware requirements. Full
compliance of the whole application with DiSEqC™ specifications is not implied by the bare
use of this IC. NOTICE: DiSEqC™ is a trademark of EUTELSAT.
Doc ID 15335 Rev 4
7/25
Pin configuration
LNBH23L
3
Pin configuration
Figure 2.
Pin connections (bottom view)
Table 2.
Pin description
8/25
Pin n°
Symbol
Name
Pin function
19
VCC
Supply input
8 to 15 V IC DC-DC power supply.
18
VCC–L
Supply input
8 to 15 V analog power supply.
4
LX
NMOS drain
Integrated N-channel power MOSFET drain.
27
VUP
Step-up voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
21
VoRX
LDO output port
Output of the integrated low drop linear regulator. See truth
tables for voltage selections and description.
22
VoTX
Output port for 22
kHz Tone TX
6
SDA
Serial data
Bi-directional data from/to I²C bus.
9
SCL
Serial clock
Clock from I²C bus.
12
DSQIN
DiSEqC input
This pin will accept the DiSEqC code from the main µController.
The LNBH23L will use this code to modulate the internally
generated 22 kHz carrier. Set to ground if not used.
14
TTX
TTX enable
This pin can be used, as well as the TTX I²C bit of the system
register, to control the TTX function enable before to start the
22 kHz tone transmission. Set floating or to GND if not used.
29
Reserved
Reserved
11
PDC
Pull down control
13
EXTM
5
P-GND
TX Output to the LNB. See truth tables for selection.
To be connected to GND.
To be connected to the external NPN transistor Base to reduce
the 22 kHz tone distortion in case of heavy capacitive load at
light output current. If not used it can be left floating.
External Modulation Input acts on VoRX linear regulator output
External modulation to superimpose an external 22 kHz signal. Needs DC
decoupling to the AC source. If not used it can be left floating.
Power ground
DC-DC converter power ground.
Doc ID 15335 Rev 4
LNBH23L
Table 2.
Pin configuration
Pin description (continued)
Pin n°
Symbol
Name
Epad
Epad
Exposed pad
20
A-GND
Analog ground
Pin function
To be connected with power grounds and to the ground layer
through vias to dissipate the heat.
Analog circuits ground.
15
BYP
By-pass capacitor
Needed for internal pre-regulator filtering. The BYP pin is
intended only to connect an external ceramic capacitor. Any
connection of this pin to external current or voltage sources
may cause permanent damage to the device.
10
ADDR
Address setting
Two I²C bus addresses available by setting the Address pin
level voltage. See address pin characteristics table.
28
ISEL
Current selection
30
Reserved
Reserved
1, 2, 3, 7, 8,
16, 17, 23,
24, 25, 26,
31, 32
N.C.
Not internally
connected
The resistor “RSEL” connected between ISEL and GND defines
the linear regulator current limit threshold by the equation:
IMAX(typ.) = 10000 / RSEL.
To be left floating. Do not connect to GND.
Not internally connected pins. These pins can be connected to
GND to improve thermal performances.
Doc ID 15335 Rev 4
9/25
Maximum ratings
LNBH23L
4
Maximum ratings
Table 3.
Absolute maximum ratings (1)
Symbol
Parameter
Value
Unit
-0.3 to 16
V
-0.3 to 24
V
Internally limited
mA
VCC-L, VCC DC power supply input voltage pins
VUP
DC input voltage
IOUT
Output current
VoRX
DC output pin voltage
-0.3 to 25
V
VoTX
Tone output pin voltage
-0.3 to 25
V
Logic input voltage (TTX, SDA, SCL, DSQIN, ADDR pins)
-0.3 to 7
V
Logic high output voltage (PDC pin)
-0.3 to 7
V
EXTM pin voltage
-0.3 to 2
V
LX input voltage
-0.3 to 24
V
VBYP
Internal reference pin voltage (2)
-0.3 to 4.6
V
ISEL
Current selection pin voltage
-0.3 to 4.6
V
TSTG
Storage temperature range
-50 to 150
°C
Operating junction temperature range
-25 to 125
°C
ESD rating with human body model (HBM) for all pins unless 4, 21, 22
2
kV
ESD rating with human body model (HBM) for pins 21, 22
4
VI
VOH
VEXTM
LX
TJ
ESD
ESD rating with human body model (HBM) for pin 4
0.6
1. Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only
and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability. All voltage values are with respect to network ground terminal.
2. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to external current or
voltage sources may cause permanent damage to the device.
Table 4.
Symbol
Thermal data
Parameter
Value
Unit
RthJC
Thermal resistance junction-case
2
°C/W
RthJA
Thermal resistance junction-ambient with device soldered
on 2s2p PC board
35
°C/W
10/25
Doc ID 15335 Rev 4
LNBH23L
Typical application circuit
5
Typical application circuit
Figure 3.
DiSEqC 1.x using internal 22 kHz tone generator
D3
Vup
C4
470nF
C3
VoTX
R9
1.5KOhm
C6
470nF
to LNB
500mA max
C15
LNBH23L
D1
EXTM
47nF
VoRX
LX
C10
220nF
L1
D2
Vcc
Vin
12V
Vcc-L
C8
220nF
C1
PDC
2
I C Bus
{
SDA
TTX
SCL
ADDR
Tone Enable control
ISEL
P-GND
A-GND
Byp
TTL
Figure 4.
R2 (RSEL)
15kOhm
DSQIN
C11
220nF
DiSEqC 1.x using internal 22 kHz tone generator and "optional" PDC circuit
D3
Vup
C4
470nF
C3
VoTX
R9
1.5KOhm
C6
470nF
to LNB
500mA max
C15
LNBH23L
D1
EXTM
47nF
VoRX
LX
C10
220nF
L1
D2
Vcc
Vin
12V
Diode
1N4148
Vcc-L
PDC
C8
220nF
C1
I2C Bus
*C14
1nF
*R7
22 Ohm
3.3V
SDA
TTX
SCL
ADDR
Tone Enable control
*TR1
*R5
2.2K Ohm
{
*R8
150 Ohm
(*) OPTIONAL components.
To be used only in case
of heavy capacitive load
ISEL
R2 (RSEL)
15kOhm
DSQIN
P-GND
A-GND
TTL
Doc ID 15335 Rev 4
Byp
C11
220nF
11/25
Typical application circuit
Figure 5.
LNBH23L
DiSEqC 1.x using external 22 kHz tone generator source through EXTM pin
D3
Vup
VoTX
C4
470nF
C3
C6
470nF
LNBH23L
D1
to LNB
500mA max
LX
VoRX
L1
D2
Vcc
Vin
12V
C10
220nF
Vcc-L
C1
C8
220nF
I2 C Bus
{
PDC
SDA
SCL
DSQIN
ADDR
ISEL
TTX
22KHz signal source
EXTM
P-GND
A -GND
Byp
C15
220nF
Table 5.
R2 (RSEL)
15kOhm
C11
220nF
BOM list
Component
Notes
R2, R9, R5 (1)
1/16 W resistors. Refer to the typical application circuit for the relative values
R7 (1), R8 (1)
1/2 W resistors. Refer to the typical application circuit for the relative values
C1
25 V electrolytic capacitor, 100 µF or higher is suitable
C3
25 V, 220 µF electrolytic capacitor, ESR in the 100 mΩ to 350 mΩ range
C4, C6, C8, C10, C11, C15,
25 V ceramic capacitors. Refer to the typ. appl. circuit for the relative values
C14 (1)
D1
STPS130A or any similar schottky diode with VRRM > 25 V and IF(AV) higher than:
IF(AV) > IOUT_MAX x (VUP_MAX/VIN_MIN)
D2
BAT43, 1N5818, or any schottky diode with IF(AV) > 0.2 A, VRRM > 25 V, VF < 0.5 V. To
be placed as close as possible to VoRX pin
D3
1N4001-07 or any similar general purpose rectifier
TR1 (1)
BC817 or similar NPN general-purpose transistor.
L1
22 µH inductor with ISAT > IPEAK where IPEAK is the boost converter peak current (see
Equation 1)
1. These components can be added to avoid any 22 kHz tone distortion due to heavy capacitive output loads. If not needed
they can be removed leaving the PDC pin floating.
12/25
Doc ID 15335 Rev 4
LNBH23L
Typical application circuit
To calculate the boost converter peak current (IPEAK) of L1, use the following formula:
Equation 1
Doc ID 15335 Rev 4
13/25
I²C bus interface
6
LNBH23L
I²C bus interface
Data transmission from main microprocessor to the LNBH23L and vice versa takes place
through the 2 wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 6, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
6.2
Start and stop condition
As shown in Figure 7 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 8). The peripheral (LNBH23L) that acknowledges has
to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed has to
generate acknowledge after the reception of each byte, otherwise the SDA line remains at
the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH23L won't generate
acknowledge if the VCC supply is below the under voltage lockout threshold (6.7 V typ.).
6.5
Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH23L, the microprocessor can use a simpler
transmission: simply it waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.
14/25
Doc ID 15335 Rev 4
LNBH23L
I²C bus interface
Figure 6.
Data validity on the I²C bus
Figure 7.
Timing diagram of I²C bus
Figure 8.
Acknowledge on the I²C bus
Doc ID 15335 Rev 4
15/25
LNBH23L software description
LNBH23L
7
LNBH23L software description
7.1
Interface protocol
The interface protocol comprises:
●
A start condition (S)
●
A chip address byte (the LSB bit determines read (=1)/write (=0) transmission)
●
A sequence of data (1 byte + acknowledge)
●
A stop condition (P)
Section address (A or B)
Data
MSB
S
0
LSB
0
0
1
0
1
X
MSB
LSB
R/W ACK
ACK
P
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, two addresses selectable by ADDR pin (see Table 10)
7.2
System register (SR, 1 byte)
Mode
MSB
LSB
Write
PCL
TTX
TEN
LLC
VSEL
EN
TEST4
TEST5
Read
TEST1
TEST2
TEST3
LLC
VSEL
EN
OTF
OLF
Write = control bits functions in write mode
Read= diagnostic bits in read mode.
All bits reset to 0 at Power-on
7.3
Transmitted data (I²C bus write mode)
When the R/W bit in the chip address is set to 0, the main microprocessor can write on the
system register (SR) of the LNBH23L via I²C bus. 6 bits are available and can be written by
the microprocessor to control the device functions as per the below truth table Table 6.
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Doc ID 15335 Rev 4
LNBH23L
Table 6.
PCL
LNBH23L software description
Truth table
TTX
TEN
LLC
VSEL
EN
TEST4 TEST5
Function
0
0
0
1
0
0
VoRX = 13.4 V, VUP = 14.5 V, (VUP - VoRX = 1.1 V)
0
0
1
1
0
0
VoRX = 18.4 V, VUP = 19.5 V, (VUP - VoRX = 1.1 V)
0
1
0
1
0
0
VoRX = 14.4 V, VUP=15.5 V, (VUP-VoRX=1.1 V)
0
1
1
1
0
0
VoRX = 19.5V, VUP=20.6 V, (VUP-VoRX=1.1 V)
0
0
1
0
0
Internal 22 kHz generator disabled, EXTM
modulation enabled
1
0
1
0
0
Internal 22 kHz controlled by DSQIN pin (only if
TTX=1)
1
1
1
0
0
Internal 22 kHz tone output is always activated
0
1
0
0
VoRX output is ON, VoTX Tone generator output is
OFF
1
1
0
0
VoRX output is ON, VoTX Tone generator output is
ON
0
X
1
0
0
Pulsed (Dynamic) current limiting is selected
1
X
1
0
0
Static current limiting is selected
X
X
0
0
0
Power block disabled
X
X
X
X = don't care
All values are typical unless otherwise specified
Valid with TTX pin floating
7.4
Diagnostic received data (I²C read mode)
LNBH23L can provide to the MCU master a copy of the diagnostic system register
information via I²C bus in read mode. The read mode is master activated by sending the
chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH23L
issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the
Master can:
●
Acknowledge the reception, starting in this way the transmission of another byte from
the LNBH23L
●
No acknowledge, stopping the read mode communication
Three bits of the register are read back as a copy of the corresponding write output voltage
register status (LLC, VSEL, EN), two bits convey diagnostic information about the overtemperature (OTF), output over-load (OLF) and three bit are for internal usage (TEST1-2-3)
and must be disregarded by the MCU software. In normal operation the diagnostic bits are
set to zero, while, if a failure is occurring, the corresponding bit is set to one. At start-up all
the bits are reset to zero.
Doc ID 15335 Rev 4
17/25
LNBH23L software description
Table 7.
TEST1
LNBH23L
Register
TEST2
TEST3
LLC
VSEL
EN
OTF
These bits are read
exactly the same as
they were left after
last write operation
X
X
OLF
Function
0
TJ < 135°C, normal operation
1
TJ > 150°C, power blocks disabled
0
IO < IOMAX, normal operation
1
IO > IOMAX, Overload protection triggered
These bits status must be disregarded by the
MCU.
X
Values are typical unless otherwise specified.
x = don’t care.
7.5
Power-on I²C interface reset
I²C interface built in LNBH23L is automatically reset at power-on. As long as the VCC stays
below the under voltage lockout (UVL) threshold (6.7 V), the interface does not respond to
any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the
power blocks disabled. Once the VCC rises above 7.3 V typ. The I²C interface becomes
operative and the SR can be configured by the main microprocessor. This is due to 500 mV
of hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset
circuit.
7.6
Address pin
It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL
compatible and can be set as per address pin characteristics Table 10.
7.7
DiSEqC™ implementation
LNBH23L helps system designer to implement DiSEqC 1.x protocol by allowing an easy
PWK modulation of the 22 kHz carrier through the EXTM and VoTX pins. Full compliance of
the system to the specification is thus not implied by the bare use of the LNBH23L (see
Figure 3, Figure 4 and Figure 5).
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LNBH23L
8
Electrical characteristics
Electrical characteristics
Refer to the typical application circuits, TJ from 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=TEST4=TEST5=TTX=0, RSEL=15 kΩ, DSQIN=LOW, VIN =12 V,
IOUT = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VOUT =
VoRX pin voltage. See software description section for I²C access to the system register.
Table 8.
Symbol
VIN
IIN
VOUT
Electrical characteristics
Parameter
Supply voltage
Supply current
Output voltage
Test conditions
Min.
Typ.
Max.
Unit
8
12
15
V
IOUT=0
7
15
EN=TEN=TTX=1, IOUT=0,
PDC circuit not connected
20
40
EN=0
2
IOUT=500mA, VSEL=LLC=1
VSEL=1
IOUT=500mA
LLC=0
VSEL=0
IOUT=500mA
LLC=0
17.8
LLC=1
18.4
mA
19.2
19.5
V
12.8
13.4
14
VOUT
Output voltage
VOUT
Line regulation
VOUT
Load regulation
VSEL=0 or 1 IOUT from 50 to 500mA
Output current limiting
thresholds
RSEL=15 kΩ
500
800
IMAX
RSEL= 22 kΩ
300
600
Output short circuit current
VSEL=0/1, AUX=0/1
1000
mA
TOFF
Dynamic overload protection
OFF time
PCL=0, output shorted
900
ms
TON
Dynamic overload protection
ON time
PCL=0, output shorted
TOFF/10
Tone frequency
DSQIN=HIGH or TEN=1, TTX=1
(Using internal tone generator)
18
22
26
kHz
ATONE
Tone amplitude
DSQIN=HIGH or TEN=1, TTX=1,
DiSEqC 1.X configuration using
internal generator, IOUT from 0 to
500mA, COUT from 0 to 750nF, PDC
Optional circuit connected to VoRX rail
0.4
0.650
0.9
VPP
DTONE
Tone duty cycle
DSQIN=HIGH or TEN=1, TTX=1
(Using internal tone generator)
40
50
60
%
tr, tf
Tone rise or fall time
DSQIN=HIGH or TEN=1, TTX=1
(Using internal tone generator)
5
8
15
µs
VPDC_OL
PDC pin logic LOW
IPDC=2mA
0.3
V
IPDC_OZ
PDC pin leakage current
VPDC=5V
1
µA
GEXTM
External modulation gain
ΔVOUT/ ΔVEXTM, freq. from 10 kHz to
50 kHz
ISC
FTONE
VIN=8 to 15V
LLC=1
14.4
VSEL=0
5
40
VSEL=1
5
60
mV
200
mA
Doc ID 15335 Rev 4
1.8
19/25
Electrical characteristics
Table 8.
LNBH23L
Electrical characteristics (continued)
Symbol
Parameter
VEXTM
External modulation input
voltage
ZEXTM
External modulation
impedance
Test conditions
Min.
Typ.
EXTM AC coupling (1)
%
220
kHz
DC-DC converter switching
frequency
VIL
DSQIN,TTX, pin logic low
VIH
DSQIN,TTX, pin logic high
IIH
DSQIN,TTX, pin input current VIH=5V
15
Output backward current
-6
ΔTSHDN
mVPP
93
FSW
TSHDN
400
kΩ
DC-DC converter efficiency
IOBK
Unit
2.0
EffDC-DC
IOUT=500mA
Max.
0.8
V
2
EN=0, VOBK=21V
V
µA
-15
mA
Thermal shut-down threshold
150
°C
Thermal shut-down
hysteresis
15
°C
1. External signal maximum voltage for which the EXTM function is guaranteed.
I²C electrical characteristics (1)
Table 9.
Symbol
Parameter
Test conditions
VIL
LOW level input voltage
SDA, SCL
VIH
HIGH level input voltage
SDA, SCL
Input current
SDA, SCL, VI = 0.4 to 4.5V
VOL
Low level output voltage
SDA (open drain), IOL = 6mA
fMAX
Maximum clock frequency
SCL
II
Min.
Typ.
Max.
Unit
0.8
V
2
V
-10
10
µA
0.6
V
400
kHz
1. TJ from 0 to 85 °C, VI = 12 V.
Table 10.
Symbol
Address pins characteristics (1)
Parameter
Test condition
Min.
Typ.
Max.
Unit
VADDR-1
"0001010(R/W)" Address pin R/W bit determines the transmission
voltage range
mode: read (R/W=1) write (R/W=0)
0
0.8
V
VADDR-2
"0001011(RW)" Address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
2
5
V
VADDR-3 (2)
"0001000(RW)" Address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
0
5
V
1. TJ from 0 to 85 °C, VI = 12 V
2. This I²C address is reserved only for internal usage. Do not use this address with other I²C peripherals to avoid address
conflicts.
20/25
Doc ID 15335 Rev 4
LNBH23L
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Doc ID 15335 Rev 4
21/25
Package mechanical data
Table 11.
LNBH23L
QFN32 (5 x 5 mm) mechanical data
(mm.)
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.02
0.05
A3
0.20
b
0.18
0.25
0.30
D
4.85
5.00
5.15
D2
3.20
E
4.85
E2
3.20
3.70
5.00
3.70
e
L
0.50
0.30
0.40
ddd
Figure 9.
5.15
0.50
0.08
QFN32 package dimensions
7376875/E
22/25
Doc ID 15335 Rev 4
LNBH23L
Package mechanical data
Tape & reel QFNxx/DFNxx (5x5 mm.) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
330
C
12.8
D
20.2
N
99
13.2
Max.
12.992
0.504
0.519
0.795
101
T
3.898
3.976
14.4
0.567
Ao
5.25
0.207
Bo
5.25
0.207
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
Doc ID 15335 Rev 4
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Revision history
LNBH23L
10
Revision history
Table 12.
Document revision history
Date
Revision
27-Jan-2009
1
Initial release.
18-May-2009
2
Modified: Figure 3 on page 11, Figure 4 on page 11 and Figure 5 on page 12.
Added: ZEXTM Table 8 on page 19.
09-Sep-2009
3
Modified: IIN, ATONE condition Table 8 on page 19 and Figure 5 on page 12.
29-Nov-2010
4
Modified Table 10 on page 20.
24/25
Changes
Doc ID 15335 Rev 4
LNBH23L
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