LNBH25L
LNB supply and control IC with step-up and I²C interface
Features
■
Complete interface between LNB and I²C bus
■
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @
0.5 A)
■
Selectable output current limit by external
resistor
■
Compliant with main satellite receiver output
voltage specifications
■
Accurate built-in 22 kHz tone generator suits
widely accepted standards
■
22 kHz tone waveform integrity guaranteed
also at no load condition
■
Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allowing low power losses
■
Overload and overtemperature internal
protection with I²C diagnostic bits
■
LNB short-circuit dynamic protection
■
+/- 4 kV ESD tolerant on output power pins
QFN24 (4 x 4 mm)
the LNB down-converter in the antenna dish or to
the multi-switch box. In this application field, it
offers a complete solution with extremely low
component count and low power dissipation
together with a simple design and I²C standard
interfacing.
Applications
■
STB satellite receivers
■
TV satellite receivers
■
PC card satellite receivers
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the
LNBH25L is a monolithic voltage regulator and
interface IC, assembled in QFN24 (4x4)
specifically designed to provide the 13/18 V
power supply and the 22 kHz tone signalling to
Table 1.
Device summary
Order code
Package
Packaging
LNBH25LPQR
QFN24 (4 x 4)
Tape and reel
February 2012
Doc ID 022634 Rev 2
1/28
www.st.com
28
Contents
LNBH25L
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
DiSEqC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4
2.3
Data encoding by external DiSEqC™ envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7
Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8
Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6
2.9
PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.10
OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7
2.11
OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
2/28
6.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.2
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1
Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.2
Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3
Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Doc ID 022634 Rev 2
LNBH25L
Contents
7.4
Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 022634 Rev 2
3/28
Block diagram
1
LNBH25L
Block diagram
Figure 1.
Block diagram
ADDR SCL SDA
PWM CTRL
DSQIN
Isense
LX
I2C Digital core
DAC
Drop control
Tone ctrl
Diagnostics
Protections
PGND
Current
Limit
selection
ISEL
Linear
Regulator
Gate ctrl
VUP
VOUT
Voltage
reference
GND
4/28
BYP VCC
Doc ID 022634 Rev 2
AM10460v1
LNBH25L
2
Application information
Application information
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates the voltages (VUP) that let the integrated LDO post-regulator (generating the
13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC™ tone) to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at
VUP - VOUT = 1 V typ.). The IC is also provided with an undervoltage lockout circuit that
disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V
typically). The step-up converter soft-start function reduces the inrush current during
startup. The SS time is internally fixed at 4ms typ. to switch from 0 to 13 V and 6 ms typ. to
switch from 0 to 18 V.
2.1
DiSEqC data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards,
and can be activated in 3 different ways:
2.2
1.
by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL
compatible). In this case the I²C tone control bits must be set: EXTM = TEN = 1.
2.
by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this
case the I²C tone control bits must be set: EXTM=0 and TEN=1.
3.
through the TEN I²C bit if a 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to “0”.
Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility an external tone signal can be input to the DSQIN pin by
setting the EXTM bit to “1”.
The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the
LNBH25L integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25L tone generator in
terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN
pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible
22 kHz signal is required for the proper control of the DSQIN pin function. Before sending
the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As
soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the
LNBH25L activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL
signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN
has expired (refer to Figure 2).
Figure 2.
Tone enable and disable timing (using external waveform)
DSQIN
~ 1 µs
~ 60 µs
Tone
Output
AM10426v1
Doc ID 022634 Rev 2
5/28
Application information
2.3
LNBH25L
Data encoding by external DiSEqC™ envelope control
through the DSQIN pin
If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz
generator activated during the tone transmission by connecting the DiSEqC envelope
source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and
TEN = 1. In this way, the internal 22 kHz signal is superimposed to the VOUT DC voltage to
generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept HIGH,
the internal control circuit activates the 22 kHz tone output.
The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL
signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to Figure 3).
Figure 3.
Tone enable and disable timing (using envelope signal)
DSQIN
15 µs ~ 60 µs
~ 6 µs
Tone
Output
AM10427v1
2.4
Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:
Equation 1
IMAX ( typ.) =
13915
RSEL1.111
where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
IMAX(typ.) is the typical current limit threshold expressed in mA. IMAX can be set up to
750 mA.
2.5
Output voltage selection
The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 4 bits of an internal DATA1 register (see Section 7.3
and Table 13 for exact programmable values). Register writing is accessible via the I²C bus.
6/28
Doc ID 022634 Rev 2
LNBH25L
2.6
Application information
Diagnostic and protection functions
The LNBH25L has 3 diagnostic internal functions provided via the I²C bus, by reading 3 bits
on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that
is no failure detected), set to LOW. Two diagnostic bits are dedicated to the overtemperature
and overload protection status (OTF and OLF). One bit is dedicated to the input voltage
power not good function (PNG). Once the OLF (or OTF or PNG) bit has been activated (set
to “1”), it is latched to “1” until the relevant cause is removed and a new register reading
operation is done.
2.7
Surge protection and TVS diodes
The LNBH25L device is directly connected to the antenna cable in a set-top box.
Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing
damage to the attached devices. Surge pulses occur due to direct or indirect lightning
strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields
causing high voltage or current transients. Transient voltage suppressor (TVS) devices are
usually used, as shown in the following schematic, to protect the STB output circuits where
the LNBH25L and other devices are electrically connected to the antenna cable.
Figure 4.
Surge protection circuit
For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically
designed by ST. The selection of the LNBTVS diode should be made based on the
maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS
datasheet for further details).
2.8
Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH25L is automatically reset at power-on. As long as the
VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does
not respond to any I²C command and all data register bits are initialized to zeroes, therefore
keeping the power blocks disabled. Once the VCC rises above 4.8 V typ. the I²C interface
becomes operative and the data registers can be configured by the main microprocessor.
2.9
PNG: input voltage minimum detection
When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1” and the FLT pin is set low. Refer to Table 12 for threshold details.
Doc ID 022634 Rev 2
7/28
Application information
2.10
LNBH25L
OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set to LOW, the
overcurrent protection circuit works dynamically: as soon as an overload is detected, the
output current is provided for a TON time of 90 ms, after which the output is set in shutdown
for a TOFF time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system
register is set to “1”. After this time has elapsed, the output is resumed for a time TON. At the
end of TON, if the overload is still detected, the protection circuit cycles again through TOFF
and TON. At the end of a full TON in which no overload is detected, normal operation is
resumed and the OLF diagnostic bit is reset to LOW after a register reading is done. Typical
TON + TOFF time is 990 ms and an internal timer determines it. This dynamic operation can
greatly reduce the power dissipation in a short-circuit condition, still ensuring excellent
power-on startup in most conditions. However, there may be some cases in which a highly
capacitive load on the output can cause a difficult startup when the dynamic protection is
chosen. This can be solved by initiating any power startup in static mode (PCL=1) and then
switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the
output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” when the current
clamp limit is reached and returns LOW when the overload condition is cleared and a
register reading is done.
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the DATA4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To reenable the output stage, the VSEL bits must be set again by the microprocessor, and the
OLF bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed,
and the OLF bit is reset to “0” after a register reading operation.
2.11
OTF: thermal protection and diagnostic
The LNBH25L is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off, the
diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition
is removed, normal operation can be resumed in two ways, according to the THERM I²C bit
on the DATA4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To reenable the output stage, the VSEL bits must be set again by the microprocessor, while the
OTF bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition is
removed, while the OTF bit is reset to “0” after a register reading operation.
8/28
Doc ID 022634 Rev 2
LNBH25L
3
Pin configuration
Pin configuration
Figure 5.
Pin connections (top view)
24
23
22
21
20
19
NC
GND
DSQIN
VUP
VOUT
GND
1
NC
GND
18
2
GND
VCC
17
3
LX
VBYP
16
4
PGND
GND
15
5
NC
NC
14
6
ADDR
NC
13
LNBH25L
Table 2.
SCL
SDA
ISEL
NC
NC
NC
7
8
9
10
11
12
AM10461v1
Pin description
Pin n°
Symbol
Name
Pin function
3
LX
N-MOS drain
Integrated N-channel Power MOSFET drain.
4
P-GND
Power ground
DC-DC converter power ground. To be connected directly to the
Epad.
6
ADDR
Address setting
Two I²C bus addresses available by setting the address pin level
voltage. SeeTable 15.
7
SCL
Serial clock
Clock from I²C bus.
8
SDA
Serial data
Bi-directional data from/to the I²C bus.
9
ISEL
Current selection
2,15, 18, 19,
23
GND
Analog ground
The resistor “RSEL” connected between ISEL and GND defines the
linear regulator current limit threshold. Refer to Section 2.4.
Analog circuits ground. To be connected directly to the Epad.
Needed for internal pre-regulator filtering. The BYP pin is intended
only to connect an external ceramic capacitor. Any connection of
Bypass capacitor
this pin to external current or voltage sources may cause permanent
damage to the device.
16
BYP
17
VCC
Supply input
20
VOUT
LNB output port
Output of the integrated very low drop linear regulator. See Table 13
for voltage selection and description.
21
VUP
Step-up voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
8 to 16 V IC DC-DC power supply.
Doc ID 022634 Rev 2
9/28
Pin configuration
Table 2.
LNBH25L
Pin description (continued)
Pin n°
Symbol
Name
Pin function
22
DSQIN
DSQIN for
DiSEqC envelope
input
or
External 22 kHz
TTL input
It can be used as DiSEqC envelope input or external 22 kHz TTL
input depending on the EXTM I²C bit setting as follows:
EXTM=0, TEN=1: it accepts the DiSEqC envelope code from the
main microcontroller. The LNBH25L uses this code to modulate the
internally generated 22 kHz carrier.
EXTM=TEN=1: it accepts external 22 kHz logic signals which
activate the 22 kHz tone output (refer to Section 2.3).
Pull up high if the tone output is activated only by the TEN I²C bit.
Epad
Epad
Exposed pad
To be connected with power grounds and to the ground layer
through vias to dissipate the heat.
1, 5, 10, 11,
12, 13, 14, 24
N.C.
Not internally
connected
Not internally connected pins. These pins can be connected to GND
to improve thermal performances.
10/28
Doc ID 022634 Rev 2
LNBH25L
Maximum ratings
4
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC power supply input voltage pins
-0.3 to 20
V
VUP
DC input voltage
-0.3 to 40
V
IOUT
Output current
Internally limited
mA
VOUT
DC output pin voltage
-0.3 to 40
V
VI
Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins)
-0.3 to 7
V
LX
LX input voltage
-0.3 to 30
V
VBYP
Internal reference pin voltage
-0.3 to 4.6
V
ISEL
Current selection pin voltage
-0.3 to 3.5
V
TSTG
Storage temperature range
-50 to 150
°C
Operating junction temperature range
-25 to 125
°C
ESD rating with human body model (HBM) all pins, unless power output
pins
2
kV
ESD rating with human body model (HBM) for power output pins
4
TJ
ESD
Table 4.
Symbol
Thermal data
Parameter
Value
Unit
RthJC
Thermal resistance junction-case
2
°C/W
RthJA
Thermal resistance junction-ambient with device soldered on 2s2p 4layer PCB provided with thermal vias below exposed pad.
40
°C/W
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to the network ground terminal.
Doc ID 022634 Rev 2
11/28
Typical application circuits
5
LNBH25L
Typical application circuits
Figure 6.
DiSEqC 1.x application circuit
D2
to LNB
21
D1
C2
Vup
Vout
20
C3
C5
3
LX
D3
LNBH25L
L1
Vin
12V
DiSEqC
22KHz
17
Vcc
22
DSQIN
C4
C1
TTL
or
DiSEqC
Envelope
TTL
2
I C Bus
{
6
ADDR
8
SDA
7
SCL
9
ISEL
R1 (RSEL)
P-GND
A-GND
4
15
Byp
16
C7
AM10462v1
Table 5.
Typical application circuit bill of material
Component
R1 (RSEL)
C1, C2
SMD resistor. Refer to Table 12 and ISEL pin description in Table 2
> 25 V electrolytic capacitor, 100 µF is suitable.
C3
From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.
C5
From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.
C4, C7
12/28
Notes
220 nF ceramic capacitors.
D1
STPS130A or similar schottky diode.
D3
BAT54, BAT43, 1N5818, or any low power schottky diode with IF (AV) > 0.2 A,
VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin.
D2
1N4001-07, S1A-S1M, or any similar general purpose rectifier.
L1
10 µH inductor with Isat > Ipeak where Ipeak is the boost converter peak current.
Doc ID 022634 Rev 2
LNBH25L
6
I²C bus interface
I²C bus interface
Data transmission from the main microprocessor to the LNBH25L and vice versa takes
place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 7, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
6.2
Start and stop condition
As shown in Figure 8, a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 9). The peripheral (LNBH25L) that acknowledges
must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA
line is stable LOW during this clock pulse. The peripheral which has been addressed must
generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH25L does not
generate an acknowledge if the VCC supply is below the undervoltage lockout threshold (4.7
V typ.).
6.5
Transmission without acknowledge
To avoid detection of the LNBH25L acknowledges, the microprocessor can use a simpler
transmission: it simply waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach is of course less protected from misworking and
decreases the noise immunity.
Doc ID 022634 Rev 2
13/28
I²C bus interface
14/28
LNBH25L
Figure 7.
Data validity on the I²C bus
Figure 8.
Timing diagram of I²C bus
Figure 9.
Acknowledge on the I²C bus
Doc ID 022634 Rev 2
LNBH25L
I²C interface protocol
7
I²C interface protocol
7.1
Write mode transmission
The LNBH25L interface protocol is made up of:
●
a start condition (S)
●
a chip address byte with the LSB bit R/W = 0
●
a register address (internal address of the first register to be accessed)
●
a sequence of data (byte to write in the addressed internal register + acknowledge)
●
the following bytes, if any, to be written in successive internal registers
●
a stop condition (P). The transfer lasts until a stop bit is encountered
●
the LNBH25L, as slave, acknowledges every byte transfer.
Figure 10. Example of writing procedure starting with first data address 0x2 (a)
CHIP ADDRESS
N/A
ACK
N/A
N/A
N/A
OLR
N/A
LSB
THERM
N/A
MSB
ACK
N/A
N/A
PCL
N/A
N/A
LSB
N/A
N/A
ACK
N/A
TEN
N/A
EXTM
N/A
N/A
DATA 4
Add=0x5
MSB
LSB
N/A
ACK
N/A
VSEL4
VSEL3
VSEL2
VSEL1
N/A
MSB
LSB
N/A
MSB
DATA 3
Add=0x4
DATA 2
Add=0x3
DATA 1
Add=0x2
N/A
0 0 0 0 0 X X X
ACK
LSB
MSB
ACK
0 X
R/W = 0
0 0 1 0
N/A
0
N/A
S
REGISTER ADDRESS
LSB
MSB
P
AM10463v1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see Table 15 for pin selection) and to
select the REGISTER ADDRESS (see Table 6 to Table 11).
a. The writing procedure can start from any register address by simply setting the X values in the register address
byte (after the chip address). It can be also stopped from the master by sending a stop condition after any
acknowledge bit.
Doc ID 022634 Rev 2
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I²C interface protocol
7.2
LNBH25L
Read mode transmission
In read mode the bytes sequence must be as follows:
●
a start condition (S)
●
a chip address byte with the LSB bit R/W=0
●
the register address byte of the internal first register to be accessed
●
a stop condition (P)
●
a new master transmission with the chip address byte and the LSB bit R/W=1
●
after the acknowledge the LNBH25L starts to send the addressed register content. As
long as the master keeps the acknowledge LOW, the LNBH25L transmits the next
address register byte content.
●
the transmission is terminated when the master sets the acknowledge HIGH with a
following stop bit.
Figure 11. Example of reading procedure starting with first status address 0X0 (b)
REGISTER ADDRESS
N/A
ACK
N/A
N/A
OLR
N/A
N/A
LSB
THERM
N/A
ACK
MSB
N/A
N/A
N/A
ACK
N/A
PCL
N/A
N/A
LSB
N/A
ACK
N/A
TEN
EXTM
N/A
N/A
N/A
DATA 4
Add=0x5
MSB
LSB
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OLF
N/A
N/A
N/A
N/A
ACK
DATA 3
Add=0x4
MSB
ACK
N/A
VSEL4
VSEL3
VSEL2
VSEL1
N/A
N/A
N/A
0 X
LSB
DATA 2
Add=0x3
LSB
0 0 1 0
MSB
LSB
PNG
OTF
MSB
DATA 1
Add=0x2
0
STATUS 2
Add=0x1
STATUS 1
Add=0x0
MSB
S
ACK
P
R/W = 1
0 0 0 0 0 X X X
N/A
0 X
N/A
0 0 1 0
LSB
MSB
N/A
0
LSB
MSB
ACK
S
R/W = 0
LSB
MSB
CHIP ADDRESS
ACK
CHIP ADDRESS
P
AM10464v1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the CHIP ADDRESS (see Table 15 for pin selection) and to
select the REGISTER ADDRESS (see Table 6 to Table 11).
b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X
values in the register address byte (after the first chip address in the above figure). It can be also stopped from
the master by sending a stop condition after any acknowledge bit.
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Doc ID 022634 Rev 2
LNBH25L
7.3
I²C interface protocol
Data registers
The data 1..4 registers can be addressed both in write and read mode. In read mode they
return the last writing byte status received in the previous write transmission.
The following tables provide the register address values of data 1..4 and a function
description of each bit.
Table 6.
Data 1 (read/write register. Register address = 0X2)
BIT
Name
Value
Description
Bit 0
(LSB)
VSEL1
0/1
Bit 1
VSEL2
0/1
Bit 2
VSEL3
0/1
Bit 3
VSEL4
0/1
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit 7
(MSB)
N/A
0
Reserved. Keep to “0”
Output voltage selection bits. (Refer to Table 13)
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 7.
Data 2 (read/write register. Register address = 0X3)
BIT
Name
Bit 0
(LSB)
TEN
Bit 1
N/A
Bit 2
EXTM
Value
Description
1
22 kHz tone enabled. Tone output controlled by the DSQIN pin
0
22 kHz tone output disabled
0
Reserved. Keep to “0”
1
DSQIN input pin is set to receive external 22 kHz TTL signal source
0
DSQIN input pin is set to receive external DiSEqC envelope TTL signal
Bit 3
N/A
0
Reserved. Keep to “0”
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit 7
(MSB)
N/A
0
Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
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I²C interface protocol
Table 8.
LNBH25L
Data 3 (read/write register. Register address = 0X4)
BIT
Name
Value
Description
Bit 0
(LSB)
N/A
0
Reserved. Keep to “0”
Bit 1
N/A
0
Reserved. Keep to “0”
1
Pulsed (Dynamic) LNB output current limiting is deactivated
Bit 2
PCL
0
Pulsed (Dynamic) LNB output current limiting is activated
Bit 3
N/A
0
Reserved. Keep to “0”
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit 7
(MSB)
N/A
0
Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 9.
Data 4 (read/write register. Register address = 0X5)
BIT
Name
Value
Bit 0
(LSB)
N/A
0
Reserved. Keep to “0”
Bit 1
N/A
0
Reserved. Keep to “0”
Bit 2
N/A
0
Reserved. Keep to “0”
1
In case of overload protection activation (OLF=1), all VSEL 1..4 bits are reset to
“0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the
master after the overcurrent condition is removed (OLF=0).
0
In case of overload protection activation (OLF=1) the LNB output (VOUT pin) is
automatically enabled as soon as the overload condition is removed (OLF=0) with
the previous VSEL bits setting.
Bit 3
Description
OLR
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
1
If thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and
LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master
after the overtemperature condition is removed (OTF=0).
0
In case of thermal protection activation (OTF=1) the LNB output (VOUT pin) is
automatically enabled as soon as the overtemperature condition is removed
(OTF=0) with the previous VSEL bits setting.
0
Reserved. Keep to “0”
Bit 6
Bit 7
(MSB)
THERM
N/A
N/A = Reserved bit.
All bits reset to “0” at power-on.
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LNBH25L
7.4
I²C interface protocol
Status registers
The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic
functions described in the following tables.
Table 10.
STATUS 1 (Read register. Register address = 0X0)
BIT
Name
Bit 0
(LSB)
OLF
Value
Description
1
VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 8 for
the overload operation settings (PCL bit).
0
No overload protection has been triggered to the VOUT pin (IOUT < IMAX).
Bit 1
N/A
-
Reserved
Bit 2
N/A
-
Reserved
Bit 3
N/A
-
Reserved
Bit 4
N/A
-
Reserved
Bit 5
N/A
-
Reserved
1
Junction overtemperature is detected, TJ > 150 °C. See also the THERM bit
setting in Table 9.
0
Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal
protection threshold.
1
Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 12.
0
Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 12.
Bit 6
Bit 7
(MSB)
OTF
PNG
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 11.
STATUS 2 (Read register. Register address = 0X1)
BIT
Name
Value
Description
Bit 0
(LSB)
N/A
-
Reserved
Bit 1
N/A
-
Reserved
Bit 2
N/A
-
Reserved
Bit 3
N/A
-
Reserved
Bit 4
N/A
-
Reserved
Bit 5
N/A
-
Reserved
Bit 6
N/A
-
Reserved
Bit 7
(MSB)
N/A
-
Reserved
N/A = Reserved bit.
All bits reset to “0” at power-on.
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Electrical characteristics
8
LNBH25L
Electrical characteristics
Refer to Section 5, TJ from 0 to 85 °C, all data 1..4 register bits set to 0 unless VSEL1 = 1,
RSEL = 16.2 kΩ, DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise stated. Typical
values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description section
for I²C access to the system register (Section 6 and Section 7).
Table 12.
Symbol
VIN
IIN
.
Electrical characteristics
Parameter
Test conditions
Supply voltage (1)
Supply current
Min.
Typ.
Max.
Unit
8
12
16
V
IOUT =0 mA
6
22 kHz tone enabled (TEN=1,
DSQIN=High), IOUT=0 mA
10
VSEL1=VSEL2=VSEL3=VSEL4=0
1
VOUT
Output voltage total accuracy Valid at any VOUT selected level
VOUT
Line regulation
VIN=8 to 16 V
VOUT
Load regulation
IOUT from 50 to 500 mA
IMAX
Output current limiting
thresholds
RSEL = 16.2 kΩ
RSEL = 22 kΩ
ISC
Output short-circuit current
RSEL= 16.2 kΩ
SS
Soft-start time
SS
-3.5
75
mA
+3.5
%
40
mV
100
500
750
350
550
mA
350
mA
VOUT from 0 to 13 V
4
ms
Soft-start time
VOUT from 0 to 18 V
6
ms
T13-18
Soft transition rise time
VOUT from 13V to 18 V
1.5
ms
T18-13
Soft transition fall time
VOUT from 18V to 13 V
1.5
ms
TOFF
Dynamic overload protection
OFF time
PCL=0, output shorted
900
TON
Dynamic overload protection
ON time
PCL=0, output shorted
TOFF/10
ATONE
Tone amplitude
DSQIN=High, EXTM=0, TEN=1
IOUT from 0 to 500 mA
CBUS from 0 to 750 nF
FTONE
Tone frequency
DTONE
Tone duty cycle
ms
tr, tf
Tone rise or fall time
DSQIN=High, EXTM=0, TEN=1
(2)
Eff DC/DC
DC-DC converter efficiency
FSW
DC-DC converter switching
frequency
UVLO
VLP
20/28
IOUT=500mA
0.55
0.675
0.8
VPP
20
22
24
kHz
43
50
57
%
5
8
15
µs
93
%
440
kHz
Undervoltage lockout
thresholds
UVLO threshold rising
4.8
UVLO threshold falling
4.7
Low power diagnostic (LPD)
thresholds
VLP threshold rising
7.2
VLP threshold falling
6.7
V
Doc ID 022634 Rev 2
V
LNBH25L
Electrical characteristics
Table 12.
Electrical characteristics (continued)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.8
V
VIL
DSQIN, pin logic low
VIH
DSQIN, pin logic high
IIH
DSQIN, pin input current
VIH=5 V
15
IOBK
Output backward current
All VSELx=0, VOBK=30 V
-3
ISINK
Output low-side sink current
VOUT forced at VOUT_nom+0.1 V
70
mA
Low-side sink current timeout VOUT forced at VOUT_nom+0.1 V
10
ms
VOUT forced at VOUT_nom+0.1 V,
after ISINK_TIME-OUT is elapsed
2
mA
ISINK_TIMEOUT
IREV
2
Max. reverse current
V
µA
-6
mA
TSHDN
Thermal shutdown threshold
150
°C
ΔTSHDN
Thermal shutdown hysteresis
15
°C
1. In applications where (VCC-VOUT) >1.3 V, the increased power dissipation inside the integrated LDO must be taken into
account in the application thermal management design.
2. Guaranteed by design.
Table 13.
Output voltage selection table (Data1 register, write mode)
VOUT
min.
VOUT pin
voltage
VOUT
max.
VSEL4
VSEL3
VSEL2
VSEL1
0
0
0
0
0
0
0
1
12.545
13.000
13.455
0
0
1
0
12.867
13.333
13.800
0
0
1
1
13.188
13.667
14.145
0
1
0
0
13.51
14.000
14.490
1
0
0
0
17.515
18.150
18.785
1
0
0
1
17.836
18.483
19.130
1
0
1
0
18.158
18.817
19.475
1
0
1
1
18.48
19.150
19.820
Function
VOUT disabled. LNBH25L set in standby
0.000
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Electrical characteristics
LNBH25L
TJ from 0 to 85 °C, VI = 12 V.
Table 14.
Symbol
I²C electrical characteristics
Parameter
Test conditions
VIL
Low level input voltage
SDA, SCL
VIH
High level input voltage
SDA, SCL
IIN
Input current
VOL
FMAX
Low level output voltage
Maximum clock frequency
Typ.
Max.
Unit
0.8
V
2
SDA, SCL, VIN = 0.4 to 4.5 V
(1)
Min.
V
-10
SDA (open drain), IOL = 6 mA
SCL
10
µA
0.6
V
400
kHz
1. Guaranteed by design.
TJ from 0 to 85 °C, VI = 12 V.
Table 15.
Address pin characteristics
Symbol
Parameter
Test condition
Min.
VADDR-1
“0001000(R/W)” address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
VADDR-2
“0001001(R/W)” address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
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Doc ID 022634 Rev 2
Typ.
Max.
Unit
0
0.8
V
2
5
V
LNBH25L
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 16.
QFN24L (4 x 4 mm) mechanical data
(mm)
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
3.90
4.00
4.10
D2
2.55
2.70
2.80
E
3.90
4.00
4.10
E2
2.55
2.70
2.80
e
0.45
0.50
0.55
L
0.25
0.35
0.45
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Package mechanical data
LNBH25L
Figure 12. QFN24L (4 x 4 mm) package dimensions
7596209_D
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Doc ID 022634 Rev 2
LNBH25L
Package mechanical data
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
330
C
12.8
D
20.2
N
99
13.2
Max.
12.992
0.504
0.519
0.795
101
T
3.898
3.976
14.4
0.567
Ao
4.35
0.171
Bo
4.35
0.171
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
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Package mechanical data
LNBH25L
Figure 13. QFN24L (4 x 4) footprint recommended data (mm.)
26/28
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LNBH25L
Revision history
10
Revision history
Table 17.
Document revision history
Date
Revision
Changes
09-Jan-2012
1
Initial release.
15-Feb-2012
2
Modified: D1 and D3 Table 5 on page 12.
Doc ID 022634 Rev 2
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LNBH25L
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