LNBH25S
LNB supply and control IC with step-up and I²C interface
Datasheet - production data
Low drop post regulator and high efficiency
step-up PWM with integrated power NMOS
allowing low power losses
LPM function (low power mode) to reduce
dissipation
Overload and overtemperature internal
protections with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
Applications
Features
Complete interface between LNB and I²C
bus
Built-in DC-DC converter for single 12 V
supply operation and high efficiency
(typ. 93% @ 0.5 A)
Selectable output current limit by external
resistor
Compliant with main satellite receiver output
voltage specifications (15 programmable
levels)
Accurate built-in 22 kHz tone generator suits
widely accepted standards
22 kHz tone waveform integrity guaranteed
at no-load condition
STB satellite receivers
TV satellite receivers
PC card satellite receivers
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the
LNBH25S is a monolithic voltage regulator and
interface IC, assembled in QFN24L (4x4 mm)
specifically designed to provide 13/18 V power
supply and 22 kHz tone signaling to the LNB
down-converter in the antenna dish or to the
multi-switch box. In this application field, it offers
a complete solution with extremely low
component count and low power dissipation
together with a simple design and I²C standard
interface.
Table 1: Device summary
Order code
Package
Packing
LNBH25SPQR
QFN24L (4x4)
Tape and reel
October 2016
DocID026736 Rev 3
This is information on a product in full production.
1/37
www.st.com
Contents
LNBH25S
Contents
1
Block diagram.................................................................................. 6
2
Application information .................................................................. 7
2.1
DiSEqC data encoding (DSQIN pin) ................................................. 7
2.2
Data encoding by external 22 kHz tone TTL signal ........................... 7
2.3
Data encoding by external DiSEqC envelope control through the
DSQIN pin ...................................................................................................... 8
2.4
LPM (low power mode) ..................................................................... 8
2.5
DiSEqC 2.0 implementation .............................................................. 8
2.6
Output current limit selection ............................................................. 9
2.7
Output voltage selection .................................................................... 9
2.8
Diagnostic and protection functions .................................................. 9
2.9
Surge protections and TVS diodes.................................................... 9
2.10
FLT (fault flag) ................................................................................. 10
2.11
VMON (output voltage diagnostic) .................................................. 10
2.12
TMON (22 kHz tone diagnostic) ...................................................... 10
2.13
TDET (22 kHz tone detection) ......................................................... 10
2.14
IMON (minimum output current diagnostic) ..................................... 10
2.15
PDO (overcurrent detection on output pull-down stage) ................. 11
2.16
Power-on I²C interface reset and undervoltage lockout .................. 11
2.17
PNG (input voltage minimum detection) .......................................... 11
2.18
ISW (inductor switching current limit) .............................................. 11
2.19
COMP (boost capacitors and inductor) ........................................... 11
2.20
OLF (overcurrent and short-circuit protection and diagnostic) ........ 12
2.21
OTF (thermal protection and diagnostic) ......................................... 12
3
4
Pin configuration ........................................................................... 13
Maximum ratings ........................................................................... 15
5
Typical application circuits........................................................... 16
6
I²C bus interface ............................................................................ 19
2/37
6.1
Data validity..................................................................................... 19
6.2
Start and stop condition .................................................................. 19
6.3
Byte format ...................................................................................... 19
6.4
Acknowledge ................................................................................... 19
DocID026736 Rev 3
LNBH25S
Contents
6.5
7
Transmission without acknowledge ................................................. 19
I²C interface protocol .................................................................... 21
7.1
Write mode transmission ................................................................. 21
7.2
Read mode transmission ................................................................ 21
7.3
Data registers .................................................................................. 23
7.4
Status registers ............................................................................... 26
8
Electrical characteristics .............................................................. 28
9
Package information ..................................................................... 33
9.1
10
QFN24L (4x4 mm) package information ......................................... 34
Revision history ............................................................................ 36
DocID026736 Rev 3
3/37
List of tables
LNBH25S
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description ............................................................................................................................ 13
Table 3: Absolute maximum ratings ......................................................................................................... 15
Table 4: Thermal data ............................................................................................................................... 15
Table 5: DiSEqC 1.x bill of material .......................................................................................................... 16
Table 6: DiSEqC 2.x bill of material .......................................................................................................... 18
Table 7: Data 1 (read/write register. Register address = 0X2) ................................................................. 23
Table 8: Data 2 (read/write register. Register address = 0X3) ................................................................. 23
Table 9: Data 3 (read/write register. Register address = 0X4) ................................................................. 24
Table 10: Data 4 (read/write register. Register address = 0X5) ............................................................... 25
Table 11: Status 1 (read register. Register address = 0X0) ..................................................................... 26
Table 12: Status 2 (read register. Register address = 0X1) ..................................................................... 27
Table 13: Electrical characteristics ........................................................................................................... 28
Table 14: Output voltage selection table (data1 register, write mode) ..................................................... 30
Table 15: I²C electrical characteristics ...................................................................................................... 30
Table 16: Address pin characteristics ....................................................................................................... 31
Table 17: Output voltage diagnostic (VMON bit, status 1 register) characteristics .................................. 31
Table 18: Output current diagnostic (IMON bit, status 2 register) characteristics .................................... 31
Table 19: 22 kHz tone diagnostic (TMON bit, status 2 register) characteristics....................................... 32
Table 20: QFN24L (4x4 mm) mechanical data ......................................................................................... 35
Table 21: Document revision history ........................................................................................................ 36
4/37
DocID026736 Rev 3
LNBH25S
List of figures
List of figures
Figure 1: Block diagram .............................................................................................................................. 6
Figure 2: Tone enable and disable timing (using external waveform) ........................................................ 8
Figure 3: Tone enable and disable timing (using envelope signal) ............................................................ 8
Figure 4: Surge protection circuit .............................................................................................................. 10
Figure 5: Pin connection (top view) .......................................................................................................... 13
Figure 6: DiSEqC 1.x application circuit ................................................................................................... 16
Figure 7: DiSEqC 2.x application circuit ................................................................................................... 17
Figure 8: Data validity on the I²C bus ....................................................................................................... 20
Figure 9: Timing diagram of I²C bus ......................................................................................................... 20
Figure 10: Acknowledge on the I²C bus.................................................................................................... 20
Figure 11: Example of writing procedure starting with first data address 0X2 ......................................... 21
Figure 12: Example of reading procedure starting with first status address 0X0 ..................................... 22
Figure 13: QFN24L (4x4 mm) package outline ........................................................................................ 34
Figure 14: QFN24L (4x4 mm) recommended footprint ............................................................................. 35
DocID026736 Rev 3
5/37
Block diagram
1
LNBH25S
Block diagram
Figure 1: Block diagram
6/37
DocID026736 Rev 3
LNBH25S
2
Application information
Application information
This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V),
generates voltages (VUP) which let the integrated LDO post-regulator (generating13 V/18 V
LNB output voltages plus 22 kHz DiSEqC™ tone) work with a minimum dissipated power of
0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at VUP-VOUT = 1 V typ.).
The LDO power dissipation can be reduced when 22 kHz tone output is disabled by setting
the LPM bit to “1” see Section 2.4: "LPM (low power mode)". The IC is also provided with
an undervoltage lockout circuit that disables the whole circuit when the supplied V CC drops
below a fixed threshold (4.7 V typ.). The step-up converter soft-start function reduces the
inrush current during startup. SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V
and 6 ms typ. switch from 0 to 18 V.
2.1
DiSEqC data encoding (DSQIN pin)
The internal 22 kHz tone generator is factory trimmed in accordance with DiSEqC
standards, and can be active in 3 different ways:
1.
2.
3.
By an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL
compatible). In this case I²C tone control bits have to be set: EXTM = TEN = 1.
By an external DiSEqC data envelope source connected to the DSQIN logic pin. In
this case I²C tone control bits must be set: EXTM = 0 and TEN = 1.
Through TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this
case the DSQIN TTL pin must be pulled high and EXTM bit is set to “0”.
Each of the above solutions requires that during the 22 kHz tone activation and/or DiSEqC
data transmission, the LPM bit has to be set to “0” see Section 2.4: "LPM (low power
mode)".
2.2
Data encoding by external 22 kHz tone TTL signal
In order to improve design flexibility, an external tone signal can be input to the DSQIN pin
by setting the EXTM bit to “1”.
The DSQIN is a logic input pin, which activates the 22 kHz tone to the VOUT pin, by using
the LNBH25S integrated tone generator.
The output tone waveforms are internally controlled by the LNBH25S tone generator in
terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN
pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible
22 kHz signal is required for the proper control of the DSQIN pin function. Before sending
the TTL signal to the DSQIN pin, the EXTM and TEN bits have to be previously set to “1”.
As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the
LNBH25S activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL
signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN
has expired, refer to Figure 2: "Tone enable and disable timing (using external waveform)".
DocID026736 Rev 3
7/37
Application information
LNBH25S
Figure 2: Tone enable and disable timing (using external waveform)
2.3
Data encoding by external DiSEqC envelope control through
the DSQIN pin
If an external DiSEqC envelope source is available, the internal 22 kHz generator can be
activated during the tone transmission by connecting the DiSEqC envelope source to the
DSQIN pin. In this case the I²C tone control bits must be set: EXTM = 0 and TEN = 1. In
this manner, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate
the LNB output 22 kHz tone. During the period in which the DSQIN is kept high, the internal
control circuit activates the 22 kHz tone output.
The 22 kHz tone on the VOUT pin is active with about 6 µs delay from the DSQIN TTL
signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the
22 kHz TTL signal on DSQIN has expired, refer to Figure 3: "Tone enable and disable
timing (using envelope signal)".
Figure 3: Tone enable and disable timing (using envelope signal)
DSQIN
15 µs ~ 60 µs
~ 6 µs
T one
output
GIPG0907141158LM
2.4
LPM (low power mode)
In order to reduce the total power loss, the LNBH25S is provided with the LPM I²C bit that
can be activated (LPM=1) in applications where the 22 kHz tone can be disabled for long
time periods. The LPM bit can be set to “1” when the DiSEqC data transmission is not
requested (no 22 kHz tone output is present); the drop voltage across the integrated LDO
regulator (VUP-VOUT) is reduced to 0.6 V typ. and, consequently, the power loss inside the
LNBH25S linear regulator is reduced as well. For example: at 500 mA load, LPM=1
allowing a minimum LDO dissipated power of 0.3 W typ. It is recommended to set the LPM
bit to “0” before starting the 22 kHz DiSEqC data transmission; at this condition the drop
voltage across the LDO is kept to 1 V typ. LPM=0 if the LPM function is not used.
2.5
DiSEqC 2.0 implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqC 2.0 interfacing.
The input pin (DETIN) has to be AC coupled to the DiSEqC bus, and extracted PWK data
is available on the DSQOUT pin. To comply with the bi-directional DiSEqC 2.0 bus
hardware requirements, an output RL filter is needed. In order to avoid 22 kHz waveform
8/37
DocID026736 Rev 3
LNBH25S
Application information
distortion during tone transmission, the LNBH25S is provided with the BPSW pin to be
connected to an external transistor, which allows the output RL filter to be bypassed in
DiSEqC 2.x applications while in transmission mode. Before starting tone transmission,
TEN bit has to be set to “1” and after ending tone transmission, TEN bit has to be set to “0”.
2.6
Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:
ILIM (typ.) = 13915
RSEL1.111
with ISET=0
ILIM (typ.) = 6808
RSEL1.068
with ISET=1
see ISET bit description in Table 9: "Data 3 (read/write register. Register address = 0X4)",
where RSEL is the resistor connected between ISEL and GND expressed in kΩ and
ILIM(typ.) is the typical current limit threshold expressed in mA. ILIM can be set up to 1 A.
2.7
Output voltage selection
The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 4 bits of an internal data 1 register, see Section
7.3: "Data registers" for exact programmable values. Register writing is accessible via I²C
bus.
2.8
Diagnostic and protection functions
The LNBH25S has 8 diagnostic internal functions provided by I²C bus, by reading 8 bits on
two status registers (in read mode). All the diagnostic bits are, in normal operation (that is
no failure detected), set to low. Two diagnostic bits are dedicated to the overtemperature
and overload protection status (OTF and OLF) while the remaining 6 bits are dedicated to
the output voltage level (VMON), to 22 kHz tone characteristics (TMON), to the minimum
load current (IMON), to external voltage source presence on the VOUT pin (PDO), to the
input voltage power not good function (PNG) and to the 22 kHz tone presence on the
DETIN pin (TDET). Once the OLF (or OTF or PNG) bit has been activated (set to “1”), it is
latched to “1” until relevant cause is removed and a new register reading operation is
performed.
2.9
Surge protections and TVS diodes
The LNBH25S device is directly connected to the antenna cable in a set-top box.
Atmospheric phenomenon can cause high voltage discharges on the antenna cable
causing damage to the attached devices. Surge pulses occur due to direct or indirect
lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic
fields causing high voltage or current transients. Transient voltage suppressor (TVS)
devices are usually placed, as shown in the following schematic, to protect the STB output
circuits where the LNBH25S and other devices are electrically connected to the antenna
cable.
DocID026736 Rev 3
9/37
Application information
LNBH25S
Figure 4: Surge protection circuit
For this purpose, the use of the LNBTVSxx surge protection diodes specifically designed
by ST is recommended. The selection of the LNBTVSxx diodes should be based on the
maximum peak power dissipation supported by the diode (see the LNBTVS datasheet for
further details).
2.10
FLT (fault flag)
In order to get an immediate feedback on diagnostic status, the LNBH25S is equipped with
a dedicated fault flag pin (FLT). In case of overload (OLF bit=1) or overheating (OTF bit=1)
or if “power no good” (PNG bit=1) condition is detected, the FLT pin (open drain output) is
set to low and is kept low until the relevant activating diagnostic bit is cleared. Diagnostic
bits: OLF, OTF and PNG, once activated, are kept latched to “1” until the root cause is
removed and a new register reading operation is performed by the microprocessor. The
FLT pin has to be connected to a positive voltage (5 V max.) by a pull-up resistor.
2.11
VMON (output voltage diagnostic)
When the device output voltage is activated (VOUT pin), its value is internally monitored
and, as long as the output voltage level is below the guaranteed limits, VMON I²C bit is set
to “1”. See Table 17: "Output voltage diagnostic (VMON bit, status 1 register)
characteristics" for more details.
2.12
TMON (22 kHz tone diagnostic)
The 22 kHz tone can be internally detected and monitored if DETIN pin is connected to the
LNB output bus, see typical application circuit in Figure 7: "DiSEqC 2.x application circuit",
through a decoupling capacitor. The tone diagnostic function is provided with TMON I²C bit.
If the 22 kHz tone amplitude and/or the tone frequency is out of the guaranteed limits, see
Table 19: "22 kHz tone diagnostic (TMON bit, status 2 register) characteristics", TMON I²C
bit is set to “1”.
2.13
TDET (22 kHz tone detection)
When a 22 kHz tone presence is detected on DETIN pin, TDET I²C bit is set to “1”.
2.14
IMON (minimum output current diagnostic)
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH25S is provided with a minimum output current flag by the
IMON I²C bit, accessible in read mode, which is set to “1” if the output current is lower than
12 mA (typ.). IMON function should be used with the 22 kHz tone transmission deactivated,
otherwise the IMON bit could be set to “0” even if the output current is below the minimum
current threshold. To activate IMON diagnostic function, set to “1” the EN_IMON I²C bit in
10/37
DocID026736 Rev 3
LNBH25S
Application information
the data 4 register. As soon as the IMON function is active by EN_IMON = 1, VOUT rises 21
V (typ.) on the VSEL bit setting. This operation is applied to be sure that the LNBH25S
output has the higher voltage in the LNB bus. Do not use this function in an application
environment where 21 V voltage level is not supported by other peripherals connected to
the LNB bus.
2.15
PDO (overcurrent detection on output pull-down stage)
When an overcurrent occurs on the pull-down output stage due to an external voltage
source greater than the LNBH25S nominal VOUT and for a time longer than ISINK_TIME-OUT (10
ms typ.), PDO I²C bit is set to “1”. This may happen due to an external voltage source on
the LNB output (VOUT pin).
For current threshold and deglitch time details, see Table 13: "Electrical characteristics".
2.16
Power-on I²C interface reset and undervoltage lockout
The I²C interface, built into the LNBH25S, is automatically reset at power-on. As long as
the VCC is below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does
not respond to any I²C command and all data register bits are initialized to zero, therefore
the power blocks are disabled. Once VCC rises above 4.8 V typ. the I²C interface becomes
operative and data registers can be configured by the main microprocessor.
2.17
PNG (input voltage minimum detection)
When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum
thresholds, the PNG I²C bit is set to “1” and the FLT pin is set low. See Table 13: "Electrical
characteristics" for threshold details.
2.18
ISW (inductor switching current limit)
In order to allow low saturation current inductors to be used, the maximum DC-DC inductor
switching current limit threshold can be set by one I²C bit (ISW). Two values are available:
2.5 A typ. (with ISW = 1) and 4 A typ. (with ISW = 0).
2.19
COMP (boost capacitors and inductor)
The DC-DC converter compensation loop can be optimized to properly work with both
ceramic and electrolytic capacitors (VUP pin). For this purpose, one I²C bit in the data 4
register, see table 10, where COMP can be set to “1” or “0” as follows:
COMP = 0 for electrolytic capacitors
COMP = 1 for ceramic capacitors
For recommended DC-DC capacitor and inductor values see Section 5: "Typical
application circuits" and the BOM in and Table 6: "DiSEqC 2.x bill of material".
DocID026736 Rev 3
11/37
Application information
2.20
LNBH25S
OLF (overcurrent and short-circuit protection and
diagnostic)
To reduce the total power dissipation during an overload or a short-circuit condition, the
device is provided with a dynamic short-circuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of I²C data 3 register. When the PCL (pulsed current limiting) bit is set low, the
overcurrent protection circuit works dynamically: as soon as an overload is detected, the
output current is provided for T ON time (90 ms or 180 ms typ., according to the TIMER bit
programmed in the data 3 register) and after that, the output is set in shutdown for T OFF
time of typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the system register
is set to “1” and the FLT pin is set to low level. After this time has elapsed, the output is
resumed for a time TON. At the end of TON, if the overload is still detected, the protection
circuit cycles again through T OFF and TON. At the end of a full TON in which no overload is
detected, normal operation is resumed and the OLF diagnostic bit is reset to low after a
register reading. Typical TON +TOFF time is 990 ms (if TIMER=0) or 1080 ms (if TIMER=1)
and it is determined by an internal timer. This dynamic operation can reduce the power
dissipation in short-circuit condition, assuring excellent power-on startup in most conditions.
However, there may be some cases in which a highly capacitive load on the output may
cause a difficult startup when the dynamic protection is chosen. This can be solved by
initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic
mode (PCL=0) after a specified period of time depending on the output capacitance. Also
in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the
current clamp limit is reached and returns low when the overload condition is cleared and
register reading is performed.
After the overload condition is removed, normal operation can be resumed in two ways,
according to the OLR I²C bit on the data 4 register.
If OLR=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To reenable the output stage, VSEL bits have to be set again by the microprocessor, and the
OLF bit is reset to “0” after a register reading operation.
If OLR=0, output is automatically re-enabled as soon as the overload condition is removed,
and the OLF bit is reset to “0” after a register reading operation.
2.21
OTF (thermal protection and diagnostic)
The LNBH25S is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the linear regulator shut off, the
diagnostic OTF bit in the status 1 register is set to “1” and the FLT pin is set to low level.
After the overtemperature condition is removed, normal operation can be resumed in two
ways, according to the THERM I²C bit on the data 4 register.
If THERM=1, all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. To
re-enable the output stage, VSEL bits must be set again by the microprocessor, while the
OTF bit is reset to “0” after a register reading operation.
If THERM=0, output is automatically re-enabled as soon as the overtemperature condition
is removed, while the OTF bit is reset to “0” after a register reading operation.
12/37
DocID026736 Rev 3
LNBH25S
3
Pin configuration
Pin configuration
Figure 5: Pin connection (top view)
24
NC
1
2
3
4
5
6
23
22
DSQOUT DSQIN/
EXTM
21
VUP
20
19
VOUT DETIN
BPSW 18
NC
FLT
VCC
LX
VBYP 16
PGND
GND
15
NC
NC
14
ADDR
NC
13
SCL
SDA
ISEL
NC
NC
NC
7
8
9
10
11
12
17
GIPG0907141409LM
Table 2: Pin description
Pin
Symbol
Name
Pin function
Open drain output for IC fault conditions. It is set low in
case of overload (OLF bit) or overheating status (OTF
bit) or power not good (PNG) is detected. To be
connected to pull-up resistor (5 V max.)
2
FLT
FLT
3
LX
NMOS drain
4
PGND
Power
ground
DC-DC converter power ground. To be connected
directly to exposed pad
6
ADDR
Address
setting
Two I²C bus addresses available by setting the address
pin level voltage.
7
SCL
Serial clock
Clock from I²C bus
8
SDA
Serial data
Bi-directional data from/to I²C bus
Integrated N-channel power MOSFET drain
The resistor “RSEL” connected between ISEL and GND
defines the linear regulator current limit threshold. Refer
to Section 2.6: "Output current limit selection" and ISET
bit description in Table 9: "Data 3 (read/write register.
Register address = 0X4)"
9
ISEL
Current
selection
15
GND
Analog
ground
Analog circuit ground. To be connected directly to the
exposed pad
16
VBYP
Bypass
capacitor
Needed for internal pre-regulator filtering. The VBYP
pin connects an external ceramic capacitor. Any
connection of this pin to external current or voltage
sources may cause permanent damage to the device
17
VCC
Supply input
8 to 16 V IC DC-DC power supply
DocID026736 Rev 3
13/37
Pin configuration
Pin
Symbol
Name
Pin function
18
BPSW
Switch
control
To be connected to an external transistor to be used to
bypass the output RL filter needed in DiSEqC 2.x
applications during DiSEqC transmitting mode, see
Section 5: "Typical application circuits". Set to ground if
it is not used. Open drain pin
19
DETIN
Tone
detector
input
22 kHz tone decoder input open drain pin has to be AC
coupled to the DiSEqC 2.0 bus. Set to ground if it is not
used
20
VOUT
LNB output
port
Output of the integrated very low drop linear regulator.
VUP
Step-up
voltage
21
Input of the linear post-regulator. The voltage on this
pin is monitored by the internal step-up controller to
keep a minimum dropout across the linear pass
transistor
It can be used as DiSEqC envelope input or external 22
kHz TTL input depending on EXTM I²C bit setting as
follows:
EXTM=0, TEN=1. It accepts the DiSEqC envelope
code from the main microcontroller. The LNBH25S
uses this code to modulate the internally generated 22
kHz carrier.
If EXTM=TEN=1. It accepts external 22 kHz logic
signals which activate the 22 kHz tone output, refer to
Section 2.3: "Data encoding by external DiSEqC
envelope control through the DSQIN pin".
Pull-up high if the tone output is activated by the TEN
I²C bit only
DSQIN
DSQIN for
DiSEqC
envelope
input
or
external 22
kHz TTL
input
23
DSQOUT
DiSEqC
output
Open drain output of the tone detector to the main
microcontroller for DiSEqC 2.0 data decoding. It is low
when tone is detected to the DETIN input pin. Set to
ground if it is not used
Epad
Epad
Exposed pad
To be connected with power ground and to the ground
layer through vias to dissipate heat
1, 5, 10,
11, 12, 13,
14, 24
NC
Not internally
connected
Not internally connected. These pins can be connected
to GND to improve thermal performance
22
14/37
LNBH25S
DocID026736 Rev 3
LNBH25S
4
Maximum ratings
Maximum ratings
Table 3: Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC power supply input voltage pins
-0.3 to 20
V
VUP
DC input voltage
-0.3 to 40
V
IOUT
Output current
Internally limited
mA
VOUT
DC output pin voltage
-0.3 to 40
V
VI
Logic input pin voltage (SDA, SCL, DSQIN, ADDR
pins)
-0.3 to 7
V
VO
Logic output pin voltage (FLT, DSQOUT)
-0.3 to 7
V
VBPSW
BPSW pin voltage
-0.3 to 40
V
VDETIN
Detector input signal amplitude
-0.6 to 2
V
10
mA
IO
Logic output pin current (FLT, DSQOUT, BPSW)
LX
LX input voltage
-0.3 to 30
V
VBYP
Internal reference pin voltage
-0.3 to 4.6
V
ISEL
Current selection pin voltage
-0.3 to 3.5
V
TSTG
Storage temperature range
-50 to 150
°C
Operating junction temperature range
-25 to 125
°C
ESD rating with human body model (HBM) all pins,
unless power output pins
2
kV
ESD rating with human body model (HBM) for
power output pins
4
TJ
ESD
Table 4: Thermal data
Symbol
Parameter
Value
Unit
RthJC
Thermal resistance junction-case
2
°C/W
RthJA
Thermal resistance junction-ambient with the device soldered
on 2s2p 4-layer PCB provided with thermal vias below exposed
pad
40
°C/W
Absolute maximum ratings are those values beyond which damage to the device
may occur. These are stress ratings only and functional operation of the device at
these conditions is not implied. Exposure to absolute maximum-rated conditions
for extended periods may affect the device reliability. All voltage values are
referred to network ground terminal.
DocID026736 Rev 3
15/37
Typical application circuits
5
LNBH25S
Typical application circuits
Figure 6: DiSEqC 1.x application circuit
Table 5: DiSEqC 1.x bill of material
Component
R1 (RSEL)
SMD resistor. Refer to Table 13: "Electrical characteristics" and ISEL pin
description in Table 2: "Pin description"
C1
> 25 V electrolytic capacitor, 100 µF or higher is suitable
or
> 25 V ceramic capacitor, 10 µF or higher is suitable
C2
With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable
or
with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is
suitable
C3
From 470 nF to 2.2 µF ceramic capacitor placed as closer as possible to VUP
pins. Higher values allow lower DC-DC noise
C5
From 100 nF to 220 nF ceramic capacitor placed as close as possible to VOUT
pins. Higher values allow lower DC-DC noise
C4, C7
16/37
Notes
220 nF ceramic capacitors. To be placed as close as possible to VOUT pin
D1
STPS130A or similar Schottky diode
D2
1N4001-07, S1A-S1M, or any similar general purpose rectifier
DocID026736 Rev 3
LNBH25S
Typical application circuits
Component
Notes
D3
BAT54, BAT43, 1N5818, or any low power Schottky diode with I F(AV) > 0.2 A,
VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin
L1
With COMP=0, use 10 µH inductor with ISAT > IPEAK where IPEAK is the boost
converter peak current, or
with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with ISAT > IPEAK where IPEAK
is the boost converter peak current
Figure 7: DiSEqC 2.x application circuit
DocID026736 Rev 3
17/37
Typical application circuits
LNBH25S
Table 6: DiSEqC 2.x bill of material
Component
R1 (RSEL)
SMD resistor. Refer to Table 13: "Electrical characteristics" and ISEL pin
description in Table 2: "Pin description"
C1
> 25 V electrolytic capacitor, 100 µF or higher is suitable
or
> 25 V ceramic capacitor, 10 µF or higher is suitable
C2
With COMP = 0, > 25 V electrolytic capacitor, 100 µF or higher is suitable
or
with COMP = 1, > 35 V ceramic capacitor, 22 µF (or 2 x10 µF) or higher is suitable
C3
From 470 nF to 2.2 µF ceramic capacitor placed as closer as possible to VUP pin.
Higher values allow lower DC-DC noise
C5
From 100 nF to 220 nF ceramic capacitor placed as closer as possible to VOUT
pin. Higher values allow lower DC-DC noise
C4, C7
220 nF ceramic capacitors. To be placed as closer as possible to VOUT pin
C6
10 nF ceramic capacitors
D1
STPS130A or similar Schottky diode
D2
1N4001-07, S1A-S1M, or any similar general purpose rectifier
D3
BAT54, BAT43, 1N5818, or any low power Schottky diode with I F(AV) > 0.2 A,
VRRM > 25 V, VF < 0.5 V. To be placed as closer as possible to VOUT pin
L1
With COMP = 0, use 10 µH inductor with ISAT > IPEAK where IPEAK is the boost
converter peak current
or
with COMP=1 and C2 = 22 µF, use 6.8 µH inductor with ISAT > IPEAK where IPEAK is
the boost converter peak current
L2
220 µH - 270 µH inductor as per DiSEqC 2.x specification
TR1
18/37
Notes
MMBTA92, 2STR2160 or any low power PNP with IC > 250 mA, VCE > 30 V, can
be used.
Also any small power PMOS with ID > 250 mA, RDS(on) < 0.5 W, VDS > 20 V, can be
used
DocID026736 Rev 3
LNBH25S
6
I²C bus interface
I²C bus interface
Data transmission from the main microprocessor to the LNBH25S and vice versa takes
place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up
resistors to positive supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 8: "Data validity on the I²C bus", the data on the SDA line must be
stable during the high semi-period of the clock. The high and low state of the data line can
only change when the clock signal on the SCL line is low.
6.2
Start and stop condition
As shown in Figure 9: "Timing diagram of I²C bus", a start condition is a transition from high
to low of the SDA line while SCL is high. The stop condition is a transition from low to high
of the SDA line while SCL is high. A stop condition must be sent before each start
condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by
an acknowledge bit. The MSB is the first to be transferred.
6.4
Acknowledge
The master (microprocessor) puts a resistive high level on the SDA line during the
acknowledge clock pulse, see Figure 10: "Acknowledge on the I²C bus". The peripheral
(LNBH25S), which acknowledges, must pull down (low) the SDA line during the
acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The
peripheral, which has been addressed, has to generate acknowledge after the reception of
each byte, otherwise the SDA line remains at high level during the ninth clock pulse time. In
this case, the master transmitter can generate the stop information in order to abort the
transfer. The LNBH25S doesn’t generate acknowledge if the VCC supply is below the
undervoltage lockout threshold (4.7 V typ.).
6.5
Transmission without acknowledge
If the detection of the LNBH25S acknowledges is not necessary, the microprocessor can
use a simpler transmission: it simply waits for one clock without checking the slave
acknowledging, and sends the new data. This approach is less protected from misworking
and decreases noise immunity.
DocID026736 Rev 3
19/37
I²C bus interface
LNBH25S
Figure 8: Data validity on the I²C bus
Figure 9: Timing diagram of I²C bus
Figure 10: Acknowledge on the I²C bus
20/37
DocID026736 Rev 3
LNBH25S
I²C interface protocol
7
I²C interface protocol
7.1
Write mode transmission
The LNBH25S interface protocol is made up of:
A start condition (S)
A chip address byte with the LSB bit R/W = 0
A register address (internal address of the first register to be accessed)
A sequence of data (byte to write to the addressed internal register + acknowledge)
The following bytes, if any, to be written to successive internal registers
A stop condition (P). The transfer lasts until a stop bit is encountered
The LNBH25S, as slave, acknowledges every byte transfer
Figure 11: Example of writing procedure starting with first data address 0X2
CHIP AD DRE SS
REGISTER AD DRE SS
DATA 3
Add=0x4
AC K
N/A
EN_IMON
N/A
N/A
OLR
LSB
LSB
T HERM
ACK
MSB
MSB
COM P
ISET
N/A
N/A
LSB
LSB
N/A
MSB
MSB
DATA 4
Add=0x5
N/A
X
LSB
LSB
N/A
N/A
MSB
MSB
ACK
VS E L1
VS E L2
VS E L3
N/A
VS E L4
X
DATA 2
Add=0x3
LSB
LSB
N/A
N/A
N/A
MSB
MSB
X
N/A
DATA 1
Add=0x2
0
PC L
0
ISW
0
N/A
0
T IM ER
0
ACK
X
AC K
0
TEN
0
LPM
1
EX T M
0
N/A
0
LSB
LSB
N/A
0
M SB
MSB
ACK
S
R/W = 0
LSB
LSB
M SB
MSB
P
GIPG1007141414LM
ACK = acknowledge
S = start
P = stop
R/W = 1/0, read/write bit
X = 0/1, set the values to select the chip address for pin selection and to select the register
address, see Table 7: "Data 1 (read/write register. Register address = 0X2)".
The writing procedure can start from any register address by simply setting X
values in the register address byte (after the chip address). It can be also stopped
by the master by sending a stop condition after any acknowledge bit.
7.2
Read mode transmission
In read mode the byte sequence as follows:
A start condition (S)
A chip address byte with the LSB bit R/W=0
The register address byte of the internal first register to be accessed
A stop condition (P)
A new master transmission with the chip address byte and the LSB bit R/W=1
DocID026736 Rev 3
21/37
I²C interface protocol
LNBH25S
After the acknowledge, the LNBH25S starts to send the addressed register content.
As long as the master keeps the acknowledge low, the LNBH25S transmits the next
address register byte content
The transmission is terminated when the master sets the acknowledge high with the
following stop bit
Figure 12: Example of reading procedure starting with first status address 0X0
REGISTER ADDRESS
LSB
LSB
MSB
MSB
ACK
N/A
N/A
N/A
N/A
TIMER
PCL
ISW
ISET
ACK
MSB
LSB
LSB
COMP
THERM
N/A
N/A
OLR
N/A
N/A
EN_IMON
MSB
LSB
LSB
N/A
N/A
N/A
N/A
N/A
EXTM
LPM
TEN
MSB
MSB
ACK
N/A
N/A
N/A
N/A
VSEL4
VSEL3
VSEL2
VSEL1
LSB
LSB
DATA 44
DATA
Add=0x5
Add=0x5
ACK
N/A
N/A
N/A
IMON
N/A
TMON
N/A
TDET
ACK
PNG
OTF
N/A
PDO
N/A
VMON
N/A
OLF
MSB
DATA 33
DATA
Add=0x4
Add=0x4
DATA 22
DATA
Add=0x3
Add=0x3
DATA 11
DATA
Add=0x2
Add=0x2
MSB
LSB
LSB
MSB
MSB
LSB
LSB
MSB
0 0 0 1 0 0 X
STATUS22
STATUS
Add=0x1
Add=0x1
STATUS11
STATUS
Add=0x0
Add=0x0
MSB
S
ACK
P
R/W = 1
0 0 0 0 0 X X X
LSB
MSB
ACK
0 0 0 1 0 0 X
CHIP ADDRESS
LSB
MSB
ACK
S
R/W = 0
LSB
ACK
CHIP ADDRESS
MSB
P
GIPG1107141218LM
ACK = acknowledge
S = start
P = stop
R/W = 1/0, read/write bit
X = 0/1, set the values to select the chip address, see Table 16: "Address pin
characteristics" for pin selection and to select the register address see Table 7: "Data 1
(read/write register. Register address = 0X2)".
The writing procedure can start from any register address (status 1,2 or data 1..4)
by simply setting X values in the register address byte (after the chip address). It
can be also stopped by the master by sending a stop condition after any
acknowledge bit.
22/37
DocID026736 Rev 3
LNBH25S
7.3
I²C interface protocol
Data registers
The data 1..4 registers can be addressed both to write and read mode. In read mode they
return the last writing byte status received in the previous write transmission.
The following tables provide the register address values of data 1..4 and a function
description of each bit.
Table 7: Data 1 (read/write register. Register address = 0X2)
Bit
Name
Value
Description
Bit 0
(LSB)
VSEL1
0/1
Bit 1
VSEL2
0/1
Bit 2
VSEL3
0/1
Bit 3
VSEL4
0/1
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit 7
(MSB)
N/A
0
Reserved. Keep to “0”
Output voltage selection bits
N/A = reserved bit
All bits reset to “0” at power-on
Table 8: Data 2 (read/write register. Register address = 0X3)
Bit
Name
Bit 0
(LSB)
TEN
Bit 1
Bit 2
Value
Description
1
22 kHz tone enabled. Tone output controlled by DSQIN pin
0
22 kHz tone output disabled
1
Low power mode active (used with 22 kHz tone output disabled
only)
0
Low power mode deactivated (keep always LPM = 0 during 22
kHz tone transmission)
1
DSQIN input pin is set to receive external 22 kHz TTL signal
source
0
DSQIN input pin is set to receive external DiSEqC envelope TTL
signal
LPM
EXTM
Bit 3
N/A
0
Reserved. Keep to “0”
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit
7(MSB)
N/A
0
Reserved. Keep to “0”
N/A = reserved bit
All bits reset to 0 at power-on
DocID026736 Rev 3
23/37
I²C interface protocol
LNBH25S
Table 9: Data 3 (read/write register. Register address = 0X4)
Bit
Bit 0
(LSB)
Name
Value
Description
1
Current limit of LNB output (VOUT pin) set to lower current range
(see Section 2.6: "Output current limit selection")
0
Current limit of LNB output (VOUT pin) set to default range
(see Section 2.6: "Output current limit selection")
1
DC-DC, inductor switching current limit set to 2.5 A typ.
0
DC-DC, inductor switching current limit set to 4 A typ.
1
Pulsed (dynamic) LNB output current limiting is deactivated
0
Pulsed (dynamic) LNB output current limiting is active
1
Pulsed (dynamic) LNB output current TON time set to 180 ms typ.
ISET
Bit 1
ISW
Bit 2
PCL
Bit 3
TIMER
0
Pulsed (dynamic) LNB output current TON time set to 90 ms typ.
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit 7
(MSB)
N/A
0
Reserved. Keep to “0”
N/A = reserved bit
All bits reset to 0 at power-on
24/37
DocID026736 Rev 3
LNBH25S
I²C interface protocol
Table 10: Data 4 (read/write register. Register address = 0X5)
Bit
Bit 0
(LSB)
Name
Value
Description
1
IMON diagnostic function is enabled.
(VOUT is set to 21 V typ.)
0
IMON diagnostic function is disabled, keep always at “0” if
IMON is not used
EN_IMON
Bit 1
N/A
-
Reserved
Bit 2
N/A
-
Reserved
1
In case of overload protection activation (OLF=1), all VSEL
1..4 bits are reset to “0” and LNB output (VOUT pin) is
disabled. VSEL bits have to be set again by the master
after the overcurrent condition is removed (OLF=0)
0
In case of overload protection activation (OLF=1) the LNB
output (VOUT pin) is automatically enabled as soon as the
overload condition is removed (OLF=0) with the previous
VSEL bits setting
Bit 3
OLR
Bit 4
N/A
-
Reserved
Bit 5
N/A
-
Reserved
1
If thermal protection is active (OTF=1), all VSEL 1..4 bits
are reset to “0” and LNB output (VOUT pin) is disabled.
VSEL bits have to be set again by the master after the
overtemperature condition is removed (OTF=0)
0
If thermal protection is active (OTF=1) the LNB output
(VOUT pin) is automatically enabled as soon as the
overtemperature condition is removed (OTF=0) with the
previous VSEL bits setting
1
DC-DC converter compensation: set to use very low ESR
capacitors or ceramic caps on VUP pin
0
DC-DC converter compensation: set to use standard
electrolytic capacitors on VUP pin
Bit 6
Bit
7(MSB)
THERM
COMP
N/A = reserved bit
All bits reset to 0 at power-on
DocID026736 Rev 3
25/37
I²C interface protocol
7.4
LNBH25S
Status registers
Status 1, 2 registers can be only addressed to read mode and provide the diagnostic
functions described in the following tables.
Table 11: Status 1 (read register. Register address = 0X0)
Bit
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Name
Description
1
VOUT pin overload protection has been triggered (I OUT > ILIM).
Refer to Table 9: "Data 3 (read/write register. Register address =
0X4)" for the overload operation settings (ISET, PCL, TIMER
bits)
0
No overload protection has been triggered to the VOUT pin (I OUT
< ILIM)
-
Reserved
1
Output voltage (VOUT pin) lower than VMON specification
thresholds. Refer to Table 17: "Output voltage diagnostic (VMON
bit, status 1 register) characteristics"
0
Output voltage (VOUT pin) is within the VMON specifications
-
Reserved
1
Overcurrent detected on output pull-down stage for a time longer
than the deglitch period. This may happen due to an external
voltage source present on the LNB output (VOUT pin)
0
No overcurrent detected on output pull-down stage
-
Reserved
1
Junction overtemperature is detected, TJ > 150 °C.
0
Junction overtemperature is not detected, TJ < 135 °C. TJ is
below thermal protection threshold
1
Input voltage (VCC pin) lower than LPD minimum thresholds.
Refer to Table 13: "Electrical characteristics"
0
Input voltage (VCC pin) higher than LPD thresholds. Refer to
Table 13: "Electrical characteristics"
OLF
N/A
VMON
N/A
PDO
Bit 5
N/A
Bit 6
OTF
Bit 7
(MSB)
Value
PNG
N/A = reserved bit
All bits reset to 0 at power-on
26/37
DocID026736 Rev 3
LNBH25S
I²C interface protocol
Table 12: Status 2 (read register. Register address = 0X1)
Bit
Name
Bit 0 (LSB)
TDET
Bit 1
N/A
Bit 2
Bit 3
Bit 4
Value
1
22 kHz tone presence is detected on the DETIN pin
0
No 22 kHz tone is detected on the DETIN pin
-
Reserved
1
22 kHz tone present on the DETIN pin is out of TMON
specification threshold: the tone frequency or the ATONE (tone
amplitude) is out of the thresholds guaranteed in the TMON
electrical characteristics
0
22 kHz tone present on the DETIN pin is within TMON
specification thresholds. Refer to Table 19: "22 kHz tone
diagnostic (TMON bit, status 2 register) characteristics"
-
Reserved
1
Output current (from VOUT pin) is lower than IMON
specification thresholds. Refer to Table 18: "Output current
diagnostic (IMON bit, status 2 register) characteristics"
0
Output current (from VOUT pin) is higher than IMON
specifications. Refer toTable 18: "Output current diagnostic
(IMON bit, status 2 register) characteristics"
TMON
N/A
Description
IMON
Bit 5
N/A
-
Reserved
Bit 6
N/A
-
Reserved
Bit 7
(MSB)
N/A
-
Reserved
N/A = reserved bit
All bits reset to 0 at power-on
DocID026736 Rev 3
27/37
Electrical characteristics
8
LNBH25S
Electrical characteristics
See Section 5: "Typical application circuits", TJ from 0 to 85 °C, all data 1..4 register bits set
to 0 unless VSEL1 = 1, RSEL = 11.5 kΩ, DSQIN = low, VIN = 12 V, IOUT = 50 mA, unless
otherwise stated. Typical values are referred to T J = 25 °C. VOUT = VOUT pin voltage.
Table 13: Electrical characteristics
Symbol
VIN
IIN
Test conditions
Supply voltage (1)
Supply current
Unit
8
12
16
V
mA
10
mA
VSEL1=VSEL2=VSEL3=
VSEL4=0
1
mA
VOUT
Line regulation
VIN = 8 to 16 V
VOUT
Load regulation
IOUT from 50 to 750 mA
ILIM
Max.
6
Valid at any VOUT selected level
Output current limiting
thresholds
Typ.
22 kHz tone enabled (TEN=1),
DSQIN = high, IOUT = 0 mA
Output voltage total
accuracy
Output current limiting
thresholds
Min.
IOUT = 0 mA
VOUT
ILIM
-3.5
+3.5
40
100
RSEL = 11.5 kΩ, ISET = 0
750
1100
RSEL = 16.2 kΩ, ISET = 0
500
750
RSEL = 22 kΩ, ISET = 0
350
550
%
mV
mA
RSEL = 11.5 kΩ, ISET = 1
500
RSEL = 16.2 kΩ, ISET = 1
350
RSEL = 22 kΩ, ISET = 1
250
500
mA
4
ms
ISC
Output short-circuit current
RSEL = 11.5 kΩ, ISET = 0
SS
Soft-start time
VOUT from 0 to 13 V
SS
mA
Soft-start time
VOUT from 0 to 18 V
6
ms
T13-18
Soft transition rise time
VOUT from 13 to 18 V
1.5
ms
T18-13
Soft transition fall time
VOUT from 18 to 13 V
1.5
ms
TOFF
Dynamic overload
protection off-time
PCL = 0, output shorted
900
TON
Dynamic overload
protection on-time
ATONE
Tone amplitude
FTONE
Tone frequency
DTONE
Tone duty cycle
tr, tf
Tone rise or fall time
PCL = TIMER = 0, output shorted
TOFF/10
PCL = 0, TIMER = 1, output
shorted
TOFF/5
DSQIN = high, EXTM=0, TEN=1
IOUT from 0 to 750 mA CBUS from
0 to 750 nF
DSQIN = high, EXTM=0, TEN=1
(2)
EffDC/DC
DC-DC converter efficiency
FSW
DC-DC converter switching
frequency
UVLO
28/37
Parameter
Undervoltage lockout
IOUT = 500 mA
UVLO threshold rising
DocID026736 Rev 3
ms
0.55
0.675
0.8
VPP
20
22
24
kHz
43
50
57
%
5
8
15
µs
93
%
440
kHz
4.8
V
LNBH25S
Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
thresholds
UVLO threshold falling
4.7
VLP
Low power diagnostic
(LPD) thresholds
VLP threshold rising
7.2
VLP threshold falling
6.7
VIL
DSQIN, pin logic low
VIH
DSQIN, pin logic high
IIH
DSQIN, pin input current
VIH = 5 V
FDETIN
Tone detector frequency
capture range (3)
0.4 VPP sine wave
19
VDETIN
Tone detector input
amplitude(3)
Sine wave signal, 22 kHz
0.3
ZDETIN
Tone detector input
impedance
VOL_BPS
W
Max.
Unit
V
0.8
2
V
V
15
22
µA
25
kHz
1.5
VPP
150
kΩ
V
BPSW pin low voltage
IOL_BPSW = 5 mA, DSQIN = high,
EXTM=0, TEN=1
0.7
VOL
DSQOUT, FLT pins logic
LOW
DETIN tone present, IOL= 2 mA
0.3
IOZ
DSQOUT, FLT pins
leakage current
DETIN tone absent, VOH = 6 V
IOBK
Output backward current
All VSELx=0, VOBK = 30 V
-3
ISINK
Output low-side sink
current
VOUT forced at VOUT_NOM + 0.1 V
70
mA
Low-side sink current timeout
VOUT forced at VOUT_NOM + 0.1 V
PDO I²C bit is set to 1 after this
time is elapsed
10
ms
Max. reverse current
VOUT forced at VOUT_NOM + 0.1 V
after PDO bit is set to 1
(ISINK_TIME-OUT elapsed)
2
mA
ISINK_
TIMEOUT
IREV
0.5
V
10
µA
-6
mA
TSHDN
Thermal shutdown
threshold
150
°C
DTSHDN
Thermal shutdown
hysteresis
15
°C
Notes:
(1)In
applications where (VCC -VOUT) > 1.3 V the increased power dissipation inside the integrated LDO must be taken into
account in the application thermal management design.
(2)Guaranteed
by design.
(3)Frequency
range in which the DETIN function is guaranteed. The V PP level is intended on the LNB bus (before the C6
capacitor. See typical application circuit for DiSEqC 2.x). IOUT from 0 to 750 mA, CBUS from 0 to 750 nF.
DocID026736 Rev 3
29/37
Electrical characteristics
LNBH25S
Table 14: Output voltage selection table (data1 register, write mode)
VSEL
4
VSEL
3
VSEL
2
VSEL
1
VOUT
min.
VOUT
voltage
VOUT
max.
0
0
0
0
0
0
0
1
12.545
13.000
13.455
0
0
1
0
12.867
13.333
13.800
0
0
1
1
13.188
13.667
14.145
0
1
0
0
13.51
14.000
14.490
0
1
0
1
13.832
14.333
14.835
0
1
1
0
14.153
14.667
15.180
0
1
1
1
14.475
15.000
15.525
1
0
0
0
17.515
18.150
18.785
1
0
0
1
17.836
18.483
19.130
1
0
1
0
18.158
18.817
19.475
1
0
1
1
18.48
19.150
19.820
1
1
0
0
18.801
19.483
20.165
1
1
0
1
19.123
19.817
20.510
1
1
1
0
19.445
20.150
20.855
1
1
1
1
19.766
20.483
21.200
Function
VOUT disabled. The LNBH25S
is set in standby mode
0.000
TJ from 0 to 85 °C, VI = 12 V
Table 15: I²C electrical characteristics
Symbol
Parameter
Test conditions
VIL
Low level input voltage
SDA, SCL
VIH
High level input voltage
SDA, SCL
IIN
Input current
SDA, SCL, VIN = 0.4 to 4.5 V
a
VOL
Low level output voltage
FMAX
Maximum clock frequency
30/37
Typ.
Max.
Unit
0.8
V
2
µA
SDA (open drain), IOL = 6 mA
0.6
V
SCL
400
kHz
Guaranteed by design.
DocID026736 Rev 3
-10
V
10
TJ from 0 to 85 °C, VI = 12 V
a
Min.
LNBH25S
Electrical characteristics
Table 16: Address pin characteristics
Symbol
Parameter
Test conditions
Min.
VADDR-1
“0001000(R/W)”
address pin voltage
range
R/W bit determines the
transmission mode: read
(R/W=1) write (R/W=0)
VADDR-2
“0001001(R/W)”
address pin voltage
range
R/W bit determines the
transmission mode: read
(R/W=1) write (R/W=0)
Typ.
Max.
Unit
0
0.8
V
2
5
V
Refer to Section 5: "Typical application circuits", TJ from 0 to 85 °C, all dat 1..4 register bits
set to “0”, RSEL = 11.5 kΩ, DSQIN = low, VIN = 12 V, IOUT = 50 mA, unless otherwise
stated. Typical values are referred to T J = 25 °C. VOUT = VOUT pin voltage. See Section 6:
"I²C bus interface" and Section 7: "I²C interface protocol".
Table 17: Output voltage diagnostic (VMON bit, status 1 register) characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VTH-L
Diagnostic low
threshold at
VOUT = 13.0 V
VSEL1 =1, VSEL2 =
VSEL3 = VSEL4 = 0
80
90
95
%
VTH-L
Diagnostic low
threshold at
VOUT = 18.15 V
VSEL4 =1, VSEL1 =
VSEL2 = VSEL3 = 0
80
90
95
%
If the output voltage is lower than the min. value, the VMON I²C bit is set to 1.
If VMON=0 then VOUT > 80% of VOUT typical
If VMON=1 then VOUT < 95% of VOUT typical
Refer to Section 5: "Typical application circuits", TJ from 0 to 85 °C, RSEL = 11.5 kΩ,
DSQIN = low, VIN = 12 V, unless otherwise stated. Typical values are referred to T J = 25
°C. VOUT = VOUT pin voltage. See Section 6: "I²C bus interface" and Section 7: "I²C
interface protocol".
Table 18: Output current diagnostic (IMON bit, status 2 register) characteristics
Symbol
Parameter
Test conditions
ITH
Minimum current
diagnostic threshold
EN_IMON = 1 (VOUT is set
to 21 V typ.)
Min.
Typ.
Max.
Unit
5
12
20
mA
If the output current is lower than the min. threshold limit, the IMON I²C bit is set to
1. If the output current is higher than the max. threshold limit, the IMON I²C bit is
set to 0.
Refer to Section 5: "Typical application circuits", TJ from 0 to 85 °C, all data 1..4 register
bits set to “0” unless VSEL1 = 1, TEN =1, RSEL = 11.5 kΩ, DSQIN = high, VIN = 12 V, IOUT
= 50 mA, unless otherwise stated. Typical values are referred to T J = 25 °C. VOUT = VOUT
pin voltage. See Section 6: "I²C bus interface" and Section 7: "I²C interface protocol".
DocID026736 Rev 3
31/37
Electrical characteristics
LNBH25S
Table 19: 22 kHz tone diagnostic (TMON bit, status 2 register) characteristics
Symbol
Parameter
ATH-L
Amplitude diagnostic low
threshold
ATH-H
Test conditions
Min.
Typ.
Max.
Unit
DETIN pin AC
coupled
200
300
400
mV
Amplitude diagnostic high
threshold
DETIN pin AC
coupled
900
1100
1200
mV
FTH-L
Frequency diagnostic low
thresholds
DETIN pin AC
coupled
13
16.5
20
kHz
FTH-H
Frequency diagnostic
high thresholds
DETIN pin AC
coupled
24
29.5
38
kHz
If the 22 kHz tone parameters are lower or higher than the above limits, the
TMON I²C bit is set to “1”.
32/37
DocID026736 Rev 3
LNBH25S
9
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
DocID026736 Rev 3
33/37
Package information
9.1
LNBH25S
QFN24L (4x4 mm) package information
Figure 13: QFN24L (4x4 mm) package outline
34/37
DocID026736 Rev 3
LNBH25S
Package information
Table 20: QFN24L (4x4 mm) mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
3.90
4.00
4.10
D2
2.55
2.70
2.80
E
3.90
4.00
4.10
E2
2.55
2.70
2.80
e
0.45
0.50
0.55
L
0.25
0.35
0.40
Figure 14: QFN24L (4x4 mm) recommended footprint
DocID026736 Rev 3
35/37
Revision history
10
LNBH25S
Revision history
Table 21: Document revision history
36/37
Date
Revision
Changes
23-Jul-2014
1
Initial release.
24-Mar-2015
2
Updated section 2.6, figure 5 and table 13.
26-Oct-2016
3
Updated Figure 6: "DiSEqC 1.x application circuit"
DocID026736 Rev 3
LNBH25S
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2016 STMicroelectronics – All rights reserved
DocID026736 Rev 3
37/37
工商网监
湘ICP备2023018690号
