LNBH26LPQR

LNBH26L Dual LNBS supply and control IC with step-up and I²C interface Features ■ Complete interface between LNB and I²C bus ■ Built-in DC-DC converter for single 12 V supply operation and high efficiency (typ. 93% @ 0.5 A) ■ Selectable output current limit by external resistor ■ Compliant with main satellite receiver output voltage specification (8 programmable levels) ■ Accurate built-in 22 kHz tone generator suits widely accepted standards ■ 22 kHz tone waveform integrity guaranteed also at no load condition ■ Low-drop post regulator and high efficiency step-up PWM with integrated power N-MOS allowing low power losses ■ Overload and overtemperature internal protection with I²C diagnostic bits ■ LNB short-circuit dynamic protection ■ +/- 4 kV ESD tolerant on output power pins Applications ■ STB satellite receivers ■ TV satellite receivers ■ PC card satellite receivers Table 1. March 2012 QFN24 (4x4 mm) Description Intended for analog and digital DUAL satellite receivers/Sat-TV, Sat-PC cards, the LNBH26L is a monolithic voltage regulator and interface IC, assembled in QFN24 (4x4) specifically designed to provide the 13 / 18 V power supply and the 22 kHz tone signalling to the LNB down-converter in the antenna dishes or to the multi-switch box. In this application field, it offers a complete solution for dual tuner satellite receivers with an extremely low component count and low power dissipation together with simple design and I²C standard interfacing. Device summary Order code Package Packaging LNBH26LPQR QFN24 (4x4) Tape and reel Doc ID 022876 Rev 1 1/28 www.st.com 28 Contents LNBH26L Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Application information (valid for each section A/B) . . . . . . . . . . . . . . . 4 2.1 DISEQC data encoding (DSQIN pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Data encoding by external 22 kHz tone TTL signal . . . . . . . . . . . . . . . . . . 4 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6 Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.7 Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.8 Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 7 2.9 PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.10 OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7 2.11 OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 2/28 6.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.2 START and STOP condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Doc ID 022876 Rev 1 LNBH26L Contents 7.4 8 Status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 022876 Rev 1 3/28 Block diagram 1 LNBH26L Block diagram Figure 1. Block diagram DSQIN-A ADDR SCL SDA DSQIN-B DAC Drop control Tone ctrl Diagnostics Protections Gate ctrl VUP-A Current Limit selection Linear Regulator PGND VUP-B Linear Regulator Gate ctrl PGND VOUT-A PWM CTRL PWM CTRL I²C Digital core Isense LX-B Isense LX-A VOUT-B Voltage reference ISEL GND 4/28 BYP VCC Doc ID 022876 Rev 1 AM10482v1 LNBH26L 2 Application information (valid for each section A/B) Application information (valid for each section A/B) This IC has a built-in DC-DC step-up converter that, from a single source (8 V to 16 V), generates the voltages (VUP) that let the integrated LDO post-regulator (generating the 13 V / 18 V LNB output voltages plus the 22 kHz DiSEqC tone) to work with a minimum dissipated power of 0.5 W typ. @ 500 mA load (the LDO drop voltage is internally kept at VUP - VOUT = 1 V typ.). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed threshold (4.7 V typically). The step-up converter soft-start function reduces the inrush current during startup. The SS time is internally fixed at 4 ms typ. to switch from 0 to 13 V and 6 ms typ. to switch from 0 to 18 V. 2.1 DISEQC data encoding (DSQIN pin) The internal 22 kHz tone generator is factory trimmed in accordance with the DiSEqC standards, and can be activated in 3 different ways: 1) by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=1. 2) by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. 3) through the TEN I²C bit if the 22 kHz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled high and the EXTM bit set to “0”. 2.2 Data encoding by external 22 kHz tone TTL signal In order to improve design flexibility, an external tone signal can be input to the DSQIN pin by setting the EXTM bit to “1”. The DSQIN is a logic input pin which activates the 22 kHz tone to the VOUT pin, by using the LNBH26L integrated tone generator. The output tone waveforms are internally controlled by the LNBH26L tone generator in terms of rise/fall time and tone amplitude, while, the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function. Before sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to “1”. As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code, the LNBH26L activates the 22 kHz tone on the VOUT output with about 1 µs delay from TTL signal activation, and it stops with about 60 µs delay after the 22 kHz TTL signal on DSQIN has expired. Refer to Figure 2. Figure 2. Tone enable and disable timing (using external waveform) DSQIN ~ 1 µs ~ 60 µs Tone Output AM10426v1 Doc ID 022876 Rev 1 5/28 Application information (valid for each section A/B) 2.3 LNBH26L Data encoding by external DiSEqC envelope control through the DSQIN pin If an external DiSEqC envelope source is available, it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM=0 and TEN=1. In this way, the internal 22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz tone. During the period in which the DSQIN is kept high the internal control circuit activates the 22 kHz tone output. The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL signal rising edge, and it stops with a delay time in the range from 15 µs to 60 µs after the 22 kHz TTL signal on DSQIN has expired (refer to Figure 3). Figure 3. Tone enable and disable timing (using envelope signal) DSQIN 15 µs ~ 60 µs ~ 6 µs Tone Output AM10427v1 2.4 Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation: Equation 1 IMAX (typ.) = 16578 RSEL1.206 with ISET=0, where RSEL is the resistor connected between ISEL and GND expressed in kΩ and IMAX (typ.) is the typical current limit threshold expressed in mA. IMAX can be set up to 750 mA for each channel. However, it is recommended to not exceed for a long period a total amount of current of 1 A from both sections (IOUT_A + IOUT_B < 1 A) in order to avoid the overtemperature protection from triggering and to thoroughly validate the PCB layout thermal management in real application environment conditions. 2.5 Output voltage selection Each linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using 4 + 4 bits of an internal DATA1 register (see Section 7.3: Data registers and Table 13: Output voltage selection table (Data1 register, write mode) for exact programmable values). Register writing is accessible via the I²C bus. 6/28 Doc ID 022876 Rev 1 LNBH26L 2.6 Application information (valid for each section A/B) Diagnostic and protection functions The LNBH26L has 4 diagnostic internal functions provided via the I²C bus, by reading 4 bits on the STATUS1 register (in read mode). All the diagnostic bits are, in normal operation (that is, no failure detected), set to LOW. One diagnostic bit is dedicated to the overtemperature (OTF), and two bits (one per section) are dedicated to overcurrent (OLF-A, OLF-B). One bit is dedicated to the input voltage power not good function (PNG). Once the OTF bit (or OLFA, OLF-B or PNG) has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a new register reading operation is done. 2.7 Surge protection and TVS diodes Each LNBH26L device section is directly connected to the antenna cable in a set-top box. Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually placed, as shown in the following schematic, to protect each section of STB output circuits where the LNBH26L and other devices are electrically connected to the antenna cable. Figure 4. Surge protection circuit For this purpose the use of LNBTVSxx surge protection diodes specifically designed by ST is recommended. The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS datasheet for further details). 2.8 Power-on I²C interface reset and undervoltage lockout The I²C interface built into the LNBH26L is automatically reset at power-on. As long as the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DATA register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DATA registers can be configured by the main microprocessor. Doc ID 022876 Rev 1 7/28 Application information (valid for each section A/B) 2.9 LNBH26L PNG: input voltage minimum detection When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to “1”. Refer to the electrical characteristics table for threshold details. 2.10 OLF: overcurrent and short-circuit protection and diagnostic In order to reduce the total power dissipation during an overload or a short-circuit condition, each section of the device is provided with a dynamic short-circuit protection. It is possible to set the short-circuit current protection either statically (simple current clamp) or dynamically through the corresponding PCL bit of the I²C DATA3 register. When the PCL (pulsed current limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for TON time 90 ms and after that, the output is set in shutdown for a TOFF time of typically 900 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the STATUS1 register is set to “1”. After this time has elapsed, the involved output is resumed for a time TON. At the end of TON, if the overload is still detected, the protection circuit cycles again through TOFF and TON. At the end of a full TON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to low after register reading is done. Typical TON + TOFF time is 990 ms and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in short-circuit condition, while still ensuring excellent power-on startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=1) and, then, switching to the dynamic mode (PCL=0) after a chosen amount of time depending on the output capacitance. Also in static mode, the diagnostic OLF bit goes to “1” (and the FLT pin is set to low) when the current clamp limit is reached and returns low when the overload condition is cleared and register reading is done. After the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DATA4 register. If OLR=1, all VSEL bits corresponding to the involved section are reset to “0” and the LNB section output (VOUT pin) is disabled. To re-enable the output stage, the VSEL bits must be set again by the microprocessor and the OLF bit is reset to “0” after a register reading operation. If OLR=0, the involved output is automatically re-enabled as soon as the overload condition is removed, and OLF bit is reset to “0” after a register reading operation. 2.11 OTF: thermal protection and diagnostic The LNBH26L is also protected against overheating: when the junction temperature exceeds 150 °C (typ.), the step-up converter and both linear regulators are shut off, the diagnostic OTF bit in the STATUS1 register is set to “1”. After the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DATA4 register. If THERM=1, all VSEL bits are reset to “0” and both LNB outputs (VOUT pins) are disabled. To re-enable the output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to “0” after a register reading operation. If THERM=0, outputs are automatically re-enabled as soon as the overtemperature condition is removed, while the OTF bit is reset to “0” after a register reading operation. 8/28 Doc ID 022876 Rev 1 LNBH26L 3 Pin configuration Pin configuration Figure 5. Table 2. Pin connections (top view) 24 23 22 21 20 19 DSQIN-B GND DSQIN-A VUP-A VOUT-A GND 1 GND GND 18 2 GND VCC 17 3 LX- A BYP 16 4 PGND GND 15 5 LX- B NC 14 6 ADDR GND 13 SCL SDA ISEL VUP-B VOUT-B GND 7 8 9 10 11 12 AM10483v1 Pin description Pin n° Symbol Name 3 LX-A N-Mos drain 4 P-GND Power ground 5 LX-B N-Mos drain 6 ADDR Address setting 7 SCL Serial clock Clock from I²C bus. 8 SDA Serial data Bi-directional data from/to I²C bus. 9 ISEL 1, 2, 12, 13, 15, 18, 19, 23 GND Pin function Channel A, integrated N-channel Power MOSFET drain. DC-DC converter power ground. To be connected directly to the Epad. Channel B, integrated N-channel Power MOSFET drain. Two I²C bus addresses available by setting the Address pin level voltage. See the Address pin characteristics table. The resistor “RSEL” connected between ISEL and GND defines Current selection for the linear regulator current limit threshold. Refer to “output both channel A and current limit selection” Section 2. The RSEL resistor defines the B same current limit both for channels A and B. Analog ground Analog circuits ground. To be connected directly to the Epad. Doc ID 022876 Rev 1 9/28 Pin configuration Table 2. LNBH26L Pin description (continued) Pin n° Symbol Name Pin function 10 VUP-B Channel B step-up voltage Input of channel B linear post-regulator. The voltage on this pin is monitored by the internal channel B step-up controller to keep a minimum dropout across the linear pass transistor. 11 VOUT-B Channel B, LNB output port Output of channel B integrated very low-drop linear regulator. Refer toTable 13 for voltage selection and description. 14 N.C. Not internally connected Not internally connected pin. Set floating if not used. Needed for internal pre-regulator filtering. The BYP pin is intended only to connect an external ceramic capacitor. Any connection of this pin to an external current or voltage sources may cause permanent damage to the device. 16 BYP Bypass capacitor 17 VCC Supply input 20 VOUT-A Channel A, LNB output port Output of channel A integrated very low-drop linear regulator. Refer to Table 13 for voltage selection and description. 21 VUP-A Channel A step-up voltage Input of channel A linear post-regulator. The voltage on this pin is monitored by the internal channel A step-up controller to keep a minimum dropout across the linear pass transistor. 8 to 16 V IC DC-DC power supply. DSQIN-A It is intended for channel A 22 kHz tone control. It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-A I²C bit setting as follows: DSQIN for DiSEqC If EXTM-A=0, TEN-A=1: it accepts the DiSEqC envelope code envelope input from the main microcontroller. The LNBH26L uses this code to or modulate the internally generated 22 kHz carrier. external 22 KHz TTL If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals input which activate the 22 kHz tone output (refer to Section 2.2). Pull up high if the tone output is activated only by the TEN-A I²C bit. 24 DSQIN-B It is intended for channel B 22 kHz tone control. It can be used as DiSEqC envelope input or external 22 kHz TTL input depending on the EXTM-B I²C bit setting as follows: DSQIN for DiSEqC If EXTM-B=0, TEN-B=1: it accepts the DiSEqC envelope code envelope Input from the main microcontroller. The LNBH26L uses this code to or modulate the internally generated 22 kHz carrier. external 22 KHz TTL If EXTM-A=TEN-A=1: it accepts external 22 kHz logic signals input which activate the 22 kHz tone output (refer to Section 2.2). Pull up high if the tone output is activated only by TEN-B I²C bit. Epad Epad 22 10/28 Exposed pad To be connected with power grounds and to the ground layer through vias to dissipate the heat. Doc ID 022876 Rev 1 LNBH26L Maximum ratings 4 Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit VCC DC power supply input voltage pins -0.3 to 20 V VUP DC input voltage -0.3 to 40 V IOUT Output current Internally limited mA VOUT DC output pin voltage -0.3 to 40 V VI Logic input pin voltage (SDA, SCL, DSQIN, ADDR pins) -0.3 to 7 V LX LX input voltage -0.3 to 30 V VBYP Internal reference pin voltage -0.3 to 4.6 V ISEL Current selection pin voltage -0.3 to 3.5 V TSTG Storage temperature range -50 to 150 °C Operating junction temperature range -25 to 125 °C TJ ESD Table 4. Symbol ESD rating with human body model (HBM) all pins, unless power output pins 2 ESD rating with human body model (HBM) for power output pins 4 kV Thermal data Parameter Value Unit RthJC Thermal resistance junction-case 2 °C/W RthJA Thermal resistance junction-ambient with device soldered on 2s2p 4layer PCB provided with thermal vias below the exposed pad. 40 °C/W Note: Absolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal. Doc ID 022876 Rev 1 11/28 Typical application circuits 5 LNBH26L Typical application circuits Figure 6. DiSEqC 1.x application circuit D2-A LNBOUT-A 21 D1-A C2-A C7 Vin 12V 3 LX-A 9 ISEL 16 Byp 17 Vcc C5-A DSQIN-A 22 DSQIN-B 24 ADDR 6 C4 C1 L1-B I2C Bus { 20 LNBH26L C3-A R1 (RSEL) L1-A VOUT-A VUP-A 8 SDA 7 SCL 5 LX-B 10 VUP-B D3-A Tone enable control DiSEqC 22KHz TTL or DiSEqC Envelope TTL D1-B C2-B VOUT-B P-GND A-GND 4 15 C3-B 11 LNBOUT-B C5-B D3-B AM10484v1 D2-B Table 5. DiSEqC 1.x bill of material (valid for A and B channels except for C1, C4, C7 and R1) Component R1 (RSEL) C1, C2 SMD resistor. Refer to Table 12 and the ISEL pin description in Table 2. > 25 V electrolytic capacitor, 100 µF is suitable. C3 From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise. C5 From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise. C4, C7 12/28 Notes 220 nF ceramic capacitors. D1 STPS130A or similar Schottky diode. D3 BAT54, BAT43, 1N5818, or any low power schottky diode with IF(AV) > 0.2 A, VRRM > 25 V, VF < 0.5 V. To be placed as close as possible to the VOUT pin. D2 1N4001-07, S1A-S1M, or any similar general purpose rectifier. L1 10 µH inductor with Isat > Ipeak where Ipeak is the boost converter peak current. Doc ID 022876 Rev 1 LNBH26L 6 I²C bus interface I²C bus interface Data transmission from the main microprocessor to the LNBH26L, and vice versa, takes place through the 2-wire I²C bus interface, consisting of the 2-line SDA and SCL (pull-up resistors to positive supply voltage must be externally connected). 6.1 Data validity As shown in Figure 7, the data on the SDA line must be stable during the high semi-period of the clock. The high and low state of the data line can only change when the clock signal on the SCL line is LOW. 6.2 START and STOP condition As shown in Figure 8, a START condition is a high to low transition of the SDA line while SCL is HIGH. The STOP condition is a low to high transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition. 6.3 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSb is transferred first. 6.4 Acknowledge The master (microprocessor) puts a resistive high level on the SDA line during the acknowledge clock pulse (see Figure 9). The peripheral (LNBH26L) which acknowledges must pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during this clock pulse. The peripheral which has been addressed must generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the high level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNBH26L won't generate acknowledge if the VCC supply is below the undervoltage lockout threshold (4.7 V typ.). 6.5 Transmission without acknowledge If the detection of LNBH26L acknowledge is not necessary, the microprocessor can use a simpler transmission; it simply waits one clock without checking the slave acknowledging, and sends the new data. This approach is of course less protected from misworking and decreases noise immunity. Doc ID 022876 Rev 1 13/28 I²C bus interface 14/28 LNBH26L Figure 7. Data validity on the I²C bus Figure 8. Timing diagram of I²C bus Figure 9. Acknowledge on the I²C bus Doc ID 022876 Rev 1 LNBH26L I²C interface protocol 7 I²C interface protocol 7.1 Write mode transmission The LNBH26L interface protocol is made up of: ● a START condition (S) ● a chip address byte with the LSb bit R/W = 0 ● a register address (internal address of the first register to be accessed) ● a sequence of data (byte to write in the addressed internal register + acknowledge) ● the following bytes, if any, to be written in successive internal registers ● a STOP condition (P), the transfer lasts until a stop bit is encountered ● the LNBH26L, as slave, acknowledges every byte transfer. Figure 10. Example of writing procedure starting with first data address 0x2(a) CHIP ADDRESS LSB MSB 0 X 0 0 0 0 0 X X X DATA 3 Add=0x4 DATA 2 Add=0x3 DATA 1 Add=0x2 MSB ACK 0 0 1 0 LSB MSB ACK 0 R/W = 0 S REGISTER ADDRESS MSB LSB DATA 4 Add=0x5 MSB LSB LSB MSB LSB N/A ACK N/A N/A N/A OLR N/A N/A THERM N/A ACK N/A N/A PCL-A N/A N/A N/A PCL-B ACK N/A TEN-A N/A EXTM-A N/A TEN-B N/A EXTM-B ACK VSEL1-A VSEL2-A VSEL3-A VSEL4-A VSEL1-B VSEL2-B VSEL3-B VSEL4-B P AM10485v1 ACK = Acknowledge S = Start P = Stop R/W = 1/0, read/write bit X = 0/1, set the values to select the chip address (see Table 15 for pin selection) and to select the register address (see Table 6 to Table 11). a. The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped from the master by sending a STOP condition after any acknowledge bit. Doc ID 022876 Rev 1 15/28 I²C interface protocol 7.2 LNBH26L Read mode transmission In read mode the bytes sequence must be as follows: ● a START condition (S) ● a chip address byte with the LSb bit R/W=0 ● the register address byte of the internal first register to be accessed ● a STOP condition (P) ● a new master transmission with the chip address byte and the LSb bit R/W=1 ● after the acknowledge, the LNBH26L starts to send the addressed register content. As long as the master keeps the acknowledge LOW, the LNBH26L transmits the next address register byte content. ● the transmission is terminated when the master sets the acknowledge high with a following stop bit. Figure 11. Example of reading procedure starting with first status address 0X0 (b) REGISTER ADDRESS CHIP ADDRESS LSB MSB P MSB 0 X LSB ACK N/A N/A MSB N/A N/A N/A N/A N/A N/A ACK N/A OLF-A OLF-B N/A N/A N/A OTF PNG DATA 3 Add=0x4 DATA 2 Add=0x3 LSB 0 0 1 0 MSB LSB DATA 1 Add=0x2 0 STATUS 2 Add=0x1 STATUS 1 Add=0x0 MSB S ACK 0 0 0 0 0 X X X R/W = 1 0 X LSB MSB ACK 0 0 1 0 MSB ACK 0 R/W = 0 S CHIP ADDRESS LSB DATA 4 Add=0x5 MSB LSB LSB MSB LSB N/A ACK N/A N/A N/A OLR N/A N/A THERM N/A ACK N/A N/A PCL-A N/A N/A N/A PCL-B ACK N/A TEN-A N/A EXTM-A N/A TEN-B N/A EXTM-B ACK VSEL1-A VSEL2-A VSEL3-A VSEL4-A VSEL1-B VSEL2-B VSEL3-B VSEL4-B P AM10486v1 ACK = Acknowledge S = Start P = Stop R/W = 1/0, read/write bit X = 0/1, set the values to select the chip address (see Table 15 for pin selection) and to select the register address (see Table 6 to Table 11). b. The reading procedure can start from any register address (Status 1, 2 or Data1..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped from the master by sending a STOP condition after any acknowledge bit. 16/28 Doc ID 022876 Rev 1 LNBH26L 7.3 I²C interface protocol Data registers The DATA 1..4 registers can be addressed both in write and read mode. In read mode they return the last writing byte status received in the previous write transmission. The following tables provide the register address values of Data 1..4 and a function description of each bit. Table 6. DATA 1 (read/write register. Register address = 0X2) Bit Name Bit 0 (LSb) VSEL1-A Bit 1 VSEL2-A Bit 2 VSEL3-A 0/1 Bit 3 VSEL4-A 0/1 Bit 4 VSEL1-B 0/1 Bit 5 VSEL2-B Bit 6 VSEL3-B Bit 7 (MSb) VSEL4-B CH Value Description 0/1 Channel A output voltage selection bits. (Refer to Table 13) 0/1 A 0/1 B Channel B output voltage selection bits. (Refer to Table 13) 0/1 0/1 N/A = Reserved bit. All bits reset to “0” at power-on. Table 7. DATA 2 (read/write register. Register address = 0X3) Bit Name Bit 0 (LSb) TEN-A Bit 1 N/A CH Value Description 1 22 kHz tone enabled. Tone output controlled by the DSQIN pin 0 22 kHz tone output disabled 0 Reserved. Keep to “0”. 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal 0 Reserved. Keep to “0”. 1 22 kHz tone enabled. Tone output controlled by the DSQIN pin 0 22 kHz tone output disabled 0 Reserved. Keep to “0”. 1 DSQIN input pin is set to receive external 22 kHz TTL signal source 0 DSQIN input pin is set to receive external DiSEqC envelope TTL signal 0 Reserved. Keep to “0”. A Bit 2 EXTM-A Bit 3 N/A Bit 4 TEN-B Bit 5 N/A B Bit 6 Bit 7 (MSb) EXTM-B N/A N/A = Reserved bit. All bits reset to “0” at power-on. Doc ID 022876 Rev 1 17/28 I²C interface protocol Table 8. DATA 3 (read/write register. Register address = 0X4) Bit Name Bit 0 (LSb) N/A Bit 1 N/A Bit 2 LNBH26L CH Value A PCL-A Description 0 Reserved. Keep to “0” 0 Reserved. Keep to “0” 1 Pulsed (Dynamic) LNB output current limiting is deactivated 0 Pulsed (Dynamic) LNB output current limiting is activated Bit 3 N/A 0 Reserved. Keep to “0” Bit 4 N/A 0 Reserved. Keep to “0” Bit 5 N/A 0 Reserved. Keep to “0” Bit 6 PCL-B 1 Pulsed (Dynamic) LNB output current limiting is deactivated 0 Pulsed (Dynamic) LNB output current limiting is activated 0 Reserved. Keep to “0” Bit 7 (MSb) B N/A N/A = Reserved bit. All bits reset to “0” at power-on. Table 9. DATA 4 (read/write register. Register address = 0X5) Bit Name CH Value Bit 0 (LSb) N/A - 0 Reserved. Keep to “0”. Bit 1 N/A - 0 Reserved. Keep to “0”. Bit 2 N/A - 0 Reserved. Keep to “0”. 1 In the case of overload protection activation (OLF=1), all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=0). 0 In the case of overload protection activation (OLF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overload condition is removed (OLF=0) with the previous VSEL bits setting. Bit 3 OLR A/B Description Bit 4 N/A - 0 Reserved. Keep to “0”. Bit 5 N/A - 0 Reserved. Keep to “0”. 1 If thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=0). 0 In the case of thermal protection activation (OTF=1) the LNB output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=0) with the previous VSEL bits setting. 0 Reserved. Keep to “0” Bit 6 Bit 7 (MSb) 18/28 THERM COMP A/B - Doc ID 022876 Rev 1 LNBH26L 7.4 I²C interface protocol Status registers The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic functions described in the following tables. Table 10. Bit Bit 0 (LSb) Bit 1 STATUS 1 (read register. Register address = 0X0) Name OLF-A OLF-B CH Value Description 1 VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 8 for the overload operation and PCL settings. 0 No overload protection has been triggered to the VOUT pin (IOUT < IMAX). 1 VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 8 for the overload operation and PCL settings. 0 No overload protection has been triggered to VOUT pin (IOUT < IMAX). A B Bit 2 N/A - - Reserved Bit 3 N/A - - Reserved Bit 4 N/A - - Reserved Bit 5 N/A - - Reserved 1 Junction overtemperature is detected, TJ > 150 °C (typ.). See also THERM bit setting in Table 9. 0 Junction overtemperature not detected, TJ 1.3 V, the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design. 2. Guaranteed by design. 8.1 Output voltage selection Each LNBH26L channel is provided with 8 output voltage levels (4 levels for 13 V range when VSEL4-A/B=0 and 4 levels for 18 V range when VSEL4-A/B=1) which can be selected through the register Data1. The following table shows the output voltage values corresponding to VSELx bit combinations both for channel A and B. If all VSELx are at “0” the device is set in standby mode and the VOUT-A/B are disabled. Doc ID 022876 Rev 1 21/28 Electrical characteristics Table 13. LNBH26L Output voltage selection table (Data1 register, write mode) (1) VOUT min. VOUT -A/B pin voltage VSEL4A/B VSEL3A/B VSEL2A/B VSEL1A/B 0 0 0 0 0 0 0 1 12.545 13.000 13.455 0 0 1 0 12.867 13.333 13.800 0 0 1 1 13.188 13.667 14.145 0 1 0 0 13.51 14.000 14.490 1 0 0 0 17.515 18.150 18.785 1 0 0 1 17.836 18.483 19.130 1 0 1 0 18.158 18.817 19.475 1 0 1 1 18.48 19.150 19.820 VOUT max. Function VOUT -A/B disabled. LNBH26L set in standby mode 0 1. TJ from 0 to 85 °C, VI = 12 V. TJ from 0 to 85 °C, VI = 12 V. Table 14. Symbol I²C electrical characteristics Parameter Test conditions VIL Low level input voltage SDA, SCL VIH High level input voltage SDA, SCL IIN Input current VOL FMAX Low level output voltage Maximum clock frequency Typ. Max. Unit 0.8 V 2 SDA, SCL, VIN = 0.4 to 4.5 V (1) Min. V -10 SDA (open drain), IOL = 6 mA SCL 10 µA 0.6 V 400 kHz 1. Guaranteed by design. TJ from 0 to 85 °C, VI = 12 V. Table 15. Symbol Address pin characteristics Parameter Test condition Min. Typ. Max. Unit VADDR-1 “0001000(R/W)” Address pin R/W bit determines the transmission voltage range mode: read (R/W=1) write (R/W=0) 0 0.8 V VADDR-2 “0001001(R/W)” Address pin R/W bit determines the transmission voltage range mode: read (R/W=1) write (R/W=0) 2 5 V 22/28 Doc ID 022876 Rev 1 LNBH26L 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 16. QFN24L (4x4 mm) mechanical data (mm) Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D 3.90 4.00 4.10 D2 2.55 2.70 2.80 E 3.90 4.00 4.10 E2 2.55 2.70 2.80 e 0.45 0.50 0.55 L 0.25 0.35 0.45 Doc ID 022876 Rev 1 23/28 Package mechanical data LNBH26L Figure 12. QFN24L (4x4 mm) package dimensions 7596209_D 24/28 Doc ID 022876 Rev 1 LNBH26L Package mechanical data Tape & reel QFNxx/DFNxx (4x4) mechanical data mm. inch. Dim. Min. Typ. A Max. Min. Typ. 330 C 12.8 D 20.2 N 99 13.2 Max. 12.992 0.504 0.519 0.795 101 T 3.898 3.976 14.4 0.567 Ao 4.35 0.171 Bo 4.35 0.171 Ko 1.1 0.043 Po 4 0.157 P 8 0.315 Doc ID 022876 Rev 1 25/28 Package mechanical data LNBH26L Figure 13. QFN24L (4x4) footprint recommended data (mm) 26/28 Doc ID 022876 Rev 1 LNBH26L Revision history 10 Revision history Table 17. Document revision history Date Revision 01-Mar-2012 1 Changes Initial release. Doc ID 022876 Rev 1 27/28 LNBH26L Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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