LNBH29
LNB supply and control IC with step-up and I²C interface
Datasheet - production data
Low-drop post regulator and high efficiency
step-up PWM with integrated power N-MOS
allowing low power losses
Overload and overtemperature internal
protection with I²C diagnostic bits
LNB short-circuit dynamic protection
+/- 4 kV ESD tolerant on output power pins
Applications
QFN16 (4x4) / (3x3)
STB satellite receivers
TV satellite receivers
PC card satellite receivers
Features
Complete interface between LNB and I²C bus
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (typ. 93% @
0.5 A)
Selectable output current limit by external
resistor
Compliant with main satellite receiver output
voltage specifications
Accurate built-in 22 kHz tone generator suits
widely accepted standards
EXTM pin, auxiliary 22 kHz modulation input
(LNBH29E) extends design flexibility
Description
Intended for analog and digital satellite
receivers/Sat-TV and Sat-PC cards, the LNBH29
series is a monolithic voltage regulator and
interface IC, assembled in QFN16 (3x3) and
QFN16 (4x4) specifically designed to provide the
13 / 18 V power supply and the 22 kHz tone
signaling to the LNB down-converter in the
antenna dish or to the multi-switch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with a simple design and I²C
standard interfacing.
22 kHz tone waveform integrity guaranteed
also at no load condition
Table 1. Device summary
Order codes
Packages
Packaging
LNBH29PTR
QFN16 (3x3)
Tape and reel
LNBH29EPTR
QFN16 (3x3)
Tape and reel
LNBH29QTR
QFN16 (4x4)
Tape and reel
LNBH29EQTR
QFN16 (4x4)
Tape and reel
March 2013
This is information on a product in full production.
DocID023065 Rev 3
1/31
www.st.com
31
Contents
LNBH29
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
DiSEqC™ data encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
LNBH29: data encoding by external DiSEqC envelope control
through the DSQIN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
LNBH29E: DISEQC data encoding by external 22 kHz signal
connected to the EXTM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.6
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7
Surge protection and TVS diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.8
VMON: output voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.9
PDO: overcurrent detection on output pull-down stage . . . . . . . . . . . . . . . 6
2.10
Power-on I²C interface reset and undervoltage lockout . . . . . . . . . . . . . . . 6
2.11
PNG: input voltage minimum detection . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.12
COMP: boost capacitors and inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.13
OLF: overcurrent and short-circuit protection and diagnostic . . . . . . . . . . . 7
2.14
OTF: thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/31
6.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.2
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DocID023065 Rev 3
LNBH29
7
Contents
I²C interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
Write mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2
Read mode transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3
DATA register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4
STATUS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID023065 Rev 3
3/31
Block diagram
1
LNBH29
Block diagram
Figure 1. Block diagram
ADDR SCL SDA
PWM CTRL
I²C Digital core
DSQIN (1)
Isense
LX
DAC
Drop control
Tone ctrl
Diagnostics
Protections
PGND
VUP
Gate ctrl
Current
Limit
selection
ISEL
Voltage
reference
R3
GND
BYP VCC
1. DSQIN pin available only on the LNBH29.
2. EXTM pin available only on the LNBH29E.
4/31
DocID023065 Rev 3
VOUT
R1
Linear
Regulator
R2
EXTM (2)
AM11889v1
LNBH29
2
Application information
Application information
This IC has a built-in DC-DC step-up converter that, from a single source from 9 V to 17.5 V,
generates the voltages (VUP) that allow the linear post-regulator to work with a minimum
dissipated power of 0.5 W typ. @ 500 mA load (the linear post-regulator drop voltage is
internally kept at VUP - VOUT = 1 V typ.). The IC is also provided with an undervoltage
lockout circuit that disables the whole circuit when the supplied VCC drops below a fixed
threshold (4.7 V typically). The step-up converter is provided with a soft-start function which
reduces the inrush current during startup. The SS time is internally fixed at 4 ms typ. to
switch from 0 to 13 V and 6 ms typ. to switch from 0 to 18 V.
2.1
DiSEqC™ data encoding
The LNBH29 series includes two versions with different DiSEqC control pin solutions:
LNBH29 with DSQIN pin and LNBH29E with EXTM pin.
The LNBH29 is provided with the DSQIN logic input pin (TTL compatible) to be controlled by
an external DiSEqC data envelope source which activates the internal 22 kHz tone
generator factory trimmed. This guarantees the tone output waveform in accordance with
the DiSEqC standards.
The LNBH29E is provided with the EXTM analogic modulation input pin to be connected to
an external 22 kHz DiSEqC tone source. The tone output waveform depends on the
characteristics of an external signal injected by means of the EXTM pin.
2.2
LNBH29: data encoding by external DiSEqC envelope control
through the DSQIN pin
If an external DiSEqC code envelope source is available, it is possible to use the internal 22
kHz generator activated during the tone transmission by connecting the DiSEqC envelope
source to the DSQIN pin (see Section 5: Typical application circuits). In this way, the internal
22 kHz signal is superimposed to the VOUT DC voltage to generate the LNB output 22 kHz
tone. During the period in which the DSQIN is kept HIGH, the internal control circuit
activates the 22 kHz tone output.
The 22 kHz tone on the VOUT pin is activated with about 6 µs delay from the DSQIN TTL
signal rising edge, and it stops with a delay time in the range of 15 µs to 60 µs after the 22
kHz TTL signal on DSQIN has expired (refer to Figure 2).
Figure 2. Tone enable and disable timing (using envelope signal)
DSQIN
15 µs ~ 60 µs
~ 6 µs
Tone
Output
AM10427v1
DocID023065 Rev 3
5/31
Application information
2.3
LNBH29
LNBH29E: DISEQC data encoding by external 22 kHz signal
connected to the EXTM pin
In order to improve design flexibility, an analogic modulation input pin is available (EXTM) to
generate the 22 kHz tone superimposed to the VOUT DC output voltage. An appropriate DC
blocking capacitor must be used to couple the 22 kHz modulating signal source to the
EXTM pin. The EXTM pin modulates the VOUT voltage through the series decoupling
capacitor, so that:
VOUT(AC) = VEXTM(AC) x GEXTM
where VOUT(AC) and VEXTM(AC) are, respectively, the peak-to-peak AC voltage on the
VOUT pin and on the EXTM pin, while GEXTM is the voltage gain between the EXTM
voltage and VOUT signal.
2.4
Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
the ISEL pin. The resistor value defines the output current limit by the equation:
Equation 1
IMAX ( typ.)
13915
RSEL1.111
where RSEL is the resistor connected between ISEL and GND expressed in k and
IMAX(typ.) is the typical current limit threshold expressed in mA. IMAX can be set up to 550
mA.
2.5
Output voltage selection
The linear regulator output voltage level can be easily programmed in order to accomplish
application specific requirements, using 3 bits of the internal DATA register (see Section 7.1:
Write mode transmission and Table 7 for exact programmable values). Register writing is
accessible via the I²C bus.
2.6
Diagnostic and protection functions
The LNBH29 series has 5 diagnostic internal functions provided via the I²C bus, by reading
5 bits on the STATUS register (in Read mode). All the diagnostic bits are, in normal
operation, set to LOW. Two diagnostic bits are dedicated to the overtemperature and
overload protection status (OTF and OLF) while the remaining 3 bits are dedicated to the
output voltage level (VMON), to external voltage source presence on the VOUT pin (PDO)
and to the input voltage power not good function (PNG). Once the OLF (or OTF or PNG) bit
has been activated (set to “1”), it is latched to “1” until the relevant cause is removed and a
new register reading operation is done (see Table 8).
6/31
DocID023065 Rev 3
LNBH29
2.7
Application information
Surge protection and TVS diodes
The LNBH29 series is directly connected to the antenna cable in a set-top box. Atmospheric
phenomenon can cause high voltage discharges on the antenna cable causing damage to
the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an
external (outdoor) circuit. This leads to currents or electromagnetic fields causing high
voltage or current transients. Transient voltage suppressor (TVS) devices are usually
placed, as shown in Figure 3, to protect the STB output circuits where the LNBH29 and
other devices are electrically connected to the antenna cable.
Figure 3. Surge protection circuit
For this purpose the use of LNBTVSxx surge protection diodes specifically designed by ST
is recommended. The selection of the LNBTVS diode should be made based on the
maximum peak power dissipation that the diode is capable of supporting (see the LNBTVS
datasheet for further details).
2.8
VMON: output voltage diagnostic
When device output voltage is activated (VOUT pin), its value is internally monitored and, as
long as the output voltage level is below the guaranteed limits, the VMON I²C bit is set to “1”.
See Table 12 for more details.
2.9
PDO: overcurrent detection on output pull-down stage
When an overcurrent occurs on the pull-down output stage due to an external voltage
source greater than the LNBH29 nominal VOUT and for a time longer than ISINK_TIME-OUT
(10 ms typ.), the PDO I²C bit is set to “1”. This may happen due to an external voltage
source presence on the LNB output (VOUT pin).
For current threshold and de-glitch time details, see Table 9.
2.10
Power-on I²C interface reset and undervoltage lockout
The I²C interface built into the LNBH29 series is automatically reset at power-on. As long as
the VCC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface
does not respond to any I²C command and all DATA register bits are initialized to zeroes,
therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ. the I²C
interface becomes operative and the DATA registers can be configured by the main
microprocessor.
DocID023065 Rev 3
7/31
Application information
2.11
LNBH29
PNG: input voltage minimum detection
When input voltage (VCC pin) is lower than LPD (low power diagnostic) minimum thresholds,
the PNG I²C bit is set to “1”. Refer to Table 9 for threshold details.
2.12
COMP: boost capacitors and inductor
The DC-DC converter compensation loop can be optimized in order to properly work with
both ceramic and electrolytic capacitors (VUP pin). For this purpose, one I²C bit in the DATA
register (COMP) can be set to “1” or “0” as follows:
COMP=0 for electrolytic capacitors
COMP=1 for ceramic capacitors
For recommended DC-DC capacitor and inductor values refer to Section 5: Typical
application circuits and to the BOM in Table 5.
2.13
OLF: overcurrent and short-circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short-circuit condition,
the device is provided with a dynamic short-circuit protection. The overcurrent protection
circuit works dynamically: as soon as an overload is detected, the output current is provided
only for TON time (90 ms typ.) and after that, the output is set in shutdown for a TOFF time of
typically 900 ms. Simultaneously, the diagnostic OLF I²C bit of the STATUS register is set to
“1”. After this time has elapsed, the output is resumed for a time TON. At the end of TON, if
the overload is still detected, the protection circuit cycles again through TOFF and TON. At
the end of a full TON in which no overload is detected, normal operation is resumed and the
OLF diagnostic bit is reset to LOW after a register reading is done. Typical TON + TOFF time
is 990 ms, determined by an internal timer. This dynamic operation can greatly reduce the
power dissipation in short-circuit conditions, while ensuring excellent power-on startup in
most conditions.
2.14
OTF: thermal protection and diagnostic
The LNBH29 series is also protected against overheating: when the junction temperature
exceeds 150 °C (typ.), the step-up converter and the linear regulator are shut off and the
diagnostic OTF bit in the STATUS register is set to “1”. As soon as the overtemperature
condition is removed, normal operation is automatically re-enabled, while the OTF bit is
reset to “0” after a register reading operation.
8/31
DocID023065 Rev 3
LNBH29
3
Pin configuration
Pin configuration
Figure 4. Pin connections QFN16 (3x3) and (4x4) (top view)
16
15
14
13
LX
NC
VUP
VOUT
1
NC
VCC
12
2
PGND
NC
11
3
DSQIN/
EXTM
4
NC
VBYP 10
GND
ADDR
SCL
SDA
ISEL
5
6
7
8
9
AM11890v1
Table 2. Pin description
Pin n°
Symbol
Name
Pin function
16
LX
N-Mos drain
2
P-GND
Power ground
DC-DC converter power ground. To be connected directly to the
Epad.
5
ADDR
Address setting
Two I²C bus addresses available by setting the address pin level
voltage. See Table 11.
6
SCL
Serial clock
Clock from I²C bus.
7
SDA
Serial data
Bi-directional data from/to I²C bus.
8
ISEL
Current selection
9
GND
Analog ground
Integrated N-channel Power MOSFET drain.
The resistor “RSEL” connected between ISEL and GND defines the
linear regulator current limit threshold. Refer to Section 2.4.
Analog circuits ground. To be connected directly to the Epad.
Needed for internal pre-regulator filtering. The BYP pin is intended
only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause
permanent damage to the device.
10
BYP
Bypass capacitor
12
VCC
Supply input
13
VOUT
LNB output port
Output of the integrated very low drop linear regulator. See Table 7
for voltage selection and description.
14
VUP
Step-up voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a minimum
dropout across the linear pass transistor.
8 to 17.5 V IC DC-DC power supply.
DocID023065 Rev 3
9/31
Pin configuration
LNBH29
Table 2. Pin description (continued)
Pin n°
Symbol
Name
Pin function
3
DSQIN
(LNBH29)
DiSEqC tone
envelope input
Available for LNBH29 version: this pin accepts DiSEqC envelope
codes (TTL compatible) from the main DiSEqC microcontroller. The
LNBH29 uses this code to enable the internally generated 22 kHz
carrier superimposed to the VOUT pin DC voltage. See Figure 5.
3
EXTM
(LNBH29E)
External 22 kHz
tone input
Available for LNBH29E version: the “external tone modulation” input
acts on the integrated linear regulator loop to superimpose an
external 22 kHz signal to the VOUT pin DC voltage. Needs DC
decoupling to the AC source. See Figure 6.
Epad
Epad
Exposed pad
To be connected with power grounds and to the ground layer
through vias to dissipate the heat.
1, 4,
11, 15
N.C.
Not internally
connected
Not internally connected pins. These pins can be connected to GND
to improve thermal performance.
10/31
DocID023065 Rev 3
LNBH29
4
Maximum ratings
Maximum ratings
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
Unit
VCC
DC power supply input voltage pins
-0.3 to 20
V
VUP
DC input voltage
-0.3 to 40
V
IOUT
Output current
Internally limited
mA
VOUT
DC output pin voltage
-0.3 to 40
V
Logic input pins voltage (SDA, SCL, DSQIN, ADDR pins)
-0.3 to 7
V
EXTM pin voltage
-0.3 to 2
V
LX input voltage
-0.3 to 30
V
VBYP
Internal reference pin voltage
-0.3 to 4.6
V
ISEL
Current selection pin voltage
-0.3 to 3.5
V
TSTG
Storage temperature range
-50 to 150
°C
Operating junction temperature range
-25 to 125
°C
ESD rating with human body model (HBM) all pins, unless
power output pins
2
kV
ESD rating with human body model (HBM) for power output
pins
4
VI
VEXTM
LX
TJ
ESD
Note:
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to the network ground terminal.
Table 4. Thermal data
Symbol
Parameter
QFN
(3x3)
QFN
(4x4)
Unit
RthJC
Thermal resistance junction-case
2
2
°C/W
RthJA
Thermal resistance junction-ambient with device soldered
on 2s2p 4-layer PCB provided with thermal vias below
exposed pad
55
40
°C/W
DocID023065 Rev 3
11/31
Typical application circuits
5
LNBH29
Typical application circuits
Figure 5. LNBH29: DiSEqC tone envelope pin control
D2
to LNB
14 Vup
Vout
13
C5
D1
C2
D3
C3
LX
16
LNBH29
L1
Vin
12V
C1
12
Vcc
7
SDA
6
SCL
5
ADDR
8
ISEL
C4
R1 (RSEL)
DSQIN
P-GND
GND
2
9
DiSEqC
Envelope
3
Byp 10
TTL
C6
AM11891v1
Figure 6. LNBH29E: external 22 kHz DiSEqC pin control
D2
to LNB
14 Vup
Vout
13
C5
D1
C2
D3
C3
16
LX
LNBH29E
L1
Vin
12V
12
C1
Vcc
C4
R1 (RSEL)
DiSEqC
22KHz
7
SDA
6
SCL
5
ADDR
8
ISEL
EXTM
3
C7
P-GND
GND
2
9
Byp 10
C6
AM11892v1
12/31
DocID023065 Rev 3
LNBH29
Typical application circuits
Table 5. Typical application circuit bill of material
Component
R1 (RSEL)
Notes
SMD resistor. Refer to IMAX current limit selection resistor values (Table 9).
C1
> 25 V electrolytic capacitor, 100 µF or higher is suitable.
or
> 25 V ceramic capacitor, 10 µF or higher is suitable.
C2
With COMP=0, > 25 V electrolytic capacitor, 100 µF or higher is suitable.
or
With COMP=1, > 35 V ceramic capacitor, 22 µF (or 2 x 10 µF) or higher is suitable.
C3
From 470 nF to 2.2 µF ceramic capacitor. Higher values allow lower DC-DC noise.
C5
From 100 nF to 220 nF ceramic capacitor. Higher values allow lower DC-DC noise.
C4, C6
220 nF ceramic capacitors.
C7
100 nF or higher is suitable.
D1
STPS130A or similar Schottky diode.
D3
BAT54, BAT43, 1N5818, or any low power Schottky diode with IF(AV) > 0.2 A, VRRM
> 25 V, VF < 0.5 V. To be placed as close as possible to VOUT pin.
D2
1N4001-07, S1A-S1M, or any similar general purpose rectifier.
L1
With COMP=0, use 10 µH inductor with Isat>Ipeak where Ipeak is the boost converter
peak current.
or
With COMP=1 and C2 = 22 µF, use 6.8 µH inductor with Isat>Ipeak where Ipeak is the
boost converter peak current.
DocID023065 Rev 3
13/31
I²C bus interface
6
LNBH29
I²C bus interface
Data transmission from the main microprocessor to the LNBH29 and vice versa takes place
through the 2-wire I²C bus interface, consisting of the 2 lines SDA and SCL (pull-up resistors
to positive supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 7, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
6.2
Start and stop condition
As shown in Figure 8, a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A stop condition must be sent before each start condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4
Acknowledge
The master (microprocessor) puts a resistive HIGH level on the SDA line during the
acknowledge clock pulse (see Figure 9). The peripheral (LNBH29) that acknowledges must
pull down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during this clock pulse. The peripheral which has been addressed must
generate an acknowledge after the reception of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse time. In this case the master transmitter can
generate the STOP information in order to abort the transfer. The LNBH29 does not
generate an acknowledge if the VCC supply is below the undervoltage lockout threshold (4.7
V typ.).
6.5
Transmission without acknowledge
If the detection of an acknowledge from the LNBH29 is not required, the microprocessor can
use a simpler transmission: it simply waits one clock cycle without checking the slave
acknowledging, and sends the new data. This approach is of course less protected from
misworking and decreases the noise immunity.
14/31
DocID023065 Rev 3
LNBH29
I²C bus interface
Figure 7. Data validity on the I²C bus
Figure 8. Timing diagram of I²C bus
Figure 9. Acknowledge on the I²C bus
DocID023065 Rev 3
15/31
I²C interface protocol
LNBH29
7
I²C interface protocol
7.1
Write mode transmission
The LNBH29 series interface protocol comprises:
a start condition (S)
a chip address byte with the LSB bit R/W = 0
a register address (internal address of the first register to be accessed)
a sequence of data (byte to write in the addressed internal register + acknowledge)
a stop condition (P). The transfer lasts until a stop bit is encountered
the LNBH29, as slave, acknowledges every byte transfer.
Figure 10. Example of writing procedure starting with first data address 0x2
ACK
VSEL1
VSEL0
N/A
COMP
VSEL2
0 0 0 0 0 0 0 1
LSB
N/A
0 X
MSB
N/A
0 0 1 0
LSB
ACK
0
MSB
ACK
S
R/W = 0
LSB
MSB
DATA
Add=0x1
REGISTER ADDRESS
N/A
CHIP ADDRESS
P
AM11893v1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the chip address (see Table 11 for pin selection).
Note:
One only DATA register address 0x1 is available for the writing procedure.
7.2
Read mode transmission
In Read mode the bytes sequence must be as follows:
16/31
a start condition (S)
a chip address byte with the LSB bit R/W=0
the register address byte of the internal first register to be accessed
a stop condition (P)
a new master transmission with the chip address byte and the LSB bit R/W=1
after the acknowledge the LNBH29 starts to send the addressed register content. As
long as the master keeps the acknowledge LOW, the LNBH29 transmits the next
address register byte content.
the transmission is terminated when the master sets the acknowledge HIGH with a
following stop bit.
DocID023065 Rev 3
LNBH29
I²C interface protocol
Figure 11. Example of reading procedure starting with first status address 0X0 (a)
REGISTER ADDRESS
0 0 0 0 0 0 0 X
P
0
0
1
0
0 X
LSB
N/A
ACK
N/A
PDO
PNG
VMON
OTF
OLF
N/A
MSB
LSB
N/A
N/A
0
DATA
Add=0x1
STATUS
Add=0x0
MSB
S
ACK
0 X
R/W = 1
0
ACK
1
N/A
0
COMP
VSEL2
VSEL1
VSEL0
0
LSB
MSB
N/A
0
LSB
MSB
ACK
S
R/W = 0
LSB
MSB
CHIP ADDRESS
ACK
CHIP ADDRESS
P
AM11894v1
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, set the values to select the chip address (see Chip Address pin selection table) and
to select the register address (0x0 for STATUS register and 0x1 for DATA register).
7.3
DATA register
The DATA register can be addressed both in Write and Read mode. In Read mode it returns
the last writing byte status received in the previous write transmission.
Table 6 provides the DATA register values with relevant function description of each bit.
a. The reading procedure can start from any register address (STATUS or DATA) by simply setting the X values
in the register address byte (after the first chip address in Figure 11). It can be also stopped from the master by
sending a stop condition after any acknowledge bit.
DocID023065 Rev 3
17/31
I²C interface protocol
LNBH29
Table 6. DATA (READ/WRITE register. Register address = 0X1)
BIT
Name
Value
Description
Bit 0
(LSB)
VSEL0
0/1
Bit 1
VSEL1
0/1
Bit 2
VSEL2
0/1
Bit 3
COMP
1
DC-DC converter compensation: set to “1” for using very low E.S.R.
capacitors or ceramic caps (VUP pin).
0
DC-DC converter compensation: set to “0” for using standard E.S.R.
capacitors (VUP pin).
Output voltage selection bits.
(Refer to Table 7)
Bit 4
N/A
0
Reserved. Keep to “0”
Bit 5
N/A
0
Reserved. Keep to “0”
Bit 6
N/A
0
Reserved. Keep to “0”
Bit 7
(MSB)
N/A
0
Reserved. Keep to “0”
N/A = Reserved bit.
All bits reset to “0” at power-on.
Table 7. Output voltage selection table (DATA register, Write mode)
18/31
VOUT
min.
VOUT pin
voltage
VOUT
max.
VSEL2
VSEL1
VSEL0
0
0
0
0
0
1
12.545
13.000
13.455
0
1
0
12.867
13.333
13.800
0
1
1
13.188
13.667
14.000
1
0
1
17.515
18.150
18.785
1
1
0
17.836
18.483
19.130
1
1
1
18.158
18.817
19.475
Function
VOUT disabled. LNBH29/LNBH29E set
in Standby mode
0.000
DocID023065 Rev 3
LNBH29
7.4
I²C interface protocol
STATUS register
The STATUS register can be addressed only in Read mode and provides the diagnostic
functions described in Table 8.
Table 8. STATUS (READ register. Register address = 0X0)
BIT
Bit 0
(LSB)
Bit 1
Bit 2
Bit 3
Bit 4
Name
Value
Description
1
Output short-circuit or VOUT pin overload protection has been triggered
(IOUT > IMAX).
0
No overload protection has been triggered to VOUT pin (IOUT < IMAX).
1
Junction overtemperature is detected, TJ > 150 °C.
0
Junction overtemperature not detected, TJ < 135 °C. TJ is below
thermal protection threshold.
1
Output voltage (VOUT pin) lower than VMON specification thresholds.
Refer to Table 12.
0
Output voltage (VOUT pin) is within the VMON specifications.
1
Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to
VLP in Table 9.
0
Input voltage (VCC pin) higher than LPD thresholds. Refer to VLP in
Table 9.
1
Overcurrent detected on output pull-down stage for a time longer than
de-glitch period. This may happen due to an external voltage source
present on the LNB output (VOUT pin).
0
No overcurrent detected on output pull-down stage.
OLF
OTF
VMON
PNG
PDO
Bit 5
N/A
-
Reserved
Bit 6
N/A
-
Reserved
Bit 7
(MSB)
N/A
Reserved
N/A = Reserved bit.
All bits reset to “0” at power-on.
DocID023065 Rev 3
19/31
Electrical characteristics
8
LNBH29
Electrical characteristics
Refer to the Section 5: Typical application circuits, TJ from 0 to 85 °C, DATA register bits set
to “0” except VSEL0 = 1, RSEL = 16.2 k, DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless
otherwise stated. Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See
software description section for I²C access to the system register (Section 6 and Section 7).
Table 9. Electrical characteristic
Symbol
VIN
IIN
Parameter
Supply voltage
Test conditions
(1)
Supply current
Min.
Typ.
Max.
Unit
8
12
17.5
V
IOUT = 0 mA
6
22 kHz tone enabled (DSQIN=high),
IOUT = 0 mA
10
VSEL0=VSEL1=VSEL2=0
1
-3.5
mA
VOUT
Output voltage total accuracy Valid at any VOUT selected level
+3.5
VOUT
Line regulation
VIN = 8 to 17.5 V
40
VOUT
Load regulation
IOUT from 50 to 500 mA
100
IMAX
Output current limiting
thresholds
RSEL = 16.2 k
RSEL = 22 k
ISC
Output short-circuit current
RSEL= 16.2 k
SS
Soft-start time
SS
%
mV
500
750
350
550
mA
400
mA
VOUT from 0 to 13 V
4
ms
Soft-start time
VOUT from 0 to 18 V
6
ms
T13-18
Soft transition rise time
VOUT from 13 V to 18 V
1.5
ms
T18-13
Soft transition fall time
VOUT from 18 V to 13 V
1.5
ms
TOFF
Dynamic overload protection
OFF-time
Output shorted
900
TON
Dynamic overload protection
ON-time
Output shorted
TOFF/
10
ATONE
Tone amplitude
DSQIN = “1” (using internal tone
generator)
IOUT from 0 to 500 mA
CBUS from 0 to 750 nF
FTONE
Tone frequency
ms
DTONE
tr, tf
Tone duty cycle
Tone rise or fall time (2)
DSQIN = “1”
(using internal tone generator)
GEXTM
External modulation gain (3)
VOUT/ VEXTM, freq. from 10 kHz to
30 kHz
VEXTM
External modulation input
voltage (3)
EXTM AC coupling (4)
ZEXTM
External modulation
impedance (3)
20/31
0.55
0.675
0.8
VPP
20
22
24
kHz
43
50
57
%
5
8
15
µs
400
mVPP
10
230
DocID023065 Rev 3
W
LNBH29
Electrical characteristics
Table 9. Electrical characteristic (continued)
Symbol
Parameter
Test conditions
Eff DC/DC
DC-DC converter efficiency
FSW
DC-DC converter switching
frequency
Min.
IOUT = 500 mA
Typ.
Max.
Unit
93
%
440
kHz
Undervoltage lockout
thresholds
UVLO threshold rising
4.8
UVLO threshold falling
4.7
Low power diagnostic (LPD)
thresholds
VLP threshold rising
7.2
VLP
VLP threshold falling
6.7
VIL
DSQIN, pin logic LOW
VIH
DSQIN, pin logic HIGH
IIH
DSQIN, pin input current
VIH = 5 V
15
IOBK
Output backward current
All VSELx=0 V, VOBK=30 V
-3
ISINK
Output low-side sink current
VOUT forced at VOUT_nom + 0.1 V
50
mA
10
ms
2
mA
UVLO
ISINK_TIMEOUT
V
0.8
2
VOUT forced at VOUT_nom + 0.1 V
Low-side sink current timeout PDO I²C bit is set to “1” after this time
has elapsed
VOUT forced at VOUT_nom + 0.1 V,
after PDO bit is set to “1”
(ISINK_TIME-OUT has elapsed)
Max. reverse current
IREV
V
V
V
µA
-6
mA
TSHDN
Thermal shutdown threshold
150
°C
TSHDN
Thermal shutdown hysteresis
15
°C
1. In applications where (VCC - VOUT) > 1.3 V, the increased power dissipation inside the integrated LDO must be taken into
account in the application thermal management design.
2. Guaranteed by design.
3. Only for type LNBH29E.
4. External signal maximum voltage for which the EXTM function is guaranteed.
TJ from 0 to 85 °C, VI = 12 V.
Table 10. I²C electrical characteristics
Symbol
Parameter
Test conditions
VIL
Low level input voltage
SDA, SCL
VIH
High level input voltage
SDA, SCL
IIN
Input current
SDA, SCL, VIN = 0.4 to 4.5 V
Low level output voltage
Maximum clock frequency
VOL
FMAX
Min.
Typ.
Max.
Unit
0.8
V
2
10
µA
SDA (open drain), IOL = 6 mA
0.6
V
SCL
400
kHz
DocID023065 Rev 3
-10
V
21/31
Electrical characteristics
LNBH29
TJ from 0 to 85 °C, VI = 12 V.
Table 11. Address pin characteristics
Symbol
Parameter
Test condition
Min.
VADDR-1
“0001000(R/W)” address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
VADDR-2
“0001001(R/W)” address pin
voltage range
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
Typ.
Max.
Unit
0
0.8
V
2
5
V
Refer to Section 5: Typical application circuits, TJ from 0 to 85 °C, DATA register bits set to
“0”, RSEL = 16 k, DSQIN = LOW, VIN = 12 V, IOUT = 50 mA, unless otherwise stated.
Typical values are referred to TJ = 25 °C. VOUT = VOUT pin voltage. See software description
section for I²C access to the STATUS register.
Table 12. Output voltage diagnostic (VMON BIT, STATUS register) characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTH-L
Diagnostic low threshold at
VOUT = 13.0 V
VSEL0=1, VSEL1=VSEL2=0
80
90
95
%
VTH-L
Diagnostic low threshold at
VOUT = 18.15 V
VSEL1=0, VSEL0=VSEL2=1
80
90
95
%
Note:
If the output voltage is lower than the min. value the VMON I²C bit is set to 1.
If VMON = 0 then VOUT > 80% of VOUT typical.
If VMON = 1 then VOUT < 95% of VOUT typical.
22/31
DocID023065 Rev 3
LNBH29
9
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Table 13. QFN16 (4 x 4 mm.) mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
A3
0.20
b
0.25
0.30
0.35
D
3.90
4.00
4.10
D2
2.50
E
3.90
E2
2.50
e
L
2.80
4.00
4.10
2.80
0.65
0.30
DocID023065 Rev 3
0.40
0.50
23/31
Package mechanical data
LNBH29
Figure 12. QFN16 (4 x 4 mm) drawing
7571203_A
24/31
DocID023065 Rev 3
LNBH29
Package mechanical data
Table 14. QFN16 (3 x 3 mm) mechanical data
mm.
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0.00
A3
0.20
b
0.18
D
2.90
D2
1.50
E
2.90
E2
1.50
e
L
0.05
0.30
3.00
3.10
1.80
3.00
3.10
1.80
0.50
0.30
DocID023065 Rev 3
0.50
25/31
Package mechanical data
LNBH29
Figure 13. QFN16 (3 x 3 mm) drawing
7509604_C
26/31
DocID023065 Rev 3
LNBH29
Package mechanical data
Tape & reel QFNxx/DFNxx (4x4) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Max.
Min.
Typ.
330
C
12.8
D
20.2
N
99
13.2
Max.
12.992
0.504
0.519
0.795
101
T
3.898
3.976
14.4
0.567
Ao
4.35
0.171
Bo
4.35
0.171
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
DocID023065 Rev 3
27/31
Package mechanical data
LNBH29
Tape and reel QFNxx/DFNxx (3x3 mm) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Min.
Typ.
330
13.2
12.8
D
20.2
0.795
N
60
2.362
0.504
0.519
18.4
0.724
Ao
3.3
0.130
Bo
3.3
0.130
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
DocID023065 Rev 3
Max.
12.992
C
T
28/31
Max.
LNBH29
Package mechanical data
Figure 14. QFN16 (4 x 4) footprint recommended data (mm)
7571203_A
Figure 15. QFN16 (3 x 3) footprint recommended data (mm)
75029604_C
DocID023065 Rev 3
29/31
Revision history
10
LNBH29
Revision history
Table 15. Document revision history
30/31
Date
Revision
Changes
03-Aug-2012
1
Initial release.
01-Oct-2012
2
Modified: L1 notes Table 5 on page 13.
15-Mar-2013
3
Modified: Maximum clock frequency Max. value Table 10 on
page 21.
DocID023065 Rev 3
LNBH29
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
ST PRODUCTS ARE NOT AUTHORIZED FOR USE IN WEAPONS. NOR ARE ST PRODUCTS DESIGNED OR AUTHORIZED FOR USE
IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH
PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR
ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED
FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN
WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE,
AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS.
PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE
CORRESPONDING GOVERNMENTAL AGENCY.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2013 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
DocID023065 Rev 3
31/31
工商网监
湘ICP备2023018690号
