LPS225HBTR

LPS225HB MEMS pressure sensor: 26 - 126 kPa absolute digital output barometer Datasheet - production data Applications  Altimeters and barometers for portable devices  GPS applications  Weather station equipment  Sport watches HLGA 8L 2.0 x 2.5 x 0.8 (max) mm Description The LPS225HB is an ultra-compact piezoresistive absolute pressure sensor. It includes a monolithic sensing element and an IC interface which communicates a digital signal from the sensing element to the application. Features  26 to 126 kPa absolute pressure range  High-resolution mode: 1 Pa RMS  Low-power mode: 3.5 Pa RMS  Current consumption down to 4 μA  High overpressure capability: 20x full scale  Embedded temperature compensation  Embedded 24-bit ADC The sensing element, which detects absolute pressure, consists of a suspended membrane inside a single mono-silicon substrate and is manufactured using a dedicated process developed by ST. The membrane is very small compared to the traditionally built silicon micromachined membranes. Membrane breakage is prevented by an intrinsic mechanical stopper.  ODR from 1 Hz to 75 Hz  SPI and I²C interfaces  Embedded FIFO  Interrupt functions: Data Ready, FIFO flags, pressure thresholds  Supply voltage: 1.7 to 3.6 V  Small and thin package  ECOPACK® lead-free compliant The IC interface is manufactured using a standard CMOS process that allows a high level of integration to design a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LPS225HB is available in a full-mold, holed LGA package (HLGA). It is guaranteed to operate over a temperature range extending from -40 °C to +85 °C. The package is holed to allow external pressure to reach the sensing element. Table 1. Device summary Order code Temperature range [°C] Package Packing LPS225HBTR -40 to +85°C HLGA-8L Tape and reel February 2017 This is information on a product in full production. DocID030115 Rev 2 1/47 www.st.com Contents LPS225HB Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 3 4 5 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.4 Dynamic-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 Stream-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 Bypass-to-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 Bypass-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 Retrieving data from FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 6 2.3.1 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 I2C serial interface (CS = High) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2.1 6.3 2/47 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID030115 Rev 2 LPS225HB Contents 6.3.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.3.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 8.1 INTERRUPT_CFG (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2 THS_P_L (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.3 THS_P_H (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.4 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.5 CTRL_REG1 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6 CTRL_REG2 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.7 CTRL_REG3 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.8 FIFO_CTRL (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.9 REF_P_XL (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.10 REF_P_L (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.11 REF_P_H (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.12 RPDS_L (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.13 RPDS_H (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.14 RES_CONF (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.15 INT_SOURCE (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.16 FIFO_STATUS (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.17 STATUS (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.18 PRESS_OUT_XL (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.19 PRESS_OUT_L (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.20 PRESS_OUT_H (2Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.21 TEMP_OUT_L (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.22 TEMP_OUT_H (2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.1 10 HLGA-8L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DocID030115 Rev 2 3/47 47 List of tables LPS225HB List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 4/47 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pressure and temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I2C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 24 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 24 Registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Output data rate bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Low-pass filter configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Register default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FIFO mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 FIFO_STATUS example: OVR/FSS details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DocID030115 Rev 2 LPS225HB List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Dynamic-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stream-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bypass-to-Stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bypass-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LPS225HB electrical connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 HLGA - 8L (2.0 x 2.5 x 0.8) package outline and mechanical data. . . . . . . . . . . . . . . . . . . 45 DocID030115 Rev 2 5/47 47 Block diagram and pin description 1 LPS225HB Block diagram and pin description MUX Sensing element I2C SPI Temperature sensor Voltage and current bias Sensor bias 6/47 ADC + digital filter Low noise analog front end p DSP for Temperature Compensation Figure 1. Block diagram DocID030115 Rev 2 Clock and timing LPS225HB Block diagram and pin description Figure 2. Pin connections %RWWRPYLHZ Table 2. Pin description Pin number Name 1 GND Function 0 V supply SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) 2 CS 3 SDA SDI SDI/SDO 4 SCL SPC I2C serial clock (SCL) SPI serial port clock (SPC) 5 SDO SA0 4-wire SPI serial data output (SDO) I2C less significant bit of the device address (SA0) 6 VDD_IO 7 INT_DRDY 8 VDD I2C serial data (SDA) 4-wire SPI serial data input (SDI) 3-wire serial data input/output (SDI/SDO) Power supply for I/O pins Interrupt or Data Ready Power supply DocID030115 Rev 2 7/47 47 Mechanical and electrical specifications LPS225HB 2 Mechanical and electrical specifications 2.1 Mechanical characteristics VDD = 1.8 V, T = 25 °C, unless otherwise noted. Table 3. Pressure and temperature sensor characteristics Symbol Parameter Test condition Min. Typ.(1) Max. Unit -40 +85 °C 0 +65 °C 1260 hPa Pressure sensor characteristics PTop Operating temperature range PTfull Full accuracy temperature range Pop Operating pressure range Pbits Pressure output data Psens Pressure sensitivity PAccRel PAccT Pnoise ODRPres 260 Relative accuracy over pressure(2) Absolute accuracy over temperature RMS pressure sensing noise(4) 24 bits 4096 LSB/ hPa P = 800 - 1100 hPa T = 25 °C ±0.1 hPa Pop T = 0 to 65 °C After OPC(3) ±0.1 Pop T = 0 to 65 °C no OPC (3) ±1 hPa with embedded filtering Pressure output data rate(5) 0.0075 hPa RMS 1 10 25 50 75 Hz Temperature sensor characteristics Top Operating temperature range Tsens Temperature sensitivity Tacc Temperature absolute accuracy ODRT -40 T = 0 to 65 °C Output temperature data rate(5) +85 °C 100 LSB/°C ±1.5 °C 1 10 25 50 75 Hz 1. Typical specifications are not guaranteed. 2. Parameter not tested at final test 3. OPC: One-Point Calibration, see RPDS_L (18h), RPDS_H (19h). 4. Pressure noise RMS evaluated in a controlled environment, based on the average standard deviation of 50 measurements at highest ODR and with LC_EN bit = 0, EN_LPFP = 1, LPFP_CFG = 1. 5. Output data rate is configured acting on ODR[2:0] in CTRL_REG1 (10h). 8/47 DocID030115 Rev 2 LPS225HB 2.2 Mechanical and electrical specifications Electrical characteristics VDD = 1.8 V, T = 25 °C, unless otherwise noted. Table 4. Electrical characteristics Symbol VDD VDD_IO Idd IddPdn Parameter Test condition Min. Typ.(1) Max. Unit Supply voltage 1.7 3.6 V IO supply voltage 1.7 VDD+0.1 V Supply current @ ODR 1Hz Supply current in power-down mode 15 μA 1 μA 1. Typical specifications are not guaranteed. DocID030115 Rev 2 9/47 47 Mechanical and electrical specifications LPS225HB 2.3 Communication interface characteristics 2.3.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and TOP. Table 5. SPI slave timing values Value(1) Symbol Parameter Unit Min tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time 6 th(CS) CS hold time 8 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time th(SO) SDO output hold time tdis(SO) SDO output disable time Max 100 ns 10 ns 50 9 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. Figure 3. SPI slave timing diagram Note: 10/47 Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. DocID030115 Rev 2 MHz LPS225HB Mechanical and electrical specifications I2C - inter-IC control interface 2.3.2 Subject to general operating conditions for Vdd and TOP. Table 6. I2C slave timing values I²C standard mode(1) Parameter (1) Symbol f(SCL) SCL clock frequency I²C fast mode(1) Min Max Min Max Unit 0 100 0 400 kHz tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0.01 3.45 μs ns 0 0.9 (2) 300 300 tr(SDA) tr(SCL) SDA and SCL rise time 1000 20 + 0.1Cb tf(SDA) tf(SCL) SDA and SCL fall time 300 20 + 0.1Cb(2) th(ST) START condition hold time 4 0.6 tsu(SR) Repeated START condition setup time 4.7 0.6 tsu(SP) STOP condition setup time 4 0.6 4.7 1.3 tw(SP:SR) Bus free time between STOP and START condition μs ns μs 1. Data based on standard I2C protocol requirement, not tested in production. 2. Cb = total capacitance of one bus line, in pF. Figure 4. I2C slave timing diagram 5(3($7(' 67$57 67$57 WVX65 WZ6365 6'$ WI6'$ WVX6'$ WU6'$ 67$57 WK6'$ WVX63 6723 6&/ WK67 Note: WZ6&// WZ6&/+ WU6&/ WI6&/ Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. DocID030115 Rev 2 11/47 47 Mechanical and electrical specifications 2.4 LPS225HB Absolute maximum ratings Stress above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Vdd Vdd_IO Vin P Note: Ratings Maximum value Unit Supply voltage -0.3 to 4.8 V I/O pins supply voltage -0.3 to 4.8 V -0.3 to Vdd_IO +0.3 V 2 MPa -40 to +125 °C 2 (HBM) kV Input voltage on any control pin Overpressure TSTG Storage temperature range ESD Electrostatic discharge protection Supply voltage on any pin should never exceed 4.8 V. This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. 12/47 DocID030115 Rev 2 LPS225HB 3 Functionality Functionality The LPS225HB is a high-resolution, digital output pressure sensor packaged in an HLGA full-mold package. The complete device includes a sensing element based on a piezoresistive Wheatstone bridge approach, and an IC interface which communicates a digital signal from the sensing element to the application. 3.1 Sensing element An ST proprietary process is used to obtain a mono-silicon μ-sized membrane for MEMS pressure sensors without requiring substrate-to-substrate bonding. When pressure is applied, the membrane deflection induces an imbalance in the Wheatstone bridge piezoresistances whose output signal is converted by the IC interface. 3.2 I2C interface The complete measurement chain is composed of a low-noise amplifier which converts the resistance unbalancing of the MEMS sensors (pressure and temperature) into an analog voltage using an analog-to-digital converter. The pressure and temperature data may be accessed through an I²C/SPI interface, thus making the device particularly suitable for direct interfacing with a microcontroller. The LPS225HB features a Data-Ready signal which indicates when a new set of measured pressure and temperature data are available, thus simplifying data synchronization in the digital system that uses the device. 3.3 Factory calibration The IC interface is factory calibrated at three temperatures and two pressures for sensitivity and accuracy. The trimming values are stored inside the device in a non-volatile structure. When the device is turned on, the trimming parameters are downloaded into the registers to be employed during normal operation which allows the device to be used without requiring any further calibration. DocID030115 Rev 2 13/47 47 FIFO 4 LPS225HB FIFO The LPS225HB embeds 32 slots of 40-bit data FIFO to store the pressure and temperature output values. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work according to seven different modes: Bypass mode, FIFO mode, Stream mode, Dynamic-Stream mode, Stream-to-FIFO mode, Bypass-to-Stream and Bypass-to-FIFO mode. The FIFO buffer is enabled when the FIFO_EN bit in CTRL_REG2 (11h) is set to '1' and each mode is selected by the FIFO_MODE[2:0] bits in FIFO_CTRL (14h). Programmable FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the FIFO_STATUS (26h) register and can be set to generate dedicated interrupts on the INT_DRDY pad using the CTRL_REG3 (12h) register. FIFO_STATUS (26h)(FTH_FIFO) goes to '1' when the number of unread samples (FIFO_STATUS (26h)(FSS5:0)) is greater than or equal to WTM[4:0] in FIFO_CTRL (14h). If FIFO_CTRL (14h)(WTM4:0) is equal to 0, FIFO_STATUS (26h)(FTH_FIFO) goes to '0'. FIFO_STATUS (26h)(OVRN) is equal to '1' if a FIFO slot is overwritten. FIFO_STATUS (26h)(FSS5:0) contains stored data levels of unread samples; when FSS[5:0] is equal to '000000', FIFO is empty, when FSS[5:0] is equal to '100000', FIFO is full and the unread samples are 32. To guarantee the switching into and out of FIFO mode, discard the first sample acquired. 4.1 Bypass mode In Bypass mode (FIFO_CTRL (14h)(FMODE2:0)=000), the FIFO is not operational and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode. As described in the next figure, for each channel only the first address is used. When new data is available, the older data is overwritten. Every time Bypass mode is selected, FIFO content is flushed. Figure 5. Bypass mode 14/47 DocID030115 Rev 2 LPS225HB 4.2 FIFO FIFO mode In FIFO mode (FIFO_CTRL (14h)(FMODE2:0) = 001) data from the output PRESS_OUT_XL (28h), PRESS_OUT_L (29h), PRESS_OUT_H (2Ah) and TEMP_OUT_L (2Bh), TEMP_OUT_H (2Ch) are stored in the FIFO until it is overwritten. To reset FIFO content, in Bypass mode the value '000' must be written in FIFO_CTRL (14h)(FMODE2:0). After this reset command, it is possible to restart FIFO mode writing the value '001' in FIFO_CTRL (14h)(FMODE2:0). The FIFO buffer memorizes 32 levels of data but the depth of the FIFO can be resized by setting the CTRL_REG2 (11h)(STOP_ON_FTH) bit. If the STOP_ON_FTH bit is set to '1', FIFO depth is limited to FIFO_CTRL (14h)(WTM4:0) + 1 data. A FIFO threshold interrupt can be enabled (F_OVR bit in CTRL_REG3 (12h) in order to be raised when the FIFO is filled to the level specified by the WTM4:0 bits of FIFO_CTRL (14h). When a FIFO threshold interrupt occurs, the first data has been overwritten and the FIFO stops collecting data from the input pressure and temperature. Figure 6. FIFO mode DocID030115 Rev 2 15/47 47 FIFO 4.3 LPS225HB Stream mode Stream mode (FIFO_CTRL (14h)(FMODE2:0) = 010) provides continuous FIFO update: as new data arrive, the older is discarded. Once the entire FIFO has been read, the last data read remains in the FIFO and hence once a new sample is acquired, the FIFO_STATUS (26h)(FSS5:0) value rises from 0 to 2. An overrun interrupt can be enabled, CTRL_REG3 (12h)(F_OVR) = '1', in order to inform when the FIFO is full and eventually read its content all at once. If an overrun occurs, the oldest sample in FIFO is overwritten, so if the FIFO was empty, the lost sample has already been read. Figure 7. Stream mode In the latter case reading all FIFO content before an overrun interrupt has occurred, the first data read is equal to the last already read in the previous burst, so the number of new data available in FIFO depends on the previous reading. 16/47 DocID030115 Rev 2 LPS225HB 4.4 FIFO Dynamic-Stream mode In Dynamic-Stream mode (FIFO_CTRL (14h)(FMODE2:0) = 110) after emptying the FIFO, the first new sample that arrives becomes the first to be read in a subsequent read burst. In this way, the number of new data available in FIFO does not depend on the previous reading. In Dynamic-Stream mode FIFO_STATUS (26h)(FSS5:0) is the number of new pressure and temperature samples available in the FIFO buffer. Stream Mode is intended to be used to read all 32 samples of FIFO within an ODR after receiving an overrun signal. Dynamic-Stream is intended to be used to read FIFO_STATUS (26h)(FSS5:0) samples when it is not possible to guarantee reading data within an ODR. Also, a FIFO threshold interrupt on the INT_DRDY pad through CTRL_REG3 (12h)(F_FTH) can be enabled in order to read data from the FIFO and leave free memory slots for incoming data. Figure 8. Dynamic-Stream mode DocID030115 Rev 2 17/47 47 FIFO 4.5 LPS225HB Stream-to-FIFO mode In Stream-to-FIFO mode (FIFO_CTRL (14h)(FMODE2:0) = 011), FIFO behavior changes according to the INT_SOURCE(IA) bit. When the INT_SOURCE(IA) bit is equal to '1', FIFO operates in FIFO mode. When the INT_SOURCE(IA) bit is equal to '0', FIFO operates in Stream mode. An interrupt generator can be set to the desired configuration through INTERRUPT_CFG (0Bh). The INTERRUPT_CFG (0Bh)(LIR) bit should be set to '1' in order to have latched interrupt. Figure 9. Stream-to-FIFO mode 18/47 DocID030115 Rev 2 LPS225HB 4.6 FIFO Bypass-to-Stream mode In Bypass-to-Stream mode (FIFO_CTRL (14h)(FMODE2:0) = '100'), data measurement storage inside FIFO operates in Stream mode when INT_SOURCE(IA) is equal to '1',otherwise FIFO content is reset (Bypass mode). An interrupt generator can be set to the desired configuration through INTERRUPT_CFG (0Bh). The INTERRUPT_CFG (0Bh)(LIR) bit should be set to '1' in order to have latched interrupt. Figure 10. Bypass-to-Stream mode DocID030115 Rev 2 19/47 47 FIFO 4.7 LPS225HB Bypass-to-FIFO mode In Bypass-to-FIFO mode (FIFO_CTRL (14h)(FMODE2:0) = '111'), data measurement storage inside FIFO operates in FIFO mode when INT_SOURCE(IA) is equal to '1', otherwise FIFO content is reset (Bypass mode). An interrupt generator can be set to the desired configuration through INTERRUPT_CFG (0Bh). The INTERRUPT_CFG (0Bh)(LIR) bit should be set to '1' in order to have latched interrupt. Figure 11. Bypass-to-FIFO mode 4.8 Retrieving data from FIFO FIFO data is read from PRESS_OUT (Addr. reg 28h, 29h, 2Ah) and TEMP_OUT (Addr. reg 2Bh, 2Ch). Each time data is read from the FIFO, the oldest data are placed in the PRESS_OUT_XL (28h), PRESS_OUT_L (29h), PRESS_OUT_H (2Ah), TEMP_OUT_L (2Bh) and TEMP_OUT_H (2Ch) registers and both single-read and read-burst operations can be used. The device automatically updates the reading address and it rolls back to 28h when register 2Ch is reached. In order to read all FIFO levels in multiple byte reading, 160 bytes (5 output registers by 32 levels) must be read. 20/47 DocID030115 Rev 2 LPS225HB 5 Application hints Application hints *1' &6 6'$6',6'2 6&/63& Figure 12. LPS225HB electrical connections     *1'   ,17B'5'< 9''B,2 9'' Q)  6'26$  9'' 7RSYLHZ 9'' X) & & *1' *1' The device core is supplied through the VDD line. Power supply decoupling capacitors (100 nF, 4.7 μF) should be placed as near as possible to the supply pad of the device (common design practice). The functionality of the device and the measured data outputs are selectable and accessible through the I²C/SPI interface. When using the I²C, CS must be tied high (i.e. connected to VDD_IO). 5.1 Soldering information The HLGA package is compliant with the ECOPACK® standard and it is qualified for soldering heat resistance according to JEDEC J-STD-020. DocID030115 Rev 2 21/47 47 Digital interfaces LPS225HB 6 Digital interfaces 6.1 I2C serial interface The registers embedded in the LPS225HB may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pads. To select/exploit the I²C interface, the CS line must be tied high (i.e. connected to Vdd_IO). Table 8. Serial interface pin description Pin name SPI enable I²C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) CS SCL/SPC I²C serial clock (SCL) SPI serial port clock (SPC) SDA SDI SDI/SDO I²C serial data (SDA) 4-wire SPI serial data input (SDI) 3-wire serial data input /output (SDI/SDO) SDO SAO 6.2 Pin description SPI serial data output (SDO) I²C less significant bit of the device address (SA0) I2C serial interface (CS = High) The LPS225HB I²C is a bus slave. The I²C is employed to write data into registers whose content can also be read back. The relevant I²C terminology is given in Table 9. Table 9. I2C terminology Term Description Transmitter The device which sends data to the bus Receiver The device which receives data from the bus Master The device which initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by the master There are two signals associated with the I²C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both lines have to be connected to Vdd_IO through pull-up resistors. The I²C interface is compliant with fast mode (400 kHz) I²C standards as well as with the normal mode. 22/47 DocID030115 Rev 2 LPS225HB 6.2.1 Digital interfaces I2C operation The transaction on the bus is started through a START (ST) signal. A start condition is defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The slave address (SAD) associated to the LPS225HB is 101110xb. The SDO/SA0 pad can be used to modify the less significant bit of the device address. If the SA0 pad is connected to voltage supply, LSb is ‘1’ (address 1011101b), otherwise if the SA0 pad is connected to ground, the LSb value is ‘0’ (address 1011100b). This solution permits to connect and address two different LPS225HB devices to the same I²C lines. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I²C embedded in the LPS225HB behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) will be transmitted: the 7 LSB represents the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is ‘1’, the SUB (register address) will be automatically increased to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 10 explains how the SAD+read/write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W Read 101110 0 1 10111001 (B9h) Write 101110 0 0 10111000 (B8h) Read 101110 1 1 10111011 (BBh) Write 101110 1 0 10111010 (BAh) Table 11. Transfer when master is writing one byte to slave Master Slave ST SAD + W SUB SAK DocID030115 Rev 2 DATA SAK SP SAK 23/47 47 Digital interfaces LPS225HB Table 12. Transfer when master is writing multiple bytes to slave Master ST SAD + W SUB Slave SAK DATA DATA SAK SAK SP SAK Table 13. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W Slave SUB SAK SR SAD + R SAK NMAK SAK SP DATA Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave Master Slave ST SAD+W SUB SAK SR SAD+R SAK MAK SAK DATA MAK DATA NMAK SP DATA Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other functions, it can hold the clock line, SCL LOW to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver does not acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be kept HIGH by the slave. The master can then abort the transfer. A LOW-to-HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes incrementing the register address, it is necessary to assert the most significant bit of the sub-address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of the first register to be read. In the presented communication format MAK is Master acknowledge and NMAK is no master acknowledge. 24/47 DocID030115 Rev 2 LPS225HB 6.3 Digital interfaces SPI bus interface The LPS225HB SPI is a bus slave. The SPI allows writing to and reading from the registers of the device. The serial interface interacts with the application using 4 wires: CS, SPC, SDI and SDO. Figure 13. Read and write protocol &6 63& 6', ', ', ', ', ', ', ', ', 5: $' $' $' $' $' $' $' 6'2 '2 '2 '2 '2 '2 '2 '2 '2 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23,...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods are added. When the IF_ADD_INC bit is 0 the address used to read/write data remains the same for every block. When the IF_ADD_INC bit is 1 the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. DocID030115 Rev 2 25/47 47 Digital interfaces 6.3.1 LPS225HB SPI read Figure 14. SPI read protocol &6 63& 6', 5: $' $' $' $' $' $' $' 6'2 '2 '2 '2 '2 '2 '2 '2 '2 The SPI read command is performed with 16 clock pulses. The multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). bit 16-...: data DO(...-8). Further data in multiple byte reads. Figure 15. Multiple byte SPI read protocol (2-byte example) $4 41$ 4%* 4%0 26/47 DocID030115 Rev 2 LPS225HB 6.3.2 Digital interfaces SPI write Figure 16. SPI write protocol &6 63& 6', ', ', ', ', ', ', ', ', 5: $' $' $' $' $' $' $' The SPI Write command is performed with 16 clock pulses. The multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written in the device (MSb first). bit 16-...: data DI(...-8). Further data in multiple byte writes. Figure 17. Multiple byte SPI write protocol (2-byte example) &6 63& 6', ', ', ', ', ', ', ', ', ',',',',',',', ', 5: $' $' $' $' $' $' $' DocID030115 Rev 2 27/47 47 Digital interfaces 6.3.3 LPS225HB SPI read in 3-wire mode A 3-wire mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG1. Figure 18. SPI read protocol in 3-wire mode &6 63& 6',2 '2 '2 '2 '2 '2 '2 '2 '2 5: $' $' $' $' $' $' $' The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode. 28/47 DocID030115 Rev 2 LPS225HB 7 Register mapping Register mapping Table 15 provides a quick overview of the 8-bit registers embedded in the device. Table 15. Registers address map Register Name Type Reserved Address Default Hex Binary 00 - 0A - Function and comment Reserved INTERRUPT_CFG R/W 0B 00000000 THS_P_L R/W 0C 00000000 THS_P_H R/W 0D 00000000 0E - Reserved Who am I Reserved WHO_AM_I R 0F 10110001 CTRL_REG1 R/W 10 00000000 CTRL_REG2 R/W 11 00010000 CTRL_REG3 R/W 12 00000000 Interrupt control 13 - Reserved Reserved FIFO_CTRL R/W 14 00000000 REF_P_XL R/W 15 00000000 REF_P_L R/W 16 00000000 REF_P_H R/W 17 00000000 RPDS_L R/W 18 00000000 RPDS_H R/W 19 00000000 RES_CONF R/W 1A 00000000 1B - 24 - Reserved INT_SOURCE R 25 - FIFO_STATUS R 26 - STATUS R 27 - PRESS_OUT_XL R 28 - PRESS_OUT_L R 29 - PRESS_OUT_H R 2A - TEMP_OUT_L R 2B - TEMP_OUT_H R 2C - DocID030115 Rev 2 Reserved 29/47 47 Register mapping LPS225HB Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. To guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 30/47 DocID030115 Rev 2 LPS225HB 8 Register description Register description The device contains a set of registers which are used to control its behavior and to retrieve pressure and temperature data. The register address, made up of 7 bits, is used to identify them and to read/write the data through the serial interface. 8.1 INTERRUPT_CFG (0Bh) Interrupt configuration 7 6 5 4 3 2 1 0 AUTORIFP RESET_ARP AUTOZERO RESET_AZ DIFF_EN LIR PLE PHE Address: 0Bh (R/W) Reset: 00h Description: Interrupt differential configuration register. See DIFF_EN bit in CTRL_REG1 (10h) [7] AUTORIFP: Enable AutoRifP. Default value: 0 (0: normal mode; 1: AutoRifP enable); [6] RESET_ARP: Reset AutoRifP function. Default value: 0 [5] AUTOZERO: Enable Autozero. Default value: 0 (0: normal mode; 1: Autozero enable) [4] RESET_AZ: Reset Autozero function. Reset RIF_P reg. (address 15h, 16h, 17h), set pressure reference to default value RPDS reg (address 18h, 19h). Default value: 0 [3] DIFF_EN: Enable interrupt generation. Default value: 0 (0: interrupt generation disabled; 1: interrupt generation enabled) [2] LIR: Latch interrupt request to the INT_SOURCE (25h) register. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) [1] PLE: Enable interrupt generation on differential pressure low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured differential pressure value lower than preset threshold) [0] PHE: Enable interrupt generation on differential pressure high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured differential pressure value higher than preset threshold) AUTORIFP, when written to ‘1’, an internal register is set with current pressure values and the bit is forced to ‘0’. From that point on the content of the internal register is subtracted from the pressure output value and result is used for the interrupt generation. The output registers (PRESS_OUT_XL (28h), PRESS_OUT_L (29h), PRESS_OUT_H (2Ah)) are updated with the actual pressure value. The RESET_ARP bit is used to disable the AutoRifP function. RESET_ARP is self-cleared. DocID030115 Rev 2 31/47 47 Register description LPS225HB AUTOZERO, when set to ‘1’, the actual pressure output value is copied in the REF_P registers. From that point on, the content of the Ref_P registers is subtracted from the pressure output value. To disable autozero, the REF_P registers have to be cleared. The RESET_AZ bit is used to reset the AutoZero function. Resetting REF_P reg (15h, 16h, 17h) sets the pressure reference to the default value in the RPDS reg (18h, 19h). RESET_AZ is self-cleared. The DIFF_EN bit is used to enable the computing of the differential pressure output. It is recommended to enable DIFF_EN after the configuration of REF_P_x and THS_P_x. 8.2 THS_P_L (0Ch) Threshold pressure (LSB) 7 6 5 4 3 2 1 0 THS7 THS6 THS5 THS4 THS3 THS2 THS1 THS0 Address: 0Ch (R/W) Reset: 00h Description: This register contains the low part of threshold value for pressure interrupt generation. The complete threshold value is given by THS_P_H (0Dh) & THS_P_L (0Ch) and is expressed as an unsigned number. P_ths (hPa) = (THS_P)/16. [7:0] THS7-0: LSB threshold pressure. 8.3 THS_P_H (0Dh) Threshold pressure (MSB) 15 14 13 12 11 10 9 8 THS15 THS14 THS13 THS12 THS11 THS10 THS9 THS8 Address: 0Dh (R/W) Reset: 00h Description: This register contains the high part of threshold value for pressure interrupt generation. (See description THS_P_L (0Ch)). [15:8] THS15-8: MSB threshold pressure. 32/47 DocID030115 Rev 2 LPS225HB 8.4 Register description WHO_AM_I (0Fh) Device Who am I 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 1 Address: 0Fh (R) Description: Contains the device Who am I address (B1h). 8.5 CTRL_REG1 (10h) Control register 1 7 6 5 4 3 2 1 0 0 ODR2 ODR1 ODR0 EN_LPFP LPF_CFG BDU SIM Address: 10h (R/W) Reset: 00h Description: Control register. [7] Reserved: this bit must be set to ‘0’ for the correct operation of the device [6:4] ODR2, ODR1, ODR0: output data rate selection. Default value: 000 (see Table 16) [3] EN_LPFP: Enable low-pass filter on pressure data. Default value: 0 (0: Low-pass filter disabled; 1: Low-pass filter enabled) [2] LPF_CFG: Low-pass configuration register. Default value: 0 (see Table 17) [1] BDU: block data update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB have been read) [0] SIM: SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) DocID030115 Rev 2 33/47 47 Register description LPS225HB Table 16. Output data rate bit configurations ODR2 ODR1 ODR0 Pressure (Hz) Temperature (Hz) 0 0 0 0 0 1 1 Hz 1 Hz 0 1 0 10 Hz 10 Hz 0 1 1 25 Hz 25 Hz 1 0 0 50 Hz 50 Hz 1 0 1 75 Hz 75 Hz Standby / One-shot enabled When ODR[2,0] are set to ‘000’ the device enables One-Shot mode. When the ONESHOT bit is set to 1 in CTRL_REG2 (11h),a new conversion for pressure and temperature starts. An ODR change will not flush FIFO content. Table 17. Low-pass filter configurations LPF_CFG Filter cutoff 0 ODR/9 1 ODR/20 The BDU bit is used to inhibit the update of the output registers between the reading of upper and lower register parts. In default mode (BDU = ‘0’), the lower and upper register parts are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different samples. The SIM bit selects the SPI serial interface mode:  0: (default value) 4-wire SPI interface mode selected  1: 3-wire SPI interface mode selected 34/47 DocID030115 Rev 2 LPS225HB 8.6 Register description CTRL_REG2 (11h) 7 6 5 4 3 2 1 0 BOOT FIFO_EN STOP_ON_FTH IF_ADD_INC I²C_DIS SWRESET 0 ONE_SHOT Address: 11h (R/W) Reset: 10h Description: Control register. [7] BOOT: Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) Self-clearing upon completion. [6] FIFO_EN: FIFO Enable. Default value: 0 (0: disable; 1: enable) [5] STOP_ON_FTH: Stop on FIFO threshold. Enable FIFO watermark level use. Default value: 0 (0: disable; 1: enable) [4] IF_ADD_INC: Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value: 1 (0: disable; 1 enable) [3] I2C_DIS: disable I2C interface. Default value: 0 (0: SPI enable;1: I2C disable) [2] SWRESET: Software reset. Default value: 0 (0: normal mode; 1: software reset) Self-clearing upon completion [1] Reserved: this bit must be set to ‘0’ for the correct operation of the device [0] ONE_SHOT: One shot enable. Default value: 0 (0: waiting for start of conversion; 1: start of a new dataset) Description: The BOOT bit is used to refresh the content of the internal registers stored in the Flash memory block. At device power-up the content of the Flash memory block is transferred to the internal registers related to the trimming functions to permit good behavior of the device itself. If for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. When the BOOT bit is set to ‘1’, the content of the internal Flash is copied inside the corresponding internal registers and is used to calibrate the device. These values are factory trimmed and they are different for every device. They permit good behavior of the device and normally they should not be changed. At the end of the boot process the BOOT bit is set again to ‘0’ by hardware. The BOOT bit takes effect after one ODR clock cycle. The SWRESET bit resets the following registers to the default value and returns to ‘0’ by hardware. During a software reset FIFO content is flushed. DocID030115 Rev 2 35/47 47 Register description LPS225HB Table 18. Register default values Name Type Addr Default INTERRUPT_CFG r/w 0Bh 00h THS_P_L r/w 0Ch 00h THS_P_H r/w 0Dh 00h CTRL_REG1 r/w 10h 00h CTRL_REG2 r/w 11h 10h CTRL_REG3 r/w 12h 00h FIFO_CTRL r/w 14h 00h REF_P_XL r/w 15h 00h REF_P_L r/w 16h 00h REF_P_H r/w 17h 00h The ONE_SHOT bit is used to start a new conversion when the ODR[2,0] bits in CTRL_REG1 (10h) are set to ‘000’. If the ONE_SHOT bit is set during a Normal Mode measurement, nothing happens. Write ‘1’ in ONE_SHOT to trigger a single measurement of pressure and temperature. Once the measurement is done, the ONE_SHOT bit will self-clear, the new data are available in the output registers, and the STATUS_REG bits are updated. If ONE_SHOT bit is set while the one-shot measurement is running, at the end of the current measurement a new one-shot measurement starts. 36/47 DocID030115 Rev 2 LPS225HB 8.7 Register description CTRL_REG3 (12h) Interrupt control 7 6 5 4 3 2 1 0 INT_H_L PP_OD F_FSS5 F_FTH F_OVR DRDY INT_S2 INT_S1 Address: 12h (R/W) Reset: 00h Description: Control register. [7] INT_H_L: Interrupt active high, low. Default value: 0 (0: active high; 1: active low) [6] PP_OD: Push-pull/open-drain selection on interrupt pads. Default value: 0 (0: push-pull; 1: open drain) [5] F_FSS5: FIFO full flag on INT_DRDY pin; (0: FIFO empty; 1: FIFO full (32 unread samples)). [4] F_FTH: FIFO threshold (watermark) status on INT_DRDY pin; (0: FIFO filling is lower than FTH level; 1: FIFO filling is equal or higher than FTH level) [3] F_OVR: FIFO overrun bit status; OVRN=‘1’ means that at least one sample in the FIFO has been overwritten [2] DRDY: Data-ready signal on INT_DRDY pin [1:0] INT_S2, INT_S1: data signal on INT_DRDY pin control bits. Default value: 00 (see Table 19) Table 19. Interrupt configurations INT_S2 INT_S1 INT_DRDY pin 0 0 Data signal (in order of priority: DRDY or F_FTH or F_OVR or F_FSS5) 0 1 Pressure high (P_high) 1 0 Pressure low (P_low) 1 1 Pressure low OR high DocID030115 Rev 2 37/47 47 Register description 8.8 LPS225HB FIFO_CTRL (14h) FIFO control 7 6 5 4 3 2 1 0 F_MODE2 F_MODE1 F_MODE0 WTM4 WTM3 WTM2 WTM1 WTM0 Address: 14h (R/W) Reset: 00h Description: The FIFO_CTRL registers allow controlling FIFO functionality. [7:5] FIFO mode selection. See Table 20. [4:0] FIFO threshold. Watermark level setting. Table 20. FIFO mode selection F_MODE2 F_MODE1 F_MODE0 FIFO mode selection mode(1) 0 0 0 Bypass 0 0 1 FIFO mode. Stops collecting data when full. 0 1 0 Stream mode: if the FIFO is full, the new sample overwrites the older sample. 0 1 1 Stream-to-FIFO mode. Stream mode until trigger deasserted, then FIFO mode. 1 0 0 Bypass-to-Stream mode. Bypass mode until trigger deasserted, then Stream mode. 1 0 1 Reserved 1 1 0 Dynamic-Stream mode 1 1 1 Bypass-to-FIFO mode. Bypass mode until trigger deasserted, then FIFO mode 1. Every time Bypass mode is selected, FIFO content is flushed. 38/47 DocID030115 Rev 2 LPS225HB 8.9 Register description REF_P_XL (15h) Reference pressure (LSB data) 7 6 5 4 3 2 1 0 REFL7 REFL6 REFL5 REFL4 REFL3 REFL2 REFL1 REFL0 Address: 15h (R/W) Reset: 00h Description: The REF_P_XL register contains the lowest part of the reference pressure value that is sum to the sensor output pressure. The full reference pressure value is composed of REF_P_XL (15h), REF_P_L (16h), RPDS_L (18h) and is represented as 2’s complement. The reference pressure value can also be used to detect a measured pressure beyond programmed limits (see CTRL_REG3 (12h)), and for Autozero function (see RESET_AZ bit, at INTERRUPT_CFG (0Bh)). [7:0] REFL7-0: LSB reference pressure data 8.10 REF_P_L (16h) Reference pressure (middle part) 15 14 13 12 11 10 9 8 REFL15 REFL14 REFL13 REFL12 REFL11 REFL10 REFL9 REFL8 Address: 16h (R/W) Reset: 00h Description: The REF_P_L register contains the middle part of the reference pressure value that is sum to the sensor output pressure. (See REF_P_XL (15h) description). [15:8] REFL15-8: Middle part reference pressure data 8.11 REF_P_H (17h) Reference pressure (MSB data) 23 22 21 20 19 18 17 16 REFL23 REFL22 REFL21 REFL20 REFL19 REFL18 REFL17 REFL16 Address: 17h (R/W) Reset: 00h Description: The REF_P_H register contains the highest part of the reference pressure value that is sum to the sensor output pressure. (See REF_P_XL (15h) description). [23:16] REFL23-16: MSB reference pressure data. DocID030115 Rev 2 39/47 47 Register description 8.12 LPS225HB RPDS_L (18h) Pressure offset (LSB) 7 6 5 4 3 2 1 0 RPDS7 RPDS6 RSPDS5 RPDS4 RPDS3 RPDS2 RPDS1 RPDS0 Address: 18h (R/W) Reset: 00h Description: This register contains the low part of the pressure offset value after soldering, for differential pressure computing. The complete value is given by RPDS_H (19h) and RPDS_L (18h) and is expressed as signed 2’s complement value. [7:0] RPDS7-0: Pressure offset for one-point calibration after soldering 8.13 RPDS_H (19h) Pressure offset (MSB) 15 14 13 12 11 10 9 8 RPDS15 RPDS14 RSPDS13 RPDS12 RPDS11 RPDS10 RPDS9 RPDS8 Address: 19h (R/W) Reset: 00h Description: This register contains the high part of the pressure offset value after soldering (see description RPDS_L (18h)) [15:8] RPDS15-8: Pressure offset for one-point calibration after soldering. 8.14 RES_CONF (1Ah) 7 6 5 4 3 2 1 0 0 0 0 0 0 0 -- LC_EN(1) 1. The LC_EN bit must be changed only with the device in power-down and not during operation. Address: 1Ah (R/W) Reset: 00h Description: This register allows enabling low-power mode) [7:2] Reserved: this bit must be set to ‘0’ for the correct operation of the device [1] Reserved: the content of this register must not be modified [0] LC_EN: Enable low-current mode. Default: 0 (0: Normal mode (low-noise mode); 1: low-current mode). 40/47 DocID030115 Rev 2 LPS225HB 8.15 Register description INT_SOURCE (25h) Interrupt source 7 6 5 4 3 2 1 0 BOOT_STATUS 0 0 0 0 IA PL PH Address: 25h (R) Reset: 00h Description: INT_SOURCE register is cleared by reading it [7] BOOT_STATUS: If ‘1’ indicates that the Boot (Reboot) phase is running [6:3] Reserved [2] IA: Interrupt active. (0: no interrupt has been generated; 1: one or more interrupt events have been generated). [1] PL: Differential pressure Low. (0: no interrupt has been generated; 1: Low differential pressure event has occurred). [0] PH: Differential pressure High. (0: no interrupt has been generated; 1: High differential pressure event has occurred). 8.16 FIFO_STATUS (26h) FIFO status 7 6 5 4 3 2 1 0 FTH_FIFO OVR FSS5 FSS4 FSS3 FSS2 FSS! FSS0 Address: 26h (R) Reset: 00h Description: [7] FTH_FIFO: FIFO threshold status. Default value: 0 (0: FIFO filling is lower than FTH level, 1: FIFO filling is equal to or higher than threshold level) Description: [6] OVRN: Overrun bit status. Default value: 0 (0: FIFO is not completely filled,1: FIFO is completely filled and at least one sample has been overwritten) Description: [5:0] FSS: number of unread samples stored in FIFO. Default value: 0 (000000: FIFO empty, 100000: FIFO full, 32 unread samples) DocID030115 Rev 2 41/47 47 Register description LPS225HB Table 21. FIFO_STATUS example: OVR/FSS details FTH OVRN 0 FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 Description 0 0 0 0 0 0 0 FIFO empty 0 0 0 0 0 0 1 1 unread sample --(1) 0 1 0 0 0 0 0 32 unread samples 1 1 1 0 0 0 0 0 At least one sample has been overwritten -- (1) ... 1. When the number of unread samples in FIFO is greater than the threshold level set in register FIFO_CTRL (14h), the FTH value is ‘1’. 8.17 STATUS (27h) Status register 7 6 RES Address: 27h (R) Reset: 00h 5 4 T_OR P_OR 3 2 RES 1 0 T_DA P_DA [7:6] Reserved [5] T_OR: Temperature data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for temperature has overwritten the previous data) [4] P_OR: Pressure data overrun. Default value: 0 (0: no overrun has occurred; 1: new data for pressure has overwritten the previous data) [3:2] Reserved [1] T_DA: Temperature data available. Default value: 0 (0: new data for temperature is not yet available; 1: new data for temperature is available) [0] P_DA: Pressure data available. Default value: 0 (0: new data for pressure is not yet available; 1: new data for pressure is available) This register is updated every ODR cycle, regardless of the BDU value in CTRL_REG1 (10h). T_OR is set to ‘1’ whenever new temperature data is available and T_DA was set in the previous ODR cycle and not cleared. T_OR is cleared when TEMP_OUT_H (2Ch) is read. P_OR is set to '1' whenever new pressure data is available and P_DA was set in the previous ODR cycle and not cleared. P_OR is cleared when PRESS_OUT_H (2Ah) is read. 42/47 DocID030115 Rev 2 LPS225HB Register description T_DA is set to 1 whenever a new temperature sample is available. T_DA is cleared when TEMP_OUT_H (2Ch) is read. P_DA is set to 1 whenever a new pressure sample is available. P_DA is cleared when PRESS_OUT_H (2Ah) register is read. 8.18 PRESS_OUT_XL (28h) Pressure data (LSB) 7 6 5 4 3 2 1 0 POUT7 POUT6 POUT5 POUT4 POUT3 POUT2 POUT1 POUT0 Address: 28h (R) Description: The PRESS_OUT_XL register contains the lowest part of the pressure output value, that is, the difference between the measured pressure and the reference pressure (REF_P registers). See AUTOZERO bit in INTERRUPT_CFG (0Bh).The full reference pressure value is composed of PRESS_OUT_H/_L/_XL and is represented as 2’s complement. Pressure values exceeding the operating pressure range (see Table 3) are clipped. [7:0] POUT7 - POUT0: Pressure data LSB 8.19 PRESS_OUT_L (29h) Pressure data (middle byte) 15 14 13 12 11 10 9 8 POUT15 POUT14 POUT13 POUT12 POUT11 POUT10 POUT9 POUT8 Address: 29h (R) Description: The PRESS_OUT_L register contains the middle part of the pressure output value. (See PRESS_OUT_XL (28h) description). [15:8] POUT15 - POUT8: Pressure data DocID030115 Rev 2 43/47 47 Register description 8.20 LPS225HB PRESS_OUT_H (2Ah) Pressure data (MSB) 23 22 21 20 19 18 17 16 POUT23 POUT22 POUT21 POUT20 POUT19 POUT18 POUT17 POUT16 Address: 2Ah (R) Description: The PRESS_OUT_H register contains the highest part of the pressure output value. (See PRESS_OUT_XL (28h) description). [23:16] POUT23 - POUT16: Pressure data MSB 8.21 TEMP_OUT_L (2Bh) Temperature data (LSB) 7 6 5 4 3 2 1 0 TOUT7 TOUT6 TOUT5 TOUT4 TOUT3 TOUT2 TOUT1 TOUT0 Address: 2Bh (R) Description: The TEMP_OUT_L register contains the low part of the temperature output value. Temperature data are expressed as PRESS_OUT_H (2Ah) & TEMP_OUT_L (2Bh) as 2’s complement numbers. 8.22 TEMP_OUT_H (2Ch) Temperature data (MSB) 15 14 13 12 11 10 9 8 TOUT15 TOUT14 TOUT13 TOUT12 TOUT11 TOUT10 TOUT9 TOUT8 Address: 2Ch (R) Description: The TEMP_OUT_H register contains the high part of the temperature output value. (See TEMP_OUT_L (2Bh)description). [15:8] TOUT15 - TOUT8: Temperature data. 44/47 DocID030115 Rev 2 LPS225HB 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 9.1 HLGA-8L package information Figure 19. HLGA - 8L (2.0 x 2.5 x 0.8) package outline and mechanical data 0D[“ƒ / +   :          501
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