LSM303DLHC
Ultra-compact high-performance eCompass module:
3D accelerometer and 3D magnetometer
Datasheet - production data
Display orientation
Gaming and virtual reality input devices
Impact recognition and logging
Vibration monitoring and compensation
Description
LGA-14 (3x5x1mm)
The LSM303DLHC is a system-in-package
featuring a 3D digital linear acceleration sensor
and a 3D digital magnetic sensor.
Features
3 magnetic field channels and 3 acceleration
channels
From ±1.3 to ±8.1 gauss magnetic field full
scale
±2g/±4g/±8g/±16g linear acceleration full scale
16-bit data output
I2C serial interface
Analog supply voltage 2.16 V to 3.6 V
Power-down mode / low-power mode
2 independent programmable interrupt
generators for free-fall and motion detection
Embedded temperature sensor
Embedded FIFO
6D/4D-orientation detection
ECOPACK® RoHS and “Green” compliant
The LSM303DLHC has linear acceleration full
scales of ±2g / ±4g / ±8g / ±16g and a magnetic
field full scale of ±1.3 / ±1.9 / ±2.5 / ±4.0 / ±4.7 /
±5.6 / ±8.1 gauss.
The LSM303DLHC includes an I2C serial bus
interface that supports standard and fast mode
100 kHz and 400 kHz. The system can be
configured to generate interrupt signals by inertial
wake-up/free-fall events as well as by the position
of the device itself. Thresholds and timing of
interrupt generators are programmable by the end
user. Magnetic and accelerometer blocks can be
enabled or put into power-down mode separately.
The LSM303DLHC is available in a plastic land
grid array package (LGA) and is guaranteed to
operate over an extended temperature range
from -40 °C to +85 °C.
Table 1. Device summary
Applications
Part number
Tilt-compensated compasses
Map rotation
Position detection
Motion-activated functions
Temperature
Package Packing
range [°C]
LSM303DLHC
-40 to +85
LGA-14
Tray
LSM303DLHCTR
-40 to +85
LGA-14
Tape
and reel
Free-fall detection
Click/double-click recognition
Pedometers
Intelligent power-saving for handheld devices
November 2013
This is information on a product in full production.
DocID018771 Rev 2
1/42
www.st.com
Contents
LSM303DLHC
Contents
1
2
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
Sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4
Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1
3
2.5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5
2/42
Linear acceleration sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6.2
Zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Pull-up resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Digital interface power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5
High-current wiring effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1
6
2.6.1
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
4
Sensor I2C - inter IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1
I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2
Linear acceleration digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.3
Magnetic field digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DocID018771 Rev 2
LSM303DLHC
7
Contents
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1
7.2
Linear acceleration register description . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1.1
CTRL_REG1_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1.2
CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1.3
CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1.4
CTRL_REG4_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.5
CTRL_REG5_A (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.1.6
CTRL_REG6_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.7
REFERENCE_A (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.8
STATUS_REG_A (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1.9
OUT_X_L_A (28h), OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.10
OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.11
OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.12
FIFO_CTRL_REG_A (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1.13
FIFO_SRC_REG_A (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.14
INT1_CFG_A (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1.15
INT1_SRC_A (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.16
INT1_THS_A (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.17
INT1_DURATION_A (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.18
INT2_CFG_A (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1.19
INT2_SRC_A (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1.20
INT2_THS_A (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.21
INT2_DURATION_A (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.1.22
CLICK_CFG_A (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.23
CLICK_SRC_A (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1.24
CLICK_THS_A (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.25
TIME_LIMIT_A (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.26
TIME_LATENCY_A (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.27
TIME_WINDOW_A (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Magnetic field sensing register description . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.1
CRA_REG_M (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.2
CRB_REG_M (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.3
MR_REG_M (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.2.4
OUT_X_H_M (03), OUT_X_L_M (04h) . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.5
OUT_Z_H_M (05), OUT_Z_L_M (06h) . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.6
OUT_Y_H_M (07), OUT_Y_L_M (08h) . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.7
SR_REG_M (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DocID018771 Rev 2
3/42
42
Contents
LSM303DLHC
7.2.8
IRx_REG_M (0Ah/0Bh/0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.2.9
TEMP_OUT_H_M (31h), TEMP_OUT_L_M (32h) . . . . . . . . . . . . . . . . 39
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/42
DocID018771 Rev 2
LSM303DLHC
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Sensor characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Accelerometer operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Transfer when master is writing multiple bytes to slave:. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Transfer when master is receiving (reading) one byte of data from slave: . . . . . . . . . . . . . 20
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 21
SAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
CTRL_REG1_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CTRL_REG1_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTRL_REG2_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTRL_REG3_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CTRL_REG4_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CTRL_REG4_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CTRL_REG5_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CTRL_REG6_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CTRL_REG6_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REFERENCE_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
REFERENCE_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STATUS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
STATUS_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIFO_CTRL_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIFO_CTRL_REG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FIFO_SRC_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
INT1_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
INT1_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INT1_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
INT1_THS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
INT1_THS_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
INT1_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
INT1_DURATION_A description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
DocID018771 Rev 2
5/42
42
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
6/42
LSM303DLHC
INT2_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
INT2_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
INT2_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
INT2_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
INT2_THS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
INT2_THS_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
INT2_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
INT2_DURATION_A description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CLICK_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CLICK_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CLICK_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
CLICK_THS_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TIME_LIMIT_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TIME_LIMIT_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TIME_LATENCY_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TIME_LATENCY_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
TIME_WINDOW_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
TIME_WINDOW_A description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CRA_REG_M register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CRA_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Data rate configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CRB_REG_M register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CRB_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Gain setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
MR_REG_M register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
MR_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Magnetic sensor operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SR_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
SR_REG_M description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IRA_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IRB_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
IRC_REG_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TEMP_OUT_H_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TEMP_OUT_L_M register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
TEMP_OUT resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID018771 Rev 2
LSM303DLHC
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
LSM303DLHC electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LGA-14: mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DocID018771 Rev 2
7/42
42
Block diagram and pin description
LSM303DLHC
1
Block diagram and pin description
1.1
Block diagram
Figure 1. Block diagram
Sensing Block
Sensing Interface
A/D
converter
Control
Logic
X+
Y+
CHARGE
AMPLIFIER
Z+
I (a)
+
MUX
SDA
Z-
SCL
DI
I2C
YX-
INT2
X+
CHARGE
AMPLIFIER
Y+
I (M)
INT1
Z+
+
MUX
ZYX-
INTERRUPT GEN.
REFERENCE
FIFO
OFFSET
CIRCUITS
TRIMMING
CIRCUITS
BUILT-IN
SET/RESET
CIRCUITS
CLOCK
TEMPERATURE
SENSOR
AM09236V1
8/42
DocID018771 Rev 2
LSM303DLHC
1.2
Block diagram and pin description
Pin description
Figure 2. Pin connections
Z
1
Y
X
DIRECTION OF
DETECTABLE
ACCELERATIONS
13
6
1
6
13
8
8
TOP VIEW
Z
1
Y
X
13
6
BOTTOM VIEW
DIRECTION OF
DETECTABLE
MAGNETIC FIELDS
8
TOP VIEW
AM09237V1
Table 2. Pin description
Pin#
Name
Function
1
Vdd_IO
2
SCL
Signal interface I2C serial clock (SCL)
3
SDA
Signal interface I2C serial data (SDA)
4
INT2
Inertial interrupt 2
5
INT1
Inertial interrupt 1
6
C1
7
GND
8
Reserved
9
DRDY
10
Reserved
Connect to GND
11
Reserved
Connect to GND
12
SETP
S/R capacitor connection (C2)
13
SETC
S/R capacitor connection (C2)
14
Vdd
Power supply for I/O pins
Reserved capacitor connection (C1)
0 V supply
Leave unconnected
Data ready
Power supply
DocID018771 Rev 2
9/42
42
Module specifications
LSM303DLHC
2
Module specifications
2.1
Sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted(a).
Table 3. Sensor characteristics
Symbol
LA_FS
M_FS
LA_So
M_GN
Parameter
Linear acceleration
measurement range(2)
Magnetic measurement range
Linear acceleration sensitivity
Magnetic gain setting
Test conditions
Min.
Typ.(1)
FS bit set to 00
±2
FS bit set to 01
±4
FS bit set to 10
±8
FS bit set to 11
±16
GN bits set to 001
±1.3
GN bits set to 010
±1.9
GN bits set to 011
±2.5
GN bits set to 100
±4.0
GN bits set to 101
±4.7
GN bits set to 110
±5.6
GN bits set to 111
±8.1
FS bit set to 00
1
FS bit set to 01
2
FS bit set to 10
4
FS bit set to 11
12
GN bits set to 001 (X,Y)
1100
GN bits set to 001 (Z)
980
GN bits set to 010 (X,Y)
855
GN bits set to 010 (Z)
760
GN bits set to 011 (X,Y)
670
GN bits set to 011 (Z)
600
GN bits set to 100 (X,Y)
450
GN bits set to 100 (Z)
400
GN bits set to 101 (X,Y)
400
GN bits set to 101 (Z)
355
GN bits set to 110 (X,Y)
330
GN bits set to 110 (Z)
295
GN bits set to 111
(2) (X,Y)
230
GN bits set to 111
(2) (Z)
205
Max.
Unit
g
gauss
mg/LSB
LSB/
gauss
a. The product is factory calibrated at 2.5 V. The operational power supply range is from 2.16 V to 3.6 V.
10/42
DocID018771 Rev 2
LSM303DLHC
Module specifications
Table 3. Sensor characteristics (continued)
Symbol
Parameter
Test conditions
Typ.(1)
Min.
Max.
Unit
LA_TCSo
Linear acceleration sensitivity
change vs. temperature
FS bit set to 00
±0.01
%/°C
LA_TyOff
Linear acceleration typical
Zero-g level offset
accuracy(3),(4)
FS bit set to 00
±60
mg
LA_TCOff
Linear acceleration Zero-g
level change vs. temperature
Max delta from 25 °C
±0.5
mg/°C
Acceleration noise density
FS bit set to 00, normal
mode(Table 8.), ODR bit
set to 1001
220
ug Hz
2
mgauss
±1
%FS/
gauss
LA_An
M_R
Magnetic resolution
Magnetic cross-axis sensitivity
Cross field = 0.5 gauss
H applied = ±3 gauss
M_EF
Maximum exposed field
No permanent effect on
sensor performance
M_DF
Magnetic disturbance field
Sensitivity starts to
degrade. Use S/R pulse to
restore sensitivity
M_CAS
Top
Operating temperature range
-40
1.
Typical specifications are not guaranteed.
2.
Verified by wafer level test and measurement of initial offset and sensitivity.
3.
Typical Zero-g level offset value after MSL3 preconditioning.
4.
Offset can be eliminated by enabling the built-in high-pass filter.
2.2
10000
gauss
20
gauss
+85
°C
Temperature sensor characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted (b).
Table 4. Temperature sensor characteristics
Symbol
Parameter
TSDr
Temperature sensor output
change vs. temperature
TODR
Temperature refresh rate
Top
Operating temperature range
Test condition
Min.
-40
Typ.(1)
Max.
Unit
8
LSB/°C(2)
ODR(3)
Hz
+85
°C
1. Typical specifications are not guaranteed.
2. 12-bit resolution.
3. For ODR configuration refer to Table 72.
b. The product is factory calibrated at 2.5 V.
DocID018771 Rev 2
11/42
42
Module specifications
2.3
LSM303DLHC
Electrical characteristics
@ Vdd = 2.5 V, T = 25 °C unless otherwise noted.
Table 5. Electrical characteristics
Symbol
Vdd
Vdd_IO
Idd
IddSL
Top
Parameter
Test
conditions
Supply voltage
2.16
Module power supply for I/O
1.71
Current consumption in normal
mode(2)
-
Current consumption in
sleep-mode(3)
Operating temperature range
-40
1. Typical specifications are not guaranteed.
2. Magnetic sensor setting ODR = 7.5 Hz, Accelerometer sensor ODR = 50 Hz.
3. Linear accelerometer in sleep-mode and magnetic sensor in power-down mode.
12/42
Min.
DocID018771 Rev 2
Typ.(1)
1.8
Max.
Unit
3.6
V
Vdd+0.1
110
μA
1
μA
+85
°C
LSM303DLHC
2.4
Module specifications
Communication interfaces characteristics
External pull-up resistors are required to support I2C standard and fast speed modes.
Sensor I2C - inter IC control interface
2.4.1
Subject to general operating conditions for Vdd and Top.
Table 6. I2C slave timing values
Symbol
I2C standard mode (1)
Parameter
f(SCL)
SCL clock frequency
I2C fast mode (1)
Min.
Max.
Min.
Max.
0
100
0
400
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0.01
3.45
ns
0.9
0.1Cb(2)
300
300
tr(SDA) tr(SCL) SDA and SCL rise time
1000
20 +
tf(SDA) tf(SCL) SDA and SCL fall time
300
20 + 0.1Cb(2)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition
setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
Bus free time between STOP
and START condition
tw(SP:SR)
kHz
μs
0.01
th(ST)
Unit
μs
ns
μs
1. Data based on standard I2C protocol requirement, not tested in production.
2. Cb = total capacitance of one bus line, in pF.
Figure 3. I2C slave timing diagram
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tf(SDA)
tsu(SDA)
tr(SDA)
START
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
tw(SCLL)
tw(SCLH)
tr(SCL)
tf(SCL)
AM09238V1
Note:
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports.
DocID018771 Rev 2
13/42
42
Module specifications
2.5
LSM303DLHC
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 7. Absolute maximum ratings
Symbol
Vdd
Vdd_IO
Vin
Ratings
Maximum value
Unit
Supply voltage
-0.3 to 4.8
V
I/O pins supply voltage
-0.3 to 4.8
V
-0.3 to Vdd_IO +0.3
V
3,000 for 0.5 ms
g
10,000 for 0.1 ms
g
3,000 for 0.5 ms
g
10,000 for 0.1 ms
g
Input voltage on any control pin (SCL, SDA)
APOW
Acceleration (any axis, powered, Vdd = 2.5 V)
AUNP
Acceleration (any axis, unpowered)
TOP
Operating temperature range
-40 to +85
°C
TSTG
Storage temperature range
-40 to +125
°C
ESD
Electrostatic discharge protection
2 (HBM)
kV
This device is sensitive to mechanical shock, improper handling can cause
permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can
cause permanent damage to the part.
14/42
DocID018771 Rev 2
LSM303DLHC
Module specifications
2.6
Terminology
2.6.1
Linear acceleration sensitivity
Linear acceleration sensitivity describes the gain of the accelerometer sensor and can be
determined by applying 1 g acceleration to it. As the sensor can measure DC accelerations,
this can be done easily by pointing the axis of interest towards the center of the Earth,
noting the output value, rotating the sensor by 180 degrees (pointing to the sky) and noting
the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting
the larger output value from the smaller one, and dividing the result by 2, leads to the actual
sensitivity of the sensor. This value changes very little over temperature and also very little
over time. The sensitivity tolerance describes the range of sensitivities of a large population
of sensors.
2.6.2
Zero-g level
Zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady-state on a horizontal surface
measures 0 g on the X axis and 0 g on the Y axis whereas the Z axis measures 1 g. The
output is ideally in the middle of the dynamic range of the sensor (content of OUT registers
00h, data expressed as two’s complement number). A deviation from the ideal value in this
case is called Zero-g offset. Offset is, to some extent, a result of stress to the MEMS sensor
and therefore the offset can slightly change after mounting the sensor onto a printed circuit
board or exposing it to extensive mechanical stress. Offset changes little over temperature,
see “Zero-g level change vs. temperature”. The Zero-g level tolerance (TyOff) describes the
standard deviation of the range of Zero-g levels of a population of sensors.
DocID018771 Rev 2
15/42
42
Functionality
3
LSM303DLHC
Functionality
The LSM303DLHC is a system-in-package featuring a 3D digital linear acceleration and 3D
digital magnetic field detection sensor.
The system includes specific sensing elements and an IC interface capable of measuring
both the linear acceleration and magnetic field applied to it and providing a signal to the
external world through an I2C serial interface with separated digital output.
The sensing system is manufactured using specialized micromachining processes, while
the IC interfaces are manufactured using CMOS technology that allows designing a
dedicated circuit which is trimmed to better match the sensing element characteristics.
The LSM303DLHC features two data-ready signals (RDY) which indicate when a new set of
measured acceleration data and magnetic data are available, therefore simplifying data
synchronization in the digital system that uses the device.
The LSM303DLHC may also be configured to generate a free-fall interrupt signal according
to a programmed acceleration event along the enabled axes.
Linear acceleration operating mode
The LSM303DLHC provides two different acceleration operating modes: “normal mode” and
“low-power mode”. While normal mode guarantees high resolution, low-power mode further
reduces current consumption.
Table 8 summarizes how to select the operating mode.
Table 8. Accelerometer operating mode selection
CTRL_REG1[3]
CTRL_REG4[3]
BW
(LPen bit)
(HR bit)
[Hz]
Turn-on time
[ms]
Low-power mode
1
0
ODR/2
1
Normal mode
0
1
ODR/9
7/ODR
Operating mode
3.1
Factory calibration
The IC interface is factory calibrated for linear acceleration sensitivity (LA_So), and linear
acceleration Zero-g level (LA_TyOff).
The trim values are stored inside the device in nonvolatile memory. Any time the device is
turned on, the trimming parameters are downloaded into the registers to be used during
normal operation. This allows the user to use the device without further calibration.
16/42
DocID018771 Rev 2
LSM303DLHC
4
Application hints
Application hints
Figure 4. LSM303DLHC electrical connections
Vdd_IO
Vdd
Vdd I2C bus
Z
Rpu
C3 = 10uF
1
Y
Rpu
10kOhm 10kOhm
X
C1=4.7uF
13
C4 = 100nF
SCL
SDA
8
INT2
C1
INT1
6
6
1
TOP VIEW
TOP VIEW
Z
8
1
Y
13
DRDY
X
13
6
C2=0.22uF
8
TOP VIEW
GND
Digital signal from/to signal controller.Signals levels are defined by proper selection of Vdd
AM09239V1
4.1
Capacitors
The C1 and C2 external capacitors should be low SR value ceramic type constructions (typ.
recommended value 200 mOhm). Reservoir capacitor C1 is nominally 4.7 μF in
capacitance, with the set/reset capacitor C2 nominally 0.22 F in capacitance.
The device core is supplied through the Vdd line. Power supply decoupling capacitors
(C4 = 100 nF ceramic, C3 = 10 μF Al) should be placed as near as possible to the supply
pin of the device (common design practice). All the voltage and ground supplies must be
present at the same time to have proper behavior of the IC (refer to Figure 4).
The functionality of the device and the measured acceleration/magnetic field data are
selectable and accessible through the I2C interface.
The functions, the threshold, and the timing of the two interrupt pins (INT1 and INT2) can be
completely programmed by the user through the I2C interface.
4.2
Pull-up resistors
Pull-up resistors (recommended value 10 kOhm) are placed on the two I2C bus lines.
DocID018771 Rev 2
17/42
42
Application hints
4.3
LSM303DLHC
Digital interface power supply
This digital interface, dedicated to the linear acceleration and to the magnetic field signal, is
capable of operating with a standard power supply (Vdd) or using a dedicated power supply
(Vdd_IO).
4.4
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS, and “Green” standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Leave “Pin 1 Indicator” unconnected during soldering.
Land pattern and soldering recommendations are available at www.st.com/mems.
4.5
High-current wiring effects
High current in the wiring and printed circuit traces can be culprits in causing errors in
magnetic field measurements for compassing.
Conductor-generated magnetic fields add to the Earth’s magnetic field, causing errors in
compass-heading computation.
Keep currents higher than 10 mA a few millimeters further away from the sensor IC.
18/42
DocID018771 Rev 2
LSM303DLHC
5
Digital interfaces
Digital interfaces
The registers embedded inside the LSM303DLHC are accessible through two separate I2C
serial interfaces, one for the accelerometer core and one for the magnetometer core.
Table 9. Serial interface pin description
Pin name
5.1
Pin description
SCL
I2
SDA
I2C serial data (SDA)
C serial clock (SCL)
I2C serial interface
The LSM303DLHC I2C is a bus slave. The I2C is employed to write the data into the
registers whose content can also be read back.
The relevant I2C terminology is given in the table below.
Table 10. Serial interface pin description
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals, and terminates a
transfer
Slave
The device addressed by the master
There are two signals associated with the I2C bus, the serial clock line (SCL) and the serial
data line (SDA). The latter is a bidirectional line used for sending and receiving the data
to/from the interface.
DocID018771 Rev 2
19/42
42
Digital interfaces
5.1.1
LSM303DLHC
I2C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a high-to-low transition on the data line while the SCL line is held high. After this
has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the start condition contains the address of the slave in the first 7 bits and bit
8 tells whether the master is receiving data from the slave or transmitting data to the slave.
When an address is sent, each device in the system compares the first seven bits after a
start condition with its address. If they match, the device considers itself addressed by the
master.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line low so that it
remains stable low during the high period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I2C embedded inside the LSM303DLHC behaves like a slave device and the following
protocol must be adhered to. After the START condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted; the
7 LSBs represent the actual register address while the MSB enables address autoincrement. If the MSB of the SUB field is ‘1’, the SUB (register address) is automatically
increased to allow multiple data Read/Write.
Table 11. Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
Slave
SAK
DATA
SAK
SP
SAK
Table 12. Transfer when master is writing multiple bytes to slave:
Master
ST
SAD + W
Slave
SUB
SAK
DATA
SAK
DATA
SAK
SP
SAK
Table 13. Transfer when master is receiving (reading) one byte of data from slave:
Master
Slave
ST
SAD + W
SUB
SAK
SR
SAK
SAD + R
NMAK
SAK
SP
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the most significant bit
(MSB) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line SCL low to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real-time function) the data line must be left high by
the slave. The master can then abort the transfer. A low-to-high transition on the SDA line
while the SCL line is high is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
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5.1.2
Digital interfaces
Linear acceleration digital interface
For linear acceleration the default (factory) 7-bit slave address is 0011001b.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write)
the master transmits to the slave with the direction unchanged. Table 14 explains how the
read/write bit pattern is composed, listing all the possible configurations.
Table 14. SAD+Read/Write patterns
Command
SAD[7:1]
R/W
SAD+R/W
Read
0011001
1
00110011 (33h)
Write
0011001
0
00110010 (32h)
In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of the first register to be read.
In the presented communication format, MAK is master acknowledge and NMAK is no
master acknowledge.
Table 15. Transfer when master is receiving (reading) multiple bytes of data from slave
Master
Slave
ST
SAD
+W
SUB
SAK
SR
SAK
SAD
+R
MAK
SAK DATA
DocID018771 Rev 2
MAK
DATA
NMAK SP
DATA
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Digital interfaces
5.1.3
LSM303DLHC
Magnetic field digital interface
For magnetic sensors the default (factory) 7-bit slave address is 0011110xb.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (read), a repeated
START (SR) condition must be issued after the two sub-address bytes. If the bit is ‘0’ (write)
the master transmits to the slave with the direction unchanged. Table 16 explains how the
SAD is composed.
Table 16. SAD
Command
SAD[6:0]
R/W
SAD+R/W
Read
0011110
1
00111101 (3Dh)
Write
0011110
0
00111100 (3Ch)
Magnetic signal interface reading/writing
The interface uses an address pointer to indicate which register location is to be read from
or written to. These pointer locations are sent from the master to this slave device and
succeed the 7-bit address plus 1 bit Read/Write identifier.
To minimize the communication between the master and magnetic digital interface of
LSM303DLHC, the address pointer updates automatically without master intervention.
This automatic address pointer update has two additional features. First, when address 12
or higher is accessed, the pointer updates to address 00, and secondly, when address 08 is
reached, the pointer rolls back to address 03. Logically, the address pointer operation
functions as shown below.
If (address pointer = 08) then the address pointer = 03
Or else, if (address pointer >= 12) then the address pointer = 0
Or else, (address pointer) = (address pointer) + 1
The address pointer value itself cannot be read via the I2C bus.
Any attempt to read an invalid address location returns 0, and any write to an invalid
address location, or an undefined bit within a valid address location, is ignored by this
device.
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6
Register mapping
Register mapping
Table 17 provides a listing of the 8-bit registers embedded in the device and the
corresponding addresses:
Table 17. Register address map
Name
Slave
address
Register address
Type
Default
Comment
--
--
Reserved
Hex
Binary
00 - 1F
Reserved (do not modify)
Table 14
CTRL_REG1_A
Table 14
rw
20
010 0000
00000111
CTRL_REG2_A
Table 14
rw
21
010 0001
00000000
CTRL_REG3_A
Table 14
rw
22
010 0010
00000000
CTRL_REG4_A
Table 14
rw
23
010 0011
00000000
CTRL_REG5_A
Table 14
rw
24
010 0100
00000000
CTRL_REG6_A
Table 14
rw
25
010 0101
00000000
REFERENCE_A
Table 14
rw
26
010 0110
00000000
STATUS_REG_A
Table 14
r
27
010 0111
00000000
OUT_X_L_A
Table 14
r
28
010 1000
output
OUT_X_H_A
Table 14
r
29
010 1001
output
OUT_Y_L_A
Table 14
r
2A
010 1010
output
OUT_Y_H_A
Table 14
r
2B
010 1011
output
OUT_Z_L_A
Table 14
r
2C
010 1100
output
OUT_Z_H_A
Table 14
r
2D
010 1101
output
FIFO_CTRL_REG_A
Table 14
rw
2E
010 1110
00000000
FIFO_SRC_REG_A
Table 14
r
2F
010 1111
INT1_CFG_A
Table 14
rw
30
011 0000
00000000
INT1_SRC_A
Table 14
r
31
011 0001
00000000
INT1_THS_A
Table 14
rw
32
011 0010
00000000
INT1_DURATION_A
Table 14
rw
33
011 0011
00000000
INT2_CFG_A
Table 14
rw
34
011 0100
00000000
INT2_SRC_A
Table 14
r
35
011 0101
00000000
INT2_THS_A
Table 14
rw
36
011 0110
00000000
INT2_DURATION_A
Table 14
rw
37
011 0111
00000000
CLICK_CFG_A
Table 14
rw
38
011 1000
00000000
CLICK_SRC_A
Table 14
rw
39
011 1001
00000000
CLICK_THS_A
Table 14
rw
3A
011 1010
00000000
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42
Register mapping
LSM303DLHC
Table 17. Register address map (continued)
Register address
Slave
address
Type
TIME_LIMIT_A
Table 14
TIME_LATENCY_A
Name
Default
Hex
Binary
rw
3B
011 1011
00000000
Table 14
rw
3C
011 1100
00000000
TIME_WINDOW_A
Table 14
rw
3D
011 1101
00000000
Reserved (do not modify)
Table 14
3E-3F
--
--
CRA_REG_M
Table 16
rw
00
00000000
0001000
CRB_REG_M
Table 16
rw
01
00000001
0010000
MR_REG_M
Table 16
rw
02
00000010
00000011
OUT_X_H_M
Table 16
r
03
00000011
output
OUT_X_L_M
Table 16
r
04
00000100
output
OUT_Z_H_M
Table 16
r
05
00000101
output
OUT_Z_L_M
Table 16
r
06
00000110
output
OUT_Y_H_M
Table 16
r
07
00000111
output
OUT_Y_L_M
Table 16
r
08
00001000
output
SR_REG_M
Table 16
r
09
00001001
00000000
IRA_REG_M
Table 16
r
0A
00001010
01001000
IRB_REG_M
Table 16
r
0B
00001011
00110100
IRC_REG_M
Table 16
r
0C
00001100
00110011
Reserved (do not modify)
Table 16
0D-30
--
--
TEMP_OUT_H_M
Table 16
31
00000000
output
TEMP_OUT_L_M
Table 16
32
00000000
output
Reserved (do not modify)
Table 16
33-3A
--
--
Comment
Reserved
Reserved
Reserved
Registers marked as “Reserved” must not be changed. Writing to these registers may cause
permanent damage to the device.
The content of the registers that are loaded at boot should not be changed. They contain the
factory calibrated values. Their content is automatically restored when the device is
powered up.
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7
Register description
Register description
The device contains a set of registers which are used to control its behavior and to retrieve
acceleration data. The register address, made up of 7 bits, is used to identify them and to
write the data through the serial interface.
7.1
Linear acceleration register description
7.1.1
CTRL_REG1_A (20h)
Table 18. CTRL_REG1_A register
ODR3
ODR2
ODR1
ODR0
LPen
Zen
Yen
Xen
Table 19. CTRL_REG1_A description
ODR[3:0]
Data rate selection. Default value: 0000
(0000: power-down, others: refer to Table 20)
Low-power mode enable. Default value: 0
(0: normal mode, 1: low-power mode)
LPen
Zen
Z-axis enable. Default value: 1
(0: Z-axis disabled, 1: Z-axis enabled)
Yen
Y-axis enable. Default value: 1
(0: Y-axis disabled, 1: Y-axis enabled)
Xen
X-axis enable. Default value: 1
(0: X-axis disabled, 1: X-axis enabled)
ODR[3:0] is used to set the power mode and ODR selection. In the following table bit
selection of ODR [3:0] for all frequencies is shown.
Table 20. Data rate configuration
ODR3
ODR2
ODR1
ODR0
Power mode and ODR selection
0
0
0
0
Power-down mode
0
0
0
1
Normal / low-power mode (1 Hz)
0
0
1
0
Normal / low-power mode (10 Hz)
0
0
1
1
Normal / low-power mode (25 Hz)
0
1
0
0
Normal / low-power mode (50 Hz)
0
1
0
1
Normal / low-power mode (100 Hz)
0
1
1
0
Normal / low-power mode (200 Hz)
0
1
1
1
Normal / low-power mode (400 Hz)
1
0
0
0
Low-power mode (1.620 kHz)
1
0
0
1
Normal (1.344 kHz) / low-power mode (5.376 kHz)
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42
Register description
7.1.2
LSM303DLHC
CTRL_REG2_A (21h)
Table 21. CTRL_REG2_A register
HPM1
HPM0
HPCF2
HPCF1
FDS
HPCLICK
HPIS2
HPIS1
Table 22. CTRL_REG2_A description
HPM[1:0]
High-pass filter mode selection. Default value: 00
(refer to Table 23)
HPCF[2:1]
High-pass filter cutoff frequency selection
FDS
Filtered data selection. Default value: 0
(0: internal filter bypassed, 1: data from internal filter sent to output register and
FIFO)
HPCLICK
High-pass filter enabled for click function
(0: filter bypassed, 1: filter enabled)
HPIS2
High-pass filter enabled for AOI function on Interrupt 2
(0: filter bypassed, 1: filter enabled)
HPIS1
High-pass filter enabled for AOI function on Interrupt 1
(0: filter bypassed, 1: filter enabled)
Table 23. High-pass filter mode configuration
HPM1
7.1.3
HPM0
High-pass filter mode
0
0
Normal mode (reset reading HP_RESET_FILTER)
0
1
Reference signal for filtering
1
0
Normal mode
1
1
Autoreset on interrupt event
CTRL_REG3_A (22h)
Table 24. CTRL_REG3_A register
I1_CLICK
I1_AOI1
I1_AOI2
I1_DRDY1
I1_DRDY2
I1_WTM
Table 25. CTRL_REG3_A description
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I1_CLICK
CLICK interrupt on INT1. Default value 0
(0: disable, 1: enable)
I1_AOI1
AOI1 interrupt on INT1. Default value 0
(0: disable, 1: enable)
I1_AOI2
AOI2 interrupt on INT1. Default value 0
(0: disable, 1: enable)
DocID018771 Rev 2
I1_OVERRUN
--
LSM303DLHC
Register description
Table 25. CTRL_REG3_A description (continued)
7.1.4
I1_DRDY1
DRDY1 interrupt on INT1. Default value 0
(0: disable, 1: enable)
I1_DRDY2
DRDY2 interrupt on INT1. Default value 0
(0: disable, 1: enable)
I1_WTM
FIFO watermark interrupt on INT1. Default value 0
(0: disable, 1: enable)
I1_OVERRUN
FIFO overrun interrupt on INT1. Default value 0
(0: disable, 1: enable)
CTRL_REG4_A (23h)
Table 26. CTRL_REG4_A register
BDU
BLE
FS1
FS0
HR
0(1)
0(1)
SIM
1. This bit must be set to ‘0’ for correct operation of the device.
Table 27. CTRL_REG4_A description
7.1.5
BDU
Block data update. Default value: 0
(0: continuous update, 1: output registers not updated until MSB and LSB
have been read
BLE
Big/little endian data selection. Default value 0.
(0: data LSB @ lower address, 1: data MSB @ lower address)
FS[1:0]
Full-scale selection. Default value: 00
(00: ±2 g, 01: ±4 g, 10: ±8 g, 11: ±16 g)
HR
High-resolution output mode: Default value: 0
(0: high-resolution disable, 1: high-resolution enable)
SIM
SPI serial interface mode selection. Default value: 0
(0: 4-wire interface, 1: 3-wire interface).
CTRL_REG5_A (24h)
Table 28. CTRL_REG5_A register
BOOT
FIFO_EN
--
--
LIR_INT1
D4D_INT1
LIR_INT2
D4D_INT2
Table 29. CTRL_REG5_A description
BOOT
Reboot memory content. Default value: 0
(0: normal mode, 1: reboot memory content)
FIFO_EN
FIFO enable. Default value: 0
(0: FIFO disable, 1: FIFO enable)
LIR_INT1
Latch interrupt request on INT1_SRC register, with INT1_SRC register cleared by
reading INT1_SRC itself. Default value: 0.
(0: interrupt request not latched, 1: interrupt request latched)
D4D_INT1
4D enable: 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set to 1.
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42
Register description
LSM303DLHC
Table 29. CTRL_REG5_A description (continued)
7.1.6
LIR_INT2
Latch interrupt request on INT2_SRC register, with INT2_SRC register cleared by
reading INT2_SRC itself. Default value: 0.
(0: interrupt request not latched, 1: interrupt request latched)
D4D_INT2
4D enable: 4D detection is enabled on INT2 when 6D bit on INT2_CFG is set to 1.
CTRL_REG6_A (25h)
Table 30. CTRL_REG6_A register
I2_CLICKen
I2_INT1
I2_INT2
BOOT_I1
P2_ACT
--
H_LACTIVE
Table 31. CTRL_REG6_A description
7.1.7
I2_CLICKen
CLICK interrupt on PAD2. Default value 0.
(0: disable, 1: enable)
I2_INT1
Interrupt 1 on PAD2. Default value 0.
(0: disable, 1: enable)
I2_INT2
Interrupt 2 on PAD2. Default value 0.
(0: disable, 1: enable)
BOOT_I1
Reboot memory content on PAD2. Default value: 0
(0: disable, 1: enable)
P2_ACT
Active function status on PAD2. Default value 0
(0: disable, 1: enable)
H_LACTIVE
Interrupt active high, low. Default value 0.
(0: active high, 1: active low)
REFERENCE_A (26h)
Table 32. REFERENCE_A register
Ref7
Ref6
Ref5
Ref4
Ref3
Ref2
Ref1
Ref0
Table 33. REFERENCE_A register description
Ref[7:0]
7.1.8
Reference value for interrupt generation. Default value: 0000 0000
STATUS_REG_A (27h)
Table 34. STATUS_A register
ZYXOR
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ZOR
YOR
XOR
ZYXDA
DocID018771 Rev 2
ZDA
YDA
XDA
--
LSM303DLHC
Register description
Table 35. STATUS_A register description
7.1.9
ZYXOR
X-, Y-, and Z-axis data overrun. Default value: 0
(0: no overrun has occurred, 1: a new set of data has overwritten the previous data)
ZOR
Z-axis data overrun. Default value: 0
(0: no overrun has occurred, 1: new data for the Z-axis has overwritten the previous data)
YOR
Y-axis data overrun. Default value: 0
(0: no overrun has occurred,
1: new data for the Y-axis has overwritten the previous data)
XOR
X-axis data overrun. Default value: 0
(0: no overrun has occurred,
1: new data for the X-axis has overwritten the previous data)
ZYXDA
X-, Y-, and Z-axis new data available. Default value: 0
(0: a new set of data is not yet available, 1: a new set of data is available)
ZDA
Z-axis new data available. Default value: 0
(0: new data for the Z-axis is not yet available,
1: new data for the Z-axis is available)
YDA
Y-axis new data available. Default value: 0
(0: new data for the Y-axis is not yet available,
1: new data for the Y-axis is available)
XDA
X-axis new data available. Default value: 0
(0: new data for the X-axis is not yet available,
1: new data for the X-axis is available)
OUT_X_L_A (28h), OUT_X_H_A (29h)
X-axis acceleration data. The value is expressed in two’s complement.
7.1.10
OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh)
Y-axis acceleration data. The value is expressed in two’s complement.
7.1.11
OUT_Z_L_A (2Ch), OUT_Z_H_A (2Dh)
Z-axis acceleration data. The value is expressed in two’s complement.
7.1.12
FIFO_CTRL_REG_A (2Eh)
Table 36. FIFO_CTRL_REG_A register
FM1
FM0
TR
FTH4
FTH3
FTH2
FTH1
FTH0
Table 37. FIFO_CTRL_REG_A description
FM[1:0]
FIFO mode selection. Default value: 00 (see Table 38)
TR
Trigger selection. Default value: 0
0: trigger event linked to trigger signal on INT1
1: trigger event linked to trigger signal on INT2
FTH[4:0]
Default value: 00000
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42
Register description
LSM303DLHC
Table 38. FIFO mode configuration
FM1
7.1.13
FM0
FIFO mode configuration
0
0
Bypass mode
0
1
FIFO mode
1
0
Stream mode
1
1
Trigger mode
FIFO_SRC_REG_A (2Fh)
Table 39. FIFO_SRC_REG_A register
WTM
7.1.14
OVRN_FIFO
EMPTY
FSS4
FSS3
FSS2
FSS1
FSS0
INT1_CFG_A (30h)
Table 40. INT1_CFG_A register
AOI
6D
ZHIE/
ZUPE
ZLIE/
ZDOWNE
YHIE/
YUPE
YLIE/
YDOWNE
XHIE/
XUPE
XLIE/
XDOWNE
Table 41. INT1_CFG_A description
AOI
AND/OR combination of interrupt events. Default value: 0 (refer to Table 42)
6D
6-direction detection function enabled. Default value: 0 (refer to Table 42)
ZHIE/
ZUPE
Enable interrupt generation on Z high event or on direction recognition. Default
value: 0 (0: disable interrupt request, 1: enable interrupt request)
ZLIE/
ZDOWNE
Enable interrupt generation on Z low event or on direction recognition. Default
value: 0 (0: disable interrupt request, 1: enable interrupt request)
YHIE/
YUPE
Enable interrupt generation on Y high event or on direction recognition. Default
value: 0 (0: disable interrupt request, 1: enable interrupt request.)
YLIE/
YDOWNE
Enable interrupt generation on Y low event or on direction recognition. Default
value: 0 (0: disable interrupt request, 1: enable interrupt request.)
XHIE/
XUPE
Enable interrupt generation on X high event or on direction recognition. Default
value: 0 (0: disable interrupt request, 1: enable interrupt request.)
XLIE/XDOWNE Enable interrupt generation on X low event or on direction recognition. Default
value: 0 (0: disable interrupt request, 1: enable interrupt request.)
Content of this register is loaded at boot. Write operation at this address is possible only
after system boot.
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LSM303DLHC
Register description
Table 42. Interrupt mode
AOI
6D
Interrupt mode
0
0
OR combination of interrupt events
0
1
6-direction movement recognition
1
0
AND combination of interrupt events
1
1
6-direction position recognition
Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation
moves from an unknown zone to a known zone. The interrupt signal remains for a duration
ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is
inside a known zone. The interrupt signal stays until the orientation is inside the zone.
7.1.15
INT1_SRC_A (31h)
Table 43. INT1_SRC_A register
0(1)
IA
ZH
ZL
YH
YL
XH
XL
1. This bit must be set to ‘0’ for correct working of the device.
Table 44. INT1_SRC_A description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated, 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt, 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 1 source register. Read-only register.
Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1
pin) and allows the refresh of data in the INT1_SRC register if the latched option was
chosen.
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42
Register description
7.1.16
LSM303DLHC
INT1_THS_A (32h)
Table 45. INT1_THS_A register
0
(1)
THS6
THS5
THS4
THS3
THS2
THS1
THS0
D1
D0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 46. INT1_THS_A description
THS[6:0]
7.1.17
Interrupt 1 threshold. Default value: 000 0000
INT1_DURATION_A (33h)
Table 47. INT1_DURATION_A register
0(1)
D6
D5
D4
D3
D2
1. This bit must be set to ‘0’ for correct operation of the device.
Table 48. INT1_DURATION_A description
D[6:0]
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. Duration
steps and maximum values depend on the ODR chosen.
7.1.18
INT2_CFG_A (34h)
Table 49. INT2_CFG_A register
AOI
6D
ZHIE
ZLIE
YHIE
YLIE
XHIE
XLIE
Table 50. INT2_CFG_A description
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AOI
AND/OR combination of interrupt events. Default value: 0
(see Table 51)
6D
6-direction detection function enabled. Default value: 0 (refer to Table 51)
ZHIE
Enable interrupt generation on Z high event. Default value: 0
(0: disable interrupt request,
1: enable interrupt request on measured accel. value higher than preset threshold)
ZLIE
Enable interrupt generation on Z low event. Default value: 0
(0: disable interrupt request,
1: enable interrupt request on measured accel. value lower than preset threshold)
YHIE
Enable interrupt generation on Y high event. Default value: 0
(0: disable interrupt request,
1: enable interrupt request on measured accel. value higher than preset threshold)
DocID018771 Rev 2
LSM303DLHC
Register description
Table 50. INT2_CFG_A description (continued)
YLIE
Enable interrupt generation on Y low event. Default value: 0
(0: disable interrupt request,
1: enable interrupt request on measured accel. value lower than preset threshold)
XHIE
Enable interrupt generation on X high event. Default value: 0
(0: disable interrupt request,
1: enable interrupt request on measured accel. value higher than preset threshold)
XLIE
Enable interrupt generation on X low event. Default value: 0
(0: disable interrupt request,
1: enable interrupt request on measured accel. value lower than preset threshold)
Table 51. Interrupt mode
AOI
6D
Interrupt mode
0
0
OR combination of interrupt events
0
1
6-direction movement recognition
1
0
AND combination of interrupt events
1
1
6-direction position recognition
Difference between AOI-6D = ‘01’ and AOI-6D = ‘11’.
AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation
moves from an unknown zone to a known zone. The interrupt signal remains for a duration
ODR.
AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is
inside a known zone. The interrupt signal remains until the orientation is inside the zone.
7.1.19
INT2_SRC_A (35h)
Table 52. INT2_SRC_A register
0(1)
IA
ZH
ZL
YH
YL
XH
XL
1. This bit must be set to ‘0’ for correct operation of the device.
Table 53. INT2_SRC_A description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated, 1: one or more interrupts have been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt, 1: Z low event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
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42
Register description
LSM303DLHC
Table 53. INT2_SRC_A description (continued)
YL
Y low. Default value: 0
(0: no interrupt, 1: Y low event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: X high event has occurred)
XL
X Low. Default value: 0
(0: no interrupt, 1: X low event has occurred)
Interrupt 2 source register. Read-only register.
Reading at this address clears the INT2_SRC IA bit (and the interrupt signal on the INT2
pin) and allows the refresh of data in the INT2_SRC register if the latched option was
chosen.
7.1.20
INT2_THS_A (36h)
Table 54. INT2_THS_A register
0(1)
THS6
THS5
THS4
THS3
THS2
THS1
THS0
D1
D0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 55. INT2_THS_A description
THS[6:0]
7.1.21
Interrupt 2 threshold. Default value: 000 0000
INT2_DURATION_A (37h)
Table 56. INT2_DURATION_A register
0(1)
D6
D5
D4
D3
D2
1. This bit must be set to ‘0’ for correct operation of the device.
Table 57. INT2_DURATION_A description
D[6:0]
Duration value. Default value: 000 0000
D6 - D0 bits set the minimum duration of the Interrupt 2 event to be recognized. Duration
time steps and maximum values depend on the ODR chosen.
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7.1.22
Register description
CLICK_CFG_A (38h)
Table 58. CLICK_CFG_A register
--
--
ZD
ZS
YD
YS
XD
XS
Table 59. CLICK_CFG_A description
7.1.23
ZD
Enable interrupt double-click on Z-axis. Default value: 0
(0: disable interrupt request, 1: enable interrupt request on measured accel. value
higher than preset threshold)
ZS
Enable interrupt single-click on Z-axis. Default value: 0
(0: disable interrupt request, 1: enable interrupt request on measured accel. value
higher than preset threshold)
YD
Enable interrupt double-click on Y-axis. Default value: 0
(0: disable interrupt request, 1: enable interrupt request on measured accel. value
higher than preset threshold)
YS
Enable interrupt single-click on Y-axis. Default value: 0
(0: disable interrupt request, 1: enable interrupt request on measured accel. value
higher than preset threshold)
XD
Enable interrupt double-click on X-axis. Default value: 0
(0: disable interrupt request, 1: enable interrupt request on measured accel. value
higher than preset threshold)
XS
Enable interrupt single-click on X-axis. Default value: 0
(0: disable interrupt request, 1: enable interrupt request on measured accel. value
higher than preset threshold)
CLICK_SRC_A (39h)
Table 60. CLICK_SRC_A register
--
IA
DCLICK
SCLICK
Sign
Z
Y
X
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated, 1: one or more interrupts have been generated)
DCLICK
Double-click enable. Default value: 0 (0: double-click detection disable, 1: double-click
detection enable)
SCLICK
Single-click enable. Default value: 0 (0: Single-click detection disable, 1: single-click
detection enable)
Sign
Click sign. 0: positive detection, 1: negative detection
Z
Z-click detection. Default value: 0
(0: no interrupt, 1: Z high event has occurred)
Y
Y-click detection. Default value: 0
(0: no interrupt, 1: Y high event has occurred)
X
X-click detection. Default value: 0
(0: no interrupt, 1: X high event has occurred)
Table 61. CLICK_SRC_A description
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Register description
7.1.24
LSM303DLHC
CLICK_THS_A (3Ah)
Table 62. CLICK_THS_A register
--
Ths6
Ths5
Ths4
Ths3
Ths2
Ths1
Ths0
Table 63. CLICK_SRC_A description
Ths[6:0]
Click threshold. Default value: 000 0000
1 LSB = full-scale / 128. Ths6 through Ths0 define the threshold which is used by the
system to start the click-detection procedure. The threshold value is expressed over 7 bits
as an unsigned number.
7.1.25
TIME_LIMIT_A (3Bh)
Table 64. TIME_LIMIT_A register
--
TLI6
TLI5
TLI4
TLI3
TLI2
TLI1
TLI0
Table 65. TIME_LIMIT_A description
TLI[6:0]
Click time limit. Default value: 000 0000
1 LSB = 1/ODR. TLI6 through TLI0 define the maximum time interval that can elapse
between the start of the click-detection procedure (the acceleration on the selected channel
exceeds the programmed threshold) and when the acceleration falls below the threshold.
7.1.26
TIME_LATENCY_A (3Ch)
Table 66. TIME_LATENCY_A register
TLA7
TLA6
TLA5
TLA4
TLA3
TLA2
TLA1
TLA0
Table 67. TIME_LATENCY_A description
TLA[7:0]
Double-click time latency. Default value: 0000 0000
1 LSB = 1/ODR. TLA7 through TLA0 define the time interval that starts after the first click
detection where the click-detection procedure is disabled, in cases where the device is
configured for double-click detection.
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7.1.27
Register description
TIME_WINDOW_A (3Dh)
Table 68. TIME_WINDOW_A register
TW7
TW6
TW5
TW4
TW3
TW2
TW1
TW0
Table 69. TIME_WINDOW_A description
TW[7:0]
Double-click time window
1 LSB = 1/ODR. TW7 through TW0 define the maximum interval of time that can elapse
after the end of the latency interval in which the click detection procedure can start, in cases
where the device is configured for double-click detection.
7.2
Magnetic field sensing register description
7.2.1
CRA_REG_M (00h)
Table 70. CRA_REG_M register
TEMP_EN
0(1)
0(1)
DO2
DO1
DO0
0(1)
0(1)
1. This bit must be set to ‘0’ for correct operation of the device.
Table 71. CRA_REG_M description
TEMP _EN
Temperature sensor enable.
0: temperature sensor disabled (default), 1: temperature sensor enabled
DO[2:0]
Data output rate bits. These bits set the rate at which data is written to all three data
output registers (refer to Table 72). Default value: 100
Table 72. Data rate configurations
DO2
DO1
DO0
Minimum data output rate (Hz)
0
0
0
0.75
0
0
1
1.5
0
1
0
3.0
0
1
1
7.5
1
0
0
15
1
0
1
30
1
1
0
75
1
1
1
220
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Register description
7.2.2
LSM303DLHC
CRB_REG_M (01h)
Table 73. CRB_REG_M register
GN2
GN1
0(1)
GN0
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to ‘0’ for correct operation of the device.
Table 74. CRB_REG_M description
Gain configuration bits. The gain configuration is common for all channels (refer to
Table 75)
GN[2:0]
Table 75. Gain setting
7.2.3
GN2
GN1
GN0
Sensor input
field range
[Gauss]
Gain X, Y, and Z
Gain Z
[LSB/Gauss]
[LSB/Gauss]
0
0
1
±1.3
1100
980
0
1
0
±1.9
855
760
0
1
1
±2.5
670
600
1
0
0
±4.0
450
400
1
0
1
±4.7
400
355
1
1
0
±5.6
330
295
1
1
1
±8.1
230
205
Output range
0xF800–0x07FF
(-2048 to +2047)
MR_REG_M (02h)
Table 76. MR_REG_M register
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
MD1
MD0
1. This bit must be set to ‘0’ for correct operation of the device.
Table 77. MR_REG_M description
Mode select bits. These bits select the operation mode of this device (refer to
Table 78)
MD[1:0]
Table 78. Magnetic sensor operating mode
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MD1
MD0
Mode
0
0
Continuous-conversion mode
0
1
Single-conversion mode
1
0
Sleep mode. Device is placed in sleep mode
1
1
Sleep mode. Device is placed in sleep mode
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LSM303DLHC
7.2.4
Register description
OUT_X_H_M (03), OUT_X_L_M (04h)
X-axis magnetic field data. The value is expressed as two’s complement.
7.2.5
OUT_Z_H_M (05), OUT_Z_L_M (06h)
Z-axis magnetic field data. The value is expressed as two’s complement.
7.2.6
OUT_Y_H_M (07), OUT_Y_L_M (08h)
Y-axis magnetic field data. The value is expressed as two’s complement.
7.2.7
SR_REG_M (09h)
Table 79. SR_REG_M register
--
--
--
--
--
--
LOCK
DRDY
Table 80. SR_REG_M description
7.2.8
LOCK
Data output register lock. Once a new set of measurements is available, this bit is
set when the first magnetic file data register has been read.
DRDY
Data-ready bit. This bit is when a new set of measurements is available.
IRx_REG_M (0Ah/0Bh/0Ch)
Table 81. IRA_REG_M register
0
1
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
1
1
TEMP5
TEMP4
--
--
Table 82. IRB_REG_M register
1
0
Table 83. IRC_REG_M register
7.2.9
1
0
TEMP_OUT_H_M (31h), TEMP_OUT_L_M (32h)
Table 84. TEMP_OUT_H_M register
TEMP11
TEMP10
TEMP9
TEMP8
TEMP7
TEMP6
Table 85. TEMP_OUT_L_M register
TEMP3
TEMP2
TEMP1
TEMP0
--
--
Table 86. TEMP_OUT resolution
TEMP[11:0]
Temperature data (8 LSB/deg - 12-bit resolution). The value is expressed as
two’s complement.
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42
Package information
8
LSM303DLHC
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 5. LGA-14: mechanical data and package dimensions
Dimens ions
R ef.
mm
Min.
Typ.
Max.
A1
Outline and
mec hanic al data
1
A2
0.785
A3
0.16
0.2
0.24
D1
2.85
3
3.15
E1
4.85
5
5.15
N1
0.8
L1
4
T1
0.8
T2
0.5
M
0.1
k
0.05
LGA 3x5x1 14L
Land Grid Array Package
8265271_A
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9
Revision history
Revision history
Table 87. Document revision history
Date
Revision
Changes
21-Apr-2011
1
Initial release
05-Nov-2013
2
Document status promoted from preliminary to production data
Added ESD to Table 7
Minor textual updates throughout document
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LSM303DLHC
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