LSM330DLTR

LSM330DL Linear sensor module 3D accelerometer sensor and 3D gyroscope sensor Preliminary data Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Analog supply voltage 2.4 V to 3.6 V Digital supply voltage I/Os, 1.8V Low-power mode Power-down mode 3 independent acceleration channels and 3 angular rate channels ±2g/±4g/±8g/±16g dynamic, selectable fullscale acceleration range ±250/±500/±2000 dps dynamic, selectable fullscale angular rate SPI/I2C serial interface (16-bit data output) Programmable interrupt generator for free-fall and motion detection ECOPACK®, RoHS, and “Green” compliant LLGA 28L 7.5 x 4.4 x 1.1 mm ST’s family of modules leverages a robust and mature manufacturing process already used for the production of micromachined accelerometers. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are based on CMOS technology that allows designing a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM330DL has a dynamic, user-selectable full-scale acceleration range of ±2g/±4g/±8g/±16g and an angular rate of ±250/±500/±2000 deg/sec. The accelerometer and gyroscope sensors can be either activated or put in low-power / powerdown mode separately for power-saving optimized applications. The LSM330DL is available in a plastic land grid array (LGA) package. Several years ago ST successfully pioneered the use of this package for accelerometers. Today, ST has the broadest manufacturing capability in the world and unrivalled expertise for the production of sensors in a plastic LGA package. Applications ■ ■ ■ ■ ■ ■ ■ ■ GPS navigation systems Impact recognition and logging Gaming and virtual reality input devices Motion-activated functions Intelligent power saving for handheld devices Vibration monitoring and compensation Free-fall detection 6D-orientation detection Description The LSM330DL is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope. Table 1. Device summary Temperature range [°C] -40 to +85 -40 to +85 Package LGA-28 LGA-28 Packing Tray Tape & reel 1/54 www.st.com 54 Part number LSM330DL LSM330DLTR July 2011 Doc ID 022018 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents LSM330DL Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 2.2 2.3 2.4 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 2.4.2 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 2.6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.1 2.6.2 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Zero level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 4.2 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 5.2 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 5.2.2 5.2.3 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/54 Doc ID 022018 Rev 1 LSM330DL Contents 7 Registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 7.25 7.26 7.27 7.28 7.29 7.30 7.31 7.32 CTRL_REG1_A (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG2_A (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG3_A (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG4_A (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG5_A (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG6_A (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 REFERENCE/DATACAPTURE_A (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STATUS_REG_A (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 OUT_X_L_A (28h), OUT_X_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . 33 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . 33 OUT_Z_L _A(2Ch), OUT_Z_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIFO_CTRL_REG_A (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIFO_SRC_REG_A (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INT1_CFG_A (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INT1_SRC_A (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_THS_A (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_DURATION_A (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CLICK_CFG _A (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CLICK_SRC_A (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLICK_THS_A (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_LIMIT_A (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_LATENCY_A (3Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME WINDOW_A (3Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CTRL_REG1_G (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CTRL_REG2_G (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CTRL_REG3_G (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG4_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG5_G (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 REFERENCE/DATACAPTURE_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUT_TEMP_G (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STATUS_REG_G (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 OUT_X_L_G (28h), OUT_X_H_G (29h) . . . . . . . . . . . . . . . . . . . . . . . . . 44 Doc ID 022018 Rev 1 3/54 Contents LSM330DL 7.33 7.34 7.35 7.36 7.37 7.38 7.39 7.40 7.41 7.42 7.43 7.44 7.45 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . 44 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIFO_CTRL_REG_G (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIFO_SRC_REG_G (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 INT1_CFG_G (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 INT1_SRC_G (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_XH_G (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_XL_G (33h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_YH_G (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_YL_G (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_ZH_G (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_ZL_G (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_DURATION_G (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4/54 Doc ID 022018 Rev 1 LSM330DL List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Part list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Serial interface terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 22 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 22 Linear acceleration SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Angular rate SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CTRL_REG1_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 CTRL_REG1_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Data rate configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG2_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG2_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 CTRL_REG3_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG3_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG4_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG4_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 CTRL_REG5_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG5_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG6_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 CTRL_REG6 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 REFERENCE/DATACAPTURE_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 REFERENCE/DATACAPTURE_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STATUS_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 STATUS_REG_A register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIFO_CTRL_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 FIFO_CTRL_REG_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 FIFO_SRC_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INT1_CFG_REG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INT1_CFG_REG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT1_THS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_THS_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Doc ID 022018 Rev 1 5/54 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. LSM330DL INT1_DURATION_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_DURATION_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CLICK_CFG_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CLICK_CFG_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLICK_SRC_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLICK_THS_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CLICK_SRC_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_LIMIT_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_LIMIT_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_LATENCY_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_LATENCY_A description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_WINDOW_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TIME_WINDOW_A description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CTRL_REG1_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CTRL_REG1_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DR and BW configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power mode selection configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CTRL_REG2_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CTRL_REG2_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 High-pass filter mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 High-pass filter cutoff frequency configuration [Hz] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CTRL_REG3_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG3_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG4_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG4_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG5_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CTRL_REG5_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Out_Sel configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 INT_SEL configuration setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 REFERENCE/DATACAPTURE_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 REFERENCE/DATACAPTURE_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUT_TEMP_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUT_TEMP_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STATUS_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STATUS_REG_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 FIFO_CTRL_REG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIFO_CTRL_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIFO mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIFO_SRC_REG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 FIFO_SRC_REG_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 INT1_CFG_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 INT1_CFG_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 INT1_SRC_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_SRC_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_XH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_XH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_XL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_XL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 INT1_THS_YH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_YH_G description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_YL_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6/54 Doc ID 022018 Rev 1 LSM330DL Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. List of tables INT1_THS_YL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_ZH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_ZH_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_ZL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_THS_ZL_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 INT1_DURATION_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 INT1_DURATION_G description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 LLGA 7.5 x 4.4 x 1.1 28L mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Doc ID 022018 Rev 1 7/54 List of figures LSM330DL List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI slave timing diagram (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C slave timing diagram (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LSM330DL electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multiple bytes SPI read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Multiple bytes SPI write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 INT1_Sel and Out_Sel configuration block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Wait disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Wait enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 LLGA 7.5 x 4.4 x 1.1 28L package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8/54 Doc ID 022018 Rev 1 LSM330DL Block diagram and pin description 1 1.1 Figure 1. Block diagram and pin description Block diagram Block diagram Sensing Block X+ Y+ Z+ Sensing Interface CHARGE AMPLIFIER CS_A/G SDA/SDI_A/G I (a) MUX ZYXX+ Y+ Z+ + I2C/ SPI - A/D converter Control Logic SDO_A/G INT1_A INT2_A INT1_G CHARGE AMPLIFIER DEMODULATOR DRDY_G/INT2_G SCL_A/G I (Ω) + MUX LOWPASS FILTER - ZYX- ANALOG CONDITIONING Feedback+ FeedbackDriveVOLTAGE GAIN AMPLIFIER AUTOMATIC GAIN CONTROL Drive+ REFERENCE TRIMMING CIRCUITS CLOCK CONTROL LOGIC & INTERRUPT GEN. SET/RESET CIRCUITS PHASE GENERATOR AM09285V1 Doc ID 022018 Rev 1 9/54 Block diagram and pin description LSM330DL 1.2 Figure 2. Pin description Pin connections SDA/SDI_A DRDY_G/INT2_G SDA/SDI_G SDO_G SDO_A DIRECTION OF DETECTABLE ACCELERATIONS X 1 Vdd_IO_A Res 10 CS_G 1 SCL_A INT2_A Z INT1_A Y Res 28 +Ω Z z +Ω VCONT LSM330DL (BOTTOM FILTVDD VIEW) 24 INT1_G Vdd Res Res Res Res 11 Res Vdd_IO_G SCL_G Y GND 25 FILTIN Y CS_A Res Res 14 15 Vdd Res 1 Y +Ω X DIRECTION OF DETECTABLE ANGULAR RATE X AM09256V1 Table 2. Pin# Pin description Name Function Accelerometer: I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) Reserved, connect to GND Accelerometer: SPI serial data output (SDO) I2C least significant bit of the device address (SA0) Accelerometer: I2C serial clock (SCL) SPI serial port clock (SPC) Gyroscope data ready/interrupt signal 2 Accelerometer interrupt signal Gyroscope: SPI serial data output (SDO) I2C least significant bit of the device address (SA0) Accelerometer interrupt signal Gyroscope: I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) 1 SDA/SDI_A 2 3 Res SDO_A 4 5 6 7 8 SCL_A DRDY_G/INT2_G INT1_A SDO_G INT2_A 9 SDA/SDI_G 10/54 Doc ID 022018 Rev 1 LSM330DL Table 2. Pin# Block diagram and pin description Pin description (continued) Name Gyroscope: Function 10 CS_G SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) Reserved, connect to GND Gyroscope power supply for I/O pins Gyroscope: I2C serial clock (SCL) SPI serial port clock (SPC) Reserved connect to GND Power supply Reserved, connect to GND Accelerometer: 11 12 13 14 15 16 Res Vdd_IO_G SCL_G Res Vdd Res 17 CS_A SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) Reserved, connect to GND Reserved, connect to GND Reserved, connect to GND Gyroscope interrupt signal 1 Power supply Reserved, connect to GND Reserved, connect to GND 0 V power supply PLL filter connection Reserved, connect to GND Accelerometer power supply for I/O pins 18 19 20 21 22 23 24 25 26 27 28 Res Res Res INT1_G Vdd Res Res GND VCONT Res Vdd_IO_A Doc ID 022018 Rev 1 11/54 Module specifications LSM330DL 2 2.1 Module specifications Mechanical characteristics The values given in the following table are for the conditions Vdd = 3 V, T = 25 °C unless otherwise noted.(a) Table 3. Symbol Mechanical characteristics Parameter Test conditions FS bit set to 00 Min. Typ.(1) Max. ±2 ±4 ±8 ±16 ±250 ±500 ±2000 1 2 4 12 8.75 17.5 70 ±0.05 ±2 ±60 10 ±0.5 ±0.03 220 0.03 -40 +85 %/°C % mg LSb mg/°C dps/°C µg/ dps/ mdps/ digit mg/digit dps Unit LA_FS Linear acceleration measurement range(2) FS bit set to 01 FS bit set to 10 FS bit set to 11 FS bit set to 00 range(2) g G_FS Angular rate measurement FS bit set to 01 FS bit set to 10 FS bit set to 00 LA_So Linear acceleration sensitivity FS bit set to 01 FS bit set to 10 FS bit set to 11 FS bit set to 00 G_So Angular rate sensitivity FS bit set to 01 FS bit set to 10 LA_So G_So LA_TyOff G_TyOff Linear acceleration Sensitivity change vs. temperature Typical zero-g level offset accuracy Typical zero-rate level(4) (3) FS bit set to 00 Angular rate sensitivity change vs. temp. from -40 to +85°C FS bit set to 00 FS bit set to 00 Max delta from 25 °C FS bit set to 00 from -40 to +85°C FS bit set to 00, normal mode, ODR bit set to 1001 FS bit set to 00, BW = 50 Hz LA_TCOff Zero-g level change vs. temperature G_TCOff An Rn Top Zero-rate level change vs. temperature Acceleration noise density Rate noise density Operating temperature range Hz Hz °C 1. Typical specifications are not guaranteed. 2. Verified by wafer level test and measurement of initial offset and sensitivity. 3. Typical zero-g level offset value after MSL3 preconditioning. 4. Offset can be eliminated by enabling the built-in high-pass filter. a. The product is factory calibrated at 3 V. The operational power supply range is from 2.4 V to 3.6 V. 12/54 Doc ID 022018 Rev 1 LSM330DL Module specifications 2.2 Electrical characteristics The values given in the following table are for the conditions Vdd = 3 V, T = 25 °C unless otherwise noted. Table 4. Symbol Vdd Vdd_IO LA_Idd Electrical characteristics Parameter Supply voltage Power supply for I/O LA current consumption in normal mode LA current consumption in low-power mode LA current consumption in power-down mode AR current consumption in normal mode AR supply current in sleep mode(2) AR current consumption in power-down mode Digital high-level input voltage Digital low-level input voltage High-level output voltage Low-level output voltage Operating temperature range -40 0.9*Vdd_IO 0.1*Vdd_IO +85 T = 25 °C 0.8*Vdd_IO 0.2*Vdd_IO ODR = 50 Hz ODR = 1 Hz ODR = 50 Hz T = 25 °C Test conditions Min. 2.4 1.71 11 µA 2 6 0.5 6.1 1.5 5 µA µA mA mA µA V V V V Typ.(1) Max. 3.6 Vdd+0.1 Unit V V LA_IddLowP LA_IddPdn G_Idd G_IddLowP G_IddPdn VIH VIL VOH VOL Top °C 1. Typical specifications are not guaranteed. 2. Sleep mode introduces a faster turn-on time compared to power-down mode. 2.3 Temperature sensor characteristics The values given in the following table are for the conditions Vdd = 3.0 V, T=25 °C, unless otherwise noted. Table 5. Symbol TSDr TODR Top Temperature sensor characteristics (1) Parameter Temperature sensor output change vs. temperature Temperature refresh rate Operating temperature range -40 Test condition Min. Typ.(2) -1 1 +85 Max. Unit °C/digit Hz °C 1. The product is factory calibrated at 3.0 V. 2. Typical specifications are not guaranteed. Doc ID 022018 Rev 1 13/54 Module specifications LSM330DL 2.4 2.4.1 Communication interface characteristics SPI - serial peripheral interface The values given in the following table are subject to the general operating conditions for Vdd and TOP. Table 6. SPI slave timing values Value(1) Parameter Min Max ns 10 6 8 5 15 50 9 50 ns MHz SPI clock cycle SPI clock frequency CS setup time CS hold time SDI input setup time SDI input hold time SDO valid output time SDO output hold time SDO output disable time 100 Unit Symbol tc(SPC) fc(SPC) tsu(CS) th(CS) tsu(SI) th(SI) tv(SO) th(SO) tdis(SO) 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. Figure 3. CS (3) SPI slave timing diagram (b) (3) t su(CS) t c(SPC) t h(CS) (3) SPC (3) t su(SI) t h(SI) LSB IN (3) SDI (3) MSB IN t v(SO) t h(SO) LSB OUT t dis(SO) (3) SDO (3) MSB OUT 3. Data on CS, SPC, SDI and SDO concern the following pins: CS_A/G, SCL_A/G, SDA/SDI_A/G, SDO_A/G b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. 14/54 Doc ID 022018 Rev 1 LSM330DL Module specifications 2.4.2 I2C - inter-IC control interface The values given in the following table are subject to the general operating conditions for Vdd and TOP. Table 7. Symbol f(SCL) tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) I2C slave timing values Parameter(1) SCL clock frequency SCL clock low time SCL clock high time SDA setup time SDA data hold time I2C standard mode Min 0 4.7 4.0 250 0.01 3.45 1000 300 4 4.7 4 4.7 Max 100 I2C fast mode (1) Unit Min 0 1.3 µs 0.6 100 0 20 + 0.1Cb (2) 20 + 0.1Cb (2) 0.6 0.6 0.6 1.3 µs 0.9 300 ns 300 ns µs Max 400 kHz tr(SDA) tr(SCL) SDA and SCL rise time tf(SDA) tf(SCL) SDA and SCL fall time th(ST) tsu(SR) tsu(SP) tw(SP:SR) START condition hold time Repeated START condition setup time STOP condition setup time Bus free time between STOP and START condition 1. SCL (SCL_A/G pin), SDA (SDA_A/G pin) Figure 4. I2C slave timing diagram (3) REPEATED START tsu(SR) START SDA tw(SP:SR) START tf(SDA) tr(SDA) tsu(SDA) th(SDA) tsu(SP) STOP SCL th(ST) tw(SCLL) tw(SCLH) tr(SCL) tf(SCL) AM09238V1 1. Data based on standard I2C protocol requirement, not tested in production. 2 Cb = total capacitance of one bus line, in pF 3. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Doc ID 022018 Rev 1 15/54 Module specifications LSM330DL 2.5 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Symbol Vdd Vdd_IO Vin Supply voltage I/O pins supply voltage Input voltage on any control pin (SCL_A/G, SDA/SDI_A/G, SDO_A/G, CS_A/G) Acceleration (any axis, powered, Vdd = 3 V) Absolute maximum ratings Ratings Maximum value -0.3 to 4.8 -0.3 to 4.8 -0.3 to Vdd_IO +0.3 3000 g for 0.5 ms Unit V V V APOW 10000 g for 0.1 ms 3000 g for 0.5 ms AUNP TOP TSTG ESD Acceleration (any axis, unpowered) Operating temperature range Storage temperature range Electrostatic discharge protection 10000 g for 0.1 ms -40 to +85 -40 to +125 2 (HBM) °C °C kV Note: Supply voltage on any pin should never exceed 4.8 V This is a device sensitive to mechanical shock, improper handling can cause permanent damage to the part This is an ESD-sensitive device, improper handling can cause permanent damage to the part 16/54 Doc ID 022018 Rev 1 LSM330DL Module specifications 2.6 2.6.1 Terminology Sensitivity Linear acceleration sensitivity can be determined by applying 1 g acceleration to the device. As the sensor can measure DC accelerations, this can be done easily by pointing the axis of interest towards the center of the Earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and then noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and also very little over time. The sensitivity tolerance describes the range of sensitivities of a large population of sensors. Angular rate sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and also very little over time. 2.6.2 Zero level Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on the X-axis and 0 g on the Y-axis whereas the Z-axis will measure 1 g. The output is ideally in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Zero-g level change vs. temperature” (refer toTable 3). The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a population of sensors. The angular rate zero-rate level describes the actual output value if there is no angular rate present. Zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and also very little over time. Doc ID 022018 Rev 1 17/54 Functionality LSM330DL 3 Functionality The LSM330DL is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope. The complete device includes specific sensing elements and two IC interfaces able to measure both the acceleration and angular rate applied to the module and to provide a signal to the external world through an SPI/I2C serial interface. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are based on CMOS technology that allows designing a dedicated circuit which is trimmed to better match the sensing element characteristics. The LSM330DL may also be configured to generate an inertial wake-up and free-fall interrupt signal according to a programmed acceleration event along the enabled axes. 3.1 Factory calibration The IC interface is factory calibrated for sensitivity and zero level. The trimming values are stored inside the device in non-volatile memory. Any time the device is turned on, the trimming parameters are downloaded into the registers to be used during normal operation. This allows using the device without further calibration. 18/54 Doc ID 022018 Rev 1 LSM330DL Application hints 4 Application hints Figure 5. Vdd_IO Vdd_IO C5 X LSM330DL electrical connections Reserved pins have to be connected to GND Z 1 Y DIRECTION OF DETECTABLE ACCELERATIONS + Ω Z SDA/SDI_G SDA/SDI_A DRDY_G GND SDO_G SDO_A INT2_A INT1_A SCL_A z + Ω 10 Res Vdd_IO_G SCL_G Res CS_G Y Res 1 Y + Ω 1 X 11 LSM330DL FILTVDD 28 X Vdd_IO_A Res VCONT C1 (TOP VIEW) 25 24 Res Res Vdd Res INT1_G Res DIRECTION OF DETECTABLE ANGULAR RATE 14 15 Vdd Res GND FILTIN Y CS_A Res C2 R2 GND C4 Vdd C3 GND Digital signal from/to signal controller.Signals levels are defined by proper selection of Vdd AM09287v1 Table 9. Part list Component C1 C2 C3 C4 C5 R2 10 kOhm Typical value 10 nF 470 nF 10 µF 100 nF 4.1 External capacitors The device core is supplied through the Vdd line. Power supply decoupling capacitors (C4=100 nF ceramic, C3=10 µF Al) should be placed as near as possible to the supply pin of the device (common design practice). All the voltage and ground supplies must be present at the same time to have proper behavior of the IC (refer to Figure 5). The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I2C interface. Doc ID 022018 Rev 1 19/54 Application hints LSM330DL The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user though the SPI/I2C interface. 4.2 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and “Green” standards. It is qualified for soldering heat resistance according to JEDEC J-STD-020D. Leave “Pin 1 Indicator” unconnected during soldering. The landing pattern and soldering recommendations are available at www.st.com/mems. 20/54 Doc ID 022018 Rev 1 LSM330DL Digital interfaces 5 Digital interfaces The registers embedded inside the LSM330DL may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. To select/exploit the I2C interface, the CS line must be tied high (i.e. connected to Vdd_IO). Table 10. Serial interface pin description Pin description Linear acceleration SPI enable Linear acceleration I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) Angular rate SPI enable Angular rate I2C/SPI mode selection (1: I2C mode; 0: SPI enabled) I2C serial clock (SCL) SPI serial port clock (SPC) I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) I2C least significant bit of the device address (SA0) SPI serial data output (SDO) Pin name CS_A CS_G SCL_A SCL_G SDA/SDI_A SDA/SDI_G SDO_A SDO_G 5.1 I2C serial interface The LSM330DL I2C is a bus slave. The I2C is employed to write data into the registers whose content can also be read back. The relevant I2C terminology is given in the table below. Table 11. Term Transmitter Receiver Master Slave Serial interface terminology Description The device which sends data to the bus The device which receives data from the bus The device which initiates a transfer, generates clock signals and terminates a transfer The device addressed by the master There are two signals associated with the I2C bus: the serial clock line (SCL) and the serial data line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Doc ID 022018 Rev 1 21/54 Digital interfaces LSM330DL 5.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its own address. If they match, the device considers itself addressed by the Master. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LSM330DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) will be transmitted: the 7 LSb represents the actual register address while the MSB enables the address auto increment. If the MSb of the SUB field is ‘1’, the SUB (register address) will be automatically increased to allow multiple data read/writes. Table 12. Master Slave Transfer when master is writing one byte to slave ST SAD + W SAK SUB SAK DATA SAK SP Table 13. Master Slave Transfer when master is writing multiple bytes to slave ST SAD + W SAK SUB SAK DATA SAK DATA SAK SP Table 14. Master Slave Transfer when master is receiving (reading) one byte of data from slave ST SAD + W SAK SUB SAK SR SAD + R SAK DATA NMAK SP Table 15. Master Slave Transfer when master is receiving (reading) multiple bytes of data from slave ST SAD+W SAK SUB SAK SR SAD+R SAK DATA MAK DATA MAK DATA NMAK SP Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait 22/54 Doc ID 022018 Rev 1 LSM330DL Digital interfaces state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function), the data line must be left HIGH by the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In order to read multiple bytes, it is necessary to assert the most significant bit of the subaddress field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the address of first register to be read. In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge. Default address The SDO/SA0 pad can be used to modify the least significant bit of the device address. If the SA0 pad is connected to a voltage supply, LSb is ‘1’ (ex. address 0011001b), else if the SA0 pad is connected to ground, the LSb value is ‘0’ (ex address 0011000b). The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes. If the bit is ‘0’ (Write), the Master will transmit to the slave with the direction unchanged. Table 16 and Table 17 explain how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Linear acceleration address: the default (factory) 7-bit slave address is 001100xb Table 16. Linear acceleration SAD+Read/Write patterns SAD[6:1] 001100 001100 001100 001100 SAD[0] = SA0 0 0 1 1 R/W 1 0 1 0 SAD+R/W 00110001 (31h) 00110000 (30h) 00110011 (33h) 00110010 (32h) Command Read Write Read Write Angular rate sensor: the default (factory) 7-bit slave address is 110100xb Table 17. Angular rate SAD+Read/Write patterns SAD[6:1] 110100 110100 110100 110100 SAD[0] = SA0 0 0 1 1 R/W 1 0 1 0 SAD+R/W 11010001 (D1h) 11010000 (D0h) 11010011 (D3h) 11010010 (D2h) Command Read Write Read Write Doc ID 022018 Rev 1 23/54 Digital interfaces LSM330DL 5.2 SPI bus interface The LSM330DL SPI is a bus slave. The SPI allows to write and read the registers of the device. The Serial Interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO (SPC, SDI, SD0 are common). Figure 6. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 Read and write protocol SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. These lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS, while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In the latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address will remain unchanged in multiple read/write commands. When 1, the address will be auto-incremented in multiple read/write commands. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). In multiple read/write commands, further blocks of 8 clock periods will be added. When the MS bit is ‘0’, the address used to read/write data remains the same for every block. When the MS bit is ‘1’, the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. 24/54 Doc ID 022018 Rev 1 LSM330DL Digital interfaces 5.2.1 SPI read Figure 7. SPI read protocol CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI Read command is performed with 16 clock pulses. The multiple byte read command is performed, adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, this bit does not increment the address. When 1, it increments the address in multiple reads. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reads. Figure 8. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 Multiple bytes SPI read protocol (2 bytes example) SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 5.2.2 SPI write Figure 9. CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SPI write protocol Doc ID 022018 Rev 1 25/54 Digital interfaces LSM330DL The SPI Write command is performed with 16 clock pulses. The multiple byte write command is performed adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1: MS bit. When 0, this bit does not increment the address, when 1, it increments the address in multiple writes. bit 2 -7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that will be written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writes. Figure 10. Multiple bytes SPI write protocol (2 bytes example) CS SPC SDI RW MS AD5 AD4 AD3 AD2 AD1 AD0 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 5.2.3 SPI read in 3-wire mode The 3-wire mode is entered by setting to ‘1’ bit SIM (SPI serial interface mode selection) in CTRL_REG4. Figure 11. SPI read protocol in 3-wire mode CS SPC SDI/O RW MS AD5 AD4 AD3 AD2 AD1 AD0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1: MS bit. When 0, this bit does not increment the address, when 1, it increments the address in multiple reads. bit 2-7: address AD(5:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). The multiple read command is also available in 3-wire mode. 26/54 Doc ID 022018 Rev 1 LSM330DL Register mapping 6 Register mapping The table given below provides a listing of the 8-bit registers embedded in the device and their respective addresses. Table 18. Register address map Name Slave address 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb rw rw rw rw rw rw rw r r r r r r r rw r rw r rw rw rw r rw rw rw rw rw rw Register address Type Hex 00 - 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 011 1001 011 1010 011 1011 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000111 00000000 00000000 00000000 00000000 00000000 00000000 00000000 output output output output output output 00000000 Binary Reserved Default Comment Reserved (do not modify) CTRL_REG1_A CTRL_REG2_A CTRL_REG3_A CTRL_REG4_A CTRL_REG5_A CTRL_REG6_A REFERENCE/DATACAPTURE_A 001100xb STATUS_REG_A OUT_X_L_A OUT_X_H_A OUT_Y_L_A OUT_Y_H_A OUT_Z_L_A OUT_Z_H_A FIFO_CTRL_REG_A FIFO_SRC_REG_A INT1_CFG_A INT1_SRC_A INT1_THS_A INT1_DURATION_A INT2_CFG_A INT2_SOURCE_A INT2_THS_A INT2_DURATION_A CLICK_CFG_A CLICK_SRC_A CLICK_THS_A TIME_LIMIT_A 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb 001100xb Doc ID 022018 Rev 1 27/54 Register mapping Table 18. Register address map (continued) Name TIME_LATENCY_A TIME_WINDOW_A Reserved (do not modify) Reserved CTRL_REG1_G CTRL_REG2_G CTRL_REG3_G CTRL_REG4_G CTRL_REG5_G Slave address 001100xb 001100xb 001100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb rw rw rw rw rw rw r r r r r r r r rw r rw r rw rw rw rw rw rw rw Register address Type Hex rw rw 3C 3D 3E-3F 00-1E 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 010 0000 010 0001 010 0010 010 0011 010 0100 010 0101 010 0110 010 0111 010 1000 010 1001 010 1010 010 1011 010 1100 010 1101 010 1110 010 1111 011 0000 011 0001 011 0010 011 0011 011 0100 011 0101 011 0110 011 0111 011 1000 00000111 00000000 00000000 00000000 00000000 00000000 output output output output output output output output 00000000 output 00000000 output 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Binary 011 1100 011 1101 00000000 00000000 Default LSM330DL Comment Reserved Reserved REFERENCE/DATACAPTURE_G 110100xb OUT_TEMP_G STATUS_REG_G OUT_X_L_G OUT_X_H_G OUT_Y_L_G OUT_Y_H_G OUT_Z_L_G OUT_Z_H_G FIFO_CTRL_REG_G FIFO_SRC_REG_G INT1_CFG_G INT1_SRC_G INT1_THS_XH_G INT1_THS_XL_G INT1_THS_YH_G INT1_THS_YL_G INT1_THS_ZH_G INT1_THS_ZL_G INT1_DURATION_G 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb 110100xb Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory-calibrated values. Their content is automatically restored when the device is powered up. 28/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7 Registers description The device contains a set of registers which are used to control its behavior and to retrieve acceleration, angular rate and temperature data. The register addresses, composed of 7 bits, are used to identify them and to write the data through the serial interface. 7.1 CTRL_REG1_A (20h) Table 19. ODR3 CTRL_REG1_A register ODR2 ODR1 ODR0 LPen Zen Yen Xen Table 20. ODR3-0 LPen Zen Yen Xen CTRL_REG1_A description Data rate selection. Default value: 0 (0000: power-down; Others: Refer to Table 21: Data rate configuration Low-power mode enable. Default value: 0 (0: normal mode, 1: low-power mode) Z-axis enable. Default value: 1 (0: Z-axis disabled; 1: Z-axis enabled) Y-axis enable. Default value: 1 (0: Y-axis disabled; 1: Y-axis enabled) X-axis enable. Default value: 1 (0: X-axis disabled; 1: X-axis enabled) ODR is used to set power mode and ODR selection. The following table gives the frequency for all combinations of ODR. Table 21. ODR3 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 Data rate configuration ODR2 0 0 1 1 0 0 1 1 0 0 ODR1 0 1 0 1 0 1 0 1 0 1 ODR0 Power mode selection Power-down mode Normal / low-power mode (1 Hz) Normal / low-power mode (10 Hz) Normal / low-power mode (25 Hz) Normal / low-power mode (50 Hz) Normal / low-power mode (100 Hz) Normal / low-power mode (200 Hz) Normal / low-power mode (400 Hz) Low-power mode (1.620 kHz) Normal (1.344 kHz) / low-power mode (5.376 kHz) Doc ID 022018 Rev 1 29/54 Registers description LSM330DL Table 22. Operating mode selection CTRL_REG1[3] (LPen bit) 1 0 CTRL_REG4[3] (HR bit) 0 1 BW [Hz] ODR/2 ODR/9 Turn-on time [ms] 1 7/ODR Operating mode Low-power mode Normal mode 7.2 CTRL_REG2_A (21h) Table 23. HPM1 CTRL_REG2_A register HPM0 HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1 Table 24. CTRL_REG2_A description High-pass filter mode selection. Default value: 00 Refer to Table 25: High-pass filter mode configuration High-pass filter cutoff frequency selection Filtered data selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO) High-pass filter enabled for CLICK function (0: filter bypassed; 1: filter enabled) High-pass filter enabled for AOI function on interrupt 2, (0: filter bypassed; 1: filter enabled) High-pass filter enabled for AOI function on interrupt 1, (0: filter bypassed; 1: filter enabled) HPM1 -HPM0 HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1 Table 25. HPM1 0 0 1 1 0 1 0 1 High-pass filter mode configuration HPM0 High-pass filter mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode Autoreset on interrupt event 30/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7.3 CTRL_REG3_A (22h) Table 26. I1_CLICK CTRL_REG3_A register I1_AOI1 0(1) I1_DRDY1 I1_DRDY2 I1_WTM I1_OVERRUN -- 1. This bit has to be set ‘0’ for correct operation. Table 27. I1_CLICK I1_AOI1 I1_DRDY1 I1_DRDY2 I1_WTM CTRL_REG3_A description CLICK interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) AOI1 interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) DRDY1 interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) DRDY2 interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) FIFO watermark interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) FIFO overrun interrupt on INT1_A. Default value 0. (0: Disable; 1: Enable) I1_OVERRUN 7.4 CTRL_REG4_A (23h) Table 28. BDU CTRL_REG4_A register BLE FS1 FS0 HR 0(1) 0(1) SIM Table 29. BDU BLE FS1-FS0 HR SIM CTRL_REG4_A description Block data update. Default value: 0(0: continuous update; 1: output registers not updated until MSB and LSB reading) Big/little endian data selection. Default value 0. (0: Data LSB at lower address; 1: Data MSB at lower address) Full-scale selection. default value: 00 (00: +/- 2G; 01: +/- 4G; 10: +/- 8G; 11: +/- 16G) Normal mode: default value: 0 (0: normal mode disable; 1: normal mode enable SPI serial interface mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) Doc ID 022018 Rev 1 31/54 Registers description LSM330DL 7.5 CTRL_REG5_A (24h) Table 30. BOOT CTRL_REG5_A register FIFO_EN --LIR_INT1 D4D_INT1 0(1) 0(1) 1. This bit has to be set ‘0’ for correct operation. Table 31. BOOT FIFO_EN LIR_INT1 CTRL_REG5_A description Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) FIFO enable. Default value: 0 (0: FIFO disable; 1: FIFO enable) Latch interrupt request on INT1_SRC_A register, with INT1_SRC_A register cleared by reading INT1_SRC_A itself. Default value: 0. (0: interrupt request not latched; 1: interrupt request latched) 4D enable: 4D detection is enabled on INT1_A when 6D bit on INT1_CFG_A is set to 1. D4D_INT1 7.6 CTRL_REG6_A (25h) Table 32. I2_CLICKen CTRL_REG6_A register I2_INT1 0(1) BOOT_I2 0(1) -H_LACTIVE -- 1. This bit has to be set to ‘0’ for correct operation. Table 33. I2_CLICKen I2_INT1 BOOT_I2 H_LACTIVE CTRL_REG6 description Click interrupt on INT2_A. Default value 0. Interrupt 1 function enabled on INT2_A. Default 0. Boot on INT2_A. 0: interrupt active high; 1: interrupt active low. 7.7 REFERENCE/DATACAPTURE_A (26h) Table 34. Ref7 REFERENCE/DATACAPTURE_A register Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 35. Ref 7-Ref0 REFERENCE/DATACAPTURE_A register description Reference value for interrupt generation. Default value: 0 32/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7.8 STATUS_REG_A (27h) Table 36. ZYXOR STATUS_REG_A register ZOR YOR XOR ZYXDA ZDA YDA XDA Table 37. ZYXOR ZOR STATUS_REG_A register description X-, Y- and Z-axis data overwrite. Default value: 0 (0: no overwrite has occurred; 1: a new set of data has overwritten the previous ones) Z-axis data overwrite. Default value: 0 (0: no overrun has occurred; 1: a new data for the Z-axis has overwritten the previous one) Y-axis data overwrite. Default value: 0 (0: no overwrite has occurred; 1: new data for the Y-axis has overwritten the previous data) X-axis data overwrite. Default value: 0 (0: no overwrite has occurred; 1: new data for the X-axis has overwritten the previous data) X-, Y- and Z-axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) Z-axis new data available. Default value: 0 (0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available) Y-axis new data available. Default value: 0 (0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available) YOR XOR ZYXDA ZDA YDA 7.9 OUT_X_L_A (28h), OUT_X_H_A (29h) This register contains X-axis acceleration data. Values are expressed in two’s complement. 7.10 OUT_Y_L_A (2Ah), OUT_Y_H_A (2Bh) This register containsY-axis acceleration data. Values are expressed in two’s complement. 7.11 OUT_Z_L _A(2Ch), OUT_Z_H_A (2Dh) This register contains Z-axis acceleration data. Values are expressed in two’s complement. 7.12 FIFO_CTRL_REG_A (2Eh) Table 38. FM1 FIFO_CTRL_REG_A register FM0 TR FTH4 FTH3 FTH2 FTH1 FTH0 Doc ID 022018 Rev 1 33/54 Registers description LSM330DL Table 39. FM1-FM0 TR FIFO_CTRL_REG_A register description FIFO mode selection. Default value: 00 (see Table 40: FIFO mode configuration) Trigger selection. Default value: 0 0: Trigger event linked to trigger signal on INT1_A 1: Trigger event linked to trigger signal on INT2_A Default value: 0 FTH4:0 Table 40. FIFO mode configuration FM0 0 1 0 1 Bypass mode FIFO mode Stream mode Trigger mode FIFO mode FM1 0 0 1 1 7.13 FIFO_SRC_REG_A (2Fh) Table 41. WTM FIFO_SRC_REG_A register OVRN_FIFO EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 7.14 INT1_CFG_A (30h) Table 42. AOI 6D INT1_CFG_REG_A register ZHIE/ ZUPE ZLIE/ ZDOWNE YHIE/ YUPE YLIE/ YDOWNE XHIE/ XUPE XLIE/ XDOWNE Table 43. AOI 6D ZHIE/ ZUPE ZLIE/ ZDOWNE YHIE/ YUPE INT1_CFG_REG_A description And/Or combination of Interrupt events. Default value: 0. Refer to Table 44: Interrupt mode 6-direction detection function enabled. Default value: 0. Refer to Table 44: Interrupt mode Enable interrupt generation on Z high event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on Z low event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request) Enable interrupt generation on Y high event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request.) YLIE/ Enable interrupt generation on Y low event or on direction recognition. Default value: 0 YDOWNE (0: disable interrupt request; 1: enable interrupt request.) 34/54 Doc ID 022018 Rev 1 LSM330DL Table 43. XHIE/ XUPE Registers description INT1_CFG_REG_A description (continued) Enable interrupt generation on X high event or on direction recognition. Default value: 0 (0: disable interrupt request; 1: enable interrupt request.) XLIE/XDO Enable interrupt generation on X low event or on direction recognition. Default value: 0 WNE (0: disable interrupt request; 1: enable interrupt request.) The contents of the INT1_CFG_REG_A register are loaded at boot. A write operation at this address is possible only after system boot. Table 44. AOI 0 0 1 1 Interrupt mode 6D 0 1 0 1 Interrupt mode OR combination of interrupt events 6-direction movement recognition AND combination of interrupt events 6-direction position recognition The difference between AOI-6D = ‘01’ and AOI-6D = ‘11’ is defined as follows: AOI-6D = ‘01’ is movement recognition. An interrupt is generated when the orientation moves from an unknown zone to a known zone. The interrupt signal stays for a duration determined by ODR. AOI-6D = ‘11’ is direction recognition. An interrupt is generated when the orientation is inside a known zone. The interrupt signal stays until orientation is inside the zone. 7.15 INT1_SRC_A (31h) Table 45. 0(1) INT1_SRC_A register IA ZH ZL YH YL XH XL 1. This bit has to be set to ‘0’ for correct operation. Table 46. IA ZH ZL YH YL INT1_SRC_A description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) Doc ID 022018 Rev 1 35/54 Registers description Table 46. XH XL LSM330DL INT1_SRC_A description X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) X low. Default value: 0 (0: no interrupt, 1: X low event has occurred) The Interrupt 1 source register is a read-only register. Reading at this address clears the INT1_SRC_A IA bit (and the interrupt signal on the INT1_A pin) and allows the refreshment of data in the INT1_SRC_A register if the latched option was chosen. 7.16 INT1_THS_A (32h) Table 47. 0(1) INT1_THS_A register THS6 THS5 THS4 THS3 THS2 THS1 THS0 1. This bit has to be set to ‘0’ for correct operation. Table 48. INT1_THS_A description Interrupt 1 threshold. Default value: 000 0000 THS6 - THS0 7.17 INT1_DURATION_A (33h) Table 49. 0(1) INT1_DURATION_A register D6 D5 D4 D3 D2 D1 D0 1. This bit has to be set to ‘0’ for correct operation. Table 50. D6 - D0 INT1_DURATION_A description Duration value. Default value: 000 0000 The D6 - D0 bits set the minimum duration of the Interrupt 1 event to be recognized. The duration of the steps and maximum values depend on the ODR chosen. 7.18 CLICK_CFG _A (38h) Table 51. -- CLICK_CFG_A register -ZD ZS YD YS XD XS 36/54 Doc ID 022018 Rev 1 LSM330DL Table 52. ZD Registers description CLICK_CFG_A description Enable interrupt double CLICK on Z-axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt single CLICK on Z-axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt double CLICK on Y-axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt single CLICK on Y-axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt double CLICK on X-axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt single CLICK on X-axis. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ZS YD YS XD XS 7.19 CLICK_SRC_A (39h) Table 53. -- CLICK_SRC_A register IA DCLICK SCLICK Sign Z Y X Table 54. IA DCLICK SCLICK Sign Z Y X CLICK_SRC_A description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Double CLICK-CLICK enable. Default value: 0 (0: double CLICK-CLICK detection disable, 1: double CLICK-CLICK detection enable) Single CLICK-CLICK enable. Default value: 0 (0: single CLICK-CLICK detection disable, 1: single CLICK-CLICK detection enable) CLICK-CLICK Sign. 0: positive detection, 1: negative detection Z CLICK-CLICK detection. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Y CLICK-CLICK detection. Default value: 0 (0: no interrupt, 1: Y high event has occurred) X CLICK-CLICK detection. Default value: 0 (0: no interrupt, 1: X high event has occurred) Doc ID 022018 Rev 1 37/54 Registers description LSM330DL 7.20 CLICK_THS_A (3Ah) Table 55. LIR CLICK_THS_A register Ths6 Ths5 Ths4 Ths3 Ths2 Ths1 Ths0 Table 56. Ths6-Ths0 LIR CLICK_SRC_A description CLICK-CLICK threshold. Default value: 000 0000 Latch interrupt request for CLICK-CLICK function enable. 0 disable, 1 enable 7.21 TIME_LIMIT_A (3Bh) Table 57. -- TIME_LIMIT_A register TLI6 TLI5 TLI4 TLI3 TLI2 TLI1 TLI0 Table 58. TLI7-TLI0 TIME_LIMIT_A description CLICK-CLICK time limit. Default value: 000 0000 7.22 TIME_LATENCY_A (3Ch) Table 59. TLA7 TIME_LATENCY_A register TLA6 TLA5 TLA4 TLA3 TLA2 TLA1 TLA0 Table 60. TLA7-TLA0 TIME_LATENCY_A description CLICK-CLICK time latency. Default value: 000 0000 7.23 TIME WINDOW_A (3Dh) Table 61. TW7 TIME_WINDOW_A register TW6 TW5 TW4 TW3 TW2 TW1 TW0 Table 62. TW7-TW0 TIME_WINDOW_A description CLICK-CLICK time window 38/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7.24 CTRL_REG1_G (20h) Table 63. DR1 CTRL_REG1_G register DR0 BW1 BW0 PD Zen Yen Xen Table 64. DR1-DR0 BW1-BW0 PD Zen Yen Xen CTRL_REG1_G description Output data rate selection. Refer to Table 65: DR and BW configuration setting Bandwidth selection. Refer to Table 65: DR and BW configuration setting Power-down mode enable. Default value: 0 (0: power-down mode, 1: normal mode or sleep mode) Z-axis enable. Default value: 1 (0: Z-axis disabled; 1: Z-axis enabled) Y-axis enable. Default value: 1 (0: Y-axis disabled; 1: Y-axis enabled) X-axis enable. Default value: 1 (0: X-axis disabled; 1: X-axis enabled) DR is used to set the ODR selection. BW is used to set bandwidth selection. The following table gives the frequencies for all combinations of the DR / BW bits. Table 65. DR and BW configuration setting BW 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 100 100 100 100 200 200 200 200 400 400 400 400 800 800 800 800 ODR [Hz] 12.5 25 25 25 12.5 25 50 70 20 25 50 110 30 35 50 110 cutoff [Hz] DR 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 Doc ID 022018 Rev 1 39/54 Registers description LSM330DL Combination of PD, Zen, Yen, Xen are used to set device in different modes (power-down / normal / sleep mode) according to the following table. Table 66. Mode Power-down Sleep Normal Power mode selection configuration PD 0 1 1 Zen 0 Yen 0 Xen 0 - 7.25 CTRL_REG2_G (21h) Table 67. 0(1) CTRL_REG2_G register 0(1) HPM1 HPM1 HPCF3 HPCF2 HPCF1 HPCF0 1. This bit has to be set to ‘0’ for correct operation. Table 68. HPM1HPM0 HPCF3HPCF0 CTRL_REG2_G description High-pass filter mode selection. Default value: 00 Refer to Table 69: High-pass filter mode configuration High-pass filter cutoff frequency selection Refer to Table 70: High-pass filter cutoff frequency configuration [Hz] Table 69. HPM1 0 0 1 1 High-pass filter mode configuration HPM0 0 1 0 1 High-pass filter mode Normal mode (reset reading HP_RESET_FILTER) Reference signal for filtering Normal mode Autoreset on interrupt event Table 70. HPCF3-0 0000 0001 0010 0011 0100 0101 High-pass filter cutoff frequency configuration [Hz] ODR = 100 Hz 8 4 2 1 0.5 0.2 15 8 4 2 1 0.5 ODR = 200 Hz 30 15 8 4 2 1 ODR = 400 Hz 56 30 15 8 4 2 ODR = 800 Hz 40/54 Doc ID 022018 Rev 1 LSM330DL Table 70. HPCF3-0 0110 0111 1000 1001 Registers description High-pass filter cutoff frequency configuration [Hz] (continued) ODR = 100 Hz 0.1 0.05 0.02 0.01 ODR = 200 Hz 0.2 0.1 0.05 0.02 ODR = 400 Hz 0.5 0.2 0.1 0.05 1 0.5 0.2 0.1 ODR = 800 Hz 7.26 CTRL_REG3_G (22h) Table 71. I1_Int1 CTRL_REG3_G register I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty Table 72. I1_Int1 I1_Boot H_Lactive PP_OD I2_DRDY I2_WTM I2_ORun I2_Empty CTRL_REG3_G description Interrupt enable on INT1_G pin. Default value 0. (0: Disable; 1: Enable) Boot status available on INT1_G. Default value 0. (0: Disable; 1: Enable) Interrupt active configuration on INT1_G. Default value 0. (0: High; 1:Low) Push-Pull / Open drain. Default value: 0. (0: Push-Pull; 1: Open drain) Date Ready on DRDY_G/INT2_G. Default value 0. (0: Disable; 1: Enable) FIFO watermark interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable) FIFO overrun interrupt on DRDY_G/INT2_G Default value: 0. (0: Disable; 1: Enable) FIFO empty interrupt on DRDY_G/INT2_G. Default value: 0. (0: Disable; 1: Enable) 7.27 CTRL_REG4_G (23h) Table 73. BDU CTRL_REG4_G register BLE FS1 FS0 -0(1) 0(1) SIM 1. This bit has to be set to ‘0’ for correct operation. Table 74. BDU CTRL_REG4_G description Block data update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB have been read) Big/little endian data selection. Default value 0. (0: Data LSB at lower address; 1: Data MSB at lower address) BLE Doc ID 022018 Rev 1 41/54 Registers description Table 74. FS1-FS0 SIM LSM330DL CTRL_REG4_G description (continued) Full-scale selection. Default value: 00 (00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps) SPI serial interface mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface). 7.28 CTRL_REG5_G (24h) Table 75. BOOT CTRL_REG5_G register FIFO_EN -HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0 Table 76. BOOT FIFO_EN HPen CTRL_REG5_G description Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content) FIFO enable. Default value: 0 (0: FIFO disable; 1: FIFO Enable) High-pass filter enable. Default value: 0 (0: HPF disabled; 1: HPF enabled See Figure 12: INT1_Sel and Out_Sel configuration block diagram) INT1 selection configuration. Default value: 0 (See Figure 12: INT1_Sel and Out_Sel configuration block diagram) Out selection configuration. Default value: 0 (See Figure 12: INT1_Sel and Out_Sel configuration block diagram) INT1_Sel1INT1_Sel0 Out_Sel1Out_Sel1 Figure 12. INT1_Sel and Out_Sel configuration block diagram Out_Sel 00 01 0 LPF2 ADC DataReg FIFO 32x16x3 10 11 LPF1 HPF 1 HPen 10 11 01 00 AM09276V1 INT1_Sel Interrupt generator 42/54 Doc ID 022018 Rev 1 LSM330DL Registers description Table 77. Hpen x x 0 1 Out_Sel configuration setting OUT_SEL1 0 0 1 1 OUT_SEL0 0 1 x x Description Data in DataReg and FIFO are non-highpass-filtered Data in DataReg and FIFO are high-passfiltered Data in DataReg and FIFO are low-passfiltered by LPF2 Data in DataReg and FIFO are high-pass and low-pass-filtered by LPF2 Table 78. Hpen x x 0 1 INT_SEL configuration setting INT_SEL1 0 0 1 1 INT_SEL2 0 1 x x Description Non-high-pass-filtered data are used for interrupt generation High-pass-filtered data are used for interrupt generation Low-pass-filtered data are used for interrupt generation High-pass and low-pass-filtered data are used for interrupt generation 7.29 REFERENCE/DATACAPTURE_G (25h) Table 79. Ref7 REFERENCE/DATACAPTURE_G register Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 80. Ref 7-Ref0 REFERENCE/DATACAPTURE_G register description Reference value for interrupt generation. Default value: 0 7.30 OUT_TEMP_G (26h) Table 81. Temp7 OUT_TEMP_G register Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0 Doc ID 022018 Rev 1 43/54 Registers description LSM330DL Table 82. OUT_TEMP_G register description Temperature data (1LSB/deg - 8-bit resolution). The value is expressed as two’s complement. Temp7-Temp0 7.31 STATUS_REG_G (27h) Table 83. ZYXOR STATUS_REG_G register ZOR YOR XOR ZYXDA ZDA YDA XDA Table 84. STATUS_REG_G description X-, Y-, Z-axis data overwrite. Default value: 0 ZYXOR (0: no overwrite has occurred; 1: new data has overwritten the previous data before it was read) ZOR YOR XOR Z-axis data overwrite. Default value: 0 (0: no overwrite has occurred; 1: new data for the Z-axis has overwritten the previous data) Y-axis data overwrite. Default value: 0 (0: no overwrite has occurred; 1: new data for the Y-axis has overwritten the previous data) X-axis data overwrite. Default value: 0 (0: no overwrite has occurred; 1: new data for the X-axis has overwritten the previous data) ZYXDA X-, Y-, Z-axis new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) ZDA YDA XDA Z-axis new data available. Default value: 0 (0: new data for the Z-axis is not yet available; 1: new data for the Z-axis is available) Y-axis new data available. Default value: 0 (0: new data for the Y-axis is not yet available; 1: new data for the Y-axis is available) X-axis new data available. Default value: 0 (0: new data for the X-axis is not yet available; 1: new data for the X-axis is available) 7.32 OUT_X_L_G (28h), OUT_X_H_G (29h) This register contains X-axis angular rate data. Values are expressed as two’s complement. 7.33 OUT_Y_L_G (2Ah), OUT_Y_H_G (2Bh) This register contains Y-axis angular rate data. Values are expressed as two’s complement. 7.34 OUT_Z_L_G (2Ch), OUT_Z_H_G (2Dh) This register contains Z-axis angular rate data. Values are expressed as two’s complement. 44/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7.35 FIFO_CTRL_REG_G (2Eh) Table 85. FM2 FIFO_CTRL_REG_G register FM1 FM0 WTM4 WTM3 WTM2 WTM1 WTM0 Table 86. FM2-FM0 FIFO_CTRL_REG_G register description FIFO mode selection. Default value: 00 (see Table 40: FIFO mode configuration FIFO threshold. Watermark level setting WTM4-WTM0 Table 87. FM2 0 0 0 0 1 0 0 1 1 0 FIFO mode configuration FM1 0 1 0 1 0 FM0 Bypass mode FIFO mode Stream mode Stream-to-FIFO mode Bypass-to-Stream mode FIFO mode 7.36 FIFO_SRC_REG_G (2Fh) Table 88. WTM FIFO_SRC_REG_G register OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSS0 Table 89. WTM OVRN EMPTY FSS4-FSS1 FIFO_SRC_REG_G register description Watermark status. (0: FIFO filling is lower than WTM level; 1: FIFO filling is equal or higher than WTM level) Overrun bit status. (0: FIFO is not completely filled; 1:FIFO is completely filled) FIFO empty bit. ( 0: FIFO not empty; 1: FIFO empty) FIFO stored data level Doc ID 022018 Rev 1 45/54 Registers description LSM330DL 7.37 INT1_CFG_G (30h) This is the configuration register for the interrupt source. Table 90. AND/OR INT1_CFG_G register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE Table 91. AND/OR INT1_CFG_G description AND/OR combination of interrupt events. Default value: 0 (0: OR combination of interrupt events 1: AND combination of interrupt events Latch Interrupt Request. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) Cleared by reading INT1_SRC_G reg. Enable interrupt generation on Z high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Z low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on Y high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on Y low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) Enable interrupt generation on X high event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) Enable interrupt generation on X low event. Default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) LIR ZHIE ZLIE YHIE YLIE XHIE XLIE 46/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7.38 INT1_SRC_G (31h) The interrupt source register is a read-only register. Reading at this address clears the INT1_SRC_G IA bit (and eventually the interrupt signal on the INT1_G pin) and allows the refreshment of data in the INT1_SRC_G register if the latched option was chosen. Table 92. 0(1) INT1_SRC_G register IA ZH ZL YH YL XH XL 1. This bit has to be set to ‘0’ for correct operation. Table 93. IA ZH ZL YH YL XH XL INT1_SRC_G description Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) Z high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) Z low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) Y high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) Y low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) X high. Default value: 0 (0: no interrupt, 1: X high event has occurred) X low. Default value: 0 (0: no interrupt, 1: X low event has occurred) 7.39 INT1_THS_XH_G (32h) Table 94. -- INT1_THS_XH_G register THSX14 THSX13 THSX12 THSX11 THSX10 THSX9 THSX8 Table 95. INT1_THS_XH_G description Interrupt threshold. Default value: 0000 0000 THSX14 - THSX9 7.40 INT1_THS_XL_G (33h) Table 96. THSX7 INT1_THS_XL_G register THSX6 THSX5 THSX4 THSX3 THSX2 THSX1 THSX0 Table 97. INT1_THS_XL_G description Interrupt threshold. Default value: 0000 0000 THSX7 - THSX0 Doc ID 022018 Rev 1 47/54 Registers description LSM330DL 7.41 INT1_THS_YH_G (34h) Table 98. -- INT1_THS_YH_G register THSY14 THSY13 THSY12 THSY11 THSY10 THSY9 THSY8 Table 99. INT1_THS_YH_G description Interrupt threshold. Default value: 0000 0000 THSY14 - THSY9 7.42 INT1_THS_YL_G (35h) Table 100. INT1_THS_YL_G register THSR7 THSY6 THSY5 THSY4 THSY3 THSY2 THSY1 THSY0 Table 101. INT1_THS_YL_G description THSY7 - THSY0 Interrupt threshold. Default value: 0000 0000 7.43 INT1_THS_ZH_G (36h) Table 102. INT1_THS_ZH_G register -THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 THSZ9 THSZ8 Table 103. INT1_THS_ZH_G description THSZ14 - THSZ9 Interrupt threshold. Default value: 0000 0000 7.44 INT1_THS_ZL_G (37h) Table 104. INT1_THS_ZL_G register THSZ7 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZ0 Table 105. INT1_THS_ZL_G description THSZ7 - THSZ0 Interrupt threshold. Default value: 0000 0000 48/54 Doc ID 022018 Rev 1 LSM330DL Registers description 7.45 INT1_DURATION_G (38h) Table 106. INT1_DURATION_G register WAIT D6 D5 D4 D3 D2 D1 D0 Table 107. INT1_DURATION_G description WAIT D6 - D0 WAIT enable. Default value: 0 (0: disable; 1: enable) Duration value. Default value: 000 0000 The D6 - D0 bits set the minimum duration of the interrupt event to be recognized. The duration of the steps and maximum values depend on the ODR chosen. The WAIT bit has the following meaning: Wait =’0’: the interrupt falls immediately if the signal crosses the selected threshold Wait =’1’: if the signal crosses the selected threshold, the interrupt falls only after the duration has counted the number of samples at the selected data rate, written into the duration counter register. Figure 13. Wait disabled Doc ID 022018 Rev 1 49/54 Registers description Figure 14. Wait enabled LSM330DL 50/54 Doc ID 022018 Rev 1 LSM330DL Package information 8 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. ECOPACK® specifications are available at: www.st.com. Doc ID 022018 Rev 1 51/54 Package information LSM330DL Table 108. LLGA 7.5 x 4.4 x 1.1 28L mechanical data mm Dim. Min. A1 A2 A3 D1 E1 N1 L1 L2 P2 T1 T2 M d k h 4.250 7.350 0.855 0.200 4.400 7.500 0.300 5.400 1.800 1.200 0.600 0.400 0.100 0.3 0.050 0.100 4.550 7.650 Typ. Max. 1.100 Figure 15. LLGA 7.5 x 4.4 x 1.1 28L package drawing Pin 1 Indicator hC = k E1 k L1 = C d N1 A A3 D P2 kE D1 E kD A2 Seating Plane A1 T2 K 8190050_B M L2 T1 B TOP VIEW 52/54 Doc ID 022018 Rev 1 LSM330DL Revision history 9 Revision history Table 109. Document revision history Date 19-Jul-2011 Revision 1 First release. Changes Doc ID 022018 Rev 1 53/54 LSM330DL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2011 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 54/54 Doc ID 022018 Rev 1