LSM6DSO
Datasheet
iNEMO inertial module: always-on 3D accelerometer and 3D gyroscope
Features
LGA-14L
(2.5 x 3.0 x 0.83 mm) typ.
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SPI / I²C & MIPI I3CSM serial interface with main processor data synchronization
Auxiliary SPI for OIS data output for gyroscope and accelerometer
Advanced pedometer, step detector and step counter
Significant Motion Detection, Tilt detection
Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click
Programmable Finite State Machine: accelerometer, gyroscope and external
sensors
Embedded temperature sensor
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ECOPACK®, RoHS and “Green” compliant
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Product status link
LSM6DSO
Product summary
Order code
LSM6DSO
Temperature
range [°C]
Package
Packing
LSM6DSOTR
-40 to +85
LGA-14L
(2.5 x 3 x 0.83 mm)
Tray
Product label
Power consumption: 0.55 mA in combo high-performance mode
“Always-on" experience with low power consumption for both accelerometer and
gyroscope
Smart FIFO up to 9 kbyte
Android compliant
±2/±4/±8/±16 g full scale
±125/±250/±500/±1000/±2000 dps full scale
Analog supply voltage: 1.71 V to 3.6 V
Independent IO supply (1.62 V)
Compact footprint: 2.5 mm x 3 mm x 0.83 mm
Applications
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Motion tracking and gesture detection
Sensor hub
Indoor navigation
IoT and connected devices
Smart power saving for handheld devices
EIS and OIS for camera applications
Vibration monitoring and compensation
Tape & Reel
Description
The LSM6DSO is a system-in-package featuring a 3D digital accelerometer and a 3D
digital gyroscope boosting performance at 0.55 mA in high-performance mode and
enabling always-on low-power features for an optimal motion experience for the
consumer.
The LSM6DSO supports main OS requirements, offering real, virtual and batch
sensors with 9 kbytes for dynamic data batching. ST’s family of MEMS sensor
modules leverages the robust and mature manufacturing processes already used for
the production of micromachined accelerometers and gyroscopes. The various
sensing elements are manufactured using specialized micromachining processes,
while the IC interfaces are developed using CMOS technology that allows the design
of a dedicated circuit which is trimmed to better match the characteristics of the
sensing element.
DS12140 - Rev 2 - January 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
LSM6DSO
The LSM6DSO has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular
rate range of ±125/±250/±500/±1000/±2000 dps.
The LSM6DSO fully supports EIS and OIS applications as the module includes a
dedicated configurable signal processing path for OIS and auxiliary SPI, configurable
for both the gyroscope and accelerometer.
High robustness to mechanical shock makes the LSM6DSO the preferred choice of
system designers for the creation and manufacturing of reliable products.The
LSM6DSO is available in a plastic land grid array (LGA) package.
DS12140 - Rev 2
page 2/172
LSM6DSO
Overview
1
Overview
The LSM6DSO is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis
digital gyroscope.
The LSM6DSO delivers best-in-class motion sensing that can detect orientation and gestures in order to
empower application developers and consumers with features and capabilities that are more sophisticated than
simply orienting their devices to portrait and landscape mode.
The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness,
implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or
inactivity, stationary/motion detection and wakeup events.
The LSM6DSO supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the
LSM6DSO can efficiently run the sensor-related features specified in Android, saving power and enabling faster
reaction time. In particular, the LSM6DSO has been designed to implement hardware features such as significant
motion detection, stationary/motion detection, tilt, pedometer functions, timestamping and to support the data
acquisition of an external magnetometer.
The LSM6DSO offers hardware flexibility to connect the pins with different mode connections to external sensors
to expand functionalities such as adding a sensor hub, auxiliary SPI, etc.
Up to 9 kbytes of FIFO with compression and dynamic allocation of significant data (i.e. external sensors,
timestamp, etc.) allows overall power saving of the system.
Like the entire portfolio of MEMS sensor modules, the LSM6DSO leverages the robust and mature in-house
manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The
various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces
are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better
match the characteristics of the sensing element.
The LSM6DSO is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address
ultra-compact solutions.
DS12140 - Rev 2
page 3/172
LSM6DSO
Embedded low-power features
2
Embedded low-power features
The LSM6DSO has been designed to be fully compliant with Android, featuring the following on-chip functions:
•
9 kybtes data buffering, data can be compressed two or three times
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100% efficiency with flexible configurations and partitioning
–
Possibility to store timestamp
•
•
•
2.1
Event-detection interrupts (fully configurable)
–
Free-fall
–
Wakeup
–
6D orientation
–
Click and double-click sensing
–
Activity/Inactivity recognition
–
Stationary/Motion detection
Specific IP blocks with negligible power consumption and high-performance
–
Pedometer functions: step detector and step counters
–
Tilt
–
Significant Motion Detection
–
Finite State Machine (FSM) for accelerometer, gyroscope, and external sensors
Sensor hub
–
Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external sensors
Tilt detection
The tilt function helps to detect activity change and has been implemented in hardware using only the
accelerometer to achieve targets of both ultra-low power consumption and robustness during the short duration of
dynamic accelerations.
The tilt function is based on a trigger of an event each time the device's tilt changes and can be used with
different scenarios, for example:
1.
Triggers when phone is in a front pants pocket and the user goes from sitting to standing or standing to
sitting;
2.
Doesn’t trigger when phone is in a front pants pocket and the user is walking, running or going upstairs.
2.2
Significant Motion Detection
The Significant Motion Detection (SMD) function generates an interrupt when a ‘significant motion’, that could be
due to a change in user location, is detected. In the LSM6DSO device this function has been implemented in
hardware using only the accelerometer.
SMD functionality can be used in location-based applications in order to receive a notification indicating when the
user is changing location.
2.3
Finite State Machine
The LSM6DSO can be configured to generate interrupt signals activated by user-defined motion patterns. To do
this, up to 16 embedded finite state machines can be programmed independently for motion detection such as
glance gestures, absolute wrist tilt, shake and double-shake detection.
Definition of Finite State Machine
A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model
composed of a finite number of states and transitions between states, similar to a flow chart in which one can
inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to
different states through transitions dependent on the inputs, and can finally end in a specific state (called stop
state). The current state is determined by the past states of the system. Figure 1. Generic state machine shows a
generic state machine.
DS12140 - Rev 2
page 4/172
LSM6DSO
Finite State Machine
Figure 1. Generic state machine
Finite State Machine in the LSM6DSO
The LSM6DSO works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate
output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature
(Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine
(Figure 2. State machine in the LSM6DSO).
All 16 finite state machines are independent: each one has its dedicated memory area and it is independently
executed. An interrupt is generated when the end state is reached or when some specific command is performed.
Figure 2. State machine in the LSM6DSO
DS12140 - Rev 2
page 5/172
LSM6DSO
Pin description
3
Pin description
Figure 3. Pin connections
3.1
Pin connections
The LSM6DSO offers flexibility to connect the pins in order to have four different mode connections and
functionalities. In detail:
DS12140 - Rev 2
•
Mode 1: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available;
•
Mode 2: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface and I²C interface master for
external sensor connections are available;
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Mode 3: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application
processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is
available for the gyroscope ONLY;
•
Mode 4: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application
processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is
available for the accelerometer and gyroscope.
page 6/172
LSM6DSO
Pin connections
Figure 4. LSM6DSO connection modes
Mode 1
Mode 2
Mode 3
Mode 4
HOST
HOST
HOST
HOST
I 2C /
SM
MIPI I3C /
SPI (3/4-w)
LSM6DSO
I 2C /
I 2C /
MIPI I3CSM /
SPI (3/4-w)
I 2C /
MIPI I3CSM /
SPI (3/4-w)
MIPI I3CSM /
SPI (3/4-w)
LSM6DSO
Master I2C
LSM6DSO
LSM6DSO
Aux SPI (3/4-w) For gyro
data only
Aux SPI (3/4-w) For XL and
gyro data
Camera
module
LSM6DSM
External
LSM6DSM
sensors
Camera
module
In the following table each mode is described for the pin connections and function.
Table 1. Pin description
Pin#
DS12140 - Rev 2
Name
Mode 1 function
Mode 2 function
Mode 3 / Mode 4 function
SPI 4-wire interface serial data
output (SDO)
SPI 4-wire interface serial data
output (SDO)
SPI 4-wire interface serial data
output (SDO)
I²C least significant bit of the
device address (SA0)
I²C least significant bit of the
device address (SA0)
I²C least significant bit of the device
address (SA0)
1
SDO/SA0
2
SDx
Connect to VDDIO or GND
I²C serial data master (MSDA)
Auxiliary SPI 3/4-wire interface serial
data input (SDI) and SPI 3-wire serial
data output (SDO)
3
SCx
Connect to VDDIO or GND
I²C serial clock master (MSCL)
Auxiliary SPI 3/4-wire interface serial
port clock (SPC_Aux)
4
INT1
Programmable interrupt in I²C and SPI
5
VDDIO(1)
Power supply for I/O pins
6
GND
0 V supply
7
GND
0 V supply
8
VDD(1)
Power supply
9
INT2
Programmable interrupt 2
(INT2) / Data enable (DEN)
Programmable interrupt 2 (INT2)/
Data enable (DEN)/I²C master
external synchronization signal
(MDRDY)
Programmable interrupt 2 (INT2)/
Data enable (DEN)
Auxiliary SPI 3/4-wire interface
enable
10
OCS_Aux Leave unconnected(2)
Leave unconnected(2)
11
Connect to VDD_IO or leave
SDO_Aux
unconnected(2)
Connect to VDD_IO or leave
unconnected(2)
Auxiliary SPI 3-wire interface: leave
unconnected(2)
Auxiliary SPI 4-wire interface: serial
data output (SDO_Aux)
page 7/172
LSM6DSO
Pin connections
Pin#
12
13
Name
CS
SCL
Mode 1 function
Mode 2 function
Mode 3 / Mode 4 function
I²C/MIPI I3CSM/SPI mode
selection
I²C/MIPI I3CSM/SPI mode
selection
I²C/MIPI I3CSM/SPI mode selection
(1: SPI idle mode / I²C/MIPI
I3CSM communication enabled;
(1: SPI idle mode / I²C/MIPI
I3CSM communication enabled;
0: SPI communication mode /
I²C/MIPI I3CSM disabled)
0: SPI communication mode / I²C/
0: SPI communication mode / I²C/
MIPI I3CSM disabled)
SM
MIPI I3C disabled)
I²C/MIPI I3CSM serial clock
(SCL)
I²C/MIPI I3CSM serial clock (SCL)
I²C/MIPI I3CSM serial clock (SCL)
SPI serial port clock (SPC)
SPI serial port clock (SPC)
I²C/MIPI I3CSM serial data (SDA)
I²C/MIPI I3CSM serial data (SDA)
SPI serial data input (SDI)
SPI serial data input (SDI)
3-wire interface serial data output
(SDO)
3-wire interface serial data
SPI serial port clock (SPC)
I²C/MIPI I3CSM serial data
(SDA)
14
SDA
SPI serial data input (SDI)
3-wire interface serial data
output (SDO)
(1: SPI idle mode / I²C/MIPI I3CSM
communication enabled;
output (SDO)
1. Recommended 100 nF filter capacitor.
2. Leave pin electrically unconnected and soldered to PCB.
DS12140 - Rev 2
page 8/172
LSM6DSO
Module specifications
4
Module specifications
4.1
Mechanical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 2. Mechanical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.(1)
Max.
Unit
±2
LA_FS
±4
Linear acceleration measurement range
±8
g
±16
±125
±250
G_FS
Angular rate measurement range
±500
dps
±1000
±2000
LA_So
G_So
G_So%
LA_SoDr
G_SoDr
LA_TyOff
G_TyOff
FS = ±2 g
0.061
FS = ±4 g
0.122
FS = ±8 g
0.244
FS = ±16 g
0.488
FS = ±125 dps
4.375
FS = ±250 dps
8.75
FS = ±500 dps
17.50
FS = ±1000 dps
35
FS = ±2000 dps
70
at component level
±1
%
from -40° to +85°
±0.01
%/°C
from -40° to +85°
±0.007
%/°C
±20
mg
±1
dps
±0.1
mg/ °C
±0.010
dps/°C
Rate noise density in high-performance mode(6)
3.8
mdps/√Hz
Gyroscope RMS noise in normal/low-power mode(7)
75
mdps
Linear acceleration sensitivity(2)
Angular rate
sensitivity(2)
Sensitivity tolerance(3)
Linear acceleration sensitivity change vs.
Angular rate sensitivity change vs.
temperature(4)
Linear acceleration zero-g level offset
Angular rate zero-rate
temperature(4)
accuracy(5)
level(5)
temperature(4)
LA_OffDr
Linear acceleration zero-g level change vs.
G_OffDr
Angular rate typical zero-rate level change vs. temperature(4)
Rn
RnRMS
An
Acceleration noise density in high-performance mode(8)
DS12140 - Rev 2
FS = ±2 g
70
FS = ±4 g
75
FS = ±8 g
80
FS = ±16 g
110
mg/LSB
mdps/LSB
µg/√Hz
page 9/172
LSM6DSO
Mechanical characteristics
Symbol
RMS
Parameter
Test conditions
Acceleration RMS noise in normal/low-power mode(9) (10)
Acceleration RMS noise in ultra-low-power mode(9)(10)
Min.
Typ.(1)
FS = ±2 g
1.8
FS = ±4 g
2.0
FS = ±8 g
2.4
FS = ±16 g
3.0
FS = ±2 g
5.5
Max.
Unit
mg(RMS)
1.6(11)
12.5
26
52
104
LA_ODR
Linear acceleration output data rate
208
416
833
1666
3332
6664
Hz
12.5
26
52
104
G_ODR
208
Angular rate output data rate
416
833
1666
3332
6664
Linear acceleration self-test output
Vst
Top
change(12)(13)(14)
Angular rate self-test output change(15) (16)
50
1700
mg
FS = 250 dps
20
80
dps
FS = 2000 dps
150
700
dps
-40
+85
°C
Operating temperature range
1. Typical specifications are not guaranteed.
2. Sensitivity values after factory calibration test and trimming.
3. Subject to change.
4. Measurements are performed in a uniform temperature setup and they are based on characterization data
in a limited number of samples. Not measured during final test for production.
5. Values after factory calibration test and trimming.
6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting.
7. Gyroscope RMS noise in normal/low-power mode is independent of the ODR and FS setting.
8. Accelerometer noise density in high-performance mode is independent of the ODR.
9. Accelerometer RMS noise in normal/low-power/ultra-low-power mode is independent of the ODR.
10. Noise RMS related to BW = ODR/2.
11. This ODR is available when the accelerometer is in low-power mode.
12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated
register for all axes.
DS12140 - Rev 2
page 10/172
LSM6DSO
Mechanical characteristics
13. The linear acceleration self-test output change is defined with the device in stationary condition as the
absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg
at ±2 g full scale.
14. Accelerometer self-test limits are full-scale independent.
15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for
all axes.
16. The angular rate self-test output change is defined with the device in stationary condition as the absolute
value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000
dps full scale.
DS12140 - Rev 2
page 11/172
LSM6DSO
Electrical characteristics
4.2
Electrical characteristics
@ Vdd = 1.8 V, T = 25 °C, unless otherwise noted.
Table 3. Electrical characteristics
Min.
Typ.(1)
Max.
Unit
Supply voltage
1.71
1.8
3.6
V
Power supply for I/O
1.62
3.6
V
Symbol
Vdd
Vdd_IO
Parameter
Test conditions
Gyroscope and accelerometer current consumption in high-performance
mode
0.55
mA
LA_IddHP
Accelerometer current consumption in high-performance mode
170
µA
LA_IddLP
Accelerometer current consumption in low-power mode
IddHP
LA_IddULP Accelerometer current consumption in ultra-low-power mode
IddPD
ODR = 52 Hz
26
ODR = 1.6 Hz
4.5
ODR = 52 Hz
9.5
ODR = 1.6 Hz
4.4
µA
µA
Gyroscope and accelerometer current consumption during power-down
3
µA
Ton
Turn-on time
35
ms
VIH
Digital high-level input voltage
VIL
Digital low-level input voltage
VOH
High-level output voltage
IOH = 4 mA(2)
VOL
Low-level output voltage
IOL = 4 mA(2)
Top
Operating temperature range
0.7 *
VDD_IO
V
0.3 *
VDD_IO
V
VDD_IO 0.2
V
-40
0.2
V
+85
°C
1. Typical specifications are not guaranteed.
2. 4 mA is the maximum driving capability, i.e. the maximum DC current that can be sourced/sunk by the digital
pin in order to guarantee the correct digital output voltage levels VOH and VOL.
4.3
Temperature sensor characteristics
@ Vdd = 1.8 V, T = 25 °C unless otherwise noted.
Table 4. Temperature sensor characteristics
Symbol
TODR(2)
Toff
TSen
TST
Parameter
Test condition
Min.
Temperature refresh rate
Temperature
Max.
52
offset(3)
-15
Temperature sensitivity
Temperature stabilization
Typ.(1)
Hz
+15
256
time(4)
T_ADC_res
Temperature ADC resolution
Top
Operating temperature range
°C
LSB/°C
500
16
-40
Unit
µs
bit
+85
°C
1. Typical specifications are not guaranteed.
2. When the accelerometer is in low-power mode or ultra-low-power mode and the gyroscope part is turned off, the TODR
value is equal to the accelerometer ODR.
3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C.
4. Time from power ON to valid data based on characterization data.
DS12140 - Rev 2
page 12/172
LSM6DSO
Communication interface characteristics
4.4
Communication interface characteristics
4.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 5. SPI slave timing values (in mode 3)
Parameter
Symbol
Value(1)
Min
tc(SPC)
SPI clock cycle
fc(SPC)
SPI clock frequency
tsu(CS)
CS setup time
5
th(CS)
CS hold time
20
tsu(SI)
SDI input setup time
5
th(SI)
SDI input hold time
15
tv(SO)
SDO valid output time
th(SO)
SDO output hold time
tdis(SO)
SDO output disable time
Max
100
Unit
ns
10
MHz
ns
50
5
50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not
tested in production
Figure 5. SPI slave timing diagram (in mode 3)
Note:
DS12140 - Rev 2
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both input and output ports.
page 13/172
LSM6DSO
Communication interface characteristics
4.4.2
I²C - inter-IC control interface
Subject to general operating conditions for Vdd and Top.
Table 6. I²C slave timing values
Symbol
I²C standard mode(1)
Parameter
f(SCL)
I²C fast mode (1)
Min
Max
Min
Max
0
100
0
400
SCL clock frequency
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0
th(ST)
START condition hold time
4
0.6
tsu(SR)
Repeated START condition setup time
4.7
0.6
tsu(SP)
STOP condition setup time
4
0.6
4.7
1.3
tw(SP:SR)
Bus free time between STOP and START condition
3.45
Unit
kHz
µs
ns
0
0.9
µs
µs
1. Data based on standard I²C protocol requirement, not tested in production.
Figure 6. I²C slave timing diagram
REPEATED
START
START
tsu(SR)
tw(SP:SR)
SDA
tsu(SDA)
START
th(SDA)
tsu(SP)
STOP
SCL
th(ST)
Note:
DS12140 - Rev 2
tw(SCLL)
tw(SCLH)
Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO for both ports.
page 14/172
LSM6DSO
Absolute maximum ratings
4.5
Absolute maximum ratings
Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device under these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
Table 7. Absolute maximum ratings
Symbol
Maximum value
Unit
Vdd
Supply voltage
-0.3 to 4.8
V
TSTG
Storage temperature range
-40 to +125
°C
20,000
g
2
kV
-0.3 to Vdd_IO +0.3
V
Sg
ESD
Vin
Note:
Ratings
Acceleration g for 0.2 ms
Electrostatic discharge protection (HBM)
Input voltage on any control pin
(including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0)
Supply voltage on any pin should never exceed 4.8 V.
This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part.
This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part.
DS12140 - Rev 2
page 15/172
LSM6DSO
Terminology
4.6
Terminology
4.6.1
Sensitivity
Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device.
Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards
the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the
output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value
from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes
very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large
number of sensors (see Table 2).
An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation
around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a
defined angular velocity to it. This value changes very little over temperature and time (see Table 2).
4.6.2
Zero-g and zero-rate level
Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal
output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on
both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic
range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from
the ideal value in this case is called zero-g offset.
Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after
mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes
little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 2. Mechanical
characteristics. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of
a group of sensors.
Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise
MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly
change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress.
This value changes very little over temperature and time (see Table 2. Mechanical characteristics).
DS12140 - Rev 2
page 16/172
LSM6DSO
Digital interfaces
5
Digital interfaces
5.1
I²C/SPI interface
The registers embedded inside the LSM6DSO may be accessed through both the I²C and SPI serial interfaces.
The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible
with SPI modes 0 and 3.
The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied
high (i.e connected to Vdd_IO).
Table 8. Serial interface pin description
Pin name
Pin description
SPI enable
CS
I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled;
0: SPI communication mode / I²C disabled)
I²C Serial Clock (SCL)
SCL/SPC
SPI Serial Port Clock (SPC)
I²C Serial Data (SDA)
SDA/SDI/SDO
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SDO/SA0
5.1.1
SPI Serial Data Output (SDO)
I²C less significant bit of the device address
I²C serial interface
The LSM6DSO I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also
be read back.
The relevant I²C terminology is provided in the table below.
Table 9. I²C terminology
Term
Transmitter
Receiver
Description
The device which sends data to the bus
The device which receives data from the bus
Master
The device which initiates a transfer, generates clock signals and terminates a transfer
Slave
The device addressed by the master
There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The
latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be
connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high.
The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with the standard mode.
In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h).
DS12140 - Rev 2
page 17/172
LSM6DSO
I²C/SPI interface
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to
LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the
bus is considered busy. The next byte of data transmitted after the start condition contains the address of the
slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting
data to the slave. When an address is sent, each device in the system compares the first seven bits after a start
condition with its address. If they match, the device considers itself addressed by the master.
The Slave ADdress (SAD) associated to the LSM6DSO is 110101xb. The SDO/SA0 pin can be used to modify the
less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’
(address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b).
This solution permits to connect and address two different inertial modules to the same I²C bus.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge
pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the
acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each
byte of data received.
The I²C embedded inside the LSM6DSO behaves like a slave device and the following protocol must be adhered
to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an
8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the CTRL3_C (12h)
(IF_INC).
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition
must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with
direction unchanged. Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible
configurations.
Table 10. SAD+Read/Write patterns
Command
SAD[6:1]
SAD[0] = SA0
R/W
SAD+R/W
Read
110101
0
1
11010101 (D5h)
Write
110101
0
0
11010100 (D4h)
Read
110101
1
1
11010111 (D7h)
Write
110101
1
0
11010110 (D6h)
Table 11. Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
Slave
SAK
DATA
SP
SAK
SAK
Table 12. Transfer when master is writing multiple bytes to slave
Master
ST
SAD + W
SUB
Slave
SAK
DATA
SAK
DATA
SAK
SP
SAK
Table 13. Transfer when master is receiving (reading) one byte of data from slave
Master
ST
SAD + W
Slave
SUB
SAK
SR
SAD + R
SAK
NMAK
SAK
SP
DATA
Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave
Master
ST
DS12140 - Rev 2
SAD+W
SUB
SR
SAD+R
MAK
MAK
NMAK
SP
page 18/172
LSM6DSO
I²C/SPI interface
Slave
SAK
SAK
SAK
DATA
DATA
DATA
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred
per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive
another complete byte of data until it has performed some other function, it can hold the clock line, SCL LOW to
force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and
releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive
because it is performing some real-time function) the data line must be left HIGH by the slave. The master can
then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a
STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition.
In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge.
DS12140 - Rev 2
page 19/172
LSM6DSO
I²C/SPI interface
5.1.2
SPI bus interface
The LSM6DSO SPI is a bus slave. The SPI allows writing and reading the registers of the device.
The serial interface communicates to the application using 4 wires: CS, SPC, SDI and SDO.
Figure 7. Read and write protocol (in mode 3)
CS
SPC
SDI
RW
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and
goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high
when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those
lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC.
Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case
of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at
the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling
edge of SPC just before the rising edge of CS.
bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is
read. In latter case, the chip will drive SDO at the start of bit 8.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first).
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
In multiple read/write commands further blocks of 8 clock periods will be added. When the CTRL3_C (12h)
(IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL3_C
(12h) (IF_INC) bit is ‘1’, the address used to read/write data is increased at every block.
The function and the behavior of SDI and SDO remain unchanged.
SPI read
Figure 8. SPI read protocol (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
The SPI Read command is performed with 16 clock pulses. A multiple byte read command is performed by
adding blocks of 8 clock pulses to the previous one.
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first).
bit 16-...: data DO(...-8). Further data in multiple byte reads.
DS12140 - Rev 2
page 20/172
LSM6DSO
I²C/SPI interface
Figure 9. Multiple byte SPI read protocol (2-byte example) (in mode 3)
CS
SPC
SDI
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SDO
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14DO13DO12 DO11DO10 DO9 DO8
SPI write
Figure 10. SPI write protocol (in mode 3)
CS
SPC
SDI
RW
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI Write command is performed with 16 clock pulses. A multiple byte write command is performed by
adding blocks of 8 clock pulses to the previous one.
bit 0: WRITE bit. The value is 0.
bit 1 -7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first).
bit 16-... : data DI(...-8). Further data in multiple byte writes.
Figure 11. Multiple byte SPI write protocol (2-byte example) (in mode 3)
CS
SPC
SDI
DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
SPI read in 3-wire mode
A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode
selection).
DS12140 - Rev 2
page 21/172
LSM6DSO
I²C/SPI interface
Figure 12. SPI read protocol in 3-wire mode (in mode 3)
CS
SPC
SDI/O
DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
RW
AD6 AD5 AD4 AD3 AD2 AD1 AD0
The SPI read command is performed with 16 clock pulses:
bit 0: READ bit. The value is 1.
bit 1-7: address AD(6:0). This is the address field of the indexed register.
bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first).
A multiple read command is also available in 3-wire mode.
DS12140 - Rev 2
page 22/172
LSM6DSO
MIPI I3CSM interface
5.2
MIPI I3CSM interface
5.2.1
MIPI I3CSM slave interface
The LSM6DSO interface includes a MIPI I3CSM SDR only slave interface (compliant with release 1.0 of the
specification) with MIPI I3CSM SDR embedded features:
•
CCC command
•
Direct CCC communication (SET and GET)
•
Broadcast CCC communication
•
Private communications
•
Private read and write for single byte
•
Multiple read and write
•
In-Band Interrupt request
Error Detection and Recovery Methods (S0-S6)
Note:
Refer to Section 5.3 I²C/I3C coexistence in LSM6DSO for details concerning the choice of the interface when
powering up the device.
5.2.2
MIPI I3CSM CCC supported commands
The list of MIPI I3CSM CCC commands supported by the device is detailed in the following table.
Table 15. MIPI I3CSM CCC commands
Command
Command code
Default
Description
ENTDAA
0x07
DAA procedure
SETDASA
0x87
Assign Dynamic Address using Static Address 0x6B/0x6A depending on SDO pin
ENEC
0x80 / 0x00
Slave activity control (direct and broadcast)
DISEC
0x81/ 0x01
Slave activity control (direct and broadcast)
ENTAS0
0x82 / 0x02
Enter activity state (direct and broadcast)
ENTAS1
0x83 / 0x03
Enter activity state (direct and broadcast)
ENTAS2
0x84 / 0x04
Enter activity state (direct and broadcast)
ENTAS3
0x85 / 0x05
Enter activity state (direct and broadcast)
SETXTIME
0x98 / 0x28
Timing information exchange
0x07
GETXTIME
0x99
0x00
0x05
Timing information exchange
0x92
RSTDAA
0x86 / 0x06
Reset the assigned dynamic address (direct and broadcast)
SETMWL
0x89 / 0x08
Define maximum write length during private write (direct and broadcast)
SETMRL
0x8A / 0x09
Define maximum read length during private read (direct and broadcast)
SETNEWDA
0x88
Change dynamic address
0x00
GETMWL
0x8B
0x08
Get maximum write length during private write
(2 byte)
DS12140 - Rev 2
page 23/172
LSM6DSO
MIPI I3CSM interface
Command
Command code
Default
Description
0x00
GETMRL
0x8C
0x10
0x09
Get maximum read length during private read
(3 byte)
0x02
0x08
GETPID
0x8D
0x00
0x6C
Device ID register
0x10
0x0B
GETBCR
0x8E
GETDCR
0x8F
0x07
(1 byte)
0x44 default
Bus characteristics register
MIPI I3CSM Device Characteristic Register
0x00
GETSTATUS
0x90
0x00
Status register
(2 byte)
0x00
GETMXDS
0x94
0x20
Return max data speed
(2 byte)
DS12140 - Rev 2
page 24/172
LSM6DSO
I²C/I3C coexistence in LSM6DSO
5.3
I²C/I3C coexistence in LSM6DSO
In the LSM6DSO, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters
on the SDA and SCL pins that are not compatible with I3C timing.
The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1
pin when the device is powered up:
•
INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 13
•
INT1 pin connected to VDD_IO: only I3C active, see Figure 14
Figure 13. I²C and I3C both active (INT1 pin not connected)
1.
Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave
is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications.
Figure 14. Only I3C active (INT1 pin connected to VDD_IO)
1.
DS12140 - Rev 2
When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR
timing.
page 25/172
LSM6DSO
Master I²C interface
5.4
Master I²C interface
If the LSM6DSO is configured in Mode 2, a master I²C line is available. The master serial interface is mapped in
the following dedicated pins.
Table 16. Master I²C pin details
Pin name
MSCL
I²C serial clock master
MSDA
I²C serial data master
MDRDY
5.5
Pin description
I²C master external synchronization signal
Auxiliary SPI interface
If the LSM6DSO is configured in Mode 3 or Mode 4, the auxiliary SPI is available. The auxiliary SPI interface is
mapped to the following dedicated pins.
Table 17. Auxiliary SPI pin details
Pin name
OCS_Aux
Pin description
Auxiliary SPI 3/4-wire enable
SDx
Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux)
SCx
Auxiliary SPI 3/4-wire interface serial port clock
SDO_Aux
Auxiliary SPI 4-wire data output (SDO_Aux)
When the LSM6DSO is configured in Mode 3 or Mode 4, the auxiliary SPI can be connected to a camera module
for OIS/EIS support. In this configuration, the auxiliary SPI can write only to the dedicated registers INT_OIS
(6Fh), CTRL1_OIS (70h), CTRL2_OIS (71h), CTRL3_OIS (72h). All the registers are accessible in Read mode
from both the primary interface and auxiliary SPI.
Mode 3 is enabled when the OIS_EN_SPI2 bit in CTRL1_OIS (70h) register is set to 1.
Mode 4 is enabled when both the OIS_EN_SPI2 bit and the Mode4_EN bit in CTRL1_OIS (70h) register are set
to 1.
DS12140 - Rev 2
page 26/172
LSM6DSO
Functionality
6
Functionality
6.1
Operating modes
In the LSM6DSO, the accelerometer and the gyroscope can be turned on/off independently of each other and are
allowed to have different ODRs and power modes.
The LSM6DSO has three operating modes available:
•
only accelerometer active and gyroscope in power-down
•
only gyroscope active and accelerometer in power-down
•
both accelerometer and gyroscope sensors active with independent ODR
The accelerometer is activated from power-down by writing ODR_XL[3:0] in CTRL1_XL (10h) while the gyroscope
is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h). For combo mode the ODRs are totally
independent.
6.2
Accelerometer power modes
In the LSM6DSO, the accelerometer can be configured in five different operating modes: power-down, ultra-lowpower, low-power, normal mode and high-performance mode. The operating mode selected depends on the value
of the XL_HM_MODE bit in CTRL6_C (15h). If XL_HM_MODE is set to '0', high-performance mode is valid for all
ODRs (from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Low-power mode is
available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and
208 Hz.
6.2.1
Accelerometer ultra-low-power mode
The LSM6DSO can be configured in ultra-low-power (ULP) mode by setting the XL_ULP_EN bit to 1 in CTRL5_C
(14h) register. This mode can be used in accelerometer-only mode (gyroscope sensor must be configured in
power-down mode) and for ODR_XL values between 1.6 Hz and 208 Hz.
When ULP mode is intended to be used, the bit XL_HM_MODE must be set to 0.
When ULP mode is switched ON/OFF, the accelerometer must be configured in power-down condition.
ULP mode cannot be used in Mode 3 or Mode 4 connection modes.
The embedded functions based on accelerometer data (free-fall, 6D/4D, tap, double tap, wake-up, activity/
inactivity, stationary/motion, step counter, step detection, significant motion, tilt) and the FIFO batching
functionality are still supported when ULP mode is enabled.
6.3
Gyroscope power modes
In the LSM6DSO, the gyroscope can be configured in four different operating modes: power-down, low-power,
normal mode and high-performance mode. The operating mode selected depends on the value of the
G_HM_MODE bit in CTRL7_G (16h). If G_HM_MODE is set to '0', high-performance mode is valid for all ODRs
(from 12.5 Hz up to 6.66 kHz).
To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Low-power mode is
available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz.
DS12140 - Rev 2
page 27/172
LSM6DSO
Block diagram of filters
6.4
Block diagram of filters
Figure 15. Block diagram of filters
M
E
M
S
S
E
N
S
O
R
Gyro UI/OIS
front-end
ADC1
Regs
array,
FIFO
Low Pass
UI XL
XL UI/OIS
front-end
Low Pass
OIS Gyro
ADC2
Temperature
sensor
Voltage and current
references
6.4.1
Low Pass
UI Gyro
Regs
array
Low Pass
OIS XL
Trimming circuit
and Test interface
Clock and phase
generator
Power
management
I2C/ MIPI I3CSM
/SPI
interface
Interrupt
mng
CS
SCL/SPC
SDA/SDI/SDO
SDO/SA0
INT1
INT2
Interrupt
mng
Auxiliary
SPI
CS
SPC_Aux
SDI_Aux
SDO_Aux
FTP
Block diagrams of the accelerometer filters
In the LSM6DSO, the filtering chain for the accelerometer part is composed of the following:
•
Analog filter (anti-aliasing)
•
Digital filter (LPF1)
•
Composite filter
Details of the block diagram appear in the following figure.
Figure 16. Accelerometer UI chain
Analog
Anti-aliasing
LP Filter
Digital
LP Filter
LPF1
ADC
Composite
Filter
ODR_XL[3:0]
DS12140 - Rev 2
page 28/172
LSM6DSO
Block diagram of filters
Figure 17. Accelerometer composite filter
LOW_PASS_ON_6D
Free-fall
0
Advanced
functions
1
LPF2_XL_EN
USR_OFF_ON_OUT
HP_SLOPE_XL_EN
0
0
Digital
LP Filter
1
LPF1
output (1)
0
USER
OFFSET
LPF2
1
USR_OFF_W
OFS_USR[7:0]
FIFO
HPCF_XL[2:0]
Digital
HP Filter
6D / 4D
1
1
0
0
Wake-up
Activity /
Inactivity
SPI /
I 2C /
MIPI I3C SM
USR_OFF_ON_WU SLOPE_FDS
001
010
…
111
1
HPCF_XL[2:0]
SLOPE
FILTER
000
HPCF_XL[2:0]
S/D Tap
1.
Note:
The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode. This
value is equal to 700 Hz when the accelerometer is in low-power or normal mode.
Advanced functions include pedometer, step detector and step counter, significant motion detection, and tilt
functions.
The accelerometer filtering chain when Mode 4 is enabled is illustrated in the following figure.
Figure 18. Accelerometer chain with Mode 4 enabled
Analog
Anti-aliasing
LP Filter
Digital
LP Filter
ODR XL
@6.6 kHz
LPF_OIS
ADC
SPI_Aux
FILTER_XL_CONF_OIS[2:0]
UI chain
DS12140 - Rev 2
page 29/172
LSM6DSO
Block diagram of filters
Note:
6.4.2
Mode 4 is enabled when Mode4_EN = 1 and OIS_EN_SPI2 = 1 in CTRL1_OIS (70h).
The configuration of the accelerometer UI chain is not affected by enabling Mode 4.
Accelerometer output values are in registers OUTX_L_A (28h) and OUTX_H_A (29h) through not found and ODR
at 6.66 kHz.
Accelerometer full-scale management between the UI chain and OIS chain depends on the setting of the
XL_FS_MODE bit in register CTRL8_XL (17h).
Block diagrams of the gyroscope filters
In the LSM6DSO, the gyroscope filtering chain depends on the mode configuration:
•
Mode 1 (for User Interface (UI) and Electronic Image Stabilization (EIS) functionality through primary
interface) and Mode 2
Figure 19. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2
ADC
SPI/
I2C/
MIPI I3CSM
0
0
LPF2
HPF
1
LPF1
1
FIFO
ODR_G[3:0]
HP_EN_G
FTYPE [2:0]
LPF1_SEL_G
In this configuration, the gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is
available if the auxiliary SPI is disabled, for more details about the filter characteristics see Table 60. Gyroscope
LPF1 bandwidth selection.
The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on the selected
gyroscope ODR, as indicated in the following table.
Table 18. Gyroscope LPF2 bandwidth selection
Note:
DS12140 - Rev 2
Gyroscope ODR [Hz]
LPF2 cutoff [Hz]
12.5
4.2
26
8.3
52
16.6
104
33.0
208
66.8
417
135.9
833
295.5
1667
1108.1
3333
1320.7
6667
1441.8
Data can be acquired from the output registers and FIFO over the primary I²C/I³C/SPI interface.
page 30/172
LSM6DSO
Block diagram of filters
•
Mode 3 / Mode 4 (for OIS and EIS functionality)
Figure 20. Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS)
Digital
LP Filter
LPF2
(3)
HP_EN_G
ADC
0
Digital
HP Filter
FIFO
1
ODR_G[3:0]
SPI / I2C /
MIPI I3CSM
HP_EN_OIS
1
(3)
Digital(1) (2)
LP Filter
LPF1
SPI_Aux
0
ODR Gyro
@6.6 kHz
FTYPE[1:0]_OIS
1.
2.
3.
When Mode3/4 is enabled, the LPF1 filter is not available in the gyroscope UI chain.
It is recommended to avoid using the LPF1 filter in Mode1/2 when Mode3/4 is intended to be used.
HP_EN_OIS can be used to select the HPF on the OIS path only if the HPF is not used in the UI chain. If
both the HP_EN_G bit and HP_EN_OIS bit are set to 1, the HP filter is applied to the UI chain only.
The auxiliary interface needs to be enabled in CTRL1_OIS (70h).
In Mode 3/4 configuration, there are two paths:
•
the chain for User Interface (UI) where the ODR is selectable from 12.5 Hz up to 6.66 kHz
•
the chain for OIS/EIS where the ODR is at 6.66 kHz and the LPF1 is available. The LPF1 configuration
depends on the setting of the FTYPE_[1;0] _OIS bit in register CTRL2_OIS (71h); for more details about the
filter characteristics see Table 151. Gyroscope OIS chain digital LPF1 filter bandwidth selection. Gyroscope
output values are in registers 22h to 27h with the selected full scale (FS[1:0]_G_OIS bit in CTRL1_OIS
(70h)).
DS12140 - Rev 2
page 31/172
LSM6DSO
FIFO
6.5
FIFO
The presence of a FIFO allows consistent power saving for the system since the host processor does not need
continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out
from the FIFO.
The LSM6DSO embeds 3 kbytes of data in FIFO (up to 9 kbytes with the compression feature enabled) to store
the following data:
•
Gyroscope
•
Accelerometer
•
External sensors (up to 4)
•
Step counter
•
Timestamp
•
Temperature
Writing data in the FIFO can be configured to be triggered by the:
•
Accelerometer / gyroscope data-ready signal
•
Sensor hub data-ready signal
•
Step detection signal
The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFOdedicated configurations: accelerometer, gyroscope and temperature sensor batching rates can be selected by
the user. External sensor writing in FIFO can be triggered by the accelerometer data-ready signal or by an
external sensor interrupt. The step counter can be stored in FIFO with associated timestamp each time a step is
detected. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32.
The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows
recognizing the meaning of a word in FIFO.
FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the
ODR or BDR (Batching Data Rate) configuration is performed, the application can correctly reconstruct the
timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores
information of the new configuration and timestamp in which the change was applied in the device.
Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbytes of data
stored in FIFO and take advantage of interface communication length for FIFO flushing and communication power
consumption.
The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the
WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh))
can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the
number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of
these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh).
The FIFO buffer can be configured according to six different modes:
•
Bypass mode
•
FIFO mode
•
Continuous mode
•
Continuous-to-FIFO mode
•
Bypass-to-continuous mode
•
Bypass-to-FIFO mode
Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register.
6.5.1
Bypass mode
In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains
empty. Bypass mode is also used to reset the FIFO when in FIFO mode.
DS12140 - Rev 2
page 32/172
LSM6DSO
FIFO
6.5.2
FIFO mode
In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the
FIFO until it is full.
To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to
'000'. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah)
(FIFO_MODE_[2:0]) to '001'.
The FIFO buffer memorizes up to 9 kBytes of data (with compression enabled) but the depth of the FIFO can be
resized by setting the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in
FIFO_CTRL2 (08h) is set to '1', FIFO depth is limited up to the WTM [8:0] bits in FIFO_CTRL1 (07h) and
FIFO_CTRL2 (08h).
6.5.3
Continuous mode
Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new
data arrives, the older data is discarded.
A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in
FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)(WTM [8:0]).
It is possible to route the FIFO_WTM_IA flag to FIFO_CTRL2 (08h) to the INT1 pin by writing in register
INT1_CTRL (0Dh)(INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL (0Eh)
(INT2_FIFO_TH) = '1'.
A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh)
(INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once.
If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag
in FIFO_STATUS2 (3Bh) is asserted.
In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples
available inFIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]).
6.5.4
Continuous-to-FIFO mode
In Continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according
to the trigger event detected in one of the following interrupt events:
•
Single tap
•
Double tap
•
Wake-up
•
Free-fall
•
D6D
When the selected trigger bit is equal to '1', FIFO operates in FIFO mode.
When the selected trigger bit is equal to '0', FIFO operates in Continuous mode.
6.5.5
Bypass-to-Continuous mode
In Bypass-to-Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '100'), data measurement storage
inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset
(Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
•
Single tap
•
Double tap
•
Wake-up
•
Free-fall
•
D6D
DS12140 - Rev 2
page 33/172
LSM6DSO
FIFO
6.5.6
Bypass-to-FIFO mode
In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO
operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode).
FIFO behavior changes according to the trigger event detected in one of the following interrupt events:
•
Single tap
•
Double tap
•
Wake-up
•
Free-fall
•
D6D
6.5.7
FIFO reading procedure
The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes:
one tag byte (FIFO_DATA_OUT_TAG (78h), in order to identify the sensor, and 6 bytes of fixed data
(FIFO_DATA_OUT registers from (79h) to (7Eh)).
The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number
of words (1 byte TAG + 6 bytes DATA) collected in FIFO.
In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The
flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter reaches a selectable threshold
(CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows
triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the
TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag
COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits
(INT1_CNT_BDR of INT1_CTRL (0Dh) and INT2_CNT_BDR of INT2_CTRL (0Eh)).
In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the
compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded
functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is
enabled, it is also possible to force writing non-compressed data at a selectable rate using the
UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h).
Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling
the ODR_CHG_EN bit in FIFO_CTRL2 (08h).
DS12140 - Rev 2
page 34/172
LSM6DSO
Application hints
7
Application hints
7.1
LSM6DSO electrical connections in Mode 1
Figure 21. LSM6DSO electrical connections in Mode 1
CS
SCL
SDA
Mode 1
HOST
14
12
I 2C /
SM
SDO/SA0
TOP
VIEW
SDx
SCx
4
INT1
8
C2
7
GND
VDDIO
5
NC
NC
GND
GND or VDDIO
11
1
MIPI I3C /
SPI (3/4-w)
(1)
(1)
LSM6DSO
Vdd
INT2
VDD
C1
100 nF
I2C configuration
GND
Vdd_IO
Rpu
Vdd_IO
100 nF
GND
Rpu
SCL
SDA
Pull-up to be added
Rpu=10kOhm
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible
through the SPI/I²C/MIPI I3CSM interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM interface.
DS12140 - Rev 2
page 35/172
LSM6DSO
LSM6DSO electrical connections in Mode 2
7.2
LSM6DSO electrical connections in Mode 2
Figure 22. LSM6DSO electrical connections in Mode 2
HOST
CS
SCL
SDA
Mode 2
I 2C /
SM
14
SDO/SA0
1
12
11
TOP
VIEW
MSDA
MSCL
8
C2
GND
7
GND
VDDIO
5
NC
NC
4
INT1
MIPI I3C /
SPI (3/4-w)
LSM6DSO
(1)
(1)
Master I2C
MDRDY/INT2
Vdd
LSM6DSM
External
LSM6DSM
sensors
VDD
C1
100 nF
I2C configuration
GND
Vdd_IO
Rpu
Vdd_IO
100 nF
GND
Rpu
SCL
SDA
Pull-up to be added
Rpu=10kOhm
1.
Leave pin electrically unconnected and soldered to PCB.
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device and the measured acceleration/angular rate data is selectable and accessible
through the SPI/I²C/MIPI I3CSM primary interface.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM primary interface.
DS12140 - Rev 2
page 36/172
LSM6DSO
LSM6DSO electrical connections in Mode 3 and Mode 4
7.3
LSM6DSO electrical connections in Mode 3 and Mode 4
SPC
CS
SDI
Figure 23. LSM6DSO electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI)
Mode 3
Mode 4
HOST
HOST
I 2C /
I 2C /
SM
14
SDO
SDI_Aux
1
11
TOP
VIEW
SPC_Aux
INT1
8
VDD
GND
MIPI I3C /
SPI (3/4-w)
LSM6DSO
LSM6DSO
OCS_Aux
Vdd
7
GND
VDDIO
5
(1)
NC
INT2
4
SM
MIPI I3C /
SPI (3/4-w)
12
C1
Aux SPI (3-w)
For gyro
data only
Aux SPI (3-w)
For XL and
gyro data
Camera
module
Camera
module
100 nF
I2C configuration
GND
Vdd_IO
C2
Vdd_IO
100 nF
GND
Rpu
Rpu
SCL
SDA
Pull-up to be added
Rpu=10kOhm
1.
Note:
Leave pin electrically unconnected and soldered to PCB.
When Mode 3 and 4 are used, the pull-up on pins 10 and 11 can be disabled (refer to Table 19. Internal pin
status). To avoid leakage current, it is recommended to not leave the SPI lines floating (also when the OIS
system is off).
The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic)
should be placed as near as possible to the supply pin of the device (common design practice).
The functionality of the device is selectable and accessible through the SPI/I²C/MIPI I3CSM primary interface.
Measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3CSM primary
interface and auxiliary SPI.
The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely
programmed by the user through the SPI/I²C/MIPI I3CSM interface.
DS12140 - Rev 2
page 37/172
DS12140 - Rev 2
Table 19. Internal pin status
pin#
Name
Mode 1 function
Mode 2 function
Mode 3 / Mode 4 function
SDO
SPI 4-wire interface serial
data output (SDO)
SPI 4-wire interface serial
data output (SDO)
SPI 4-wire interface serial
data output (SDO)
I²C least significant bit of
the device address (SA0)
I²C least significant bit of
the device address (SA0)
I²C least significant bit of
the device address (SA0)
MIPI I3CSM least significant
bit of the static address
(SA0)
MIPI I3CSM least significant
bit of the static address
(SA0)
MIPI I3CSM least significant
bit of the static address
(SA0)
Connect to VDDIO or GND
I²C serial data master
(MSDA)
Auxiliary SPI 3/4-wire
interface serial data input
(SDI) and SPI 3-wire serial
data output (SDO)
Auxiliary SPI 3/4-wire
interface serial port clock
(SPC_Aux)
1
SA0
2
SDx
SCx
Connect to VDDIO or GND
4
INT1
Programmable interrupt 1 /
If device is used as MIPI
I3CSM pure slave, this pin
must be set to ‘1’.
Programmable interrupt 1 /
If device is used as MIPI
I3CSM pure slave, this pin
must be set to ‘1’.
Programmable interrupt 1 /
If device is used as MIPI
I3CSM pure slave, this pin
must be set to ‘1’.
5
VDDIO
Power supply for I/O pins
Power supply for I/O pins
Power supply for I/O pins
6
GND
0 V supply
0 V supply
0 V supply
7
GND
0 V supply
0 V supply
0 V supply
8
VDD
Power supply
Power supply
Power supply
9
INT2
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
Programmable interrupt 2
(INT2) / Data enabled
(DEN) / I²C master external
synchronization signal
(MDRDY)
Programmable interrupt 2
(INT2) / Data enabled
(DEN)
10
OCS_Aux
Leave unconnected
Leave unconnected
Auxiliary SPI 3/4-wire
interface enabled
11
SDO_Aux
Connect to VDDIO or leave
unconnected
Connect to VDDIO or leave
unconnected
Auxiliary SPI 3-wire
interface: leave
unconnected / Auxiliary SPI
4-wire interface: serial data
output (SDO_Aux)
I²C/SPI mode selection
I²C/SPI mode selection
I²C/SPI mode selection
(1:SPI idle mode / I²C
communication enabled;
(1:SPI idle mode / I²C
communication enabled;
(1:SPI idle mode / I²C
communication enabled;
0: SPI communication
mode / I²C disabled)
0: SPI communication
mode / I²C disabled)
0: SPI communication
mode / I²C disabled)
12
CS
Pin status Mode 2
Pin status Mode 3/4 (1)
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Pull-up is enabled if bit
SDO_PU_EN = 1 in reg 02h.
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up).
Pull-up is enabled if bit
SHUB_PU_EN = 1 in reg 14h in
sensor hub registers (see Note to
enable pull-up)
Default: input with pull-down(2)
Default: input with pull-down(2)
Default: input with pull-down(2)
Default: output forced to ground
Default: output forced to ground
Default: output forced to ground
Default: input with pull-up
Default: input with pull-up
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Default: input without pull-up
(regardless of the value of bit
OIS_PU_DIS in reg 02h.)
Default: input with pull-up
Default: input with pull-up
Default: input with pull-up
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Pull-up is disabled if bit
OIS_PU_DIS = 1 in reg 02h.
Pull-up is enabled if bit SIM_OIS = 1
(Aux_SPI 3-wire) in reg 70h and bit
OIS_PU_DIS = 0 in reg 02h.
Default: input with pull-up
Default: input with pull-up
Default: input with pull-up
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
Pull-up is disabled if bit
I2C_disable = 1 in reg 13h and
I3C_disable = 1 in reg 18h.
LSM6DSO
page 38/172
3
I²C serial clock master
(MSCL)
Pin status Mode 1
DS12140 - Rev 2
pin#
Name
Mode 1 function
Mode 2 function
Mode 3 / Mode 4 function
Pin status Mode 1
Pin status Mode 2
Pin status Mode 3/4 (1)
13
SCL
I²C/MIPI I3CSM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3CSM serial clock
(SCL) / SPI serial port clock
(SPC)
I²C/MIPI I3CSM serial clock
(SCL) / SPI serial port clock
(SPC)
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
SDA
I²C/MIPI I3CSM serial data
(SDA) / SPI serial data
input (SDI) / 3-wire
interface serial data output
(SDO)
I²C/MIPI I3CSM serial data
(SDA) / SPI serial data
input (SDI) / 3-wire
interface serial data output
(SDO)
I²C/MIPI I3CSM serial data
(SDA) / SPI serial data
input (SDI) / 3-wire
interface serial data output
(SDO)
Default: input without pull-up
Default: input without pull-up
Default: input without pull-up
14
1. Mode 3 is enabled when the OIS_EN_SPI2 bit in the CTRL1_OIS (70h) register is set to 1. Mode 4 is enabled when both the OIS_EN_SPI2 bit and
the Mode4_EN bit in the CTRL1_OIS (70h) register are set to 1.
2. INT1 must be set to '0' or left unconnected during power-on if the I²C/SPI interfaces are used.
Internal pull-up value is from 30 kΩ to 50 kΩ, depending on VDDIO.
Note:
The procedure to enable the pull-up on pins 2 and 3 is as follows:
1. From the primary I²C/I³C/SPI interface: write 40h in register at address 01h (enable access to the sensor hub registers)
2. From the primary I²C/I³C/SPI interface: write 08h in register at address 14h (enable the pull-up on pins 2 and 3)
3. From the primary I²C/I³C/SPI interface: write 00h in register at address 01h (disable access to the sensor hub registers)
LSM6DSO
page 39/172
LSM6DSO
Register mapping
8
Register mapping
The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding
addresses.
Table 20. Registers address map
Name
Type
FUNC_CFG_ACCESS
RW
PIN_CTRL
Register address
Default
Hex
Binary
01
00000001
00000000
00000010
00111111
Comment
RW
02
RESERVED
-
03-06
FIFO_CTRL1
RW
07
00000111
00000000
FIFO_CTRL2
RW
08
00001000
00000000
FIFO_CTRL3
RW
09
00001001
00000000
FIFO_CTRL4
RW
0A
00001010
00000000
COUNTER_BDR_REG1
RW
0B
00001011
00000000
COUNTER_BDR_REG2
RW
0C
00001100
00000000
INT1_CTRL
RW
0D
00001101
00000000
INT2_CTRL
RW
0E
00001110
00000000
WHO_AM_I
R
0F
00001111
01101100
R (SPI2)
CTRL1_XL
RW
10
00010000
00000000
R (SPI2)
CTRL2_G
RW
11
00010001
00000000
R (SPI2)
CTRL3_C
RW
12
00010010
00000100
R (SPI2)
CTRL4_C
RW
13
00010011
00000000
R (SPI2)
CTRL5_C
RW
14
00010100
00000000
R (SPI2)
CTRL6_C
RW
15
00010101
00000000
R (SPI2)
CTRL7_G
RW
16
00010110
00000000
R (SPI2)
CTRL8_XL
RW
17
0001 0111
00000000
R (SPI2)
CTRL9_XL
RW
18
00011000
11100000
R (SPI2)
CTRL10_C
RW
19
00011001
00000000
R (SPI2)
ALL_INT_SRC
R
1A
00011010
output
WAKE_UP_SRC
R
1B
00011011
output
TAP_SRC
R
1C
00011100
output
R
1D
00011101
output
R
1E
00011110
output
RESERVED
-
1F
00011111
OUT_TEMP_L
R
20
00100000
output
OUT_TEMP_H
R
21
00100001
output
OUTX_L_G
R
22
00100010
output
OUTX_H_G
R
23
00100011
output
OUTY_L_G
R
24
00100100
output
D6D_SRC
STATUS_REG(1)
DS12140 - Rev 2
/
STATUS_SPIAux(2)
page 40/172
LSM6DSO
Register mapping
Name
Type
Register address
Hex
Binary
Default
Comment
OUTY_H_G
R
25
00100101
output
OUTZ_L_G
R
26
00100110
output
OUTZ_H_G
R
27
00100111
output
OUTX_L_A
R
28
00101000
output
OUTX_H_A
R
29
00101001
output
OUTY_L_A
R
2A
00101010
output
OUTY_H_A
R
2B
00101011
output
OUTZ_L_A
R
2C
00101100
output
OUTZ_H_A
R
2D
00101101
output
RESERVED
-
2E-34
EMB_FUNC_STATUS_MAINPAGE
R
35
00110101
output
FSM_STATUS_A_MAINPAGE
R
36
00110110
output
FSM_STATUS_B_MAINPAGE
R
37
00110111
output
RESERVED
-
38
STATUS_MASTER_MAINPAGE
R
39
00111001
output
FIFO_STATUS1
R
3A
00111010
output
FIFO_STATUS2
R
3B
00111011
output
RESERVED
-
3C-3F
TIMESTAMP0
R
40
01000000
output
R (SPI2)
TIMESTAMP1
R
41
01000001
output
R (SPI2)
TIMESTAMP2
R
42
01000010
output
R (SPI2)
TIMESTAMP3
R
43
01000011
output
R (SPI2)
RESERVED
-
44-55
TAP_CFG0
RW
56
01010110
00000000
TAP_CFG1
RW
57
01010111
00000000
TAP_CFG2
RW
58
01011000
00000000
TAP_THS_6D
RW
59
01011001
00000000
INT_DUR2
RW
5A
01011010
00000000
WAKE_UP_THS
RW
5B
01011011
00000000
WAKE_UP_DUR
RW
5C
01011100
00000000
FREE_FALL
RW
5D
01011101
00000000
MD1_CFG
RW
5E
01011110
00000000
MD2_CFG
RW
5F
01011111
00000000
-
60-61
RW
62
01100010
00000000
INTERNAL_FREQ_FINE
R
63
01100011
output
RESERVED
-
64-6E
INT_OIS
R
6F
01101111
00000000
RW (SPI2)
CTRL1_OIS
R
70
01110000
00000000
RW (SPI2)
RESERVED
I3C_BUS_AVB
DS12140 - Rev 2
00000000
page 41/172
LSM6DSO
Register mapping
Name
Type
Register address
Hex
Binary
Default
Comment
CTRL2_OIS
R
71
01110001
00000000
RW (SPI2)
CTRL3_OIS
R
72
01110010
00000000
RW (SPI2)
X_OFS_USR
RW
73
01110011
00000000
Y_OFS_USR
RW
74
01110100
00000000
Z_OFS_USR
RW
75
01110101
00000000
RESERVED
-
76-77
FIFO_DATA_OUT_TAG
R
78
01111000
output
FIFO_DATA_OUT_X_L
R
79
01111001
output
FIFO_DATA_OUT_X_H
R
7A
01111010
output
FIFO_DATA_OUT_Y_L
R
7B
01111011
output
FIFO_DATA_OUT_Y_H
R
7C
01111100
output
FIFO_DATA_OUT_Z_L
R
7D
01111101
output
FIFO_DATA_OUT_X_H
R
7E
01111110
output
1. This register status is read using the primary interface for user interface data.
2. This register status is read using the auxiliary SPI for OIS data.
DS12140 - Rev 2
page 42/172
LSM6DSO
Register description
9
Register description
The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration,
angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to
write the data through the serial interface.
9.1
FUNC_CFG_ACCESS (01h)
Enable embedded functions register (r/w)
Table 21. FUNC_CFG_ACCESS register
FUNC_CFG_
ACCESS
SHUB_REG
ACCESS
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 22. FUNC_CFG_ACCESS register description
FUNC_CFG_ACCESS
SHUB_REG_ACCESS
Enable access to the embedded functions configuration registers.(1)
Default value: 0
Enable access to the sensor hub (I²C master) registers.(2)
Default value: 0
1. Details concerning the embedded functions configuration registers are available in Section 10 Embedded functions register
mapping and Section 11 Embedded functions register description.
2. Details concerning the sensor hub registers are available in Section 14 Sensor hub register mapping and Section 15 Sensor
hub register description.
9.2
PIN_CTRL (02h)
SDO, OCS_AUX, SDO_AUX pins pull-up enable/disable register (r/w)
Table 23. PIN_CTRL register
OIS_
PU_DIS
SDO_
PU_EN
1
1
1
1
1
1
Table 24. PIN_CTRL register description
Disable pull-up on both OCS_Aux and SDO_Aux pins. Default value: 0
OIS_PU_DIS
(0: OCS_Aux and SDO_Aux pins with pull-up;
1: OCS_Aux and SDO_Aux pins pull-up disconnected)
SDO_PU_EN
DS12140 - Rev 2
Enable pull-up on SDO pin
(0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up)
page 43/172
LSM6DSO
FIFO_CTRL1 (07h)
9.3
FIFO_CTRL1 (07h)
FIFO control register 1 (r/w)
Table 25. FIFO_CTRL1 register
WTM7
WTM6
WTM5
WTM4
WTM3
WTM2
WTM1
WTM0
Table 26. FIFO_CTRL1 register description
FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h)
WTM[7:0] 1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level.
9.4
FIFO_CTRL2 (08h)
FIFO control register 2 (r/w)
Table 27. FIFO_CTRL2 register
STOP_ON
_WTM
FIFO_
COMPR_
RT_EN
0
ODRCHG
_EN
0
UNCOPTR_
RATE_1
UNCOPTR_
RATE_0
WTM8
Table 28. FIFO_CTRL2 register description
Sensing chain FIFO stop values memorization at threshold level
STOP_ON_WTM
(0: FIFO depth is not limited (default);
1: FIFO depth is limited to threshold level, defined in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h))
FIFO_COMPR_RT_EN(1)
Enables/Disables compression algorithm runtime
ODRCHG_EN
Enables ODR CHANGE virtual sensor to be batched in FIFO
This field configures the compression algorithm to write non-compressed data at each rate.
(0: Non-compressed data writing is not forced;
UNCOPTR_RATE_[1:0]
1: Non-compressed data every 8 batch data rate;
2: Non-compressed data every 16 batch data rate;
3: Non-compressed data every 32 batch data rate)
FIFO watermark threshold, in conjunction with WTM_FIFO[7:0] in FIFO_CTRL1 (07h)
WTM8
1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO
Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the
threshold level.
1. This bit is effective if the FIFO_COMPR_EN bit of EMB_FUNC_EN_B (05h) is set to 1.
DS12140 - Rev 2
page 44/172
LSM6DSO
FIFO_CTRL3 (09h)
9.5
FIFO_CTRL3 (09h)
FIFO control register 3 (r/w)
Table 29. FIFO_CTRL3 register
BDR_GY_3
BDR_GY_2
BDR_GY_1
BDR_GY_0
BDR_XL_3
BDR_XL_2
BDR_XL_1
BDR_XL_0
Table 30. FIFO_CTRL3 register description
Selects Batching Data Rate (writing frequency in FIFO) for gyroscope data.
(0000: Gyro not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
BDR_GY_[3:0]
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011: 6.5 Hz;
1100-1111: not allowed)
Selects Batching Data Rate (writing frequency in FIFO) for accelerometer data.
(0000: Accelerometer not batched in FIFO (default);
0001: 12.5 Hz;
0010: 26 Hz;
0011: 52 Hz;
0100: 104 Hz;
BDR_XL_[3:0]
0101: 208 Hz;
0110: 417 Hz;
0111: 833 Hz;
1000: 1667 Hz;
1001: 3333 Hz;
1010: 6667 Hz;
1011: 1.6 Hz;
1100-1111: not allowed)
DS12140 - Rev 2
page 45/172
LSM6DSO
FIFO_CTRL4 (0Ah)
9.6
FIFO_CTRL4 (0Ah)
FIFO control register 4 (r/w)
Table 31. FIFO_CTRL4 register
DEC_TS_
BATCH_1
DEC_TS_
BATCH_0
ODR_T_
BATCH_1
ODR_T_
BATCH_0
0
FIFO_
MODE2
FIFO_
MODE1
FIFO_
MODE0
Table 32. FIFO_CTRL4 register description
Selects decimation for timestamp batching in FIFO. Writing rate will be the maximum rate between
XL and GYRO BDR divided by decimation decoder.
(00: Timestamp not batched in FIFO (default);
DEC_TS_BATCH_[1:0]
01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz];
10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz];
11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz])
Selects batching data rate (writing frequency in FIFO) for temperature data
(00: Temperature not batched in FIFO (default);
ODR_T_BATCH_[1:0]
01: 1.6 Hz;
10: 12.5 Hz;
11: 52 Hz)
FIFO mode selection
(000: Bypass mode: FIFO disabled;
001: FIFO mode: stops collecting data when FIFO is full;
010: Reserved;
FIFO_MODE[2:0]
011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode;
100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode;
101: Reserved;
110: Continuous mode: if the FIFO is full, the new sample overwrites the older one;
111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.)
DS12140 - Rev 2
page 46/172
LSM6DSO
COUNTER_BDR_REG1 (0Bh)
9.7
COUNTER_BDR_REG1 (0Bh)
Counter batch data rate register 1 (r/w)
Table 33. COUNTER_BDR_REG1 register
dataready_
pulsed
RST_
COUNTER
TRIG_
COUNTER
_BDR
_BDR
0
0
CNT_BDR_
TH_10
CNT_BDR_
TH_9
CNT_BDR_
TH_8
Table 34. COUNTER_BDR_REG1 register description
Enables pulsed data-ready mode
dataready_pulsed
(0: Data-ready latched mode (returns to 0 only after an interface reading) (default);
1: Data-ready pulsed mode (the data ready pulses are 75 µs long)
RST_COUNTER_BDR
Resets the internal counter of batching events for a single sensor.
This bit is automatically reset to zero if it was set to ‘1’.
Selects the trigger for the internal counter of batching events between XL and gyro.
TRIG_COUNTER_BDR (0: XL batching event;
1: GYRO batching event)
CNT_BDR_TH_[10:8]
DS12140 - Rev 2
In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the
internal counter of batching events. When this counter reaches the threshold, the counter is reset
and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
page 47/172
LSM6DSO
COUNTER_BDR_REG2 (0Ch)
9.8
COUNTER_BDR_REG2 (0Ch)
Counter batch data rate register 2 (r/w)
Table 35. COUNTER_BDR_REG2 register
CNT_BDR_
TH_7
CNT_BDR_
TH_6
CNT_BDR_
TH_5
CNT_BDR_
TH_4
CNT_BDR_
TH_3
CNT_BDR_
TH_2
CNT_BDR_
TH_1
CNT_BDR_
TH_0
Table 36. COUNTER_BDR_REG2 register description
In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the
CNT_BDR_TH_[7:0] internal counter of batching events. When this counter reaches the threshold, the counter is reset and
the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’.
9.9
INT1_CTRL (0Dh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT1 when the MIPI I3CSM dynamic address is not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI (In-Band Interrupt) when the MIPI
I3CSM interface is used. The output of the pin will be the OR combination of the signals selected here and in
MD1_CFG (5Eh).
Table 37. INT1_CTRL register
DEN_DRDY
_flag
INT1_
CNT_BDR
INT1_
FIFO_FULL
INT1_
FIFO_OVR
INT1_
FIFO_TH
INT1_
BOOT
INT1_
DRDY_G
INT1_
DRDY_XL
Table 38. INT1_CTRL register description
DS12140 - Rev 2
DEN_DRDY_flag
Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT1 pin
INT1_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT1
INT1_FIFO_FULL
Enables FIFO full flag interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM
interface is used.
INT1_FIFO_OVR
Enables FIFO overrun interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM
interface is used.
INT1_FIFO_TH
Enables FIFO threshold interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM
interface is used.
INT1_BOOT
Enables boot status on INT1 pin
INT1_DRDY_G
Enables gyroscope data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI
I3CSM interface is used.
INT1_DRDY_XL
Enables accelerometer data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the
MIPI I3CSM interface is used.
page 48/172
LSM6DSO
INT2_CTRL (0Eh)
9.10
INT2_CTRL (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried out on INT2 when the MIPI I3CSM dynamic address in not
assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the MIPI I3CSM interface is used.
The output of the pin will be the OR combination of the signals selected here and in MD2_CFG (5Fh).
Table 39. INT2_CTRL register
0
INT2_
CNT_BDR
INT2_
FIFO_FULL
INT2_
FIFO_OVR
INT2_
FIFO_TH
INT2_
DRDY_TEMP
INT2_
DRDY_G
INT2_
DRDY_XL
Table 40. INT2_CTRL register description
INT2_CNT_BDR
Enables COUNTER_BDR_IA interrupt on INT2
INT2_FIFO_FULL
Enables FIFO full flag interrupt on INT2 pin
INT2_FIFO_OVR
Enables FIFO overrun interrupt on INT2 pin
INT_FIFO_TH
Enables FIFO threshold interrupt on INT2 pin
Enables temperature sensor data-ready interrupt on INT2 pin. It
INT2_DRDY_TEMP can be also used to trigger an IBI when the MIPI I3CSM interface is used and INT2_ON_INT1 = ‘1’ in
CTRL4_C (13h).
9.11
INT2_DRDY_G
Gyroscope data-ready interrupt on INT2 pin
INT2_DRDY_XL
Accelerometer data-ready interrupt on INT2 pin
WHO_AM_I (0Fh)
WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Ch.
Table 41. WhoAmI register
0
DS12140 - Rev 2
1
1
0
1
1
0
0
page 49/172
LSM6DSO
CTRL1_XL (10h)
9.12
CTRL1_XL (10h)
Accelerometer control register 1 (r/w)
Table 42. CTRL1_XL register
ODR_XL3
ODR_XL2
ODR_XL1
ODR_XL0
FS1_XL
FS0_XL
LPF2_XL_EN
0
Table 43. CTRL1_XL register description
ODR_XL[3:0]
Accelerometer ODR selection (see Table 44)
FS[1:0]_XL
Accelerometer full-scale selection (see Table 45)
Accelerometer high-resolution selection
LPF2_XL_EN
(0: output from first stage digital filtering selected (default);
1: output from LPF2 second filtering stage selected)
Table 44. Accelerometer ODR register setting
ODR selection [Hz] when
ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 XL_HM_MODE = 1 in CTRL6_C
(15h)
ODR selection [Hz] when
XL_HM_MODE = 0 in CTRL6_C
(15h)
0
0
0
0
Power-down
Power-down
1
0
1
1
1.6 Hz (low power only)
12.5 Hz (high performance)
0
0
0
1
12.5 Hz (low power)
12.5 Hz (high performance)
0
0
1
0
26 Hz (low power)
26 Hz (high performance)
0
0
1
1
52 Hz (low power)
52 Hz (high performance)
0
1
0
0
104 Hz (normal mode)
104 Hz (high performance)
0
1
0
1
208 Hz (normal mode)
208 Hz (high performance)
0
1
1
0
416 Hz (high performance)
416 Hz (high performance)
0
1
1
1
833 Hz (high performance)
833 Hz (high performance)
1
0
0
0
1.66 kHz (high performance)
1.66 kHz (high performance)
1
0
0
1
3.33 kHz (high performance)
3.33 kHz (high performance)
1
0
1
0
6.66 kHz (high performance)
6.66 kHz (high performance)
1
1
x
x
Not allowed
Not allowed
Table 45. Accelerometer full-scale selection
DS12140 - Rev 2
FS[1:0]_XL
XL_FS_MODE = ‘0’ in CTRL8_XL (17h)
XL_FS_MODE = ‘1’ in CTRL8_XL (17h)
00 (default)
2g
2g
01
16 g
2g
10
4g
4g
11
8g
8g
page 50/172
LSM6DSO
CTRL2_G (11h)
9.13
CTRL2_G (11h)
Gyroscope control register 2 (r/w)
Table 46. CTRL2_G register
ODR_G3
ODR_G2
ODR_G1
ODR_G0
FS1_G
FS0_G
FS_125
0
Table 47. CTRL2_G register description
Gyroscope output data rate selection. Default value: 0000
ODR_G[3:0]
(Refer to Table 48)
Gyroscope UI chain full-scale selection
(00: 250 dps;
FS[1:0]_G
01: 500 dps;
10: 1000 dps;
11: 2000 dps)
Selects gyro UI chain full-scale 125 dps
FS_125
(0: FS selected through bits FS[1:0]_G;
1: FS set to 125 dps)
Table 48. Gyroscope ODR configuration setting
ODR [Hz] when G_HM_MODE = 1
in CTRL7_G (16h)
ODR [Hz] when G_HM_MODE = 0
in CTRL7_G (16h)
ODR_G3
ODR_G2
ODR_G1
ODR_G0
0
0
0
0
Power down
Power down
0
0
0
1
12.5 Hz (low power)
12.5 Hz (high performance)
0
0
1
0
26 Hz (low power)
26 Hz (high performance)
0
0
1
1
52 Hz (low power)
52 Hz (high performance)
0
1
0
0
104 Hz (normal mode)
104 Hz (high performance)
0
1
0
1
208 Hz (normal mode)
208 Hz (high performance)
0
1
1
0
416 Hz (high performance)
416 Hz (high performance)
0
1
1
1
833 Hz (high performance)
833 Hz (high performance)
1
0
0
0
1.66 kHz (high performance)
1.66 kHz (high performance)
1
0
0
1
3.33 kHz (high performance
3.33 kHz (high performance)
1
0
1
0
6.66 kHz (high performance
6.66 kHz (high performance)
1
0
1
1
Not available
Not available
DS12140 - Rev 2
page 51/172
LSM6DSO
CTRL3_C (12h)
9.14
CTRL3_C (12h)
Control register 3 (r/w)
Table 49. CTRL3_C register
BOOT
BDU
H_LACTIVE
PP_OD
SIM
IF_INC
0
SW_RESET
Table 50. CTRL3_C register description
Reboots memory content. Default value: 0
BOOT
(0: normal mode; 1: reboot memory content)
This bit is automatically cleared.
Block Data Update. Default value: 0
BDU
(0: continuous update;
1: output registers are not updated until MSB and LSB have been read)
H_LACTIVE
PP_OD
SIM
IF_INC
Interrupt activation level. Default value: 0
(0: interrupt output pins active high; 1: interrupt output pins active low)
Push-pull/open-drain selection on INT1 and INT2 pins. Default value: 0
(0: push-pull mode; 1: open-drain mode)
SPI Serial Interface Mode selection. Default value: 0
(0: 4-wire interface; 1: 3-wire interface)
Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI).
Default value: 1
(0: disabled; 1: enabled)
Software reset. Default value: 0
SW_RESET (0: normal mode; 1: reset device)
This bit is automatically cleared.
DS12140 - Rev 2
page 52/172
LSM6DSO
CTRL4_C (13h)
9.15
CTRL4_C (13h)
Control register 4 (r/w)
Table 51. CTRL4_C register
0
SLEEP_G
INT2_on
_INT1
0
DRDY_MASK
I2C_disable
LPF1_
SEL_G
0
Table 52. CTRL4_C register description
SLEEP_G
Enables gyroscope Sleep mode. Default value:0
(0: disabled; 1: enabled)
All interrupt signals available on INT1 pin enable. Default value: 0
INT2_on_INT1 (0: interrupt signals divided between INT1 and INT2 pins;
1: all interrupt signals in logic or on INT1 pin)
Enables data available
DRDY_MASK
(0: disabled;
1: mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked).
I2C_disable
LPF1_SEL_G
Disables I²C interface. Default value: 0
(0: SPI, I²C and MIPI I3CSM interfaces enabled (default); 1: I²C interface disabled)
Enables gyroscope digital LPF1 if auxiliary SPI is disabled; the bandwidth can be selected through
FTYPE[2:0] in CTRL6_C (15h).
(0: disabled; 1: enabled)
DS12140 - Rev 2
page 53/172
LSM6DSO
CTRL5_C (14h)
9.16
CTRL5_C (14h)
Control register 5 (r/w)
Table 53. CTRL5_C register
XL_ULP_EN
ROUNDING1
ROUNDING0
0
ST1_G
ST0_G
ST1_XL
ST0_XL
Table 54. CTRL5_C register description
Accelerometer ultra-low-power mode enable. Default value: 0(1)
XL_ULP_EN
(0: Ultra-low-power mode disabled; 1: Ultra-low-power mode enabled)
Circular burst-mode (rounding) read from the output registers. Default value: 00
(00: no rounding;
ROUNDING[1:0]
01: accelerometer only;
10: gyroscope only;
11: gyroscope + accelerometer)
Angular rate sensor self-test enable. Default value: 00
ST[1:0]_G
(00: Self-test disabled; Other: refer to Table 55)
Linear acceleration sensor self-test enable. Default value: 00
ST[1:0]_XL
(00: Self-test disabled; Other: refer to Table 56)
1. Further details about the accelerometer ultra-low-power mode are provided in Section 6.2.1 Accelerometer ultra-low-power
mode.
Table 55. Angular rate sensor self-test mode selection
ST1_G
ST0_G
0
0
Normal mode
0
1
Positive sign self-test
1
0
Not allowed
1
1
Negative sign self-test
Self-test mode
Table 56. Linear acceleration sensor self-test mode selection
DS12140 - Rev 2
ST1_XL
ST0_XL
0
0
Normal mode
0
1
Positive sign self-test
1
0
Negative sign self-test
1
1
Not allowed
Self-test mode
page 54/172
LSM6DSO
CTRL6_C (15h)
9.17
CTRL6_C (15h)
Control register 6 (r/w)
Table 57. CTRL6_C register
TRIG_EN
LVL1_EN
LVL2_EN
XL_HM
_MODE
USR_
OFF_W
FTYPE_2
FTYPE_1
FTYPE_0
Table 58. CTRL6_C register description
TRIG_EN
DEN data edge-sensitive trigger enable. Refer to Table 59.
LVL1_EN
DEN data level-sensitive trigger enable. Refer to Table 59.
LVL2_EN
DEN level-sensitive latched enable. Refer toTable 59.
High-performance operating mode disable for accelerometer. Default value: 0
XL_HM_MODE
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h)
USR_OFF_W
(0: 2-10 g/LSB;
1: 2-6 g/LSB)
Gyroscope's low-pass filter (LPF1) bandwidth selection
FTYPE[2:0]
Table 59 shows the selectable bandwidth values (available if auxiliary SPI is disabled).
Table 59. Trigger mode selection
TRIG_EN, LVL1_EN, LVL2_EN
Trigger mode
100
Edge-sensitive trigger mode is selected
010
Level-sensitive trigger mode is selected
011
Level-sensitive latched mode is selected
110
Level-sensitive FIFO enable mode is selected
Table 60. Gyroscope LPF1 bandwidth selection
FTYPE
[2:0]
12.5 Hz
26 Hz
52 Hz
104 Hz
208 Hz
416 Hz
833 Hz
1.67 kHz
3.33 kHz
6.67 kHz
000
4.2
8.3
16.6
33.0
67.0
136.6
239.2
304.2
328.5
335.5
001
4.2
8.3
16.6
33.0
67.0
130.5
192.4
220.7
229.6
232.0
010
4.2
8.3
16.6
33.0
67.0
120.3
154.2
166.6
170.1
171.1
011
4.2
8.3
16.6
33.0
67.0
137.1
281.8
453.2
559.2
609.0
100
4.2
8.3
16.7
33.0
62.4
86.7
96.6
99.6
NA
NA
101
4.2
8.3
16.8
31.0
43.2
48.0
49.4
49.8
NA
NA
110
4.1
7.8
13.4
19.0
23.1
24.6
25.0
25.1
NA
NA
111
3.9
6.7
9.7
11.5
12.2
12.4
12.5
12.5
NA
NA
DS12140 - Rev 2
page 55/172
LSM6DSO
CTRL7_G (16h)
9.18
CTRL7_G (16h)
Control register 7 (r/w)
Table 61. CTRL7_G register
G_HM_
MODE
HP_EN_G
HPM1_G
HPM0_G
0(1)
OIS_ON_EN
USR_OFF
_ON_OUT
OIS_ON
1. This bit must be set to '0' for the correct operation of the device.
Table 62. CTRL7_G register description
Disables high-performance operating mode for gyroscope. Default value: 0
G_HM_MODE
(0: high-performance operating mode enabled;
1: high-performance operating mode disabled)
HP_EN_G
Enables gyroscope digital high-pass filter. The filter is enabled only if the gyro is in HP mode. Default
value: 0
(0: HPF disabled; 1: HPF enabled)
Gyroscope digital HP filter cutoff selection. Default: 00
(00: 16 mHz;
HPM_G[1:0]
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
Selects how to enable and disable the OIS chain, after first configuration and enabling through SPI2.
OIS_ON_EN(1)
(0: OIS chain is enabled/disabled with SPI2 interface;
1: OIS chain is enabled/disabled with primary interface)
USR_OFF_ON_
OUT
Enables accelerometer user offset correction block; it's valid for the low-pass path - see
Figure 17. Accelerometer composite filter. Default value: 0
(0: accelerometer user offset correction block bypassed;
1: accelerometer user offset correction block enabled)
OIS_ON(1)
Enables/disables the OIS chain from primary interface when the OIS_ON_EN bit is '1'.
(0: OIS disabled; 1: OIS enabled)
1. First, enabling OIS and OIS configurations must be done through SPI2, with OIS_ON_EN and OIS_ON set to '0'.
DS12140 - Rev 2
page 56/172
LSM6DSO
CTRL8_XL (17h)
9.19
CTRL8_XL (17h)
Control register 8 (r/w)
Table 63. CTRL8_XL register
HPCF_XL_2
HPCF_XL_1
HP_REF_
MODE_XL
HPCF_XL_0
FASTSETTL_
MODE_XL
HP_SLOPE_
XL_EN
XL_FS_
MODE
LOW_PASS_
ON_6D
Table 64. CTRL8_XL register description
HPCF_XL_[2:0] Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 65.
Enables accelerometer high-pass filter reference mode (valid for high-pass path - HP_SLOPE_XL_EN bit
must be ‘1’). Default value: 0(1)
HP_REF_
MODE_XL
(0: disabled, 1: enabled)
Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after writing
this bit. Active only during device exit from power- down mode. Default value: 0
FASTSETTL
_MODE_XL
(0: disabled, 1: enabled)
HP_SLOPE_
XL_EN
Accelerometer slope filter / high-pass filter selection. Refer to Figure 24. Accelerometer block diagram.
Accelerometer full-scale management between UI chain and OIS chain
XL_FS_MODE
(0: Old full-scale mode. When XL UI is on, the full scale is the same between UI/OIS and is chosen by the UI
CTRL registers; when XL UI is in PD, the OIS can choose the FS.
1: New full-scale mode. Full scales are independent between the UI/OIS chain but both bound to 8 g.)
LPF2 on 6D function selection. Refer to Figure 24. Default value: 0
LOW_PASS
_ON_6D
(0: ODR/2 low-pass filtered data sent to 6D interrupt function;
1: LPF2 output data sent to 6D interrupt function)
1. When enabled, the first output data have to be discarded.
Table 65. Accelerometer bandwidth configurations
Filter type
Low pass
DS12140 - Rev 2
HP_SLOPE_
XL_EN
0
LPF2_XL_EN
HPCF_XL_[2:0]
Bandwidth
0
-
ODR/2
000
ODR/4
001
ODR/10
010
ODR/20
011
ODR/45
100
ODR/100
101
ODR/200
110
ODR/400
111
ODR/800
1
page 57/172
LSM6DSO
CTRL8_XL (17h)
HP_SLOPE_
Filter type
LPF2_XL_EN
XL_EN
High pass
1
HPCF_XL_[2:0]
Bandwidth
000
SLOPE (ODR/4)
001
ODR/10
010
ODR/20
011
ODR/45
100
ODR/100
101
ODR/200
110
ODR/400
111
ODR/800
-
Figure 24. Accelerometer block diagram
LOW_PASS_ON_6D
Free-fall
0
Advanced
functions
1
LPF2_XL_EN
USR_OFF_ON_OUT
HP_SLOPE_XL_EN
0
0
Digital
LP Filter
1
LPF1
output (1)
0
USER
OFFSET
LPF2
1
USR_OFF_W
OFS_USR[7:0]
FIFO
HPCF_XL[2:0]
Digital
HP Filter
1
1
0
0
Wake-up
Activity /
Inactivity
SPI /
I 2C /
MIPI I3C SM
USR_OFF_ON_WU SLOPE_FDS
001
010
…
111
1
HPCF_XL[2:0]
SLOPE
FILTER
6D / 4D
000
HPCF_XL[2:0]
S/D Tap
DS12140 - Rev 2
page 58/172
LSM6DSO
CTRL9_XL (18h)
9.20
CTRL9_XL (18h)
Control register 9 (r/w)
Table 66. CTRL9_XL register
DEN_X
DEN_Y
DEN_Z
DEN_XL_G
DEN_XL_EN
DEN_LH
I3C_disable
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 67. CTRL9_XL register description
DEN_X
DEN_Y
DEN_Z
DEN value stored in LSB of X-axis. Default value: 1
(0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB)
DEN value stored in LSB of Y-axis. Default value: 1
(0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB)
DEN value stored in LSB of Z-axis. Default value: 1
(0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB)
DEN stamping sensor selection. Default value: 0
DEN_XL_G
(0: DEN pin info stamped in the gyroscope axis selected by bits [7:5];
1: DEN pin info stamped in the accelerometer axis selected by bits [7:5])
DEN_XL_EN
DEN_LH
Extends DEN functionality to accelerometer sensor. Default value: 0
(0: disabled; 1: enabled)
DEN active level configuration. Default value: 0
(0: active low; 1: active high)
Disables MIPI I3CSM communication protocol(1)
I3C_disable
(0: SPI, I²C, MIPI I3CSM interfaces enabled (default);
1: MIPI I3CSM interface disabled)
1. It is recommended to set this bit to '1' during the initial device configuration phase, when the I3C interface is not used.
DS12140 - Rev 2
page 59/172
LSM6DSO
CTRL10_C (19h)
9.21
CTRL10_C (19h)
Control register 10 (r/w)
Table 68. CTRL10_C register
0
TIMESTAMP
_EN
0
0
0
0
0
0
Table 69. CTRL10_C register description
Enables timestamp counter. default value: 0
TIMESTAMP_EN
(0: disabled; 1: enabled)
The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and
TIMESTAMP3 (43h).
9.22
ALL_INT_SRC (1Ah)
Source register for all interrupts (r)
Table 70. ALL_INT_SRC register
TIMESTAMP
_ENDCOUNT
0
SLEEP_
CHANGE_IA
D6D_IA
DOUBLE_
TAP
SINGLE_
TAP
WU_IA
FF_IA
Table 71. ALL_INT_SRC register description
TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms
SLEEP_CHANGE_IA
D6D_IA
DOUBLE_TAP
SINGLE_TAP
WU_IA
FF_IA
DS12140 - Rev 2
Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0
(0: change in position not detected; 1: change in position detected)
Double-tap event status. Default value: 0
(0:event not detected, 1: event detected)
Single-tap event status. Default value:0
(0: event not detected, 1: event detected)
Wake-up event status. Default value: 0
(0: event not detected, 1: event detected)
Free-fall event status. Default value: 0
(0: event not detected, 1: event detected)
page 60/172
LSM6DSO
WAKE_UP_SRC (1Bh)
9.23
WAKE_UP_SRC (1Bh)
Wake-up interrupt source register (r)
Table 72. WAKE_UP_SRC register
0
SLEEP_
CHANGE_IA
FF_IA
SLEEP_
STATE
WU_IA
X_WU
Y_WU
Z_WU
Table 73. WAKE_UP_SRC register description
SLEEP_ CHANGE_IA
FF_IA
SLEEP_STATE
WU_IA
X_WU
Y_WU
Z_WU
DS12140 - Rev 2
Detects change event in activity/inactivity status. Default value: 0
(0: change status not detected; 1: change status detected)
Free-fall event detection status. Default value: 0
(0: free-fall event not detected; 1: free-fall event detected)
Sleep status bit. Default value: 0
(0: Activity status; 1: Inactivity status)
Wakeup event detection status. Default value: 0
(0: wakeup event not detected; 1: wakeup event detected.)
Wakeup event detection status on X-axis. Default value: 0
(0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected)
Wakeup event detection status on Y-axis. Default value: 0
(0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected)
Wakeup event detection status on Z-axis. Default value: 0
(0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected)
page 61/172
LSM6DSO
TAP_SRC (1Ch)
9.24
TAP_SRC (1Ch)
Tap source register (r)
Table 74. TAP_SRC register
0
TAP_IA
SINGLE_
TAP
DOUBLE_
TAP
TAP_SIGN
X_TAP
Y_TAP
Z_TAP
Table 75. TAP_SRC register description
TAP_IA
SINGLE_TAP
DOUBLE_TAP
Tap event detection status. Default: 0
(0: tap event not detected; 1: tap event detected)
Single-tap event status. Default value: 0
(0: single tap event not detected; 1: single tap event detected)
Double-tap event detection status. Default value: 0
(0: double-tap event not detected; 1: double-tap event detected.)
Sign of acceleration detected by tap event. Default: 0
TAP_SIGN
(0: positive sign of acceleration detected by tap event;
1: negative sign of acceleration detected by tap event)
X_TAP
Y_TAP
Z_TAP
DS12140 - Rev 2
Tap event detection status on X-axis. Default value: 0
(0: tap event on X-axis not detected; 1: tap event on X-axis detected)
Tap event detection status on Y-axis. Default value: 0
(0: tap event on Y-axis not detected; 1: tap event on Y-axis detected)
Tap event detection status on Z-axis. Default value: 0
(0: tap event on Z-axis not detected; 1: tap event on Z-axis detected)
page 62/172
LSM6DSO
D6D_SRC (1Dh)
9.25
D6D_SRC (1Dh)
Portrait, landscape, face-up and face-down source register (r)
Table 76. D6D_SRC register
DEN_DRDY
D6D_IA
ZH
ZL
YH
YL
XH
XL
Table 77. D6D_SRC register description
DEN_DRDY
D6D_IA
ZH
ZL
YH
YL
XH
XL
DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active
condition.(1)
Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0
(0: change position not detected; 1: change position detected)
Z-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
Z-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
Y-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over-threshold) detected)
Y-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
X-axis high event (over threshold). Default value: 0
(0: event not detected; 1: event (over threshold) detected)
X-axis low event (under threshold). Default value: 0
(0: event not detected; 1: event (under threshold) detected)
1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the
COUNTER_BDR_REG1 (0Bh) register.
DS12140 - Rev 2
page 63/172
LSM6DSO
STATUS_REG (1Eh) / STATUS_SPIAux (1Eh)
9.26
STATUS_REG (1Eh) / STATUS_SPIAux (1Eh)
The STATUS_REG register is read by the primary interface SPI/I²C & MIPI I3CSM (r).
Table 78. STATUS_REG register
0
0
0
0
0
TDA
GDA
XLDA
GDA
XLDA
Table 79. STATUS_REG register description
Temperature new data available. Default: 0
TDA
(0: no set of data is available at temperature sensor output;
1: a new set of data is available at temperature sensor output)
Gyroscope new data available. Default value: 0
GDA
(0: no set of data available at gyroscope output;
1: a new set of data is available at gyroscope output)
Accelerometer new data available. Default value: 0
XLDA
(0: no set of data available at accelerometer output;
1: a new set of data is available at accelerometer output)
The STATUS_SPIAux register is read by the auxiliary SPI.
Table 80. STATUS_SPIAux register
0
0
0
0
0
GYRO_
SETTLING
Table 81. STATUS_SPIAux description
DS12140 - Rev 2
GYRO_
SETTLING
High when the gyroscope output is in the settling phase
GDA
Gyroscope data available (reset when one of the high parts of the output data is read)
XLDA
Accelerometer data available (reset when one of the high parts of the output data is read)
page 64/172
LSM6DSO
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
9.27
OUT_TEMP_L (20h), OUT_TEMP_H (21h)
Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement.
Table 82. OUT_TEMP_L register
Temp7
Temp6
Temp5
Temp4
Temp3
Temp2
Temp1
Temp0
Temp10
Temp9
Temp8
Table 83. OUT_TEMP_H register
Temp15
Temp14
Temp13
Temp12
Temp11
Table 84. OUT_TEMP register description
Temp[15:0]
9.28
Temperature sensor output data
The value is expressed as two’s complement sign extended on the MSB.
OUTX_L_G (22h) and OUTX_H_G (23h)
Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G
(11h)) of gyro user interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of
the OIS gyro.
Table 85. OUTX_L_G register
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
Table 86. OUTX_H_G register
D15
D14
D13
D12
D11
Table 87. OUTX_H_G register description
Pitch axis (X) angular rate value
D[15:0]
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3CSM: Gyro UI chain pitch axis output
SPI2: Gyro OIS chain pitch axis output
DS12140 - Rev 2
page 65/172
LSM6DSO
OUTY_L_G (24h) and OUTY_H_G (25h)
9.29
OUTY_L_G (24h) and OUTY_H_G (25h)
Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G
(11h)) of the gyro user interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of
the OIS gyro.
Table 88. OUTY_L_G register
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
Table 89. OUTY_H_G register
D15
D14
D13
D12
D11
Table 90. OUTY_H_G register description
Roll axis (Y) angular rate value
D[15:0]
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3CSM: Gyro UI chain roll axis output
SPI2: Gyro OIS chain roll axis output
9.30
OUTZ_L_G (26h) and OUTZ_H_G (27h)
Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s
complement.
If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G
(11h)) of the gyro user interface.
If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of
the OIS gyro.
Table 91. OUTZ_L_G register
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
Table 92. OUTZ_H_G register
D15
D14
D13
D12
D11
Table 93. OUTZ_H_G register description
Yaw axis (Z) angular rate value
D[15:0]
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3CSM: Gyro UI chain yaw axis output
SPI2: Gyro OIS chain yaw axis output
DS12140 - Rev 2
page 66/172
LSM6DSO
OUTX_L_A (28h) and OUTX_H_A (29h)
9.31
OUTX_L_A (28h) and OUTX_H_A (29h)
Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL
(10h)) of the accelerometer user interface.
If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of
the OIS (CTRL3_OIS (72h)).
Table 94. OUTX_L_A register
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
Table 95. OUTX_H_A register
D15
D14
D13
D12
D11
Table 96. OUTX_H_A register description
X-axis linear acceleration value.
D[15:0]
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3CSM: Accelerometer UI chain X-axis output
SPI2: Accelerometer OIS chain X-axis output
9.32
OUTY_L_A (2Ah) and OUTY_H_A (2Bh)
Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL
(10h)) of the accelerometer user interface.
If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of
the OIS (CTRL3_OIS (72h)).
Table 97. OUTY_L_A register
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
Table 98. OUTY_H_A register
D15
D14
D13
D12
D11
Table 99. OUTY_H_A register description
Y-axis linear acceleration value
D[15:0]
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3CSM: Accelerometer UI chain Y-axis output
SPI2: Accelerometer OIS chain Y-axis output
DS12140 - Rev 2
page 67/172
LSM6DSO
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
9.33
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh)
Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s
complement.
If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL
(10h)) of the accelerometer user interface.
If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of
the OIS (CTRL3_OIS (72h)).
Table 100. OUTZ_L_A register
D7
D6
D5
D4
D3
D2
D1
D0
D10
D9
D8
0
0
Table 101. OUTZ_H_A register
D15
D14
D13
D12
D11
Table 102. OUTZ_H_A register description
Z-axis linear acceleration value
D[15:0]
D[15:0] expressed in two’s complement and its value depends on the interface used:
SPI1/I²C/MIPI I3CSM: Accelerometer UI chain Z-axis output
SPI2: Accelerometer OIS chain Z-axis output
9.34
EMB_FUNC_STATUS_MAINPAGE (35h)
Embedded function status register (r)
Table 103. EMB_FUNC_STATUS_MAINPAGE register
IS_FSM_LC
0
IS_SIGMOT
IS_TILT
IS_STEP_DET
0
Table 104. EMB_FUNC_STATUS_MAINPAGE register description
IS_FSM_LC
IS_SIGMOT
IS_TILT
IS_STEP_DET
DS12140 - Rev 2
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for significant motion detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for tilt detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for step detection
(1: interrupt detected; 0: no interrupt)
page 68/172
LSM6DSO
FSM_STATUS_A_MAINPAGE (36h)
9.35
FSM_STATUS_A_MAINPAGE (36h)
Finite State Machine status register (r)
Table 105. FSM_STATUS_A_MAINPAGE register
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
Table 106. FSM_STATUS_A_MAINPAGE register description
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
DS12140 - Rev 2
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 69/172
LSM6DSO
FSM_STATUS_B_MAINPAGE (37h)
9.36
FSM_STATUS_B_MAINPAGE (37h)
Finite State Machine status register (r)
Table 107. FSM_STATUS_B_MAINPAGE register
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 108. FSM_STATUS_B_MAINPAGE register description
Interrupt status bit for FSM16 interrupt event.
IS_FSM16
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event.
IS_FSM15
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event.
IS_FSM14
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event.
IS_FSM13
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event.
IS_FSM12
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event.
IS_FSM11
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event.
IS_FSM10
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event.
IS_FSM9
9.37
(1: interrupt detected; 0: no interrupt)
STATUS_MASTER_MAINPAGE (39h)
Sensor hub source register (r)
Table 109. STATUS_MASTER_MAINPAGE register
WR_ONCE_
DONE
SLAVE3_
NACK
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0
0
SENS_HUB_
ENDOP
Table 110. STATUS_MASTER_MAINPAGE register description
WR_ONCE_DONE
When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the
write operation on slave 0 has been performed and completed. Default value: 0
SLAVE3_NACK
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
SLAVE2_NACK
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
SLAVE1_NACK
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK
This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
Sensor hub communication status. Default value: 0
SENS_HUB_ENDOP (0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS12140 - Rev 2
page 70/172
LSM6DSO
FIFO_STATUS1 (3Ah)
9.38
FIFO_STATUS1 (3Ah)
FIFO status register 1 (r)
Table 111. FIFO_STATUS1 register
DIFF_
FIFO_7
DIFF_
FIFO_6
DIFF_
FIFO_5
DIFF_
FIFO_4
DIFF_
FIFO_3
DIFF_
FIFO_2
DIFF_
FIFO_1
DIFF_
FIFO_0
DIFF_
FIFO_9
DIFF_
FIFO_8
Table 112. FIFO_STATUS1 register description
Number of unread sensor data (TAG + 6 bytes) stored in FIFO
DIFF_FIFO_[7:0]
9.39
In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh).
FIFO_STATUS2 (3Bh)
FIFO status register 2 (r)
Table 113. FIFO_STATUS2 register
FIFO_
WTM_IA
FIFO_
OVR_IA
FIFO_
FULL_IA
COUNTER
_BDR_IA
FIFO_OVR_
LATCHED
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 114. FIFO_STATUS2 register description
FIFO watermark status. Default value: 0
FIFO_
WTM_IA
(0: FIFO filling is lower than WTM;
1: FIFO filling is equal to or greater than WTM)
Watermark is set through bits WTM[8:0] in FIFO_CTRL2 (08h) and FIFO_CTRL1 (07h).
FIFO_
OVR_IA
FIFO overrun status. Default value: 0
FIFO_
FULL_IA
Smart FIFO full status. Default value: 0
(0: FIFO is not completely filled; 1: FIFO is completely filled)
(0: FIFO is not full; 1: FIFO will be full at the next ODR)
Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and
COUNTER_ COUNTER_BDR_REG2 (0Ch). Default value: 0
BDR_IA
This bit is reset when these registers are read.
FIFO_OVR_ Latched FIFO overrun status. Default value: 0
LATCHED
This bit is reset when this register is read.
DIFF_
FIFO_[9:8]
DS12140 - Rev 2
Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00
In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah)
page 71/172
LSM6DSO
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h),
and TIMESTAMP3 (43h)
9.40
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3
(43h)
Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 µs.
Table 115. TIMESTAMP output registers
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 116. TIMESTAMP output register description
D[31:0]
DS12140 - Rev 2
Timestamp output registers: 1LSB = 25 µs
page 72/172
LSM6DSO
TAP_CFG0 (56h)
9.41
TAP_CFG0 (56h)
Activity/inactivity functions, configuration of filtering, and tap recognition functions (r/w)
Table 117. TAP_CFG0 register
0
INT_CLR_
ON_READ
SLEEP_
STATUS_
ON_INT
SLOPE_FDS
TAP_X_EN
TAP_Y_EN
TAP_Z_EN
LIR
Table 118. TAP_CFG0 register description
This bit allows immediately clearing the latched interrupts of an event detection upon the read of
the corresponding status register. It must be set to 1 together with LIR. Default value: 0
INT_CLR_ON_READ
(0: latched interrupt signal cleared at the end of the ODR period;
1: latched interrupt signal immediately cleared)
Activity/inactivity interrupt mode configuration.
SLEEP_STATUS_ON_INT
If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or
sleep change on the INT pins. Default value: 0
(0: sleep change notification on INT pins; 1: sleep status reported on INT pins)
SLOPE_FDS
TAP_X_EN
TAP_Y_EN
TAP_Z_EN
LIR
DS12140 - Rev 2
HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions. Default value: 0 (
0: SLOPE filter applied; 1: HPF applied)
Enable X direction in tap recognition. Default value: 0
(0: X direction disabled; 1: X direction enabled)
Enable Y direction in tap recognition. Default value: 0
(0: Y direction disabled; 1: Y direction enabled)
Enable Z direction in tap recognition. Default value: 0
(0: Z direction disabled; 1: Z direction enabled)
Latched Interrupt. Default value: 0
(0: interrupt request not latched; 1: interrupt request latched)
page 73/172
LSM6DSO
TAP_CFG1 (57h)
9.42
TAP_CFG1 (57h)
Tap configuration register (r/w)
Table 119. TAP_CFG1 register
TAP_
PRIORITY_2
TAP_
PRIORITY_1
TAP_
PRIORITY_0
TAP_THS_X_4
TAP_THS_X_3
TAP_THS_X_2
TAP_THS_X_1
TAP_THS_X_0
Table 120. TAP_CFG1 register description
TAP_PRIORITY_[2:0]
Selection of axis priority for TAP detection (see Table 121)
X-axis tap recognition threshold. Default value: 0
TAP_THS_X_[4:0]
1 LSB = FS_XL / (25)
Table 121. TAP priority decoding
9.43
TAP_PRIORITY_[2:0]
Max. priority
Mid. priority
Min. priority
000
X
Y
Z
001
Y
X
Z
010
X
Z
Y
011
Z
Y
X
100
X
Y
Z
101
Y
Z
X
110
Z
X
Y
111
Z
Y
X
TAP_CFG2 (58h)
Enables interrupt and inactivity functions, and tap recognition functions (r/w).
Table 122. TAP_CFG2 register
INTERRUPTS_
ENABLE
INACT_EN1
INACT_EN0
TAP_THS_Y_4
TAP_THS_Y_3
TAP_THS_Y_2
TAP_THS_Y_1
TAP_THS_Y_0
Table 123. TAP_CFG2 register description
INTERRUPTS_
ENABLE
Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default value: 0
(0: interrupt disabled; 1: interrupt enabled)
Enable activity/inactivity (sleep) function. Default value: 00
(00: stationary/motion-only interrupts generated, XL and gyro do not change;
INACT_EN[1:0]
01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change;
10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode;
11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode)
TAP_THS_Y_[4:0]
DS12140 - Rev 2
Y-axis tap recognition threshold. Default value: 0
1 LSB = FS_XL / (25)
page 74/172
LSM6DSO
TAP_THS_6D (59h)
9.44
TAP_THS_6D (59h)
Portrait/landscape position and tap function threshold register (r/w).
Table 124. TAP_THS_6D register
D4D_EN
SIXD_THS1
SIXD_THS0
TAP_
THS_Z_4
TAP_
THS_Z_3
TAP_
THS_Z_2
TAP_
THS_Z_1
TAP_
THS_Z_0
Table 125. TAP_THS_6D register description
4D orientation detection enable. Z-axis position detection is disabled.
D4D_EN
Default value: 0
(0: enabled; 1: disabled)
SIXD_THS[1:0]
TAP_THS_Z_[4:0]
Threshold for 4D/6D function. Default value: 00
For details, refer to Table 126.
Z-axis recognition threshold. Default value: 0
1 LSB = FS_XL / (25)
Table 126. Threshold for D4D/D6D function
DS12140 - Rev 2
SIXD_THS[1:0]
Threshold value
00
80 degrees
01
70 degrees
10
60 degrees
11
50 degrees
page 75/172
LSM6DSO
INT_DUR2 (5Ah)
9.45
INT_DUR2 (5Ah)
Tap recognition function setting register (r/w).
Table 127. INT_DUR2 register
DUR3
DUR2
DUR1
DUR0
QUIET1
QUIET0
SHOCK1
SHOCK0
Table 128. INT_DUR2 register description
Duration of maximum time gap for double tap recognition. Default: 0000
DUR[3:0]
When double tap recognition is enabled, this register expresses the maximum time between two consecutive
detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to
16*ODR_XL time. If the DUR[3:0] bits are set to a different value, 1LSB corresponds to 32*ODR_XL time.
Expected quiet time after a tap detection. Default value: 00
QUIET[1:0]
Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default
value of these bits is 00b which corresponds to 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
value, 1LSB corresponds to 4*ODR_XL time.
Maximum duration of overthreshold event. Default value: 00
Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event.
SHOCK[1:0] The default value of these bits is 00b which corresponds to 4*ODR_XL time. If the SHOCK[1:0] bits are set to a
different value, 1LSB
corresponds to 8*ODR_XL time.
9.46
WAKE_UP_THS (5Bh)
Single/double-tap selection and wake-up configuration (r/w)
Table 129. WAKE_UP_THS register
SINGLE_
DOUBLE_
TAP
USR_OFF_
ON_WU
WK_THS5
WK_THS4
WK_THS3
WK_THS2
WK_THS1
WK_THS0
Table 130. WAKE_UP_THS register description
Single/double-tap event enable. Default: 0
SINGLE_
(0: only single-tap event enabled;
DOUBLE_TAP
1: both single and double-tap events enabled)
DS12140 - Rev 2
USR_OFF_
ON_WU
Drives the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the wakeup
function.
WK_THS[5:0]
Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch). Default value:
000000
page 76/172
LSM6DSO
WAKE_UP_DUR (5Ch)
9.47
WAKE_UP_DUR (5Ch)
Free-fall, wakeup and sleep mode functions duration setting register (r/w)
Table 131. WAKE_UP_DUR register
FF_DUR5
WAKE_DUR1 WAKE_DUR0
WAKE_THS_
W
SLEEP_DUR
3
SLEEP_DUR
2
SLEEP_DUR
1
SLEEP_DUR
0
Table 132. WAKE_UP_DUR register description
Free fall duration event. Default: 0
FF_DUR5
For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in FREE_FALL (5Dh)
configuration.
1 LSB = 1 ODR_time
WAKE_DUR[1:0]
Wake up duration event. Default: 00
1LSB = 1 ODR_time
Weight of 1 LSB of wakeup threshold. Default: 0
WAKE_THS_W
(0: 1 LSB = FS_XL / (26);
1: 1 LSB = FS_XL / (28) )
SLEEP_DUR[3:0]
DS12140 - Rev 2
Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR)
1 LSB = 512 ODR
page 77/172
LSM6DSO
FREE_FALL (5Dh)
9.48
FREE_FALL (5Dh)
Free-fall function duration setting register (r/w)
Table 133. FREE_FALL register
FF_DUR4
FF_DUR3
FF_DUR2
FF_DUR1
FF_DUR0
FF_THS2
FF_THS1
FF_THS0
Table 134. FREE_FALL register description
Free-fall duration event. Default: 0
FF_DUR[4:0] For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch)
configuration
FF_THS[2:0]
Free fall threshold setting. Default: 000
For details refer to Table 135.
Table 135. Threshold for free-fall function
DS12140 - Rev 2
FF_THS[2:0]
Threshold value
000
156 mg
001
219 mg
010
250 mg
011
312 mg
100
344 mg
101
406 mg
110
469 mg
111
500 mg
page 78/172
LSM6DSO
MD1_CFG (5Eh)
9.49
MD1_CFG (5Eh)
Functions routing on INT1 register (r/w)
Table 136. MD1_CFG register
INT1_
INT1_
SLEEP_
CHANGE
SINGLE_
TAP
INT1_
INT1_WU
INT1_FF
DOUBLE_
TAP
INT1_6D
INT1_
EMB_FUNC
INT1_
SHUB
Table 137. MD1_CFG register description
Routing of activity/inactivity recognition event on INT1. Default: 0
INT1_SLEEP_CHANGE(1)
(0: routing of activity/inactivity event on INT1 disabled;
1: routing of activity/inactivity event on INT1 enabled)
Routing of single-tap recognition event on INT1. Default: 0
INT1_SINGLE_TAP
(0: routing of single-tap event on INT1 disabled;
1: routing of single-tap event on INT1 enabled)
Routing of wakeup event on INT1. Default value: 0
INT1_WU
(0: routing of wakeup event on INT1 disabled;
1: routing of wakeup event on INT1 enabled)
Routing of free-fall event on INT1. Default value: 0
INT1_FF
(0: routing of free-fall event on INT1 disabled;
1: routing of free-fall event on INT1 enabled)
Routing of tap event on INT1. Default value: 0
INT1_DOUBLE_TAP
(0: routing of double-tap event on INT1 disabled;
1: routing of double-tap event on INT1 enabled)
Routing of 6D event on INT1. Default value: 0
INT1_6D
(0: routing of 6D event on INT1 disabled;
1: routing of 6D event on INT1 enabled)
Routing of embedded functions event on INT1. Default value: 0
INT1_EMB_FUNC
(0: routing of embedded functions event on INT1 disabled;
1: routing embedded functions event on INT1 enabled)
Routing of sensor hub communication concluded event on INT1.
INT1_SHUB
Default value: 0
(0: routing of sensor hub communication concluded event on INT1 disabled;
1: routing of sensor hub communication concluded event on INT1 enabled)
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in TAP_CFG0
(56h) register.
DS12140 - Rev 2
page 79/172
LSM6DSO
MD2_CFG (5Fh)
9.50
MD2_CFG (5Fh)
Functions routing on INT2 register (r/w)
Table 138. MD2_CFG register
INT2_
SLEEP_
CHANGE
INT2_
INT2_
SINGLE_
TAP
INT2_WU
INT2_FF
DOUBLE_
INT2_
INT2_6D
TAP
EMB_
INT2_
TIMESTAMP
FUNC
Table 139. MD2_CFG register description
Routing of activity/inactivity recognition event on INT2. Default: 0
INT2_SLEEP_CHANGE(1)
(0: routing of activity/inactivity event on INT2 disabled;
1: routing of activity/inactivity event on INT2 enabled)
Single-tap recognition routing on INT2. Default: 0
INT2_SINGLE_TAP
(0: routing of single-tap event on INT2 disabled;
1: routing of single-tap event on INT2 enabled)
Routing of wakeup event on INT2. Default value: 0
INT2_WU
(0: routing of wakeup event on INT2 disabled;
1: routing of wake-up event on INT2 enabled)
Routing of free-fall event on INT2. Default value: 0
INT2_FF
(0: routing of free-fall event on INT2 disabled;
1: routing of free-fall event on INT2 enabled)
Routing of tap event on INT2. Default value: 0
INT2_DOUBLE_TAP
(0: routing of double-tap event on INT2 disabled;
1: routing of double-tap event on INT2 enabled)
Routing of 6D event on INT2. Default value: 0
INT2_6D
(0: routing of 6D event on INT2 disabled;
1: routing of 6D event on INT2 enabled)
Routing of embedded functions event on INT2. Default value: 0
INT2_EMB_FUNC
(0: routing of embedded functions event on INT2 disabled;
1: routing embedded functions event on INT2 enabled)
INT2_TIMESTAMP
Enables routing on INT2 pin of the alert for timestamp overflow within
6.4 ms
1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in TAP_CFG0
(56h) register.
DS12140 - Rev 2
page 80/172
LSM6DSO
I3C_BUS_AVB (62h)
9.51
I3C_BUS_AVB (62h)
I3C_BUS_AVB register (r/w)
Table 140. I3C_BUS_AVB register
0(1)
0(1)
0(1)
I3C_Bus_Avb I3C_Bus_Avb
_Sel1
_Sel0
0(1)
0(1)
PD_DIS_
INT1
1. This bit must be set to '0' for the correct operation of the device.
Table 141. I3C_BUS_AVB register description
This bit allows disabling the INT1 pull-down.
(0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed
to the INT1 pin or when I3C dynamic address is assigned);
PD_DIS_INT1
1: Pull-down on INT1 disabled (pull-down not connected)
These bits are used to select the bus available time when I3C IBI is used.
Default value: 00
I3C_Bus_Avb_Sel[1:0]
(00: bus available time equal to 50 µsec (default);
01: bus available time equal to 2 µsec;
10: bus available time equal to 1 msec;
11: bus available time equal to 25 msec)
9.52
INTERNAL_FREQ_FINE (63h)
Internal frequency register (r)
Table 142. INTERNAL_FREQ_FINE register
FREQ_
FINE7
FREQ_
FINE6
FREQ_
FINE5
FREQ_
FINE4
FREQ_
FINE3
FREQ_
FINE2
FREQ_
FINE1
FREQ_
FINE0
Table 143. INTERNAL_FREQ_FINE register description
FREQ_FINE[7:0]
DS12140 - Rev 2
Difference in percentage of the effective ODR (and Timestamp Rate) with respect to the typical. Step:
0.15%. 8-bit format, 2's complement.
page 81/172
LSM6DSO
INT_OIS (6Fh)
9.53
INT_OIS (6Fh)
OIS interrupt configuration register and accelerometer self-test enable setting. Primary interface for read-only (r);
only Aux SPI can write to this register (r/w).
Table 144. INT_OIS register
INT2_
DRDY_OIS
LVL2_OIS
DEN_LH_OIS
-
-
0
ST1_XL_OIS
ST0_XL_OIS
Table 145. INT_OIS register description
INT2_DRDY_OIS
Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings.
LVL2_OIS
Enables level-sensitive latched mode on the OIS chain. Default value: 0
Indicates polarity of DEN signal on OIS chain
DEN_LH_OIS
(0: DEN pin is active-low;
1: DEN pin is active-high)
Selects accelerometer self-test – effective only if XL OIS chain is enabled. Default value: 00
(00: Normal mode;
ST[1:0]_XL_OIS
01: Positive sign self-test;
10: Negative sign self-test;
11: not allowed)
DS12140 - Rev 2
page 82/172
LSM6DSO
CTRL1_OIS (70h)
9.54
CTRL1_OIS (70h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
Table 146. CTRL1_OIS register
0
LVL1_OIS
SIM_OIS
Mode4_EN
FS1_G_
OIS
FS0_G_
OIS
FS_125_
OIS
OIS_EN_
SPI2
Table 147. CTRL1_OIS register description
LVL1_OIS
Enables OIS data level-sensitive trigger
SPI2 3- or 4-wire interface. Default value: 0
SIM_OIS
(0: 4-wire SPI2;
1: 3-wire SPI2)
Mode4_EN
Enables accelerometer OIS chain. OIS outputs are available through SPI2 in registers 28h-2Dh.
Note: OIS_EN_SPI2 must be enabled (i.e. set to ‘1’) to enable also XL OIS chain.
Selects gyroscope OIS chain full-scale
(00: 250 dps;
FS[1:0]_G_OIS 01: 500 dps;
10: 1000 dps;
11: 2000 dps)
Selects gyroscope OIS chain full-scale 125 dps
FS_125_OIS
(0: FS selected through bits FS[1:0]_OIS_G;
1: 125 dps)
Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data
in and Mode 4 (mode4_en = 1).
OIS_EN_SPI2
When the OIS chain is enabled, the OIS outputs are available through the SPI2 in registers OUTX_L_G
(22h) and OUTX_H_G (23h) through not found and STATUS_REG (1Eh) / STATUS_SPIAux (1Eh), and LPF1
is dedicated to this chain.
DEN mode selection can be done using the LVL1_OIS bit of register CTRL1_OIS (70h) and the LVL2_OIS bit of
register INT_OIS (6Fh).
DEN mode on the OIS path is active in the gyroscope only.
Table 148. DEN mode selection
DS12140 - Rev 2
LVL1_OIS, LVL2_OIS
DEN mode
10
Level-sensitive trigger mode is selected
11
Level-sensitive latched mode is selected
page 83/172
LSM6DSO
CTRL2_OIS (71h)
9.55
CTRL2_OIS (71h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
Table 149. CTRL2_OIS register
-
-
HPM1_OIS
HPM0_OIS
0
FTYPE_1
_OIS
FTYPE_0
_OIS
HP_EN_OIS
Table 150. CTRL2_OIS register description
Selects gyroscope OIS chain digital high-pass filter cutoff. Default value: 00
(00: 16 mHz;
HPM[1:0]_OIS
01: 65 mHz;
10: 260 mHz;
11: 1.04 Hz)
FTYPE_[1:0]_OIS
Selects gyroscope digital LPF1 filter bandwidth. Table 151 shows cutoff and phase values obtained with all
configurations.
HP_EN_OIS
Enables gyroscope OIS chain digital high-pass filter
Table 151. Gyroscope OIS chain digital LPF1 filter bandwidth selection
DS12140 - Rev 2
FTYPE_[1:0]_OIS
Cutoff [Hz]
Phase @ 20 Hz [°]
00
335.5
-6.69
01
232.0
-8.78
10
171.1
-11.18
11
609.0
-4.91
page 84/172
LSM6DSO
CTRL3_OIS (72h)
9.56
CTRL3_OIS (72h)
OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w).
Table 152. CTRL3_OIS register
FS1_XL_
OIS
FS0_XL_
OIS
FILTER_XL_ FILTER_XL_ FILTER_XL_
CONF_OIS_2 CONF_OIS_1 CONF_OIS_0
ST1_OIS
ST_OIS_
CLAMPDIS
ST0_OIS
Table 153. CTRL3_OIS register description
FS[1:0]_XL_OIS
Selects accelerometer OIS channel full-scale. See Table 154.
FILTER_XL_
CONF_OIS_[2:0]
Selects accelerometer OIS channel bandwidth. See Table 155.
Selects gyroscope OIS chain self-test. Default value: 00
Table 156 lists the output variation when the self-test is enabled and ST_OIS_CLAMPDIS = '1'.
(00: Normal mode;
ST[1:0]_OIS
01: Positive sign self-test;
10: Normal mode;
11: Negative sign self-test)
Disables OIS chain clamp
ST_OIS_
CLAMPDIS
(0: All OIS chain outputs = 8000h during self-test;
1: OIS chain self-test outputs as shown in Table 156.
Table 154. Accelerometer OIS channel full-scale selection
XL_FS_MODE = ‘0’
FS[1:0]_XL_OIS
XL UI ON
00 (default)
01
Full-scale selected from user interface
10
11
XL_FS_MODE = ‘1’
XL UI PD
-
2g
2g
16 g
2g
4g
4g
8g
8g
Note:
XL_FS_MODE bit is in CTRL8_XL (17h).
Note:
When the accelerometer full-scale value is selected only from the UI side it is readable also from the OIS side.
Table 155. Accelerometer OIS channel bandwidth and phase
DS12140 - Rev 2
FILTER_XL_CONF_OIS[2:0]
Typ. overall bandwidth [Hz]
Typ. overall phase [°]
000
289
-5.72 @ 20 Hz
001
258
-6.80 @ 20 Hz
010
120
-13.2 @ 20 Hz
011
65.1
-21.5 @ 20 Hz
100
33.2
-19.1 @ 10 Hz
101
16.6
-33.5 @ 10 Hz
page 85/172
LSM6DSO
X_OFS_USR (73h)
FILTER_XL_CONF_OIS[2:0]
Typ. overall bandwidth [Hz]
Typ. overall phase [°]
110
8.30
-26.7 @ 4 Hz
111
4.14
-26.2 @ 2 Hz
Table 156. Self-test nominal output variation
9.57
Full scale
Ouput variation [dps]
2000
400
1000
200
500
100
250
50
125
25
X_OFS_USR (73h)
Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is
internally subtracted from the acceleration value measured on the X-axis.
Table 157. X_OFS_USR register
X_OFS_
USR_7
X_OFS_
USR_6
X_OFS_
USR_5
X_OFS_
USR_4
X_OFS_
USR_3
X_OFS_
USR_2
X_OFS_
USR_1
X_OFS_
USR_0
Table 158. X_OFS_USR register description
X_OFS_USR_[7:0]
9.58
Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127].
Y_OFS_USR (74h)
Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Y-axis.
Table 159. Y_OFS_USR register
Y_OFS_
USR_7
Y_OFS_
USR_6
Y_OFS_
USR_5
Y_OFS_
USR_4
Y_OFS_
USR_3
Y_OFS_
USR_2
Y_OFS_
USR_1
Y_OFS_
USR_0
Table 160. Y_OFS_USR register description
Y_OFS_USR_[7:0]
DS12140 - Rev 2
Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
page 86/172
LSM6DSO
Z_OFS_USR (75h)
9.59
Z_OFS_USR (75h)
Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is
internally subtracted from the acceleration value measured on the Z-axis.
Table 161. Z_OFS_USR register
Z_OFS_
USR_7
Z_OFS_
USR_6
Z_OFS_
USR_5
Z_OFS_
USR_4
Z_OFS_
USR_3
Z_OFS_
USR_2
Z_OFS_
USR_1
Z_OFS_
USR_0
Table 162. Z_OFS_USR register description
Z_OFS_USR_[7:0]
9.60
Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on
USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127].
FIFO_DATA_OUT_TAG (78h)
FIFO tag register (r)
Table 163. FIFO_DATA_OUT_TAG register
TAG_
SENSOR_4
TAG_
SENSOR_3
TAG_
SENSOR_2
TAG_
SENSOR_1
TAG_
SENSOR_0
TAG_CNT_1
TAG_CNT_0
TAG_
PARITY
Table 164. FIFO_DATA_OUT_TAG register description
FIFO tag: identifies the sensor in:
TAG_SENSOR_[4:0]
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah), FIFO_DATA_OUT_Y_L (7Bh) and
FIFO_DATA_OUT_Y_H (7Ch), and FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
For details, refer to Table 165
TAG_CNT_[1:0]
2-bit counter which identifies sensor time slot
TAG_PARITY
Parity check of TAG content
Table 165. FIFO tag
DS12140 - Rev 2
TAG_SENSOR_[4:0]
Sensor name
0x01
Gyroscope NC
0x02
Accelerometer NC
0x03
Temperature
0x04
Timestamp
0x05
CFG_Change
0x06
Accelerometer NC_T_2
0x07
Accelerometer NC_T_1
0x08
Accelerometer 2xC
0x09
Accelerometer 3xC
0x0A
Gyroscope NC_T_2
0x0B
Gyroscope NC_T_1
0x0C
Gyroscope 2xC
0x0D
Gyroscope 3xC
0x0E
Sensor Hub Slave 0
page 87/172
LSM6DSO
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
9.61
TAG_SENSOR_[4:0]
Sensor name
0x0F
Sensor Hub Slave 1
0x10
Sensor Hub Slave 2
0x11
Sensor Hub Slave 3
0x12
Step Counter
0x19
Sensor Hub Nack
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah)
FIFO data output X (r)
Table 166. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 167. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
FIFO X-axis output
D[15:0]
9.62
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch)
FIFO data output Y (r)
Table 168. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 169. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
FIFO Y-axis output
D[15:0]
9.63
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh)
FIFO data output Z (r)
Table 170. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 171. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description
D[15:0]
DS12140 - Rev 2
FIFO Z-axis output
page 88/172
LSM6DSO
Embedded functions register mapping
10
Embedded functions register mapping
The table given below provides a list of the registers for the embedded functions available in the device and the
corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in
FUNC_CFG_ACCESS (01h).
Table 172. Register address map - embedded functions
Name
Type
Register address
Hex
Binary
Default
PAGE_SEL
r/w
02
00000010
00000001
EMB_FUNC_EN_A
r/w
04
00000100
00000000
EMB_FUNC_EN_B
r/w
05
00000101
00000000
PAGE_ADDRESS
r/w
08
00001000
00000000
PAGE_VALUE
r/w
09
00001001
00000000
EMB_FUNC_INT1
r/w
0A
00001010
00000000
FSM_INT1_A
r/w
0B
00001011
00000000
FSM_INT1_B
r/w
0C
00001100
00000000
EMB_FUNC_INT2
r/w
0E
00001110
00000000
FSM_INT2_A
r/w
0F
00001111
00000000
FSM_INT2_B
r/w
10
00010000
00000000
EMB_FUNC_STATUS
r
12
00010010
output
FSM_STATUS_A
r
13
00010011
output
FSM_STATUS_B
r
14
00010100
output
r/w
17
00010111
00000000
PAGE_RW
RESERVED
18-43
EMB_FUNC_FIFO_CFG
r/w
44
01000100
00000000
FSM_ENABLE_A
r/w
46
01000110
00000000
FSM_ENABLE_B
r/w
47
01000111
00000000
FSM_LONG_COUNTER_L
r/w
48
01001000
00000000
FSM_LONG_COUNTER_H
r/w
49
01001001
00000000
FSM_LONG_COUNTER_CLEAR
r/w
4A
01001010
00000000
r
4C
01001100
output
FSM_OUTS1
FSM_OUTS2
r
4D
01001101
output
FSM_OUTS3
r
4E
01001110
output
FSM_OUTS4
r
4F
01001111
output
FSM_OUTS5
r
50
01010000
output
FSM_OUTS6
r
51
01010001
output
FSM_OUTS7
r
52
01010010
output
FSM_OUTS8
r
53
01010011
output
FSM_OUTS9
r
54
01010100
output
FSM_OUTS10
r
55
01010101
output
DS12140 - Rev 2
Comment
page 89/172
LSM6DSO
Embedded functions register mapping
Name
Type
Register address
Hex
Binary
Default
FSM_OUTS11
r
56
01010110
output
FSM_OUTS12
r
57
01010111
output
FSM_OUTS13
r
58
01011000
output
FSM_OUTS14
r
59
01011001
output
FSM_OUTS15
r
5A
01011010
output
FSM_OUTS16
r
5B
01011011
output
5E
01011110
r/w
5F
01011111
01001011
STEP_COUNTER_L
r
62
01100010
output
STEP_COUNTER_H
r
63
01100011
output
EMB_FUNC_SRC
r/w
64
01100100
output
EMB_FUNC_INIT_A
r/w
66
01100110
00000000
EMB_FUNC_INIT_B
r/w
67
01100111
00000000
RESERVED
EMB_FUNC_ODR_CFG_B
Comment
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to
the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
DS12140 - Rev 2
page 90/172
LSM6DSO
Embedded functions register description
11
Embedded functions register description
11.1
PAGE_SEL (02h)
Enable advanced features dedicated page (r/w)
Table 173. PAGE_SEL register
PAGE_SEL3
PAGE_SEL2
PAGE_SEL1
0(1)
PAGE_SEL0
0(1)
0(1)
1(2)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
Table 174. PAGE_SEL register description
Select the advanced features dedicated page
PAGE_SEL[3:0]
11.2
Default value: 0000
EMB_FUNC_EN_A (04h)
Embedded functions enable register (r/w)
Table 175. EMB_FUNC_EN_A register
0(1)
0(1)
SIGN_
MOTION_EN
TILT_EN
PEDO_EN
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 176. EMB_FUNC_EN_A register description
Enable significant motion detection function. Default value: 0
SIGN_MOTION_EN
(0: significant motion detection function disabled;
1: significant motion detection function enabled)
Enable tilt calculation. Default value: 0
TILT_EN
(0: tilt algorithm disabled;
1: tilt algorithm enabled)
Enable pedometer algorithm. Default value: 0
PEDO_EN
(0: pedometer algorithm disabled;
1: pedometer algorithm enabled)
DS12140 - Rev 2
page 91/172
LSM6DSO
EMB_FUNC_EN_B (05h)
11.3
EMB_FUNC_EN_B (05h)
Embedded functions enable register (r/w)
Table 177. EMB_FUNC_EN_B register
0(1)
0(1)
PEDO_
ADV_EN
0(1)
FIFO_
COMPR_EN
0(1)
0(1)
FSM_EN
1. This bit must be set to '0' for the correct operation of the device.
Table 178. EMB_FUNC_EN_B register description
Enable pedometer false-positive rejection block and advanced detection feature block. Default value: 0
PEDO_ADV_EN
(0: Pedometer advanced features block disabled;
1: Pedometer advanced features block enabled)
Enable FIFO compression feature. Default value: 0
FIFO_COMPR_EN(1)
(0: FIFO compression feature disabled;
1: FIFO compression feature enabled)
FSM_EN
Enable Finite State Machine (FSM) feature. Default value: 0
(0: FSM feature disabled; 1: FSM feature enabled)
1. This bit is effective if the FIFO_COMPR_RT_EN bit of FIFO_CTRL2 (08h) is set to 1.
11.4
PAGE_ADDRESS (08h)
Page address register (r/w)
Table 179. PAGE_ADDRESS register
PAGE_
ADDR7
PAGE_
ADDR6
PAGE_
ADDR5
PAGE_
ADDR4
PAGE_
ADDR3
PAGE_
ADDR2
PAGE_
ADDR1
PAGE_
ADDR0
Table 180. PAGE_ADDRESS register description
After setting the bit PAGE_WRITE / PAGE_READ in register PAGE_RW (17h), this register is used to set
PAGE_ADDR[7:0] the address of the register to be written/read in the advanced features page selected through the bits
PAGE_SEL[3:0] in register PAGE_SEL (02h).
DS12140 - Rev 2
page 92/172
LSM6DSO
PAGE_VALUE (09h)
11.5
PAGE_VALUE (09h)
Page value register (r/w)
Table 181. PAGE_VALUE register
PAGE_
VALUE7
PAGE_
VALUE6
PAGE_
VALUE5
PAGE_
VALUE4
PAGE_
VALUE3
PAGE_
VALUE2
PAGE_
VALUE1
PAGE_
VALUE0
Table 182. PAGE_VALUE register description
These bits are used to write (if the bit PAGE_WRITE = 1 in register PAGE_RW (17h)) or read (if the bit
PAGE_VALUE[7:0] PAGE_READ = 1 in register PAGE_RW (17h)) the data at the address PAGE_ADDR[7:0] of the selected
advanced features page.
11.6
EMB_FUNC_INT1 (0Ah)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 183. EMB_FUNC_INT1 register
INT1_
FSM_LC
0(1)
INT1_
SIG_MOT
INT1_TILT
INT1_STEP_
DETECTOR
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 184. EMB_FUNC_INT1 register description
INT1_FSM_LC(1)
INT1_SIG_MOT(1)
INT1_TILT(1)
INT1_STEP_
DETECTOR(1)
Routing of FSM long counter timeout interrupt event on INT1. Default value: 0 (0: routing on INT1
disabled; 1: routing on INT1 enabled)
Routing of significant motion event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of tilt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of pedometer step recognition event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
DS12140 - Rev 2
page 93/172
LSM6DSO
FSM_INT1_A (0Bh)
11.7
FSM_INT1_A (0Bh)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 185. FSM_INT1_A register
INT1_
FSM8
INT1_
FSM7
INT1_
FSM6
INT1_
FSM5
INT1_
FSM4
INT1_
FSM3
INT1_
FSM2
INT1_
FSM1
Table 186. FSM_INT1_A register description
INT1_FSM8(1)
INT1_FSM7(1)
INT1_FSM6(1)
INT1_FSM5(1)
INT1_FSM4(1)
INT1_FSM3(1)
INT1_FSM2(1)
INT1_FSM1(1)
Routing of FSM8 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM7 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM6 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM5 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM4 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM3 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM2 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM1 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
DS12140 - Rev 2
page 94/172
LSM6DSO
FSM_INT1_B (0Ch)
11.8
FSM_INT1_B (0Ch)
INT1 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT1. The pin's output will supply the OR
combination of the selected signals.
Table 187. FSM_INT1_B register
INT1_
FSM16
INT1_
FSM15
INT1_
FSM14
INT1_
FSM13
INT1_
FSM12
INT1_
FSM11
INT1_
FSM10
INT1_
FSM9
Table 188. FSM_INT1_B register description
INT1_FSM16(1)
INT1_FSM15(1)
INT1_FSM14(1)
INT1_FSM13(1)
INT1_FSM12(1)
INT1_FSM11(1)
INT1_FSM10(1)
INT1_FSM9(1)
Routing of FSM16 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM15 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM14 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM13 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM12 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM11 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM10 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
Routing of FSM9 interrupt event on INT1. Default value: 0
(0: routing on INT1 disabled; 1: routing on INT1 enabled)
1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1.
DS12140 - Rev 2
page 95/172
LSM6DSO
EMB_FUNC_INT2 (0Eh)
11.9
EMB_FUNC_INT2 (0Eh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 189. EMB_FUNC_INT2 register
INT2_
FSM_LC
0(1)
INT2_
SIG_MOT
INT2_TILT
INT2_STEP_
DETECTOR
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 190. EMB_FUNC_INT2 register description
INT2_FSM_LC(1)
INT2_SIG_MOT(1)
INT2_TILT(1)
INT2_STEP_
DETECTOR(1)
Routing of FSM long counter timeout interrupt event on INT2. Default value: 0 (0: routing on INT2
disabled; 1: routing on INT2 enabled)
Routing of significant motion event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of tilt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of pedometer step recognition event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
DS12140 - Rev 2
page 96/172
LSM6DSO
FSM_INT2_A (0Fh)
11.10
FSM_INT2_A (0Fh)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 191. FSM_INT2_A register
INT2_
FSM8
INT2_
FSM7
INT2_
FSM6
INT2_
FSM5
INT2_
FSM4
INT2_
FSM3
INT2_
FSM2
INT2_
FSM1
Table 192. FSM_INT2_A register description
INT2_FSM8(1)
INT2_FSM7(1)
INT2_FSM6(1)
INT2_FSM5(1)
INT2_FSM4(1)
INT2_FSM3(1)
INT2_FSM2(1)
INT2_FSM1(1)
Routing of FSM8 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM7 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM6 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM5 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM4 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM3 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM2 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM1 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
DS12140 - Rev 2
page 97/172
LSM6DSO
FSM_INT2_B (10h)
11.11
FSM_INT2_B (10h)
INT2 pin control register (r/w)
Each bit in this register enables a signal to be carried through INT2. The pin's output will supply the OR
combination of the selected signals.
Table 193. FSM_INT2_B register
INT2_
FSM16
INT2_
FSM15
INT2_
FSM14
INT2_
FSM13
INT2_
FSM12
INT2_
FSM11
INT2_
FSM10
INT2_
FSM9
Table 194. FSM_INT2_B register description
INT2_FSM16(1)
INT2_FSM15(1)
INT2_FSM14(1)
INT2_FSM13(1)
INT2_FSM12(1)
INT2_FSM11(1)
INT2_FSM10(1)
INT2_FSM9(1)
Routing of FSM16 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM15 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM14 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM13 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM12 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM11 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM10 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
Routing of FSM9 interrupt event on INT2. Default value: 0
(0: routing on INT2 disabled; 1: routing on INT2 enabled)
1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1.
DS12140 - Rev 2
page 98/172
LSM6DSO
EMB_FUNC_STATUS (12h)
11.12
EMB_FUNC_STATUS (12h)
Embedded function status register (r)
Table 195. EMB_FUNC_STATUS register
IS_
FSM_LC
0
IS_
SIGMOT
IS_
TILT
IS_
STEP_DET
0
0
0
Table 196. EMB_FUNC_STATUS register description
IS_FSM_LC
IS_SIGMOT
IS_TILT
IS_STEP_DET
DS12140 - Rev 2
Interrupt status bit for FSM long counter timeout interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for significant motion detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for tilt detection
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for step detection
(1: interrupt detected; 0: no interrupt)
page 99/172
LSM6DSO
FSM_STATUS_A (13h)
11.13
FSM_STATUS_A (13h)
Finite State Machine status register (r)
Table 197. FSM_STATUS_A register
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
Table 198. FSM_STATUS_A register description
IS_FSM8
IS_FSM7
IS_FSM6
IS_FSM5
IS_FSM4
IS_FSM3
IS_FSM2
IS_FSM1
DS12140 - Rev 2
Interrupt status bit for FSM8 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM7 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM6 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM5 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM4 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM3 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM2 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM1 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 100/172
LSM6DSO
FSM_STATUS_B (14h)
11.14
FSM_STATUS_B (14h)
Finite State Machine status register (r)
Table 199. FSM_STATUS_B register
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
Table 200. FSM_STATUS_B register description
IS_FSM16
IS_FSM15
IS_FSM14
IS_FSM13
IS_FSM12
IS_FSM11
IS_FSM10
IS_FSM9
DS12140 - Rev 2
Interrupt status bit for FSM16 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM15 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM14 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM13 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM12 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM11 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM10 interrupt event.
(1: interrupt detected; 0: no interrupt)
Interrupt status bit for FSM9 interrupt event.
(1: interrupt detected; 0: no interrupt)
page 101/172
LSM6DSO
PAGE_RW (17h)
11.15
PAGE_RW (17h)
Enable read and write mode of advanced features dedicated page (r/w)
Table 201. PAGE_RW register
EMB_
FUNC_LIR
PAGE_
WRITE
PAGE_
READ
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 202. PAGE_RW register description
Latched Interrupt mode for embedded functions. Default value: 0
EMB_FUNC_LIR
(0: Embedded Functions interrupt request not latched;
1: Embedded Functions interrupt request latched)
Enable writes to the selected advanced features dedicated page. (1)
PAGE_WRITE
Default value: 0
(1: enable; 0: disable)
Enable reads from the selected advanced features dedicated page.(1)
PAGE_READ
Default value: 0
(1: enable; 0: disable)
1. Page selected by PAGE_SEL[3:0] in PAGE_SEL (02h) register.
11.16
EMB_FUNC_FIFO_CFG (44h)
Embedded functions batching configuration register (r/w)
Table 203. EMB_FUNC_FIFO_CFG register
0(1)
PEDO_
FIFO_EN
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 204. EMB_FUNC_FIFO_CFG register description
PEDO_FIFO_EN
DS12140 - Rev 2
Enable FIFO batching of step counter values. Default value: 0
page 102/172
LSM6DSO
FSM_ENABLE_A (46h)
11.17
FSM_ENABLE_A (46h)
FSM enable register (r/w)
Table 205. FSM_ENABLE_A register
FSM8_EN
FSM7_EN
FSM6_EN
FSM5_EN
FSM4_EN
FSM3_EN
FSM2_EN
FSM1_EN
FSM10_EN
FSM9_EN
Table 206. FSM_ENABLE_A register description
11.18
FSM8_EN
FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled)
FSM7_EN
FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled)
FSM6_EN
FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled)
FSM5_EN
FSM5 enable. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled)
FSM4_EN
FSM4 enable. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled)
FSM3_EN
FSM3 enable. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled)
FSM2_EN
FSM2 enable. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled)
FSM1_EN
FSM1 enable. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled)
FSM_ENABLE_B (47h)
FSM enable register (r/w)
Table 207. FSM_ENABLE_B register
FSM16_EN
FSM15_EN
FSM14_EN
FSM13_EN
FSM12_EN
FSM11_EN
Table 208. FSM_ENABLE_B register description
DS12140 - Rev 2
FSM16_EN
FSM16 enable. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled)
FSM15_EN
FSM15 enable. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled)
FSM14_EN
FSM14 enable. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled)
FSM13_EN
FSM13 enable. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled)
FSM12_EN
FSM12 enable. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled)
FSM11_EN
FSM11 enable. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled)
FSM10_EN
FSM10 enable. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled)
FSM9_EN
FSM9 enable. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled)
page 103/172
LSM6DSO
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
11.19
FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h)
FSM long counter status register (r/w)
Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit
in FSM_LONG_COUNTER_CLEAR (4Ah) register.
Table 209. FSM_LONG_COUNTER_L register
FSM_LC_7
FSM_LC_6
FSM_LC_5
FSM_LC_4
FSM_LC_3
FSM_LC_2
FSM_LC_1
FSM_LC_0
FSM_LC_9
FSM_LC_8
FSM_LC_
CLEARED
FSM_LC_
CLEAR
Table 210. FSM_LONG_COUNTER_L register description
FSM_LC_[7:0]
Long counter current value (LSbyte). Default value: 00000000
Table 211. FSM_LONG_COUNTER_H register
FSM_LC_15
FSM_LC_14
FSM_LC_13
FSM_LC_12
FSM_LC_11
FSM_LC_10
Table 212. FSM_LONG_COUNTER_H register description
FSM_LC_[15:8]
11.20
Long counter current value (MSbyte). Default value: 00000000
FSM_LONG_COUNTER_CLEAR (4Ah)
FSM long counter reset register (r/w)
Table 213. FSM_LONG_COUNTER_CLEAR register
0(1)
0(1)
0(1)
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 214. FSM_LONG_COUNTER_CLEAR register description
DS12140 - Rev 2
FSM_LC_CLEARED
This read-only bit is automatically set to 1 when the long counter reset is done. Default value: 0
FSM_LC_CLEAR
Clear FSM long counter value. Default value: 0
page 104/172
LSM6DSO
FSM_OUTS1 (4Ch)
11.21
FSM_OUTS1 (4Ch)
FSM1 output register (r)
Table 215. FSM_OUTS1 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 216. FSM_OUTS1 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM1 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM1 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM1 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM1 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 105/172
LSM6DSO
FSM_OUTS2 (4Dh)
11.22
FSM_OUTS2 (4Dh)
FSM2 output register (r)
Table 217. FSM_OUTS2 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 218. FSM_OUTS2 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM2 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM2 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM2 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM2 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 106/172
LSM6DSO
FSM_OUTS3 (4Eh)
11.23
FSM_OUTS3 (4Eh)
FSM3 output register (r)
Table 219. FSM_OUTS3 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 220. FSM_OUTS3 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM3 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM3 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM3 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM3 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 107/172
LSM6DSO
FSM_OUTS4 (4Fh)
11.24
FSM_OUTS4 (4Fh)
FSM4 output register (r)
Table 221. FSM_OUTS4 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 222. FSM_OUTS4 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM4 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM4 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM4 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM4 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 108/172
LSM6DSO
FSM_OUTS5 (50h)
11.25
FSM_OUTS5 (50h)
FSM5 output register (r)
Table 223. FSM_OUTS5 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 224. FSM_OUTS5 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM5 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM5 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM5 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM5 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 109/172
LSM6DSO
FSM_OUTS6 (51h)
11.26
FSM_OUTS6 (51h)
FSM6 output register (r)
Table 225. FSM_OUTS6 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 226. FSM_OUTS6 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM6 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM6 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM6 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM6 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 110/172
LSM6DSO
FSM_OUTS7 (52h)
11.27
FSM_OUTS7 (52h)
FSM7 output register (r)
Table 227. FSM_OUTS7 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 228. FSM_OUTS7 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM7 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM7 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM7 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM7 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 111/172
LSM6DSO
FSM_OUTS8 (53h)
11.28
FSM_OUTS8 (53h)
FSM8 output register (r)
Table 229. FSM_OUTS8 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 230. FSM_OUTS8 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM8 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM8 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM8 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM8 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 112/172
LSM6DSO
FSM_OUTS9 (54h)
11.29
FSM_OUTS9 (54h)
FSM9 output register (r)
Table 231. FSM_OUTS9 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 232. FSM_OUTS9 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM9 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM9 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM9 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM9 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 113/172
LSM6DSO
FSM_OUTS10 (55h)
11.30
FSM_OUTS10 (55h)
FSM10 output register (r)
Table 233. FSM_OUTS10 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 234. FSM_OUTS10 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM10 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM10 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM10 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM10 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 114/172
LSM6DSO
FSM_OUTS11 (56h)
11.31
FSM_OUTS11 (56h)
FSM11 output register (r)
Table 235. FSM_OUTS11 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 236. FSM_OUTS11 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM11 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM11 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM11 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM11 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 115/172
LSM6DSO
FSM_OUTS12 (57h)
11.32
FSM_OUTS12 (57h)
FSM12 output register (r)
Table 237. FSM_OUTS12 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 238. FSM_OUTS12 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM12 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM12 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM12 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM12 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 116/172
LSM6DSO
FSM_OUTS13 (58h)
11.33
FSM_OUTS13 (58h)
FSM13 output register (r)
Table 239. FSM_OUTS13 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 240. FSM_OUTS13 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM13 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM13 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM13 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM13 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 117/172
LSM6DSO
FSM_OUTS14 (59h)
11.34
FSM_OUTS14 (59h)
FSM14 output register (r)
Table 241. FSM_OUTS14 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 242. FSM_OUTS14 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM14 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM14 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM14 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM14 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 118/172
LSM6DSO
FSM_OUTS15 (5Ah)
11.35
FSM_OUTS15 (5Ah)
FSM15 output register (r)
Table 243. FSM_OUTS15 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 244. FSM_OUTS15 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM15 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM15 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM15 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM15 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 119/172
LSM6DSO
FSM_OUTS16 (5Bh)
11.36
FSM_OUTS16 (5Bh)
FSM16 output register (r)
Table 245. FSM_OUTS16 register
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
Table 246. FSM_OUTS16 register description
P_X
N_X
P_Y
N_Y
P_Z
N_Z
P_V
N_V
DS12140 - Rev 2
FSM16 output: positive event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the X-axis.
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the Y-axis.
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM16 output: negative event detected on the Z-axis.
(0: event not detected; 1: event detected)
FSM16 output: positive event detected on the vector.
(0: event not detected; 1: event detected
FSM16 output: negative event detected on the vector.
(0: event not detected; 1: event detected)
page 120/172
LSM6DSO
EMB_FUNC_ODR_CFG_B (5Fh)
11.37
EMB_FUNC_ODR_CFG_B (5Fh)
Finite State Machine output data rate configuration register (r/w)
Table 247. EMB_FUNC_ODR_CFG_B register
0(1)
1(2)
0(1)
FSM_ODR1
FSM_ODR0
0(1)
1(2)
1(2)
STEP_1
STEP_0
STEP_9
STEP_8
1. This bit must be set to '0' for the correct operation of the device.
2. This bit must be set to '1' for the correct operation of the device.
Table 248. EMB_FUNC_ODR_CFG_B register description
Finite State Machine ODR configuration:
(00: 12.5 Hz;
FSM_ODR[1:0]
01: 26 Hz (default);
10: 52 Hz;
11: 104 Hz)
11.38
STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h)
Step counter output register (r)
Table 249. STEP_COUNTER_L register
STEP_7
STEP_6
STEP_5
STEP_4
STEP_3
STEP_2
Table 250. STEP_COUNTER_L register description
STEP_[7:0]
Step counter output (LSbyte)
Table 251. STEP_COUNTER_H register
STEP_15
STEP_14
STEP_13
STEP_12
STEP_11
STEP_10
Table 252. STEP_COUNTER_H register description
STEP_[15:8]
DS12140 - Rev 2
Step counter output (MSbyte)
page 121/172
LSM6DSO
EMB_FUNC_SRC (64h)
11.39
EMB_FUNC_SRC (64h)
Embedded function source register (r/w)
Table 253. EMB_FUNC_SRC register
STEP_
PEDO_RST
_STEP
STEP_
DETECTED
0
COUNT_
STEP_
OVERFLOW
STEPCOUNT
ER_BIT_SET
0
0
DELTA_IA
Table 254. EMB_FUNC_SRC register description
Reset pedometer step counter. Read/write bit.
PEDO_RST_STEP
(0: disabled; 1: enabled)
Step detector event detection status. Read-only bit.
STEP_DETECTED
(0: step detection event not detected; 1: step detection event detected)
Pedometer step recognition on delta time status. Read-only bit.
STEP_COUNT_DELTA_IA
(0: no step recognized during delta time;
1: at least one step recognized during delta time)
Step counter overflow status. Read-only bit.
STEP_OVERFLOW
(0: step counter value < 216; 1: step counter value reached 216)
This bit is equal to 1 when the step count is increased. If a timer period is programmed in
PEDO_SC_DELTAT_L (D0h) & PEDO_SC_DELTAT_H (D1h) embedded advanced features
STEPCOUNTER_BIT_SET (page 1) registers, this bit is kept to 0.
Read-only bit.
11.40
EMB_FUNC_INIT_A (66h)
Embedded functions initialization register (r/w)
Table 255. EMB_FUNC_INIT_A register
0(1)
0(1)
SIG_MOT
_INIT
TILT
_INIT
STEP_DET
_INIT
0(1)
0(1)
0(1)
1. This bit must be set to '0' for the correct operation of the device.
Table 256. EMB_FUNC_INIT_A register description
SIG_MOT_INIT
Significant motion detection algorithm initialization request. Default value: 0
TILT_INIT
Tilt algorithm initialization request. Default value: 0
STEP_DET_INIT
DS12140 - Rev 2
Pedometer step counter/detector algorithm initialization request.
Default value: 0
page 122/172
LSM6DSO
EMB_FUNC_INIT_B (67h)
11.41
EMB_FUNC_INIT_B (67h)
Embedded functions initialization register (r/w)
Table 257. EMB_FUNC_INIT_B register
0(1)
0(1)
0(1)
0(1)
FIFO_
COMPR_INIT
0(1)
0(1)
FSM_INIT
1. This bit must be set to '0' for the correct operation of the device.
Table 258. EMB_FUNC_INIT_B register description
DS12140 - Rev 2
FIFO_COMPR_INIT
FIFO compression feature initialization request. Default value: 0
FSM_INIT
FSM initialization request. Default value: 0
page 123/172
LSM6DSO
Embedded advanced features pages
12
Embedded advanced features pages
The table given below provides a list of the registers for the embedded advanced features page 0. These
registers are accessible when PAGE_SEL[3:0] are set to 0000 in PAGE_SEL (02h).
Table 259. Register address map - embedded advanced features page 0
Name
Register address
Type
Hex
Binary
10111010
Default
MAG_SENSITIVITY_L
r/w
BA
MAG_SENSITIVITY_H
r/w
BB
10111011
00010110
MAG_OFFX_L
r/w
C0
11000000
00000000
MAG_OFFX_H
r/w
C1
11000001
00000000
MAG_OFFY_L
r/w
C2
11000010
00000000
MAG_OFFY_H
r/w
C3
11000011
00000000
MAG_OFFZ_L
r/w
C4
11000100
00000000
MAG_OFFZ_H
r/w
C5
11000101
00000000
MAG_SI_XX_L
r/w
C6
11000110
00000000
MAG_SI_XX_H
r/w
C7
11000111
00111100
MAG_SI_XY_L
r/w
C8
11001000
00000000
MAG_SI_XY_H
r/w
C9
11001001
00000000
MAG_SI_XZ_L
r/w
CA
11001010
00000000
MAG_SI_XZ_H
r/w
CB
11001011
00000000
MAG_SI_YY_L
r/w
CC
11001100
00000000
MAG_SI_YY_H
r/w
CD
11001101
00111100
MAG_SI_YZ_L
r/w
CE
11001110
00000000
MAG_SI_YZ_H
r/w
CF
11001111
00000000
MAG_SI_ZZ_L
r/w
D0
11010000
00000000
MAG_SI_ZZ_H
r/w
D1
11010001
00111100
MAG_CFG_A
r/w
D4
11010100
00000101
MAG_CFG_B
r/w
D5
11010101
00000010
Comment
00100100
The table given below provides a list of the registers for the embedded advanced features page 1. These
registers are accessible when PAGE_SEL[3:0] are set to 0001 in PAGE_SEL (02h).
Table 260. Register address map - embedded advanced features page 1
Name
DS12140 - Rev 2
Type
Register address
Hex
Binary
Default
FSM_LC_TIMEOUT_L
r/w
7A
01111010
00000000
FSM_LC_TIMEOUT_H
r/w
7B
01111011
00000000
FSM_PROGRAMS
r/w
7C
01111100
00000000
Comment
page 124/172
LSM6DSO
Embedded advanced features pages
Name
Type
Register address
Hex
Binary
Default
FSM_START_ADD_L
r/w
7E
01111110
00000000
FSM_START_ADD_H
r/w
7F
01111111
00000000
PEDO_CMD_REG
r/w
83
10000011
00000000
PEDO_DEB_STEPS_CONF
r/w
84
10000100
00001010
PEDO_SC_DELTAT_L
r/w
D0
11010000
00000000
PEDO_SC_DELTAT_H
r/w
D1
11010001
00000000
Comment
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to
the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
Write procedure example:
Example: write value 06h register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
2. Write bit PAGE_WRITE = 1 in PAGE_RW (17h) register
// Select write operation mode
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h)
// Select page 1
4. Write 84h in PAGE_ADDR register (08h)
// Set address
5. Write 06h in PAGE_DATA register (09h)
// Set value to be written
6. Write bit PAGE_WRITE = 0 in PAGE_RW (17h) register
// Write operation disabled
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h)
// Disable access to embedded functions registers
Read procedure example:
Example: read value of register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1
Note:
DS12140 - Rev 2
1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h)
// Enable access to embedded functions registers
2. Write bit PAGE_READ = 1 in PAGE_RW (17h) register
// Select read operation mode
3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h)
// Select page 1
4. Write 84h in PAGE_ADDR register (08h)
// Set address
5. Read value of PAGE_DATA register (09h)
// Get register value
6. Write bit PAGE_READ = 0 in PAGE_RW (17h) register
// Read operation disabled
7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h)
// Disable access to embedded functions registers
Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps 6 and 7
of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple
operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, the multiple operations
involve consecutive registers, only step 5 can be performed.
page 125/172
LSM6DSO
Embedded advanced features register description
13
Embedded advanced features register description
13.1
Page 0 - Embedded advanced features registers
13.1.1
MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
External magnetometer sensitivity value register (r/w) for the Finite State Machine
This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor. The
register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5
exponent bits; F: 10 fraction bits).
Default value of MAG_SENS[15:0] is 0x1624, corresponding to 0.0015 gauss/LSB.
Table 261. MAG_SENSITIVITY_L register
MAG_
SENS_7
MAG_
SENS_6
MAG_
SENS_5
MAG_
SENS_4
MAG_
SENS_3
MAG_
SENS_2
MAG_
SENS_1
MAG_
SENS_0
MAG_
SENS_9
MAG_
SENS_8
Table 262. MAG_SENSITIVITY_L register description
MAG_SENS_[7:0]
External magnetometer sensitivity (LSbyte). Default value: 00100100
Table 263. MAG_SENSITIVITY_H register
MAG_
SENS_15
MAG_
SENS_14
MAG_
SENS_13
MAG_
SENS_12
MAG_
SENS_11
MAG_
SENS_10
Table 264. MAG_SENSITIVITY_H register description
MAG_SENS_[15:8]
DS12140 - Rev 2
External magnetometer sensitivity (MSbyte). Default value: 00010110
page 126/172
LSM6DSO
Page 0 - Embedded advanced features registers
13.1.2
MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h)
Offset for X-axis hard-iron compensation register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 265. MAG_OFFX_L register
MAG_OFFX_7
MAG_OFFX_6
MAG_OFFX_5
MAG_OFFX_4
MAG_OFFX_3
MAG_OFFX_2
MAG_OFFX_1
MAG_OFFX_0
Table 266. MAG_OFFX_L register description
MAG_OFFX_[7:0]
Offset for X-axis hard-iron compensation (LSbyte). Default value: 00000000
Table 267. MAG_OFFX_H register
MAG_OFFX_15
MAG_OFFX_14
MAG_OFFX_13
MAG_OFFX_12
MAG_OFFX_11
MAG_OFFX_10
MAG_OFFX_9
MAG_OFFX_8
Table 268. MAG_OFFX_H register description
MAG_OFFX_[15:8]
13.1.3
Offset for X-axis hard-iron compensation (MSbyte). Default value: 00000000
MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h)
Offset for Y-axis hard-iron compensation register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 269. MAG_OFFY_L register
MAG_OFFY_7
MAG_OFFY_6
MAG_OFFY_5
MAG_OFFY_4
MAG_OFFY_3
MAG_OFFY_2
MAG_OFFY_1
MAG_OFFY_0
Table 270. MAG_OFFY_L register description
MAG_OFFY_[7:0]
Offset for Y-axis hard-iron compensation (LSbyte). Default value: 00000000
Table 271. MAG_OFFY_H register
MAG_OFFY_15
MAG_OFFY_14
MAG_OFFY_13
MAG_OFFY_12
MAG_OFFY_11
MAG_OFFY_10
MAG_OFFY_9
MAG_OFFY_8
Table 272. MAG_OFFY_H register description
MAG_OFFY_[15:8]
DS12140 - Rev 2
Offset for Y-axis hard-iron compensation (MSbyte). Default value: 00000000
page 127/172
LSM6DSO
Page 0 - Embedded advanced features registers
13.1.4
MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h)
Offset for Z-axis hard-iron compensation register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 273. MAG_OFFZ_L register
MAG_OFFZ_7
MAG_OFFZ_6
MAG_OFFZ_5
MAG_OFFZ_4
MAG_OFFZ_3
MAG_OFFZ_2
MAG_OFFZ_1
MAG_OFFZ_0
Table 274. MAG_OFFZ_L register description
MAG_OFFZ_[7:0]
Offset for Z-axis hard-iron compensation (LSbyte). Default value: 00000000
Table 275. MAG_OFFZ_H register
MAG_OFFZ_15
MAG_OFFZ_14
MAG_OFFZ_13
MAG_OFFZ_12
MAG_OFFZ_11
MAG_OFFZ_10
MAG_OFFZ_9
MAG_OFFZ_8
Table 276. MAG_OFFZ_H register description
MAG_OFFZ_[15:8]
13.1.5
Offset for Z-axis hard-iron compensation (MSbyte). Default value: 00000000
MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 277. MAG_SI_XX_L register
MAG_SI_XX_7
MAG_SI_XX_6
MAG_SI_XX_5
MAG_SI_XX_4
MAG_SI_XX_3
MAG_SI_XX_2
MAG_SI_XX_1
MAG_SI_XX_0
Table 278. MAG_SI_XX_L register description
MAG_SI_XX_[7:0]
Soft-iron correction row1 col1 coefficient (LSbyte). Default value: 00000000
Table 279. MAG_SI_XX_H register
MAG_SI_XX_15
MAG_SI_XX_14
MAG_SI_XX_13
MAG_SI_XX_12
MAG_SI_XX_11
MAG_SI_XX_10
MAG_SI_XX_9
MAG_SI_XX_8
Table 280. MAG_SI_XX_H register description
MAG_SI_XX_[15:8]
DS12140 - Rev 2
Soft-iron correction row1 col1 coefficient (MSbyte). Default value: 00111100
page 128/172
LSM6DSO
Page 0 - Embedded advanced features registers
13.1.6
MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 281. MAG_SI_XY_L register
MAG_SI_XY_7
MAG_SI_XY_6
MAG_SI_XY_5
MAG_SI_XY_4
MAG_SI_XY_3
MAG_SI_XY_2
MAG_SI_XY_1
MAG_SI_XY_0
Table 282. MAG_SI_XY_L register description
MAG_SI_XY_[7:0]
Soft-iron correction row1 col2 (and row2 col1) coefficient (LSbyte). Default value: 00000000
Table 283. MAG_SI_XY_H register
MAG_SI_XY_15
MAG_SI_XY_14
MAG_SI_XY_13
MAG_SI_XY_12
MAG_SI_XY_11
MAG_SI_XY_10
MAG_SI_XY_9
MAG_SI_XY_8
Table 284. MAG_SI_XY_H register description
MAG_SI_XY_[15:8]
13.1.7
Soft-iron correction row1 col2 (and row2 col1) coefficient (MSbyte). Default value: 00000000
MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 285. MAG_SI_XZ_L register
MAG_SI_XZ_7
MAG_SI_XZ_6
MAG_SI_XZ_5
MAG_SI_XZ_4
MAG_SI_XZ_3
MAG_SI_XZ_2
MAG_SI_XZ_1
MAG_SI_XZ_0
Table 286. MAG_SI_XZ_L register description
MAG_SI_XZ_[7:0]
Soft-iron correction row1 col3 (and row3 col1) coefficient (LSbyte). Default value: 00000000
Table 287. MAG_SI_XZ_H register
MAG_SI_XZ_15
MAG_SI_XZ_14
MAG_SI_XZ_13
MAG_SI_XZ_12
MAG_SI_XZ_11
MAG_SI_XZ_10
MAG_SI_XZ_9
MAG_SI_XZ_8
Table 288. MAG_SI_XZ_H register description
MAG_SI_XZ_[15:8]
DS12140 - Rev 2
Soft-iron correction row1 col3 (and row3 col1) coefficient (MSbyte). Default value: 00000000
page 129/172
LSM6DSO
Page 0 - Embedded advanced features registers
13.1.8
MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 289. MAG_SI_YY_L register
MAG_SI_YY_7
MAG_SI_YY_6
MAG_SI_YY_5
MAG_SI_YY_4
MAG_SI_YY_3
MAG_SI_YY_2
MAG_SI_YY_1
MAG_SI_YY_0
Table 290. MAG_SI_YY_L register description
MAG_SI_YY_[7:0]
Soft-iron correction row2 col2 coefficient (LSbyte). Default value: 00000000
Table 291. MAG_SI_YY_H register
MAG_SI_YY_15
MAG_SI_YY_14
MAG_SI_YY_13
MAG_SI_YY_12
MAG_SI_YY_11
MAG_SI_YY_10
MAG_SI_YY_9
MAG_SI_YY_8
Table 292. MAG_SI_YY_H register description
MAG_SI_YY_[15:8]
13.1.9
Soft-iron correction row2 col2 coefficient (MSbyte). Default value: 00111100
MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 293. MAG_SI_YZ_L register
MAG_SI_YZ_7
MAG_SI_YZ_6
MAG_SI_YZ_5
MAG_SI_YZ_4
MAG_SI_YZ_3
MAG_SI_YZ_2
MAG_SI_YZ_1
MAG_SI_YZ_0
MAG_SI_YZ_9
MAG_SI_YZ_8
Table 294. MAG_SI_YZ_L register description
MAG_SI_YZ_[7:0]
Soft-iron correction row2 col3 (and row3 col2) coefficient (LSbyte).
Default value: 00000000
Table 295. MAG_SI_YZ_H register
MAG_SI_YZ_15
MAG_SI_YZ_14
MAG_SI_YZ_13
MAG_SI_YZ_12
MAG_SI_YZ_11
MAG_SI_YZ_10
Table 296. MAG_SI_YZ_H register description
MAG_SI_YZ_[15:8]
DS12140 - Rev 2
Soft-iron correction row2 col3 (and row3 col2) coefficient (MSbyte).
Default value: 00000000
page 130/172
LSM6DSO
Page 0 - Embedded advanced features registers
13.1.10
MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h)
Soft-iron (3x3 symmetric) matrix correction register (r/w)
The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
bits; F: 10 fraction bits).
Table 297. MAG_SI_ZZ_L register
MAG_SI_ZZ_7
MAG_SI_ZZ_6
MAG_SI_ZZ_5
MAG_SI_ZZ_4
MAG_SI_ZZ_3
MAG_SI_ZZ_2
MAG_SI_ZZ_1
MAG_SI_ZZ_0
Table 298. MAG_SI_ZZ_L register description
MAG_SI_ZZ_[7:0]
Soft-iron correction row3 col3 coefficient (LSbyte). Default value: 00000000
Table 299. MAG_SI_ZZ_H register
MAG_SI_ZZ_15
MAG_SI_ZZ_14
MAG_SI_ZZ_13
MAG_SI_ZZ_12
MAG_SI_ZZ_11
MAG_SI_ZZ_10
MAG_SI_ZZ_9
MAG_SI_ZZ_8
Table 300. MAG_SI_ZZ_H register description
MAG_SI_ZZ_[15:8]
DS12140 - Rev 2
Soft-iron correction row3 col3 coefficient (MSbyte). Default value: 00111100
page 131/172
LSM6DSO
Page 0 - Embedded advanced features registers
13.1.11
MAG_CFG_A (D4h)
External magnetometer coordinates (Y and Z axes) rotation register (r/w)
Table 301. MAG_CFG_A register
0(1)
MAG_Y_
AXIS2
MAG_Y_
AXIS1
MAG_Y_
AXIS0
0(1)
MAG_Z_
AXIS2
MAG_Z_
AXIS1
MAG_Z_
AXIS0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 302. MAG_CFG_A description
Magnetometer Y-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: Y = Y; (default)
001: Y = -Y;
MAG_Y_AXIS[2:0]
010: Y = X;
011: Y = -X;
100: Y = -Z;
101: Y = Z;
Others: Y = Y)
Magnetometer Z-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: Z = Y;
001: Z = -Y;
MAG_Z_AXIS[2:0]
010: Z = X;
011: Z = -X;
100: Z = -Z;
101: Z = Z; (default)
Others: Z = Y)
13.1.12
MAG_CFG_B (D5h)
External magnetometer coordinates (X-axis) rotation register (r/w).
Table 303. MAG_CFG_B register
0(1)
0(1)
0(1)
0(1)
0(1)
MAG_X_
AXIS2
MAG_X_
AXIS1
MAG_X_
AXIS0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 304. MAG_CFG_B description
Magnetometer X-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation)
(000: X = Y;
001: X = -Y;
MAG_X_AXIS[2:0]
010: X = X; (default)
011: X = -X;
100: X = -Z;
101: X = Z;
Others: X = Y)
DS12140 - Rev 2
page 132/172
LSM6DSO
Page 1 - Embedded advanced features registers
13.2
Page 1 - Embedded advanced features registers
13.2.1
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh)
FSM long counter timeout register (r/w)
The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reaches
this value, the FSM generates an interrupt.
Table 305. FSM_LC_TIMEOUT_L register
FSM_LC_
TIMEOUT7
FSM_LC_
TIMEOUT6
FSM_LC_
TIMEOUT5
FSM_LC_
TIMEOUT4
FSM_LC_
TIMEOUT3
FSM_LC_
TIMEOUT2
FSM_LC_
TIMEOUT1
FSM_LC_
TIMEOUT0
Table 306. FSM_LC_TIMEOUT_L register description
FSM_LC_TIMEOUT[7:0]
FSM long counter timeout value (LSbyte). Default value: 00000000
Table 307. FSM_LC_TIMEOUT_H register
FSM_LC_
TIMEOUT15
FSM_LC_
TIMEOUT14
FSM_LC_
TIMEOUT13
FSM_LC_
TIMEOUT12
FSM_LC_
TIMEOUT11
FSM_LC_
TIMEOUT10
FSM_LC_
TIMEOUT9
FSM_LC_
TIMEOUT8
Table 308. FSM_LC_TIMEOUT_H register description
FSM_LC_TIMEOUT[15:8]
13.2.2
FSM long counter timeout value (MSbyte). Default value: 00000000
FSM_PROGRAMS (7Ch)
FSM number of programs register (r/w)
Table 309. FSM_PROGRAMS register
FSM_N_
PROG7
FSM_N_
PROG6
FSM_N_
PROG5
FSM_N_
PROG4
FSM_N_
PROG3
FSM_N_
PROG2
FSM_N_
PROG1
FSM_N_
PROG0
Table 310. FSM_PROGRAMS register description
FSM_N_PROG[7:0]
DS12140 - Rev 2
Number of FSM programs; must be less than or equal to 16.
Default value: 00000000
page 133/172
LSM6DSO
Page 1 - Embedded advanced features registers
13.2.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh)
FSM start address register (r/w). First available address is 0x033C.
Table 311. FSM_START_ADD_L register
FSM_
START7
FSM_
START6
FSM_
START5
FSM_
START4
FSM_
START3
FSM_
START2
FSM_
START1
FSM_
START0
FSM_
START9
FSM_
START8
0(1)
AD_
DET_EN
Table 312. FSM_START_ADD_L register description
FSM_START[7:0]
FSM start address value (LSbyte). Default value: 00000000
Table 313. FSM_START_ADD_H register
FSM_
START15
FSM_
START14
FSM_
START13
FSM_
START12
FSM_
START11
FSM_
START10
Table 314. FSM_START_ADD_H register description
FSM_START[15:8]
13.2.4
FSM start address value (MSbyte). Default value: 00000000
PEDO_CMD_REG (83h)
Pedometer configuration register (r/w)
Table 315. PEDO_CMD_REG register
FP_
0(1)
0(1)
0(1)
0(1)
CARRY_
COUNT_EN
REJECTION_
EN
1. This bit must be set to '0' for the correct operation of the device.
Table 316. PEDO_CMD_REG register description
CARRY_COUNT_EN
Set when user wants to generate interrupt only on count overflow event.
FP_REJECTION_EN(1)
Enables the false-positive rejection feature.
AD_DET_EN(2)
Enables the advanced detection feature.
1. This bit is effective if the PEDO_ADV_EN bit of EMB_FUNC_EN_B (05h) is set to 1.
2. This bit is effective if both the FP_REJECTION_EN bit in PEDO_CMD_REG (83h) register and the PEDO_ADV_EN bit of
EMB_FUNC_EN_B (05h) are set to 1.
DS12140 - Rev 2
page 134/172
LSM6DSO
Page 1 - Embedded advanced features registers
13.2.5
PEDO_DEB_STEPS_CONF (84h)
Pedometer debounce configuration register (r/w)
Table 317. PEDO_DEB_STEPS_CONF register
DEB_
STEP7
DEB_
STEP6
DEB_
STEP5
DEB_
STEP4
DEB_
STEP3
DEB_
STEP2
DEB_
STEP1
DEB_
STEP0
Table 318. PEDO_DEB_STEPS_CONF register description
DEB_STEP[7:0]
13.2.6
Debounce threshold. Minimum number of steps to increment the step counter (debounce).
Default value: 00001010
PEDO_SC_DELTAT_L (D0h) & PEDO_SC_DELTAT_H (D1h)
Time period register for step detection on delta time (r/w)
Table 319. PEDO_SC_DELTAT_L register
PD_SC_7
PD_SC_6
PD_SC_5
PD_SC_4
PD_SC_3
PD_SC_2
PD_SC_1
PD_SC_0
PD_SC_9
PD_SC_8
Table 320. PEDO_SC_DELTAT_H register
PD_SC_15
PD_SC_14
PD_SC_13
PD_SC_12
PD_SC_11
PD_SC_10
Table 321. PEDO_SC_DELTAT_H/L register description
PD_SC_[15:0]
DS12140 - Rev 2
Time period value (1LSB = 6.4 ms)
page 135/172
LSM6DSO
Sensor hub register mapping
14
Sensor hub register mapping
The table given below provides a list of the registers for the sensor hub functions available in the device and the
corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to '1' in
FUNC_CFG_ACCESS (01h).
Table 322. Register address map - sensor hub registers
Name
DS12140 - Rev 2
Type
Register address
Hex
Binary
Default
SENSOR_HUB_1
r
02
00000010
output
SENSOR_HUB_2
r
03
00000011
output
SENSOR_HUB_3
r
04
00000100
output
SENSOR_HUB_4
r
05
00000101
output
SENSOR_HUB_5
r
06
00000110
output
SENSOR_HUB_6
r
07
00000111
output
SENSOR_HUB_7
r
08
00001000
output
SENSOR_HUB_8
r
09
00001001
output
SENSOR_HUB_9
r
0A
00001010
output
SENSOR_HUB_10
r
0B
00001011
output
SENSOR_HUB_11
r
0C
00001100
output
SENSOR_HUB_12
r
0D
00001101
output
SENSOR_HUB_13
r
0E
00001110
output
SENSOR_HUB_14
r
0F
00001111
output
SENSOR_HUB_15
r
10
00010000
output
SENSOR_HUB_16
r
11
00010001
output
SENSOR_HUB_17
r
12
00010010
output
SENSOR_HUB_18
r
13
00010011
output
MASTER_CONFIG
rw
14
00010100
00000000
SLV0_ADD
rw
15
00010101
00000000
SLV0_SUBADD
rw
16
00010110
00000000
SLV0_CONFIG
rw
17
0001 0111
00000000
SLV1_ADD
rw
18
00011000
00000000
SLV1_SUBADD
rw
19
00011001
00000000
SLV1_CONFIG
rw
1A
00011010
00000000
SLV2_ADD
rw
1B
00011011
00000000
SLV2_SUBADD
rw
1C
00011100
00000000
SLV2_CONFIG
rw
1D
00011101
00000000
SLV3_ADD
rw
1E
00011110
00000000
SLV3_SUBADD
rw
1F
00011111
00000000
SLV3_CONFIG
rw
20
00100000
00000000
DATAWRITE_SLV0
rw
21
00100001
00000000
STATUS_MASTER
r
22
00100010
output
Comment
page 136/172
LSM6DSO
Sensor hub register mapping
Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to
the device.
The content of the registers that are loaded at boot should not be changed. They contain the factory calibration
values. Their content is automatically restored when the device is powered up.
DS12140 - Rev 2
page 137/172
LSM6DSO
Sensor hub register description
15
Sensor hub register description
15.1
SENSOR_HUB_1 (02h)
Sensor hub output register (r)
First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 323. SENSOR_HUB_1 register
Sensor
Hub1_7
Sensor
Hub1_6
Sensor
Hub1_5
Sensor
Hub1_4
Sensor
Hub1_3
Sensor
Hub1_2
Sensor
Hub1_1
Sensor
Hub1_0
Table 324. SENSOR_HUB_1 register description
SensorHub1[7:0]
15.2
First byte associated to external sensors
SENSOR_HUB_2 (03h)
Sensor hub output register (r)
Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 325. SENSOR_HUB_2 register
Sensor
Hub2_7
Sensor
Hub2_6
Sensor
Hub2_5
Sensor
Hub2_4
Sensor
Hub2_3
Sensor
Hub2_2
Sensor
Hub2_1
Sensor
Hub2_0
Table 326. SENSOR_HUB_2 register description
SensorHub2[7:0]
15.3
Second byte associated to external sensors
SENSOR_HUB_3 (04h)
Sensor hub output register (r)
Third byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 327. SENSOR_HUB_3 register
Sensor
Hub3_7
Sensor
Hub3_6
Sensor
Hub3_5
Sensor
Hub3_4
Sensor
Hub3_3
Sensor
Hub3_2
Sensor
Hub3_1
Sensor
Hub3_0
Table 328. SENSOR_HUB_3 register description
SensorHub3[7:0]
DS12140 - Rev 2
Third byte associated to external sensors
page 138/172
LSM6DSO
SENSOR_HUB_4 (05h)
15.4
SENSOR_HUB_4 (05h)
Sensor hub output register (r)
Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 329. SENSOR_HUB_4 register
Sensor
Hub4_7
Sensor
Hub4_6
Sensor
Hub4_5
Sensor
Hub4_4
Sensor
Hub4_3
Sensor
Hub4_2
Sensor
Hub4_1
Sensor
Hub4_0
Table 330. SENSOR_HUB_4 register description
SensorHub4[7:0]
15.5
Fourth byte associated to external sensors
SENSOR_HUB_5 (06h)
Sensor hub output register (r)
Fifth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 331. SENSOR_HUB_5 register
Sensor
Hub5_7
Sensor
Hub5_6
Sensor
Hub5_5
Sensor
Hub5_4
Sensor
Hub5_3
Sensor
Hub5_2
Sensor
Hub5_1
Sensor
Hub5_0
Table 332. SENSOR_HUB_5 register description
SensorHub5[7:0]
15.6
Fifth byte associated to external sensors
SENSOR_HUB_6 (07h)
Sensor hub output register (r)
Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 333. SENSOR_HUB_6 register
Sensor
Hub6_7
Sensor
Hub6_6
Sensor
Hub6_5
Sensor
Hub6_4
Sensor
Hub6_3
Sensor
Hub6_2
Sensor
Hub6_1
Sensor
Hub6_0
Table 334. SENSOR_HUB_6 register description
SensorHub6[7:0]
DS12140 - Rev 2
Sixth byte associated to external sensors
page 139/172
LSM6DSO
SENSOR_HUB_7 (08h)
15.7
SENSOR_HUB_7 (08h)
Sensor hub output register (r)
Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 335. SENSOR_HUB_7 register
Sensor
Hub7_7
Sensor
Hub7_6
Sensor
Hub7_5
Sensor
Hub7_4
Sensor
Hub7_3
Sensor
Hub7_2
Sensor
Hub7_1
Sensor
Hub7_0
Table 336. SENSOR_HUB_7 register description
SensorHub7[7:0]
15.8
Seventh byte associated to external sensors
SENSOR_HUB_8 (09h)
Sensor hub output register (r)
Eighth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 337. SENSOR_HUB_8 register
Sensor
Hub8_7
Sensor
Hub8_6
Sensor
Hub8_5
Sensor
Hub8_4
Sensor
Hub8_3
Sensor
Hub8_2
Sensor
Hub8_1
Sensor
Hub8_0
Table 338. SENSOR_HUB_8 register description
SensorHub8[7:0]
15.9
Eighth byte associated to external sensors
SENSOR_HUB_9 (0Ah)
Sensor hub output register (r)
Ninth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 339. SENSOR_HUB_9 register
Sensor
Hub9_7
Sensor
Hub9_6
Sensor
Hub9_5
Sensor
Hub9_4
Sensor
Hub9_3
Sensor
Hub9_2
Sensor
Hub9_1
Sensor
Hub9_0
Table 340. SENSOR_HUB_9 register description
SensorHub9[7:0]
DS12140 - Rev 2
Ninth byte associated to external sensors
page 140/172
LSM6DSO
SENSOR_HUB_10 (0Bh)
15.10
SENSOR_HUB_10 (0Bh)
Sensor hub output register (r)
Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 341. SENSOR_HUB_10 register
Sensor
Hub10_7
Sensor
Hub10_6
Sensor
Hub10_5
Sensor
Hub10_4
Sensor
Hub10_3
Sensor
Hub10_2
Sensor
Hub10_1
Sensor
Hub10_0
Table 342. SENSOR_HUB_10 register description
SensorHub10[7:0]
15.11
Tenth byte associated to external sensors
SENSOR_HUB_11 (0Ch)
Sensor hub output register (r)
Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 343. SENSOR_HUB_11 register
Sensor
Hub11_7
Sensor
Hub11_6
Sensor
Hub11_5
Sensor
Hub11_4
Sensor
Hub11_3
Sensor
Hub11_2
Sensor
Hub11_1
Sensor
Hub11_0
Table 344. SENSOR_HUB_11 register description
SensorHub11[7:0]
15.12
Eleventh byte associated to external sensors
SENSOR_HUB_12 (0Dh)
Sensor hub output register (r)
Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 345. SENSOR_HUB_12 register
Sensor
Hub12_7
Sensor
Hub12_6
Sensor
Hub12_5
Sensor
Hub12_4
Sensor
Hub12_3
Sensor
Hub12_2
Sensor
Hub12_1
Sensor
Hub12_0
Table 346. SENSOR_HUB_12 register description
SensorHub12[7:0]
DS12140 - Rev 2
Twelfth byte associated to external sensors
page 141/172
LSM6DSO
SENSOR_HUB_13 (0Eh)
15.13
SENSOR_HUB_13 (0Eh)
Sensor hub output register (r)
Thirteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 347. SENSOR_HUB_13 register
Sensor
Hub13_7
Sensor
Hub13_6
Sensor
Hub13_5
Sensor
Hub13_4
Sensor
Hub13_3
Sensor
Hub13_2
Sensor
Hub13_1
Sensor
Hub13_0
Table 348. SENSOR_HUB_13 register description
SensorHub13[7:0]
15.14
Thirteenth byte associated to external sensors
SENSOR_HUB_14 (0Fh)
Sensor hub output register (r)
Fourteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 349. SENSOR_HUB_14 register
Sensor
Hub14_7
Sensor
Hub14_6
Sensor
Hub14_5
Sensor
Hub14_4
Sensor
Hub14_3
Sensor
Hub14_2
Sensor
Hub14_1
Sensor
Hub14_0
Table 350. SENSOR_HUB_14 register description
SensorHub14[7:0]
15.15
Fourteenth byte associated to external sensors
SENSOR_HUB_15 (10h)
Sensor hub output register (r)
Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 351. SENSOR_HUB_15 register
Sensor
Hub15_7
Sensor
Hub15_6
Sensor
Hub15_5
Sensor
Hub15_4
Sensor
Hub15_3
Sensor
Hub15_2
Sensor
Hub15_1
Sensor
Hub15_0
Table 352. SENSOR_HUB_15 register description
SensorHub15[7:0]
DS12140 - Rev 2
Fifteenth byte associated to external sensors
page 142/172
LSM6DSO
SENSOR_HUB_16 (11h)
15.16
SENSOR_HUB_16 (11h)
Sensor hub output register (r)
Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG
number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 353. SENSOR_HUB_16 register
Sensor
Hub16_7
Sensor
Hub16_6
Sensor
Hub16_5
Sensor
Hub16_4
Sensor
Hub16_3
Sensor
Hub16_2
Sensor
Hub16_1
Sensor
Hub16_0
Table 354. SENSOR_HUB_16 register description
SensorHub16[7:0]
15.17
Sixteenth byte associated to external sensors
SENSOR_HUB_17 (12h)
Sensor hub output register (r)
Seventeenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 355. SENSOR_HUB_17 register
Sensor
Hub17_7
Sensor
Hub17_6
Sensor
Hub17_5
Sensor
Hub17_4
Sensor
Hub17_3
Sensor
Hub17_2
Sensor
Hub17_1
Sensor
Hub17_7
Table 356. SENSOR_HUB_17 register description
SensorHub17[7:0]
15.18
Seventeenth byte associated to external sensors
SENSOR_HUB_18 (13h)
Sensor hub output register (r)
Eighteenth byte associated to external sensors. The content of the register is consistent with the
SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3).
Table 357. SENSOR_HUB_17 register
Sensor
Hub18_7
Sensor
Hub18_6
Sensor
Hub18_5
Sensor
Hub18_4
Sensor
Hub18_3
Sensor
Hub18_2
Sensor
Hub18_1
Sensor
Hub18_0
Table 358. SENSOR_HUB_17 register description
SensorHub18[7:0]
DS12140 - Rev 2
Eighteenth byte associated to external sensors
page 143/172
LSM6DSO
MASTER_CONFIG (14h)
15.19
MASTER_CONFIG (14h)
Master configuration register (r/w)
Table 359. MASTER_CONFIG register
RST_MASTER
_REGS
WRITE_
ONCE
PASS_
START_
CONFIG
THROUGH
_MODE
SHUB_
PU_EN
MASTER_ON
AUX_
SENS_ON1
AUX_
SENS_ON0
Table 360. MASTER_CONFIG register description
Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Default value: 0
RST_MASTER_REGS
Slave 0 write operation is performed only at the first sensor hub cycle. Default value: 0
WRITE_ONCE
(0: write operation for each sensor hub cycle;
1: write operation only for the first sensor hub cycle)
Sensor hub trigger signal selection. Default value: 0
START_CONFIG
(0: sensor hub trigger signal is the accelerometer/gyro data-ready;
1: sensor hub trigger signal external from INT2 pin)
I²C interface pass-through. Default value: 0
PASS_THROUGH_MODE
(0: pass-through disabled;
1: pass-through enabled, main I²C line is short-circuited with the auxiliary line)
Master I²C pull-up enable. Default value: 0
SHUB_PU_EN
(0: internal pull-up on auxiliary I²C line disabled;
1: internal pull-up on auxiliary I²C line enabled)
Sensor hub I²C master enable. Default: 0
MASTER_ON
(0: master I²C of sensor hub disabled; 1: master I²C of sensor hub enabled)
Number of external sensors to be read by the sensor hub.
(00: one sensor (default);
AUX_SENS_ON[1:0]
01: two sensors;
10: three sensors;
11: four sensors)
15.20
SLV0_ADD (15h)
I²C slave address of the first external sensor (Sensor 1) register (r/w).
Table 361. SLV0_ADD register
slave0_
add6
slave0_
add5
slave0_
add4
slave0_
add3
slave0_
add2
slave0_
add1
slave0_
add0
rw_0
Table 362. SLV_ADD register description
slave0_add[6:0]
rw_0
DS12140 - Rev 2
I²C slave address of Sensor1 that can be read by the sensor hub.
Default value: 0000000
Read/write operation on Sensor 1. Default value: 0
(0: write operation; 1: read operation)
page 144/172
LSM6DSO
SLV0_SUBADD (16h)
15.21
SLV0_SUBADD (16h)
Address of register on the first external sensor (Sensor 1) register (r/w)
Table 363. SLV0_SUBADD register
slave0_
reg7
slave0_
reg6
slave0_
reg5
slave0_
reg4
slave0_
reg3
slave0_
reg2
slave0_
reg1
slave0_
reg0
Table 364. SLV0_SUBADD register description
slave0_reg[7:0]
15.22
Address of register on Sensor1 that has to be read/written according to the rw_0 bit value in SLV0_ADD
(15h). Default value: 00000000
SLAVE0_CONFIG (17h)
First external sensor (Sensor1) configuration and sensor hub settings register (r/w)
Table 365. SLAVE0_CONFIG register
SHUB_
ODR_1
SHUB_
ODR_0
0(1)
0(1)
BATCH_EXT
_SENS_0_EN
Slave0_
numop2
Slave0_
numop1
Slave0_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 366. SLAVE0_CONFIG register description
Rate at which the master communicates. Default value: 00
(00: 104 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 104 Hz);
SHUB_ODR_[1:0]
01: 52 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 52 Hz);
10: 26 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 26 Hz);
11: 12.5 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 12.5 Hz)
15.23
BATCH_EXT_
SENS_0_EN
Enable FIFO batching data of first slave. Default value: 0
Slave0_numop[2:0]
Number of read operations on Sensor 1. Default value: 000
SLV1_ADD (18h)
I²C slave address of the second external sensor (Sensor 2) register (r/w)
Table 367. SLV1_ADD register
Slave1_
add6
Slave1_
add5
Slave1_
add4
Slave1_
add3
Slave1_
add2
Slave1_
add1
Slave1_
add0
r_1
Table 368. SLV1_ADD register description
Slave1_add[6:0]
r_1
DS12140 - Rev 2
I²C slave address of Sensor 2 that can be read by the sensor hub.
Default value: 0000000
Read operation on Sensor 2 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
page 145/172
LSM6DSO
SLV1_SUBADD (19h)
15.24
SLV1_SUBADD (19h)
Address of register on the second external sensor (Sensor 2) register (r/w)
Table 369. SLV1_SUBADD register
Slave1_
reg7
Slave1_
reg6
Slave1_
reg5
Slave1_
reg4
Slave1_
reg3
Slave1_
reg2
Slave1_
reg1
Slave1_
reg0
Table 370. SLV1_SUBADD register description
Slave1_reg[7:0]
15.25
Address of register on Sensor 2 that has to be read/written according to the r_1 bit value in SLV1_ADD
(18h).
SLAVE1_CONFIG (1Ah)
Second external sensor (Sensor 2) configuration register (r/w)
Table 371. SLAVE1_CONFIG register
0(1)
0(1)
0(1)
0(1)
BATCH_EXT_
SENS_1_EN
Slave1_
numop2
Slave1_
numop1
Slave1_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 372. SLAVE1_CONFIG register description
15.26
BATCH_EXT_SENS_1_EN
Enable FIFO batching data of second slave. Default value: 0
Slave1_numop[2:0]
Number of read operations on Sensor 2. Default value: 000
SLV2_ADD (1Bh)
I²C slave address of the third external sensor (Sensor 3) register (r/w)
Table 373. SLV2_ADD register
Slave2_
add6
Slave2_
add5
Slave2_
add4
Slave2_
add3
Slave2_
add2
Slave2_
add1
Slave2_
add0
r_2
Table 374. SLV2_ADD register description
Slave2_add[6:0]
r_2
DS12140 - Rev 2
I²C slave address of Sensor 3 that can be read by the sensor hub.
Read operation on Sensor 3 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
page 146/172
LSM6DSO
SLV2_SUBADD (1Ch)
15.27
SLV2_SUBADD (1Ch)
Address of register on the third external sensor (Sensor 3) register (r/w)
Table 375. SLV2_SUBADD register
Slave2_
reg7
Slave2_
reg6
Slave2_
reg5
Slave2_
reg4
Slave2_
reg3
Slave2_
reg2
Slave2_
reg1
Slave2_
reg0
Table 376. SLV2_SUBADD register description
Slave2_reg[7:0]
15.28
Address of register on Sensor 3 that has to be read/written according to the r_2 bit value in SLV2_ADD
(1Bh).
SLAVE2_CONFIG (1Dh)
Third external sensor (Sensor 3) configuration register (r/w)
Table 377. SLAVE2_CONFIG register
0(1)
0(1)
0(1)
0(1)
BATCH_EXT
_SENS_2_EN
Slave2_
numop2
Slave2_
numop1
Slave2_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 378. SLAVE2_CONFIG register description
15.29
BATCH_EXT_SENS_2_EN
Enable FIFO batching data of third slave. Default value: 0
Slave2_numop[2:0]
Number of read operations on Sensor 3. Default value: 000
SLV3_ADD (1Eh)
I²C slave address of the fourth external sensor (Sensor 4) register (r/w)
Table 379. SLV3_ADD register
Slave3_
add6
Slave3_
add5
Slave3_
add4
Slave3_
add3
Slave3_
add2
Slave3_
add1
Slave3_
add0
r_3
Table 380. SLV3_ADD register description
Slave3_add[6:0]
r_3
DS12140 - Rev 2
I²C slave address of Sensor 4 that can be read by the sensor hub.
Read operation on Sensor 4 enable. Default value: 0
(0: read operation disabled; 1: read operation enabled)
page 147/172
LSM6DSO
SLV3_SUBADD (1Fh)
15.30
SLV3_SUBADD (1Fh)
Address of register on the fourth external sensor (Sensor 4) register (r/w)
Table 381. SLV3_SUBADD register
Slave3_
reg7
Slave3_
reg6
Slave3_
reg5
Slave3_
reg4
Slave3_
reg3
Slave3_
reg2
Slave3_
reg1
Slave3_
reg0
Table 382. SLV3_SUBADD register description
Slave3_reg[7:0]
15.31
Address of register on Sensor 4 that has to be read according to the r_3 bit value in SLV3_ADD (1Eh).
SLAVE3_CONFIG (20h)
Fourth external sensor (Sensor 4) configuration register (r/w)
Table 383. SLAVE3_CONFIG register
0(1)
0(1)
0(1)
0(1)
BATCH_EXT
_SENS_3_EN
Slave3_
numop2
Slave3_
numop1
Slave3_
numop0
1. This bit must be set to ‘0’ for the correct operation of the device.
Table 384. SLAVE3_CONFIG register description
15.32
BATCH_EXT_SENS_3_EN
Enable FIFO batching data of fourth slave. Default value: 0
Slave3_numop[2:0]
Number of read operations on Sensor 4. Default value: 000
DATAWRITE_SLV0 (21h)
Data to be written into the slave device register (r/w)
Table 385. DATAWRITE_SLV0 register
Slave0_
dataw7
Slave0_
dataw6
Slave0_
dataw5
Slave0_
dataw4
Slave0_
dataw3
Slave0_
dataw2
Slave0_
dataw1
Slave0_
dataw0
Table 386. DATAWRITE_SLV0 register description
Slave0_dataw[7:0]
DS12140 - Rev 2
Data to be written into the slave 0 device according to the rw_0 bit in register SLV0_ADD (15h).
Default value: 00000000
page 148/172
LSM6DSO
STATUS_MASTER (22h)
15.33
STATUS_MASTER (22h)
Sensor hub source register (r)
Table 387. STATUS_MASTER register
WR_ONCE_
DONE
SLAVE3_
NACK
SLAVE2_
NACK
SLAVE1_
NACK
SLAVE0_
NACK
0
0
SENS_HUB
_ENDOP
Table 388. STATUS_MASTER register description
WR_ONCE_DONE
When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the
write operation on slave 0 has been performed and completed. Default value: 0
SLAVE3_NACK
This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0
SLAVE2_NACK
This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0
SLAVE1_NACK
This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0
SLAVE0_NACK
This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0
Sensor hub communication status. Default value: 0
SENS_HUB_ENDOP (0: sensor hub communication not concluded;
1: sensor hub communication concluded)
DS12140 - Rev 2
page 149/172
LSM6DSO
Soldering information
16
Soldering information
The LGA package is compliant with the ECOPACK®, RoHS and "Green" standard.
It is qualified for soldering heat resistance according to JEDEC J-STD-020.
Land pattern and soldering recommendations are available at www.st.com/mems.
DS12140 - Rev 2
page 150/172
LSM6DSO
Package information
17
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
17.1
LGA-14L package information
Figure 25. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data
Pin1 indicator
Pin1 indicator
H
0.5
4x
1
TOP VIEW
(0.1)
14x
0.5
L
1.5
W
14x
0.25±0.05
0.475±0.05
BOTTOM VIEW
Dimensions are in millimeter unless otherwise specified
General tolerance is +/-0.1mm unless otherwise specified
OUTER DIMENSIONS
ITEM
Length [L]
W idth [W ]
Height [H]
DIMENSION [mm]
2.50
3.00
0.86
TOLERANCE [mm]
±0.1
±0.1
MA X
DM00249496_1
DS12140 - Rev 2
page 151/172
LSM6DSO
LGA-14 packing information
17.2
LGA-14 packing information
Figure 26. Carrier tape information for LGA-14 package
Figure 27. LGA-14 package orientation in carrier tape
DS12140 - Rev 2
page 152/172
LSM6DSO
LGA-14 packing information
Figure 28. Reel information for carrier tape of LGA-14 package
T
40mm min.
Access hole at
slot location
B
C
N
D
A
Full radius
G measured at hub
Tape slot
in core for
tape start
2.5mm min. width
Table 389. Reel dimensions for carrier tape of LGA-14 package
Reel dimensions (mm)
DS12140 - Rev 2
A (max)
330
B (min)
1.5
C
13 ±0.25
D (min)
20.2
N (min)
60
G
12.4 +2/-0
T (max)
18.4
page 153/172
LSM6DSO
Revision history
Table 390. Document revision history
Date
Revision
22-Aug-2018
1
Changes
Initial release
Added product label indicating ST's commitment to sustainable technology
Updated LA_TyOff in Table 2. Mechanical characteristics
25-Jan-2019
2
Updated footnotes in Table 4. Temperature sensor characteristics
Updated Table 60. Gyroscope LPF1 bandwidth selection
Updated EMB_FUNC_ODR_CFG_B (5Fh)
Textual update in MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh)
DS12140 - Rev 2
page 154/172
LSM6DSO
Contents
Contents
1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2
Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Tilt detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Significant Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3.1
4
5
Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4.1
SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.2
I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.1
Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6.2
Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5.1
5.2
6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
I²C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.1
I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1.2
SPI bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MIPI I3CSM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2.1
MIPI I3CSM slave interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2.2
MIPI I3CSM CCC supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3
I²C/I3C coexistence in LSM6DSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.4
Master I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.5
Auxiliary SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DS12140 - Rev 2
page 155/172
LSM6DSO
Contents
6.1
Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2
Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.1
6.3
Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4
Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.5
7
Accelerometer ultra-low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1
Block diagrams of the accelerometer filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.4.2
Block diagrams of the gyroscope filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.1
Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5.2
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.3
Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.4
Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.5
Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.5.6
Bypass-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5.7
FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
7.1
LSM6DSO electrical connections in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2
LSM6DSO electrical connections in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.3
LSM6DSO electrical connections in Mode 3 and Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
9
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
9.1
FUNC_CFG_ACCESS (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.2
PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9.3
FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.4
FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
9.5
FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9.6
FIFO_CTRL4 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.7
COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.8
COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.9
INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.10
INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DS12140 - Rev 2
page 156/172
LSM6DSO
Contents
9.11
WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.12
CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.13
CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.14
CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.15
CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.16
CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.17
CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.18
CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.19
CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.20
CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
9.21
CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.22
ALL_INT_SRC (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
9.23
WAKE_UP_SRC (1Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
9.24
TAP_SRC (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
9.25
D6D_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
9.26
STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.27
OUT_TEMP_L (20h), OUT_TEMP_H (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.28
OUTX_L_G (22h) and OUTX_H_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.29
OUTY_L_G (24h) and OUTY_H_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.30
OUTZ_L_G (26h) and OUTZ_H_G (27h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.31
OUTX_L_A (28h) and OUTX_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.32
OUTY_L_A (2Ah) and OUTY_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.33
OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.34
EMB_FUNC_STATUS_MAINPAGE (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.35
FSM_STATUS_A_MAINPAGE (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.36
FSM_STATUS_B_MAINPAGE (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.37
STATUS_MASTER_MAINPAGE (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.38
FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.39
FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.40
TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 72
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9.41
TAP_CFG0 (56h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.42
TAP_CFG1 (57h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.43
TAP_CFG2 (58h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.44
TAP_THS_6D (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
9.45
INT_DUR2 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.46
WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.47
WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.48
FREE_FALL (5Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.49
MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
9.50
MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.51
I3C_BUS_AVB (62h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.52
INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
9.53
INT_OIS (6Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.54
CTRL1_OIS (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
9.55
CTRL2_OIS (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.56
CTRL3_OIS (72h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.57
X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.58
Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
9.59
Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.60
FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.61
FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . . . . . . . . . . . . . . . . 88
9.62
FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . . . . . . . . . . . . . . . . . 88
9.63
FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . . . . . . . . . . . . . . . . 88
10
Embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
11
Embedded functions register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
11.1
PAGE_SEL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.2
EMB_FUNC_EN_A (04h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
11.3
EMB_FUNC_EN_B (05h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.4
PAGE_ADDRESS (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.5
PAGE_VALUE (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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11.6
EMB_FUNC_INT1 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.7
FSM_INT1_A (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.8
FSM_INT1_B (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.9
EMB_FUNC_INT2 (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.10 FSM_INT2_A (0Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.11 FSM_INT2_B (10h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
11.12 EMB_FUNC_STATUS (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.13 FSM_STATUS_A (13h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
11.14 FSM_STATUS_B (14h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
11.15 PAGE_RW (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.16 EMB_FUNC_FIFO_CFG (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
11.17 FSM_ENABLE_A (46h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.18 FSM_ENABLE_B (47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
11.19 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) . . . . . . . . . . . . . . 104
11.20 FSM_LONG_COUNTER_CLEAR (4Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11.21 FSM_OUTS1 (4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
11.22 FSM_OUTS2 (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
11.23 FSM_OUTS3 (4Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.24 FSM_OUTS4 (4Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.25 FSM_OUTS5 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.26 FSM_OUTS6 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
11.27 FSM_OUTS7 (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
11.28 FSM_OUTS8 (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
11.29 FSM_OUTS9 (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.30 FSM_OUTS10 (55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
11.31 FSM_OUTS11 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.32 FSM_OUTS12 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
11.33 FSM_OUTS13 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
11.34 FSM_OUTS14 (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
11.35 FSM_OUTS15 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
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11.36 FSM_OUTS16 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
11.37 EMB_FUNC_ODR_CFG_B (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.38 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.39 EMB_FUNC_SRC (64h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11.40 EMB_FUNC_INIT_A (66h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
11.41 EMB_FUNC_INIT_B (67h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12
Embedded advanced features pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
13
Embedded advanced features register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.1
Page 0 - Embedded advanced features registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
13.1.1
MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) . . . . . . . . . . . . . . . . . . 126
13.1.2
MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.1.3
MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
13.1.4
MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.1.5
MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
13.1.6
MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.1.7
MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
13.1.8
MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.1.9
MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
13.1.11 MAG_CFG_A (D4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.1.12 MAG_CFG_B (D5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
13.2
Page 1 - Embedded advanced features registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.2.1
FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh). . . . . . . . . . . . . . . . . . . 133
13.2.2
FSM_PROGRAMS (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
13.2.3
FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) . . . . . . . . . . . . . . . . . . . . 134
13.2.4
PEDO_CMD_REG (83h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
13.2.5
PEDO_DEB_STEPS_CONF (84h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
13.2.6
PEDO_SC_DELTAT_L (D0h) & PEDO_SC_DELTAT_H (D1h) . . . . . . . . . . . . . . . . . . . . 135
14
Sensor hub register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
15
Sensor hub register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.1
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SENSOR_HUB_1 (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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15.2
SENSOR_HUB_2 (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.3
SENSOR_HUB_3 (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
15.4
SENSOR_HUB_4 (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.5
SENSOR_HUB_5 (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.6
SENSOR_HUB_6 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
15.7
SENSOR_HUB_7 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.8
SENSOR_HUB_8 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.9
SENSOR_HUB_9 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
15.10 SENSOR_HUB_10 (0Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.11 SENSOR_HUB_11 (0Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.12 SENSOR_HUB_12 (0Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
15.13 SENSOR_HUB_13 (0Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.14 SENSOR_HUB_14 (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.15 SENSOR_HUB_15 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
15.16 SENSOR_HUB_16 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.17 SENSOR_HUB_17 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.18 SENSOR_HUB_18 (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.19 MASTER_CONFIG (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.20 SLV0_ADD (15h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.21 SLV0_SUBADD (16h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
15.22 SLAVE0_CONFIG (17h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.23 SLV1_ADD (18h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.24 SLV1_SUBADD (19h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
15.25 SLAVE1_CONFIG (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.26 SLV2_ADD (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.27 SLV2_SUBADD (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.28 SLAVE2_CONFIG (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.29 SLV3_ADD (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
15.30 SLV3_SUBADD (1Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15.31 SLAVE3_CONFIG (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
DS12140 - Rev 2
page 161/172
LSM6DSO
Contents
15.32 DATAWRITE_SLV0 (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
15.33 STATUS_MASTER (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
16
Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
17
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
17.1
LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
17.2
LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
DS12140 - Rev 2
page 162/172
LSM6DSO
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI slave timing values (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer when master is writing one byte to slave. . . . . . . . . . . . . . . . . . . .
Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . .
Transfer when master is receiving (reading) one byte of data from slave . . . .
Transfer when master is receiving (reading) multiple bytes of data from slave
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. 7
. 9
12
12
13
14
15
17
17
18
18
18
18
18
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
MIPI I3CSM CCC commands . . . . . . . . . . . .
Master I²C pin details . . . . . . . . . . . . . . . . .
Auxiliary SPI pin details . . . . . . . . . . . . . . .
Gyroscope LPF2 bandwidth selection . . . . . .
Internal pin status . . . . . . . . . . . . . . . . . . .
Registers address map . . . . . . . . . . . . . . . .
FUNC_CFG_ACCESS register . . . . . . . . . .
FUNC_CFG_ACCESS register description . .
PIN_CTRL register. . . . . . . . . . . . . . . . . . .
PIN_CTRL register description . . . . . . . . . .
FIFO_CTRL1 register . . . . . . . . . . . . . . . . .
FIFO_CTRL1 register description. . . . . . . . .
FIFO_CTRL2 register . . . . . . . . . . . . . . . . .
FIFO_CTRL2 register description. . . . . . . . .
FIFO_CTRL3 register . . . . . . . . . . . . . . . . .
FIFO_CTRL3 register description. . . . . . . . .
FIFO_CTRL4 register . . . . . . . . . . . . . . . . .
FIFO_CTRL4 register description. . . . . . . . .
COUNTER_BDR_REG1 register . . . . . . . . .
COUNTER_BDR_REG1 register description .
COUNTER_BDR_REG2 register . . . . . . . . .
COUNTER_BDR_REG2 register description .
INT1_CTRL register . . . . . . . . . . . . . . . . . .
INT1_CTRL register description . . . . . . . . . .
INT2_CTRL register . . . . . . . . . . . . . . . . . .
INT2_CTRL register description . . . . . . . . . .
WhoAmI register . . . . . . . . . . . . . . . . . . . .
CTRL1_XL register . . . . . . . . . . . . . . . . . .
CTRL1_XL register description . . . . . . . . . .
Accelerometer ODR register setting . . . . . . .
Accelerometer full-scale selection . . . . . . . .
CTRL2_G register . . . . . . . . . . . . . . . . . . .
CTRL2_G register description . . . . . . . . . . .
Gyroscope ODR configuration setting . . . . . .
CTRL3_C register . . . . . . . . . . . . . . . . . . .
CTRL3_C register description . . . . . . . . . . .
CTRL4_C register . . . . . . . . . . . . . . . . . . .
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23
26
26
30
38
40
43
43
43
43
44
44
44
44
45
45
46
46
47
47
48
48
48
48
49
49
49
50
50
50
50
51
51
51
52
52
53
DS12140 - Rev 2
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page 163/172
LSM6DSO
List of tables
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
CTRL4_C register description . . . . . . . . . . . . . . . . . .
CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL5_C register description . . . . . . . . . . . . . . . . . .
Angular rate sensor self-test mode selection . . . . . . . .
Linear acceleration sensor self-test mode selection . . .
CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL6_C register description . . . . . . . . . . . . . . . . . .
Trigger mode selection . . . . . . . . . . . . . . . . . . . . . . .
Gyroscope LPF1 bandwidth selection . . . . . . . . . . . . .
CTRL7_G register . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL7_G register description . . . . . . . . . . . . . . . . . .
CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL8_XL register description . . . . . . . . . . . . . . . . .
Accelerometer bandwidth configurations . . . . . . . . . . .
CTRL9_XL register . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL9_XL register description . . . . . . . . . . . . . . . . .
CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL10_C register description . . . . . . . . . . . . . . . . .
ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . . . .
ALL_INT_SRC register description. . . . . . . . . . . . . . .
WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_SRC register description . . . . . . . . . . . . .
TAP_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP_SRC register description . . . . . . . . . . . . . . . . . .
D6D_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . .
D6D_SRC register description . . . . . . . . . . . . . . . . . .
STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . .
STATUS_REG register description . . . . . . . . . . . . . . .
STATUS_SPIAux register . . . . . . . . . . . . . . . . . . . . .
STATUS_SPIAux description . . . . . . . . . . . . . . . . . . .
OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . .
OUT_TEMP register description. . . . . . . . . . . . . . . . .
OUTX_L_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_G register description. . . . . . . . . . . . . . . . .
OUTY_L_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_G register description. . . . . . . . . . . . . . . . .
OUTZ_L_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_G register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_G register description . . . . . . . . . . . . . . . . .
OUTX_L_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTX_H_A register description . . . . . . . . . . . . . . . . .
OUTY_L_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTY_H_A register description . . . . . . . . . . . . . . . . .
OUTZ_L_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . . . .
OUTZ_H_A register description . . . . . . . . . . . . . . . . .
EMB_FUNC_STATUS_MAINPAGE register . . . . . . . .
EMB_FUNC_STATUS_MAINPAGE register description
FSM_STATUS_A_MAINPAGE register . . . . . . . . . . . .
DS12140 - Rev 2
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53
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page 164/172
LSM6DSO
List of tables
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
FSM_STATUS_A_MAINPAGE register description . . . . . . .
FSM_STATUS_B_MAINPAGE register . . . . . . . . . . . . . . .
FSM_STATUS_B_MAINPAGE register description . . . . . . .
STATUS_MASTER_MAINPAGE register. . . . . . . . . . . . . .
STATUS_MASTER_MAINPAGE register description . . . . .
FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS1 register description . . . . . . . . . . . . . . . . .
FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_STATUS2 register description . . . . . . . . . . . . . . . . .
TIMESTAMP output registers . . . . . . . . . . . . . . . . . . . . .
TIMESTAMP output register description . . . . . . . . . . . . . .
TAP_CFG0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP_CFG0 register description . . . . . . . . . . . . . . . . . . . .
TAP_CFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP_CFG1 register description . . . . . . . . . . . . . . . . . . . .
TAP priority decoding . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP_CFG2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP_CFG2 register description . . . . . . . . . . . . . . . . . . . .
TAP_THS_6D register . . . . . . . . . . . . . . . . . . . . . . . . . .
TAP_THS_6D register description . . . . . . . . . . . . . . . . . .
Threshold for D4D/D6D function . . . . . . . . . . . . . . . . . . .
INT_DUR2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INT_DUR2 register description . . . . . . . . . . . . . . . . . . . .
WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_THS register description . . . . . . . . . . . . . . . .
WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . . . .
WAKE_UP_DUR register description . . . . . . . . . . . . . . . .
FREE_FALL register . . . . . . . . . . . . . . . . . . . . . . . . . . .
FREE_FALL register description . . . . . . . . . . . . . . . . . . .
Threshold for free-fall function . . . . . . . . . . . . . . . . . . . . .
MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD1_CFG register description. . . . . . . . . . . . . . . . . . . . .
MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MD2_CFG register description. . . . . . . . . . . . . . . . . . . . .
I3C_BUS_AVB register . . . . . . . . . . . . . . . . . . . . . . . . . .
I3C_BUS_AVB register description. . . . . . . . . . . . . . . . . .
INTERNAL_FREQ_FINE register. . . . . . . . . . . . . . . . . . .
INTERNAL_FREQ_FINE register description. . . . . . . . . . .
INT_OIS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INT_OIS register description . . . . . . . . . . . . . . . . . . . . . .
CTRL1_OIS register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL1_OIS register description. . . . . . . . . . . . . . . . . . . .
DEN mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL2_OIS register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL2_OIS register description. . . . . . . . . . . . . . . . . . . .
Gyroscope OIS chain digital LPF1 filter bandwidth selection
CTRL3_OIS register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
CTRL3_OIS register description. . . . . . . . . . . . . . . . . . . .
Accelerometer OIS channel full-scale selection . . . . . . . . .
Accelerometer OIS channel bandwidth and phase . . . . . . .
Self-test nominal output variation . . . . . . . . . . . . . . . . . . .
X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . .
X_OFS_USR register description . . . . . . . . . . . . . . . . . . .
Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS12140 - Rev 2
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page 165/172
LSM6DSO
List of tables
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Y_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_TAG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . . . . .
FIFO tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers . . . . . . . .
FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description
FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers . . . . . . . .
FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description
FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers . . . . . . . .
FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description.
Register address map - embedded functions . . . . . . . . . . . . . . . . . . . .
PAGE_SEL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_SEL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_EN_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_EN_A register description . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_EN_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_EN_B register description . . . . . . . . . . . . . . . . . . . . . . .
PAGE_ADDRESS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_ADDRESS register description . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_VALUE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_VALUE register description . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT1 register description . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT1_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INT2 register description . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT2_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT2_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT2_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_INT2_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_STATUS register description. . . . . . . . . . . . . . . . . . . . . .
FSM_STATUS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_STATUS_A register description . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_STATUS_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_STATUS_B register description . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_RW register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE_RW register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_FIFO_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_FIFO_CFG register description . . . . . . . . . . . . . . . . . . . .
FSM_ENABLE_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_ENABLE_A register description . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_ENABLE_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_ENABLE_B register description . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_LONG_COUNTER_L register . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_LONG_COUNTER_L register description . . . . . . . . . . . . . . . . . .
FSM_LONG_COUNTER_H register . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_LONG_COUNTER_H register description. . . . . . . . . . . . . . . . . .
FSM_LONG_COUNTER_CLEAR register. . . . . . . . . . . . . . . . . . . . . .
DS12140 - Rev 2
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page 166/172
LSM6DSO
List of tables
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
Table 257.
Table 258.
Table 259.
Table 260.
Table 261.
Table 262.
Table 263.
Table 264.
Table 265.
Table 266.
Table 267.
FSM_LONG_COUNTER_CLEAR register description. . . . . . .
FSM_OUTS1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS1 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS2 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS3 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS4 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS5 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS6 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS6 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS7 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS7 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS8 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS9 register description. . . . . . . . . . . . . . . . . . . . .
FSM_OUTS10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS10 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS11 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS11 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS12 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS12 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS13 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS13 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS14 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS14 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS15 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS15 register description . . . . . . . . . . . . . . . . . . . .
FSM_OUTS16 register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FSM_OUTS16 register description . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_ODR_CFG_B register . . . . . . . . . . . . . . . . . . .
EMB_FUNC_ODR_CFG_B register description . . . . . . . . . . .
STEP_COUNTER_L register. . . . . . . . . . . . . . . . . . . . . . . .
STEP_COUNTER_L register description. . . . . . . . . . . . . . . .
STEP_COUNTER_H register . . . . . . . . . . . . . . . . . . . . . . .
STEP_COUNTER_H register description . . . . . . . . . . . . . . .
EMB_FUNC_SRC register . . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_SRC register description . . . . . . . . . . . . . . . . .
EMB_FUNC_INIT_A register . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INIT_A register description. . . . . . . . . . . . . . . .
EMB_FUNC_INIT_B register . . . . . . . . . . . . . . . . . . . . . . . .
EMB_FUNC_INIT_B register description. . . . . . . . . . . . . . . .
Register address map - embedded advanced features page 0 .
Register address map - embedded advanced features page 1 .
MAG_SENSITIVITY_L register . . . . . . . . . . . . . . . . . . . . . .
MAG_SENSITIVITY_L register description . . . . . . . . . . . . . .
MAG_SENSITIVITY_H register . . . . . . . . . . . . . . . . . . . . . .
MAG_SENSITIVITY_H register description . . . . . . . . . . . . . .
MAG_OFFX_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAG_OFFX_L register description. . . . . . . . . . . . . . . . . . . .
MAG_OFFX_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS12140 - Rev 2
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104
105
105
106
106
107
107
108
108
109
109
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.110
.111
.111
.112
.112
.113
.113
.114
.114
.115
.115
.116
.116
.117
.117
.118
.118
.119
.119
120
120
121
121
121
121
121
121
122
122
122
122
123
123
124
124
126
126
126
126
127
127
127
page 167/172
LSM6DSO
List of tables
Table 268.
Table 269.
Table 270.
Table 271.
Table 272.
Table 273.
Table 274.
Table 275.
Table 276.
Table 277.
Table 278.
Table 279.
Table 280.
Table 281.
Table 282.
Table 283.
Table 284.
Table 285.
Table 286.
Table 287.
Table 288.
Table 289.
Table 290.
Table 291.
Table 292.
Table 293.
Table 294.
Table 295.
Table 296.
Table 297.
Table 298.
Table 299.
Table 300.
Table 301.
Table 302.
Table 303.
Table 304.
Table 305.
Table 306.
Table 307.
Table 308.
Table 309.
Table 310.
Table 311.
Table 312.
Table 313.
Table 314.
Table 315.
Table 316.
Table 317.
Table 318.
Table 319.
Table 320.
Table 321.
MAG_OFFX_H register description . . . . . . . . .
MAG_OFFY_L register . . . . . . . . . . . . . . . . . .
MAG_OFFY_L register description. . . . . . . . . .
MAG_OFFY_H register. . . . . . . . . . . . . . . . . .
MAG_OFFY_H register description . . . . . . . . .
MAG_OFFZ_L register . . . . . . . . . . . . . . . . . .
MAG_OFFZ_L register description . . . . . . . . . .
MAG_OFFZ_H register. . . . . . . . . . . . . . . . . .
MAG_OFFZ_H register description . . . . . . . . .
MAG_SI_XX_L register. . . . . . . . . . . . . . . . . .
MAG_SI_XX_L register description . . . . . . . . .
MAG_SI_XX_H register . . . . . . . . . . . . . . . . .
MAG_SI_XX_H register description . . . . . . . . .
MAG_SI_XY_L register. . . . . . . . . . . . . . . . . .
MAG_SI_XY_L register description . . . . . . . . .
MAG_SI_XY_H register . . . . . . . . . . . . . . . . .
MAG_SI_XY_H register description . . . . . . . . .
MAG_SI_XZ_L register. . . . . . . . . . . . . . . . . .
MAG_SI_XZ_L register description . . . . . . . . .
MAG_SI_XZ_H register . . . . . . . . . . . . . . . . .
MAG_SI_XZ_H register description . . . . . . . . .
MAG_SI_YY_L register. . . . . . . . . . . . . . . . . .
MAG_SI_YY_L register description . . . . . . . . .
MAG_SI_YY_H register . . . . . . . . . . . . . . . . .
MAG_SI_YY_H register description . . . . . . . . .
MAG_SI_YZ_L register. . . . . . . . . . . . . . . . . .
MAG_SI_YZ_L register description . . . . . . . . .
MAG_SI_YZ_H register . . . . . . . . . . . . . . . . .
MAG_SI_YZ_H register description . . . . . . . . .
MAG_SI_ZZ_L register . . . . . . . . . . . . . . . . . .
MAG_SI_ZZ_L register description. . . . . . . . . .
MAG_SI_ZZ_H register . . . . . . . . . . . . . . . . .
MAG_SI_ZZ_H register description . . . . . . . . .
MAG_CFG_A register . . . . . . . . . . . . . . . . . .
MAG_CFG_A description . . . . . . . . . . . . . . . .
MAG_CFG_B register . . . . . . . . . . . . . . . . . .
MAG_CFG_B description . . . . . . . . . . . . . . . .
FSM_LC_TIMEOUT_L register . . . . . . . . . . . .
FSM_LC_TIMEOUT_L register description . . . .
FSM_LC_TIMEOUT_H register . . . . . . . . . . . .
FSM_LC_TIMEOUT_H register description . . . .
FSM_PROGRAMS register . . . . . . . . . . . . . . .
FSM_PROGRAMS register description. . . . . . .
FSM_START_ADD_L register . . . . . . . . . . . . .
FSM_START_ADD_L register description . . . . .
FSM_START_ADD_H register . . . . . . . . . . . . .
FSM_START_ADD_H register description. . . . .
PEDO_CMD_REG register . . . . . . . . . . . . . . .
PEDO_CMD_REG register description . . . . . . .
PEDO_DEB_STEPS_CONF register . . . . . . . .
PEDO_DEB_STEPS_CONF register description
PEDO_SC_DELTAT_L register . . . . . . . . . . . .
PEDO_SC_DELTAT_H register . . . . . . . . . . . .
PEDO_SC_DELTAT_H/L register description. . .
DS12140 - Rev 2
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127
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page 168/172
LSM6DSO
List of tables
Table 322.
Table 323.
Table 324.
Table 325.
Table 326.
Table 327.
Table 328.
Table 329.
Table 330.
Table 331.
Table 332.
Table 333.
Table 334.
Table 335.
Table 336.
Table 337.
Table 338.
Table 339.
Table 340.
Table 341.
Table 342.
Table 343.
Table 344.
Table 345.
Table 346.
Table 347.
Table 348.
Table 349.
Table 350.
Table 351.
Table 352.
Table 353.
Table 354.
Table 355.
Table 356.
Table 357.
Table 358.
Table 359.
Table 360.
Table 361.
Table 362.
Table 363.
Table 364.
Table 365.
Table 366.
Table 367.
Table 368.
Table 369.
Table 370.
Table 371.
Table 372.
Table 373.
Table 374.
Table 375.
Register address map - sensor hub registers .
SENSOR_HUB_1 register. . . . . . . . . . . . . .
SENSOR_HUB_1 register description . . . . .
SENSOR_HUB_2 register. . . . . . . . . . . . . .
SENSOR_HUB_2 register description . . . . .
SENSOR_HUB_3 register. . . . . . . . . . . . . .
SENSOR_HUB_3 register description . . . . .
SENSOR_HUB_4 register. . . . . . . . . . . . . .
SENSOR_HUB_4 register description . . . . .
SENSOR_HUB_5 register. . . . . . . . . . . . . .
SENSOR_HUB_5 register description . . . . .
SENSOR_HUB_6 register. . . . . . . . . . . . . .
SENSOR_HUB_6 register description . . . . .
SENSOR_HUB_7 register. . . . . . . . . . . . . .
SENSOR_HUB_7 register description . . . . .
SENSOR_HUB_8 register. . . . . . . . . . . . . .
SENSOR_HUB_8 register description . . . . .
SENSOR_HUB_9 register. . . . . . . . . . . . . .
SENSOR_HUB_9 register description . . . . .
SENSOR_HUB_10 register . . . . . . . . . . . . .
SENSOR_HUB_10 register description. . . . .
SENSOR_HUB_11 register . . . . . . . . . . . . .
SENSOR_HUB_11 register description . . . . .
SENSOR_HUB_12 register . . . . . . . . . . . . .
SENSOR_HUB_12 register description. . . . .
SENSOR_HUB_13 register . . . . . . . . . . . . .
SENSOR_HUB_13 register description. . . . .
SENSOR_HUB_14 register . . . . . . . . . . . . .
SENSOR_HUB_14 register description. . . . .
SENSOR_HUB_15 register . . . . . . . . . . . . .
SENSOR_HUB_15 register description. . . . .
SENSOR_HUB_16 register . . . . . . . . . . . . .
SENSOR_HUB_16 register description. . . . .
SENSOR_HUB_17 register . . . . . . . . . . . . .
SENSOR_HUB_17 register description. . . . .
SENSOR_HUB_17 register . . . . . . . . . . . . .
SENSOR_HUB_17 register description. . . . .
MASTER_CONFIG register. . . . . . . . . . . . .
MASTER_CONFIG register description . . . .
SLV0_ADD register . . . . . . . . . . . . . . . . . .
SLV_ADD register description . . . . . . . . . . .
SLV0_SUBADD register . . . . . . . . . . . . . . .
SLV0_SUBADD register description . . . . . . .
SLAVE0_CONFIG register . . . . . . . . . . . . .
SLAVE0_CONFIG register description . . . . .
SLV1_ADD register . . . . . . . . . . . . . . . . . .
SLV1_ADD register description . . . . . . . . . .
SLV1_SUBADD register . . . . . . . . . . . . . . .
SLV1_SUBADD register description . . . . . . .
SLAVE1_CONFIG register . . . . . . . . . . . . .
SLAVE1_CONFIG register description . . . . .
SLV2_ADD register . . . . . . . . . . . . . . . . . .
SLV2_ADD register description . . . . . . . . . .
SLV2_SUBADD register . . . . . . . . . . . . . . .
DS12140 - Rev 2
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136
138
138
138
138
138
138
139
139
139
139
139
139
140
140
140
140
140
140
141
141
141
141
141
141
142
142
142
142
142
142
143
143
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page 169/172
LSM6DSO
List of tables
Table 376.
Table 377.
Table 378.
Table 379.
Table 380.
Table 381.
Table 382.
Table 383.
Table 384.
Table 385.
Table 386.
Table 387.
Table 388.
Table 389.
Table 390.
SLV2_SUBADD register description . . . . . . . . . . . .
SLAVE2_CONFIG register . . . . . . . . . . . . . . . . . .
SLAVE2_CONFIG register description . . . . . . . . . .
SLV3_ADD register . . . . . . . . . . . . . . . . . . . . . . .
SLV3_ADD register description . . . . . . . . . . . . . . .
SLV3_SUBADD register . . . . . . . . . . . . . . . . . . . .
SLV3_SUBADD register description . . . . . . . . . . . .
SLAVE3_CONFIG register . . . . . . . . . . . . . . . . . .
SLAVE3_CONFIG register description . . . . . . . . . .
DATAWRITE_SLV0 register. . . . . . . . . . . . . . . . . .
DATAWRITE_SLV0 register description . . . . . . . . .
STATUS_MASTER register . . . . . . . . . . . . . . . . . .
STATUS_MASTER register description. . . . . . . . . .
Reel dimensions for carrier tape of LGA-14 package
Document revision history . . . . . . . . . . . . . . . . . . .
DS12140 - Rev 2
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147
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page 170/172
LSM6DSO
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
DS12140 - Rev 2
Generic state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State machine in the LSM6DSO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LSM6DSO connection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI slave timing diagram (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read and write protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . .
SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . .
SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . .
I²C and I3C both active (INT1 pin not connected) . . . . . . . . . . . . . . . . . . . . . .
Only I3C active (INT1 pin connected to VDD_IO) . . . . . . . . . . . . . . . . . . . . . .
Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer UI chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accelerometer chain with Mode 4 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2 . . . . . . . . . . . . . . . . . .
Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS) . . . . . . . . . . . . . . . . . . .
LSM6DSO electrical connections in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
LSM6DSO electrical connections in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . .
LSM6DSO electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI).
Accelerometer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data . . . . . . . . .
Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . .
LGA-14 package orientation in carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . .
Reel information for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . .
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.. 5
.. 5
.. 6
.. 7
. 13
. 14
. 20
. 20
. 21
. 21
. 21
. 22
. 25
. 25
. 28
. 28
. 29
. 29
. 30
. 31
. 35
. 36
. 37
. 58
151
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152
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page 171/172
LSM6DSO
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12140 - Rev 2
page 172/172
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