LSM6DSRXTR

LSM6DSRX Datasheet iNEMO inertial module with embedded Machine Learning Core: always-on 3D accelerometer and 3D gyroscope Features LGA-14L (2.5 x 3.0 x 0.83 mm) typ. • • • • • • • • Extended full-scale range for gyroscope up to 4000 dps High stability over temperature and time Smart FIFO up to 9 kbytes Android compliant Auxiliary SPI for OIS data output for gyroscope and accelerometer ±2/±4/±8/±16 g full scale ±125/±250/±500/±1000/±2000/±4000 dps full scale Analog supply voltage: 1.71 V to 3.6 V • • SPI / I²C & MIPI I3CSM serial interface with main processor data synchronization Supports sensor synchronization S4S for Qualcomm, full spec compliant (I²C, MIPI I3CSM, SPI) Advanced pedometer, step detector and step counter Significant Motion Detection, tilt detection Programmable Finite State Machine: accelerometer, gyroscope, and external sensors Machine Learning Core Standard interrupts: free-fall, wakeup, 6D/4D orientation, click and double-click Embedded temperature sensor ECOPACK, RoHS and “Green” compliant • • • • • • • Product status link LSM6DSRX Product summary Order code LSM6DSRX LSM6DSRXTR Temp. range [°C] -40 to +85 Package LGA-14L (2.5 x 3.0 x 0.83 mm) Packing Tray Tape & Reel Product label Applications • • • • • • • • • • • Motion tracking and gesture detection Virtual and augmented reality OIS for camera applications Sensor hub Indoor navigation IoT and connected devices Sports applications Vibration monitoring and compensation Drones Robotics High-precision systems Description Product resources AN5382 (LSM6DSRX) AN5393 (Machine Learning Core) AN5389 (Finite State Machine) The LSM6DSRX is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope with an extended full-scale range for the gyroscope, up to 4000 dps, and high stability over temperature and time. The LSM6DSRX supports main OS requirements, offering real, virtual and batch sensors with 9 kbytes with FIFO compression up to three times for dynamic data batching. TN0018 (Design and soldering) DS13007 - Rev 3 - November 2020 For further information contact your local STMicroelectronics sales office. www.st.com LSM6DSRX ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The LSM6DSRX has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±125/±250/±500/±1000/±2000/±4000 dps. The LSM6DSRX embeds a broad range of advanced functions supporting Android wearable sensors and programmable sensors (suitable for activity recognition). The LSM6DSRX embeds a Machine Learning Core able to identify if a data pattern matches an activity in a user-defined set of classes, reducing power consumption and increasing performance of the sensor. The LSM6DSRX is available in a plastic land grid array (LGA) package. DS13007 - Rev 3 page 2/171 LSM6DSRX Overview 1 Overview The LSM6DSRX is a system-in-package featuring a high-performance 3-axis digital accelerometer and 3-axis digital gyroscope. The LSM6DSRX delivers best-in-class motion sensing that can detect orientation and gestures in order to empower application developers and consumers with features and capabilities that are more sophisticated than simply orienting their devices to portrait and landscape mode. This device is suitable for augmented reality and virtual reality applications as well as Optical Image Stabilization and motion-based gaming controllers as a result of its high stability over temperature and time, combined with superior sensing precision. The LSM6DSRX fully supports OIS applications using both the gyroscope and accelerometer sensor. The device can output OIS data through a dedicated auxiliary SPI and includes a dedicated configurable signal processing path for OIS. For both the gyroscope and accelerometer, the UI signal processing path is completely independent from that of the OIS and is readable through FIFO. Moreover, self -test and full scale are available for both the UI and OIS chains. The event-detection interrupts enable efficient and reliable motion tracking and contextual awareness, implementing hardware recognition of free-fall events, 6D orientation, click and double-click sensing, activity or inactivity, and wakeup events. The LSM6DSRX supports main OS requirements, offering real, virtual and batch mode sensors. In addition, the LSM6DSRX can efficiently run the sensor-related features specified in Android. In particular, the LSM6DSRX has been designed to implement hardware features such as significant motion, tilt, pedometer functions, timestamping and to support the data acquisition of an external magnetometer. The LSM6DSRX offers hardware flexibility to connect the pins with different mode connections to external sensors to expand functionalities such as adding a sensor hub. Up to 9 kbytes of FIFO with compression and dynamic allocation of significant data (i.e. external sensors, timestamp, etc.) allows overall power saving of the system. Like the entire portfolio of MEMS sensor modules, the LSM6DSRX leverages the robust and mature in-house manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the characteristics of the sensing element. The LSM6DSRX is available in a small plastic land grid array (LGA) package of 2.5 x 3.0 x 0.83 mm to address ultra-compact solutions. DS13007 - Rev 3 page 3/171 LSM6DSRX Embedded low-power features 2 Embedded low-power features The LSM6DSRX has been designed to be fully compliant with Android, featuring the following on-chip functions: • 9 kbytes data buffering, data can be compressed two or three times – 100% efficiency with flexible configurations and partitioning – Possibility to store timestamp • Event-detection interrupts (fully configurable): – Free-fall – Wakeup – 6D orientation – Click and double-click sensing – Activity/inactivity recognition – Stationary/Motion detection • Specific IP blocks with negligible power consumption and high-performance: – Pedometer functions: step detector and step counters – Tilt – Significant Motion Detection – Finite State Machine (FSM) for accelerometer, gyroscope, and external sensors – Machine Learning Core (MLC) • Sensor hub – Up to 6 total sensors: 2 internal (accelerometer and gyroscope) and 4 external sensors • S4S data rate synchronization with external trigger for reduced sensor access and enhanced fusion 2.1 Tilt detection The tilt function helps to detect activity change and has been implemented in hardware using only the accelerometer to achieve targets of both ultra-low power consumption and robustness during the short duration of dynamic accelerations. The tilt function is based on a trigger of an event each time the device's tilt changes and can be used with different scenarios, for example: • Triggers when phone is in a front pants pocket and the user goes from sitting to standing or standing to sitting; • Doesn’t trigger when phone is in a front pants pocket and the user is walking, running or going up stairs. 2.2 Significant Motion Detection The Significant Motion Detection (SMD) function generates an interrupt when a ‘significant motion’, that could be due to a change in user location, is detected. In the LSM6DSRX device this function has been implemented in hardware using only the accelerometer. SMD functionality can be used in location-based applications in order to receive a notification indicating when the user is changing location. DS13007 - Rev 3 page 4/171 LSM6DSRX Finite State Machine 2.3 Finite State Machine The LSM6DSRX can be configured to generate interrupt signals activated by user-defined motion patterns. To do this, up to 16 embedded finite state machines can be programmed independently for motion detection such as glance gestures, absolute wrist tilt, shake and double-shake detection. Definition of Finite State Machine A state machine is a mathematical abstraction used to design logic connections. It is a behavioral model composed of a finite number of states and transitions between states, similar to a flow chart in which one can inspect the way logic runs when certain conditions are met. The state machine begins with a start state, goes to different states through transitions dependent on the inputs, and can finally end in a specific state (called stop state). The current state is determined by the past states of the system. The following figure shows a generic state machine. Figure 1. Generic state machine Finite State Machine in the LSM6DSRX The LSM6DSRX works as a combo accelerometer-gyroscope sensor, generating acceleration and angular rate output data. It is also possible to connect an external sensor (magnetometer) by using the Sensor Hub feature (Mode 2). These data can be used as input of up to 16 programs in the embedded Finite State Machine (Figure 2. State machine in the LSM6DSRX). All 16 finite state machines are independent: each one has its dedicated memory area and it is independently executed. An interrupt is generated when the end state is reached or when some specific command is performed. Figure 2. State machine in the LSM6DSRX DS13007 - Rev 3 page 5/171 LSM6DSRX Machine Learning Core 2.4 Machine Learning Core The LSM6DSRX embeds a dedicated core for machine learning processing that provides system flexibility, allowing some algorithms run in the application processor to be moved to the MEMS sensor with the advantage of consistent reduction in power consumption. Machine Learning Core logic allows identifying if a data pattern (for example motion, pressure, temperature, magnetic data, etc.) matches a user-defined set of classes. Typical examples of applications could be activity detection like running, walking, driving, etc. The LSM6DSRX Machine Learning Core works on data patterns coming from the accelerometer and gyro sensors, but it is also possible to connect and process external sensor data (like magnetometer) by using the Sensor Hub feature (Mode 2). The input data can be filtered using a dedicated configurable computation block containing filters and features computed in a fixed time window defined by the user. Machine learning processing is based on logical processing composed of a series of configurable nodes characterized by "if-then-else" conditions where the "feature" values are evaluated against defined thresholds. Figure 3. Machine Learning Core in the LSM6DSRX Sensor Data & Hub Machine Learning Core OUTPUT Accelerometer Filters Results Gyroscope Features Interrupts INPUT Machine Learning Core Logical processing External Sensor The LSM6DSRX can be configured to run up to 8 flows simultaneously and independently and every flow can generate up to 256 results. The total number of nodes can be up to 512. The results of the machine learning processing are available in dedicated output registers readable from the application processor at any time. The LSM6DSRX Machine Learning Core can be configured to generate an interrupt when a change in the result occurs. DS13007 - Rev 3 page 6/171 LSM6DSRX Pin description 3 Pin description Figure 4. Pin connections Z ΩY ΩR SDO_Aux OCS_Aux INT2 Vdd SDA SCL X 11 1 BOTTOM VIEW 8 4 5 GND 7 GND SDO/SA0 SDx SCx INT1 Vdd_IO Direction of detectable acceleration (top view) CS Y ΩP Direction of detectable angular rate (top view) DS13007 - Rev 3 page 7/171 LSM6DSRX Pin connections 3.1 Pin connections The LSM6DSRX offers flexibility to connect the pins in order to have four different mode connections and functionalities. In detail: • Mode 1: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available; • Mode 2: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface and I²C interface master for external sensor connections are available; • Mode 3: I²C/ MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is available for the gyroscope ONLY; • Mode 4: I²C / MIPI I3CSM slave interface or SPI (3- and 4-wire) serial interface is available for the application processor interface while an auxiliary SPI (3- and 4-wire) serial interface for external sensor connections is available for the accelerometer and gyroscope. Figure 5. LSM6DSRX connection modes Mode 1 Mode 2 Mode 3 Mode 4 HOST HOST HOST HOST I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSRX I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSRX Master I2C LSM6DSM External LSM6DSM sensors I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSRX Aux SPI (3/4-w) For gyro data only Camera module I 2C / MIPI I3CSM / SPI (3/4-w) LSM6DSRX Aux SPI (3/4-w) For XL and gyro data Camera module In the following table each mode is described for the pin connections and function. DS13007 - Rev 3 page 8/171 LSM6DSRX Pin connections Table 1. Pin description Pin # Name Mode 1 function Mode 2 function Mode 3/4 function SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) I²C least significant bit of the device address (SA0) I²C least significant bit of the device address (SA0) I²C least significant bit of the device address (SA0) 1 SDO/SA0 2 SDx Connect to Vdd_IO or GND I²C serial data master (MSDA) Auxiliary SPI 3/4-wire interface serial data input (SDI) and SPI 3-wire serial data output (SDO) 3 SCx Connect to Vdd_IO or GND I²C serial clock master (MSCL) Auxiliary SPI 3/4-wire interface serial port clock (SPC_Aux) 4 INT1 Programmable interrupt in I²C and SPI 5 Vdd_IO(1) Power supply for I/O pins 6 GND 0 V supply 7 GND 0 V supply 8 Vdd(1) Power supply Programmable interrupt 2 (INT2) / Data enabled (DEN) / I²C master external synchronization signal (MDRDY) Programmable interrupt 2 (INT2) / Data enabled (DEN) Auxiliary SPI 3/4-wire interface enable 9 INT2 Programmable interrupt 2 (INT2) / Data enabled (DEN) 10 OCS_Aux Leave unconnected(2) Leave unconnected(2) SDO_Aux Connect to Vdd_IO or leave unconnected(2) Connect to Vdd_IO or leave unconnected(2) 11 12 CS 13 SCL 14 SDA Auxiliary SPI 3-wire interface: leave unconnected(2) Auxiliary SPI 4-wire interface: serial data output (SDO_Aux) I²C and MIPI I3CSM/SPI mode I²C and MIPI I3CSM/SPI mode I²C and MIPI I3CSM/SPI mode selection (1: SPI idle mode / I²C and selection (1: SPI idle mode / I²C and selection (1: SPI idle mode / I²C and MIPI I3CSM communication enabled; MIPI I3CSM communication enabled; MIPI I3CSM communication enabled; 0: SPI communication mode / I²C and 0: SPI communication mode / I²C and 0: SPI communication mode / I²C and MIPI I3CSM disabled) MIPI I3CSM disabled) MIPI I3CSM disabled) I²C/MIPI I3CSMserial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSMserial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSMserial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSM serial data (SDA) I²C/MIPI I3CSM serial data (SDA) I²C/MIPI I3CSM serial data (SDA) SPI serial data input (SDI) SPI serial data input (SDI) SPI serial data input (SDI) 3-wire interface serial data output (SDO) 3-wire interface serial data output (SDO) 3-wire interface serial data output (SDO) 1. Recommended 100 nF filter capacitor. 2. Leave pin electrically unconnected and soldered to PCB. DS13007 - Rev 3 page 9/171 LSM6DSRX Module specifications 4 Module specifications 4.1 Mechanical characteristics @ Vdd = 1.8 V, T = 25 °C, unless otherwise noted. Table 2. Mechanical characteristics Symbol Parameter Test conditions Min. Typ. (1) Max. Unit ±2 LA_FS ±4 Linear acceleration measurement range ±8 g ±16 ±125 ±250 G_FS ±500 Angular rate measurement range ±1000 dps ±2000 ±4000 LA_So G_So G_So% LA_SoDr G_SoDr Linear acceleration sensitivity(2) Angular rate sensitivity(2) Sensitivity tolerance(3) Linear acceleration sensitivity change vs. temperature(4) Angular rate sensitivity change vs. temperature(4) accuracy(5) LA_TyOff Linear acceleration zero-g level offset G_TyOff Angular rate zero-rate level(5) LA_OffDr Linear acceleration zero-g level change vs. temperature(4) G_OffDr Angular rate typical zero-rate level change vs. temperature(4) Rn RnRMS An RMS Rate noise density in high-performance mode(6) Gyroscope RMS noise in low-power mode(7) Acceleration noise density in high-performance mode(8) Acceleration RMS noise in low-power mode(9)(10) DS13007 - Rev 3 FS = ±2 g 0.061 FS = ±4 g 0.122 FS = ±8 g 0.244 FS = ±16 g 0.488 FS = ±125 dps 4.375 FS = ±250 dps 8.75 FS = ±500 dps 17.50 FS = ±1000 dps 35 FS = ±2000 dps 70 FS = ±4000 dps 140 at component level ±1 % from -40 °C to +85 °C ±0.01 %/°C from -40 °C to +85 °C ±0.007 %/°C ±10 mg ±1 dps ±0.1 mg/°C ±0.005 dps/°C 5 mdps/√Hz 90 mdps 60 µg/√Hz 1.8 mg(RMS) mg/LSB mdps/LSB page 10/171 LSM6DSRX Mechanical characteristics Symbol Parameter Test conditions Min. Typ. (1) Max. Unit 1.6(11) 12.5 26 52 104 LA_ODR Linear acceleration output data rate 208 416 833 1666 3332 6667 Hz 12.5 26 52 104 G_ODR 208 Angular rate output data rate 416 833 1666 3332 6667 Linear acceleration self-test output Vst Top change(12) (13) (14) Angular rate self-test output change (15)(16) 40 1700 mg FS = ±250 dps 20 80 dps FS = ±2000 dps 150 700 dps -40 +85 °C Operating temperature range 1. Typical specifications are not guaranteed. 2. Sensitivity values after factory calibration test and trimming. 3. Subject to change. 4. Measurements are performed in a uniform temperature setup and they are based on characterization data in a limited number of samples. Not measured during final test for production. 5. Values after factory calibration test and trimming. 6. Gyroscope rate noise density in high-performance mode is independent of the ODR and FS setting. 7. Gyroscope RMS noise in low-power mode is independent of the ODR and FS setting. 8. Accelerometer noise density in high-performance mode is independent of the ODR and full scale. 9. Accelerometer RMS noise in low-power mode is independent of the ODR. 10. Noise RMS related to BW = ODR/2. 11. This ODR is available when the accelerometer is in low-power mode. 12. The sign of the linear acceleration self-test output change is defined by the STx_XL bits in a dedicated register for all axes. 13. The linear acceleration self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 0.061 mg at ±2 g full scale. 14. Accelerometer self-test limits are full-scale independent. 15. The sign of the angular rate self-test output change is defined by the STx_G bits in a dedicated register for all axes. 16. The angular rate self-test output change is defined with the device in stationary condition as the absolute value of: OUTPUT[LSb] (self-test enabled) - OUTPUT[LSb] (self-test disabled). 1LSb = 70 mdps at ±2000 dps full scale DS13007 - Rev 3 page 11/171 LSM6DSRX Electrical characteristics 4.2 Electrical characteristics @ Vdd = 1.8 V, T = 25 °C, unless otherwise noted. Table 3. Electrical characteristics Min. Typ.(1) Max. Unit Supply voltage 1.71 1.8 3.6 V Power supply for I/O 1.62 3.6 V Symbol Vdd Vdd_IO Parameter Test conditions IddHP Gyroscope and accelerometer current consumption in high-performance mode IddNM Gyroscope and accelerometer current consumption in normal mode ODR = 208 Hz LA_IddHP Accelerometer current consumption in high-performance mode LA_IddLM Accelerometer current consumption in low-power mode IddPD 1.2 mA 0.7 mA 360 µA ODR = 52 Hz 32 ODR = 12.5 Hz 11 ODR = 1.6 Hz 5.5 µA Gyroscope and accelerometer current consumption during power-down 3 µA Ton Turn-on time 35 ms VIH Digital high-level input voltage VIL Digital low-level input voltage 0.7 * Vdd_IO V 0.3 * Vdd_IO mA(2) VOH Digital high-level output voltage IOH = 4 VOL Digital low-level output voltage IOL = 4 mA(2) Top Operating temperature range Vdd_IO - 0.2 V V -40 0.2 V +85 °C 1. Typical specifications are not guaranteed. 2. 4 mA is the minimum driving capability, i.e. the minimum DC current that can be sourced/sunk by the digital pad in order to guarantee the correct digital output voltage levels VOH and VOL. Temperature sensor characteristics 4.3 @ Vdd = 1.8 V, T = 25 °C unless otherwise noted. Table 4. Temperature sensor characteristics Symbol TODR(2) Toff Parameter Test condition Min. Temperature refresh rate Temperature offset(3) TSen Temperature sensitivity TST Temperature stabilization time(4) T_ADC_res Temperature ADC resolution Top Operating temperature range Typ.(1) Max. 52 -15 Hz +15 256 °C LSB/°C 500 16 -40 Unit µs bit +85 °C 1. Typical specifications are not guaranteed. 2. When the accelerometer is in low-power mode and the gyroscope part is turned off, the TODR value is equal to the accelerometer ODR. 3. The output of the temperature sensor is 0 LSB (typ.) at 25 °C. 4. Time from power ON to valid output data. Based on characterization data. DS13007 - Rev 3 page 12/171 LSM6DSRX Communication interface characteristics 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 5. SPI slave timing values (in mode 3) Symbol Parameter Value(1) Min tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time 5 th(CS) CS hold time 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time th(SO) SDO output hold time tdis(SO) SDO output disable time Max Unit ns 100 10 MHz ns 50 5 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 6. SPI slave timing diagram (in mode 3) Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both input and output ports. DS13007 - Rev 3 page 13/171 LSM6DSRX Communication interface characteristics 4.4.2 I²C - inter-IC control interface Subject to general operating conditions for Vdd and Top. Table 6. I²C slave timing values Symbol f(SCL) I²C fast mode(1)(2) Parameter SCL clock frequency I²C fast mode +(1)(2) Min Max Min Max 0 400 0 1000 tw(SCLL) SCL clock low time 1.3 0.5 tw(SCLH) SCL clock high time 0.6 0.26 tsu(SDA) SDA setup time 100 50 th(SDA) SDA data hold time 0 0.9 START/REPEATED START condition hold time 0.6 0.26 tsu(SR) REPEATED START condition setup time 0.6 0.26 tsu(SP) STOP condition setup time 0.6 0.26 Bus free time between STOP and START condition 1.3 0.5 CB kHz µs ns 0 th(ST) tw(SP:SR) Unit µs Data valid time 0.9 0.45 Data valid acknowledge time 0.9 0.45 Capacitive load for each bus line 400 550 pF 1. Data based on standard I²C protocol requirement, not tested in production. 2. Data for I²C fast mode and I²C fast mode + have been validated by characterization, not tested in production. Figure 7. I²C slave timing diagram REPEATED START START tsu(SR) tw(SP:SR) SDA tsu (SDA) START th(SDA) tsu(SP) STOP SCL th(ST) tw(SCLL) tw(SCLH) Note: Measurement points are done at 0.3·Vdd_IO and 0.7·Vdd_IO for both ports. DS13007 - Rev 3 page 14/171 LSM6DSRX Absolute maximum ratings 4.5 Absolute maximum ratings Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Ratings Maximum value Unit Vdd Supply voltage -0.3 to 4.8 V TSTG Storage temperature range -40 to +125 °C 20,000 g 2 kV -0.3 to Vdd_IO +0.3 V Sg ESD Vin Acceleration g for 0.2 ms Electrostatic discharge protection (HBM) Input voltage on any control pin (including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) Note: Supply voltage on any pin should never exceed 4.8 V. This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. DS13007 - Rev 3 page 15/171 LSM6DSRX Terminology 4.6 4.6.1 Terminology Sensitivity Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors (see Table 2). An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time (see Table 2). 4.6.2 Zero-g and zero-rate level Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as 2’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 2. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. Zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time (see Table 2). DS13007 - Rev 3 page 16/171 LSM6DSRX Digital interfaces 5 Digital interfaces 5.1 I²C/SPI interface The registers embedded inside the LSM6DSRX may be accessed through both the I²C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The device is compatible with SPI modes 0 and 3. The serial interfaces are mapped onto the same pins. To select/exploit the I²C interface, the CS line must be tied high (i.e connected to Vdd_IO). Table 8. Serial interface pin description Pin name Pin description SPI enable CS I²C/SPI mode selection (1: SPI idle mode / I²C communication enabled; 0: SPI communication mode / I²C disabled) I²C Serial Clock (SCL) SCL/SPC SPI Serial Port Clock (SPC) I²C Serial Data (SDA) SDA/SDI/SDO SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SDO/SA0 5.1.1 SPI Serial Data Output (SDO) I²C less significant bit of the device address I²C serial interface The LSM6DSRX I²C is a bus slave. The I²C is employed to write the data to the registers, whose content can also be read back. The relevant I²C terminology is provided in the table below. Table 9. I²C terminology Term Transmitter Receiver Description The device which sends data to the bus The device which receives data from the bus Master The device which initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by the master There are two signals associated with the I²C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through external pull-up resistors. When the bus is free, both the lines are high. The I²C interface is implemented with fast mode (400 kHz) I²C standards as well as with fast mode plus (1000 kHz). In order to disable the I²C block, (I2C_disable) = 1 must be written in CTRL4_C (13h). DS13007 - Rev 3 page 17/171 LSM6DSRX I²C/SPI interface 5.1.1.1 I²C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The Slave ADdress (SAD) associated to the LSM6DSRX is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to the supply voltage, LSb is ‘1’ (address 1101011b); else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two different inertial modules to the same I²C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I²C embedded inside the LSM6DSRX behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the CTRL3_C (12h) (IF_INC). The slave address is completed with a Read/Write bit. If the bit is ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W Read 110101 0 1 11010101 (D5h) Write 110101 0 0 11010100 (D4h) Read 110101 1 1 11010111 (D7h) Write 110101 1 0 11010110 (D6h) Table 11. Transfer when master is writing one byte to slave Master ST SAD + W SUB Slave DATA SAK SP SAK SAK Table 12. Transfer when master is writing multiple bytes to slave Master ST SAD + W SUB Slave SAK DATA SAK DATA SP SAK SAK Table 13. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W Slave SUB SAK SR SAD + R SAK NMAK SAK SP DATA Table 14. Transfer when master is receiving (reading) multiple bytes of data from slave Master ST Slave DS13007 - Rev 3 SAD+W SUB SAK SR SAK SAD+R MAK SAK DATA MAK DATA NMAK SP DATA page 18/171 LSM6DSRX I²C/SPI interface Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left HIGH by the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge. DS13007 - Rev 3 page 19/171 LSM6DSRX I²C/SPI interface 5.1.2 SPI bus interface The LSM6DSRX SPI is a bus slave. The SPI allows writing and reading the registers of the device. The serial interface communicates with the application using 4 wires: CS, SPC, SDI and SDO. Figure 8. Read and write protocol (in mode 3) CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When the CTRL3_C (12h) (IF_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL3_C (12h) (IF_INC) bit is ‘1’, the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. DS13007 - Rev 3 page 20/171 LSM6DSRX I²C/SPI interface 5.1.2.1 SPI read Figure 9. SPI read protocol (in mode 3) CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-...: data DO(...-8). Further data in multiple byte reads. Figure 10. Multiple byte SPI read protocol (2-byte example) (in mode 3) CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14DO13DO12 DO11DO10 DO9 DO8 DS13007 - Rev 3 page 21/171 LSM6DSRX I²C/SPI interface 5.1.2.2 SPI write Figure 11. SPI write protocol (in mode 3) CS SPC SDI RW DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writes. Figure 12. Multiple byte SPI write protocol (2-byte example) (in mode 3) CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 DS13007 - Rev 3 page 22/171 LSM6DSRX I²C/SPI interface 5.1.2.3 SPI read in 3-wire mode A 3-wire mode is entered by setting the CTRL3_C (12h) (SIM) bit equal to ‘1’ (SPI serial interface mode selection). Figure 13. SPI read protocol in 3-wire mode (in mode 3) CS SPC SDI/O DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode. DS13007 - Rev 3 page 23/171 LSM6DSRX MIPI I3CSM interface 5.2 MIPI I3CSM interface 5.2.1 MIPI I3CSM slave interface The LSM6DSRX interface includes a MIPI I3CSM SDR only slave interface (compliant with release 1.0 of the specification) with MIPI I3CSM SDR embedded features: • CCC command • Direct CCC communication (SET and GET) • Broadcast CCC communication • Private communications • Private read and write for single byte • Multiple read and write • In-Band Interrupt request • Error Detection and Recovery Methods (S0-S6) Note: Refer to Section 5.3 I²C/I3C coexistence in LSM6DSRX for details concerning the choice of the interface when powering up the device. 5.2.2 MIPI I3CSM CCC supported commands The list of MIPI I3CSM CCC commands supported by the device is detailed in the following table. Table 15. MIPI I3CSM CCC commands Command Command code Default Description ENTDAA 0x07 DAA procedure SETDASA 0x87 Assign Dynamic Address using Static Address 0x6B/0x6A depending on SDO pin ENEC 0x80 / 0x00 Slave activity control (direct and broadcast) DISEC 0x81/ 0x01 Slave activity control (direct and broadcast) ENTAS0 0x82 / 0x02 Enter activity state (direct and broadcast) ENTAS1 0x83 / 0x03 Enter activity state (direct and broadcast) ENTAS2 0x84 / 0x04 Enter activity state (direct and broadcast) ENTAS3 0x85 / 0x05 Enter activity state (direct and broadcast) SETXTIME 0x98 / 0x28 Timing information exchange 0x07 GETXTIME 0x99 0x00 0x05 Timing information exchange 0x92 RSTDAA 0x86 / 0x06 Reset the assigned dynamic address (direct and broadcast) SETMWL 0x89 / 0x08 Define maximum write length during private write (direct and broadcast) SETMRL 0x8A / 0x09 Define maximum read length during private read (direct and broadcast) SETNEWDA 0x88 Change dynamic address 0x00 GETMWL 0x8B 0x08 Get maximum write length during private write (2 byte) 0x00 GETMRL 0x8C 0x10 Get maximum read length during private read 0x09 DS13007 - Rev 3 page 24/171 LSM6DSRX MIPI I3CSM interface Command Command code Default Description (3 byte) 0x02 0x08 GETPID 0x8D 0x00 0x6B Device ID register 0x10 0x0B GETBCR 0x8E GETDCR 0x8F GETSTATUS 0x90 0x07 (1 byte) 0x00 Bus characteristics register MIPI I3CSM device characteristics register 0x00 0x00 Status register (2 byte) 0x00 GETMXDS 0x94 0x38 Return max data speed (2 byte) DS13007 - Rev 3 page 25/171 LSM6DSRX I²C/I3C coexistence in LSM6DSRX 5.3 I²C/I3C coexistence in LSM6DSRX In the LSM6DSRX, the SDA and SCL lines are common to both I²C and I3C. The I²C bus requires anti-spike filters on the SDA and SCL pins that are not compatible with I3C timing. The device can be connected to both I²C and I3C or only to the I3C bus depending on the connection of the INT1 pin when the device is powered up: • INT1 pin floating (internal pull-down): I²C/I3C both active, see Figure 14 • INT1 pin connected to Vdd_IO: only I3C active, see Figure 15 Figure 14. I²C and I3C both active (INT1 pin not connected) INT1 pin not connected I²C/I3C both active I²C/I3C (both active) I3C bus case I²C bus case Master sends I²C r/w Slave performs requested r/w 1. Master assigns DA to the slave(1) Master resets DA I3C private R/W with and without 7Eh CCC commands Slave event management Error detection and recovery Address assignment (DAA or ENTDA) must be performed with I²C Fast Mode Plus Timing. When the slave is addressed, the I²C slave is disabled and the timing is compatible with I3C specifications. Figure 15. Only I3C active (INT1 pin connected to Vdd_IO) INT1 pin connected to Vdd_IO Only I3C active I²C/I3C I3C bus case Dynamic Address Assignment (1) Master resets DA I3C private R/W with and without 7Eh CCC commands Slave event management Error detection and recovery 1. DS13007 - Rev 3 When the slave is I3C only, the I²C slave is always disabled. The address can be assigned using I3C SDR timing. page 26/171 LSM6DSRX Master I²C interface 5.4 Master I²C interface If the LSM6DSRX is configured in Mode 2, a master I²C line is available. The master serial interface is mapped in the following dedicated pins. Table 16. Master I²C pin details Pin name MSCL I²C serial clock master MSDA I²C serial data master MDRDY 5.5 Pin description I²C master external synchronization signal Auxiliary SPI interface If the LSM6DSRX is configured in Mode 3 or Mode 4, the auxiliary SPI is available. The auxiliary SPI interface is mapped to the following dedicated pins. Table 17. Auxiliary SPI pin details Pin name OCS_Aux Pin description Auxiliary SPI 3/4-wire enable SDx Auxiliary SPI 3/4-wire data input (SDI_Aux) and SPI 3-wire data output (SDO_Aux) SCx Auxiliary SPI 3/4-wire interface serial port clock SDO_Aux Auxiliary SPI 4-wire data output (SDO_Aux) When the LSM6DSRX is configured in Mode 3 or Mode 4, the auxiliary SPI can be connected to a camera module for OIS/EIS support. In this configuration, the auxiliary SPI can write only to the dedicated registers INT_OIS (6Fh), CTRL1_OIS (70h), CTRL2_OIS (71h), CTRL3_OIS (72h). All the registers are accessible in Read mode from both the primary interface and auxiliary SPI. Mode 3 is enabled when the OIS_EN_SPI2 bit in CTRL1_OIS (70h) register is set to 1. Mode 4 is enabled when both the OIS_EN_SPI2 bit and the Mode4_EN bit in CTRL1_OIS (70h) register are set to 1. DS13007 - Rev 3 page 27/171 LSM6DSRX Functionality 6 Functionality 6.1 Operating modes In the LSM6DSRX, the accelerometer and the gyroscope can be turned on/off independently of each other and are allowed to have different ODRs and power modes. The LSM6DSRX has three operating modes available: • only accelerometer active and gyroscope in power-down or sleep mode • only gyroscope active and accelerometer in power-down • both accelerometer and gyroscope sensors active with independent ODR The accelerometer is activated from power-down by writing ODR_XL[3:0] in CTRL1_XL (10h) while the gyroscope is activated from power-down by writing ODR_G[3:0] in CTRL2_G (11h). For combo-mode the ODRs are totally independent. 6.2 Gyroscope power modes In the LSM6DSRX, the gyroscope can be configured in four different operating modes: power-down, lowpower, normal mode and high-performance mode. The operating mode selected depends on the value of the G_HM_MODE bit in CTRL7_G (16h). If G_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz). To enable the low-power and normal mode, the G_HM_MODE bit has to be set to '1'. Low-power mode is available for lower ODRs (12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz. 6.3 Accelerometer power modes In the LSM6DSRX, the accelerometer can be configured in four different operating modes: power-down, lowpower, normal mode and high-performance mode. The operating mode selected depends on the value of the XL_HM_MODE bit in CTRL6_C (15h). If XL_HM_MODE is set to '0', high-performance mode is valid for all ODRs (from 12.5 Hz up to 6.66 kHz). To enable the low-power and normal mode, the XL_HM_MODE bit has to be set to '1'. Low-power mode is available for lower ODRs (1.6, 12.5, 26, 52 Hz) while normal mode is available for ODRs equal to 104 and 208 Hz. 6.4 Block diagram of filters Figure 16. Block diagram of filters M E M S S E N S O R Gyro UI/OIS front-end Low Pass UI XL XL UI/OIS front-end ADC2 Temperature sensor Voltage and current references DS13007 - Rev 3 ADC1 Low Pass UI Gyro Low Pass OIS Gyro Low Pass OIS XL Trimming circuit and Test interface Clock and phase generator Regs array, FIFO Regs array Power management I2C/ MIPI I3CSM /SPI interface Interrupt mng CS SCL/SPC SDA/SDI/SDO SDO/SA0 INT1 INT2 Interrupt mng Auxiliary SPI CS SPC_Aux SDI_Aux SDO_Aux FTP page 28/171 LSM6DSRX Block diagram of filters 6.4.1 Block diagrams of the accelerometer filters In the LSM6DSRX, the filtering chain for the accelerometer part is composed of the following: • Digital filter (LPF1) • Composite filter Details of the block diagram appear in the following figure. Figure 17. Accelerometer UI chain Digital LP Filter LPF1 Composite Filter ADC ODR_XL[3:0] Figure 18. Accelerometer composite filter LOW_PASS_ON_6D Free-fall 0 Advanced functions 1 LPF2_XL_EN USR_OFF_ON_OUT HP_SLOPE_XL_EN 0 0 Digital LP Filter 1 LPF1 output (1) 0 USER OFFSET LPF2 1 USR_OFF_W OFS_USR[7:0] FIFO HPCF_XL[2:0] Digital HP Filter 1 1 0 0 Wake-up Activity / Inactivity SPI / I 2C / MIPI I3C SM USR_OFF_ON_WU SLOPE_FDS 001 010 … 111 1 HPCF_XL[2:0] SLOPE FILTER 6D / 4D 000 HPCF_XL[2:0] S/D Tap 1. The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode and ODR up to 833 Hz. This value is equal to 780 Hz when the accelerometer is in low-power or normal mode. Note: Advanced functions include pedometer, step detector and step counter, significant motion detection, tilt function, Finite State Machine and Machine Learning Core. The accelerometer filtering chain when Mode 4 is enabled is illustrated in the following figure. DS13007 - Rev 3 page 29/171 LSM6DSRX Block diagram of filters Figure 19. Accelerometer chain with Mode 4 enabled ODR XL @6.6 kHz Digital LP Filter LPF_OIS ADC SPI_Aux FILTER_XL_CONF_OIS[2:0] UI chain Note: Mode 4 is enabled when Mode4_EN = 1 and OIS_EN_SPI2 = 1 in CTRL1_OIS (70h). The configuration of the accelerometer UI chain is not affected by enabling Mode 4. Accelerometer output values are in registers OUTX_L_A (28h) and OUTX_H_A (29h) through OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) and ODR at 6.66 kHz. 6.4.2 Block diagrams of the gyroscope filters In the LSM6DSRX, the gyroscope filtering chain depends on the mode configuration: • Mode 1 (for User Interface (UI) and Electronic Image Stabilization (EIS) functionality through primary interface) and Mode 2 Figure 20. Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2 SPI / I2 C / MIPI I3CSM ADC 0 0 LPF2 HPF 1 LPF1 FIFO 1 ODR_G[3:0] HP_EN_G FTYPE [2:0] LPF1_SEL_G FSM / MLC In this configuration, the gyroscope ODR is selectable from 12.5 Hz up to 6.66 kHz. A low-pass filter (LPF1) is available if the auxiliary SPI is disabled, for more details about the filter characteristics see Table 65. Gyroscope LPF1 bandwidth selection. The digital LPF2 filter cannot be configured by the user and its cutoff frequency depends on the selected gyroscope ODR, as indicated in the following table. DS13007 - Rev 3 page 30/171 LSM6DSRX Block diagram of filters Table 18. Gyroscope LPF2 bandwidth selection Gyroscope ODR [Hz] LPF2 cutoff [Hz] 12.5 4.3 26 8.3 52 16.7 104 33 208 67 417 133 833 267 1667 539 3333 1137 6667 3333 Data can be acquired from the output registers and FIFO over the primary I²C/I3C/SPI interface. • Mode 3 / Mode 4 (for OIS and EIS functionality) Figure 21. Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS) SPI / I2C / MIPI I3CSM Digital LP Filter LPF2 (3) HP_EN_G ADC 0 Digital HP Filter FIFO 1 ODR_G[3:0] FSM / MLC HP_EN_OIS 1 (3) Digital(1) (2) LP Filter LPF1 SPI_Aux 0 ODR Gyro @6.6 kHz FTYPE[1:0]_OIS 1. 2. 3. When Mode3/4 is enabled, the LPF1 filter is not available in the gyroscope UI chain. It is recommended to avoid using the LPF1 filter in Mode1/2 when Mode3/4 is intended to be used. HP_EN_OIS can be used to select the HPF on the OIS path only if the HPF is not used in the UI chain. If both the HP_EN_G bit and HP_EN_OIS bit are set to 1, the HP filter is applied to the UI chain only. Note: When S4S is enabled in the UI chain, the HPF is not available in the OIS chain. The auxiliary interface needs to be enabled in CTRL1_OIS (70h). In Mode 3/4 configuration, there are two paths: • the chain for User Interface (UI) where the ODR is selectable from 12.5 Hz up to 6.66 kHz DS13007 - Rev 3 page 31/171 LSM6DSRX OIS • 6.5 the chain for OIS/EIS where the ODR is at 6.66 kHz and the LPF1 is available. The LPF1 configuration depends on the setting of the FTYPE_[1:0] _OIS bit in register CTRL2_OIS (71h); for more details about the filter characteristics see Table 160. Gyroscope OIS chain digital LPF1 filter bandwidth selection. Gyroscope output values are in registers 22h to 27h with the selected full scale (FS[1:0]_G_OIS bit in CTRL1_OIS (70h)). OIS This paragraph describes OIS functionality and the dedicated accelerometer-gyroscope DSP chain. There is a dedicated gyroscope and accelerometer DSP for OIS. Other features can be configured: • Self-test on OIS side • DEN on OIS side The camera module is completely independent from the application processor as shown in Figure 22. The Auxiliary SPI can configure OIS functionality through INT_OIS (6Fh), CTRL1_OIS (70h), CTRL2_OIS (71h), CTRL3_OIS (72h). Reading from the Auxiliary SPI is enabled only when the OIS_EN_SPI2 bit in the CTRL1_OIS (70h) register is set to '1'. This bit also turns on the gyroscope OIS chain. The Primary Interface can access the OIS control registers (INT_OIS (6Fh), CTRL1_OIS (70h), CTRL2_OIS (71h), CTRL3_OIS (72h)) in read mode. Figure 22. Auxiliary SPI full control (a) and enabling primary interface (b) Camera Module Camera Module Image Sensor Actuator Image Sensor Actuator OIS Driver OIS Driver AP AP I3C/SPI/I2C I3C/SPI/I2C SPI_Aux 6x SPI_Aux (a) DS13007 - Rev 3 6x UI/OIS UI/OIS (b) page 32/171 LSM6DSRX FIFO 6.6 FIFO The presence of a FIFO allows consistent power saving for the system since the host processor does not need continuously poll data from the sensor, but It can wake up only when needed and burst the significant data out from the FIFO. The LSM6DSRX embeds 3 kbytes of data (up to 9 kbytes with the compression feature enabled) in FIFO to store the following data: • Gyroscope • Accelerometer • External sensors (up to 4) • Step counter • Timestamp • Temperature Writing data in the FIFO can be configured to be triggered by the: • Accelerometer / gyroscope data-ready signal • Sensor hub data-ready signal • Step detection signal The applications have maximum flexibility in choosing the rate of batching for physical sensors with FIFOdedicated configurations: accelerometer, gyroscope and temperature sensor batch rates can be selected by the user. External sensor writing in FIFO can be triggered by the accelerometer data-ready signal or by an external sensor interrupt. The step counter can be stored in FIFO with associated timestamp each time a step is detected. It is possible to select decimation for timestamp batching in FIFO with a factor of 1, 8, or 32. The reconstruction of a FIFO stream is a simple task thanks to the FIFO_DATA_OUT_TAG byte that allows recognizing the meaning of a word in FIFO. FIFO allows correct reconstruction of the timestamp information for each sensor stored in FIFO. If a change in the ODR or BDR (Batch Data Rate) configuration is performed, the application can correctly reconstruct the timestamp and know exactly when the change was applied without disabling FIFO batching. FIFO stores information of the new configuration and timestamp in which the change was applied in the device. Finally, FIFO embeds a compression algorithm that the user can enable in order to have up to 9 kbyte data stored in FIFO and take advantage of interface communication length for FIFO flushing and communication power consumption. The programmable FIFO watermark threshold can be set in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) using the WTM[8:0] bits. To monitor the FIFO status, dedicated registers (FIFO_STATUS1 (3Ah), FIFO_STATUS2 (3Bh)) can be read to detect FIFO overrun events, FIFO full status, FIFO empty status, FIFO watermark status and the number of unread samples stored in the FIFO. To generate dedicated interrupts on the INT1 and INT2 pins of these status events, the configuration can be set in INT1_CTRL (0Dh) and INT2_CTRL (0Eh). The FIFO buffer can be configured according to six different modes: • Bypass mode • FIFO mode • Continuous mode • Continuous-to-FIFO mode • Bypass-to-continuous mode • Bypass-to-FIFO mode Each mode is selected by the FIFO_MODE_[2:0] bits in the FIFO_CTRL4 (0Ah) register. DS13007 - Rev 3 page 33/171 LSM6DSRX FIFO 6.6.1 Bypass mode In Bypass mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 000), the FIFO is not operational and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode. 6.6.2 FIFO mode In FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 001) data from the output channels are stored in the FIFO until it is full. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0]) to '000'. After this reset command, it is possible to restart FIFO mode by writing FIFO_CTRL4 (0Ah) (FIFO_MODE_[2:0]) to '001'. The FIFO buffer memorizes up to 9 kbytes of data (with compression enabled) but the depth of the FIFO can be resized by setting the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). If the STOP_ON_WTM bit in FIFO_CTRL2 (08h) is set to '1', FIFO depth is limited up to the WTM [8:0] bits in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). 6.6.3 Continuous mode Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 110) provides a continuous FIFO update: as new data arrives, the older data is discarded. A FIFO threshold flag FIFO_STATUS2 (3Bh)(FIFO_WTM_IA) is asserted when the number of unread samples in FIFO is greater than or equal to FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h)(WTM [8:0]). It is possible to route the FIFO_WTM_IA flag to the INT1 pin by writing in register INT1_CTRL (0Dh) (INT1_FIFO_TH) = '1' or to the INT2 pin by writing in register INT2_CTRL (0Eh)(INT2_FIFO_TH) = '1'. A full-flag interrupt can be enabled, INT1_CTRL (0Dh)(INT1_FIFO_FULL) = '1' or INT2_CTRL (0Eh) (INT2_FIFO_FULL) = '1', in order to indicate FIFO saturation and eventually read its content all at once. If an overrun occurs, at least one of the oldest samples in FIFO has been overwritten and the FIFO_OVR_IA flag in FIFO_STATUS2 (3Bh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh)(DIFF_FIFO_[9:0]). 6.6.4 Continuous-to-FIFO mode In Continuous-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = 011), FIFO behavior changes according to the trigger event detected in one of the following interrupt events: • Single tap • Double tap • Wake-up • Free-fall • D6D When the selected trigger bit is equal to '1', FIFO operates in FIFO mode. When the selected trigger bit is equal to '0', FIFO operates in Continuous mode. 6.6.5 Bypass-to-Continuous mode In Bypass-to-Continuous mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode). FIFO behavior changes according to the trigger event detected in one of the following interrupt events: • Single tap • Double tap • Wake-up • Free-fall • D6D DS13007 - Rev 3 page 34/171 LSM6DSRX FIFO 6.6.6 Bypass-to-FIFO mode In Bypass-to-FIFO mode (FIFO_CTRL4 (0Ah)(FIFO_MODE_[2:0] = '111'), data measurement storage inside FIFO operates in FIFO mode when selected triggers are equal to '1', otherwise FIFO content is reset (Bypass mode). FIFO behavior changes according to the trigger event detected in one of the following interrupt events: • Single tap • Double tap • Wake-up • Free-fall • D6D 6.6.7 FIFO reading procedure The data stored in FIFO are accessible from dedicated registers and each FIFO word is composed of 7 bytes: one tag byte (FIFO_DATA_OUT_TAG (78h)), in order to identify the sensor, and 6 bytes of fixed data (FIFO_DATA_OUT registers from (79h) to (7Eh)). The DIFF_FIFO_[9:0] field in the FIFO_STATUS1 (3Ah) and FIFO_STATUS2 (3Bh) registers contains the number of words (1 byte TAG + 6 bytes DATA) collected in FIFO. In addition, it is possible to configure a counter of the batch events of accelerometer or gyroscope sensors. The flag COUNTER_BDR_IA in FIFO_STATUS2 (3Bh) alerts that the counter reaches a selectable threshold (CNT_BDR_TH_[10:0] field in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch)). This allows triggering the reading of FIFO with the desired latency of one single sensor. The sensor is selectable using the TRIG_COUNTER_BDR bit in COUNTER_BDR_REG1 (0Bh). As for the other FIFO status events, the flag COUNTER_BDR_IA can be routed on the INT1 or INT2 pins by asserting the corresponding bits (INT1_CNT_BDR of INT1_CTRL (0Dh)) and INT2_CNT_BDR of INT2_CTRL (0Eh)). In order to maximize the amount of accelerometer and gyroscope data in FIFO, the user can enable the compression algorithm by setting to 1 both the FIFO_COMPR_EN bit in EMB_FUNC_EN_B (05h) (embedded functions registers bank) and the FIFO_COMPR_RT_EN bit in FIFO_CTRL2 (08h). When compression is enabled, it is also possible to force writing non-compressed data at a selectable rate using the UNCOPTR_RATE_[1:0] field in FIFO_CTRL2 (08h). Meta information about accelerometer and gyroscope sensor configuration changes can be managed by enabling the ODR_CHG_EN bit in FIFO_CTRL2 (08h). DS13007 - Rev 3 page 35/171 LSM6DSRX Application hints 7 Application hints 7.1 LSM6DSRX electrical connections in Mode 1 Figure 23. LSM6DSRX electrical connections in Mode 1 14 CS SCL SDA Mode 1 HOST 12 I 2C / SM SDO/SA0 TOP VIEW SDx SCx 4 INT1 8 C2 7 GND Vdd_IO 5 NC NC GND GND or Vdd_IO 11 1 MIPI I3C / SPI (3/4-w) (1) (1) LSM6DSRX Vdd INT2 Vdd C1 100 nF I2C configuration GND Vdd_IO Rpu Vdd_IO 100 nF GND Rpu SCL SDA Pull-up to be added Rpu=10kOhm 1. Leave pin electrically unconnected and soldered to PCB. The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice). The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3CSM interface. The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C/MIPI I3CSM interface. DS13007 - Rev 3 page 36/171 LSM6DSRX LSM6DSRX electrical connections in Mode 2 7.2 LSM6DSRX electrical connections in Mode 2 Figure 24. LSM6DSRX electrical connections in Mode 2 HOST CS SCL SDA Mode 2 I 2C / SM MIPI I3C / SPI (3/4-w) 14 SDO/SA0 1 12 11 TOP VIEW MSDA MSCL NC 4 8 C2 7 GND Vdd_IO 5 GND INT1 NC LSM6DSRX (1) (1) Master I2C MDRDY/INT2 Vdd LSM6DSM External LSM6DSM sensors Vdd C1 100 nF I2C configuration GND Vdd_IO Rpu Vdd_IO 100 nF GND Rpu SCL SDA Pull-up to be added Rpu=10kOhm 1. Leave pin electrically unconnected and soldered to PCB. The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice). The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3CSM primary interface. The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C/MIPI I3CSM primary interface. DS13007 - Rev 3 page 37/171 LSM6DSRX LSM6DSRX electrical connections in Mode 3 and Mode 4 7.3 LSM6DSRX electrical connections in Mode 3 and Mode 4 Figure 25. LSM6DSRX electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI) Mode 4 HOST CS SDI SPC Mode 3 I 2C HOST I 2C / 14 SDO SDI_Aux 1 11 TOP VIEW SPC_Aux INT1 12 8 Vdd Vdd GND 7 GND Vdd_IO MIPI I3C / SPI (3/4-w) LSM6DSRX OCS_Aux INT2 4 5 (1) NC C1 Aux SPI (3/4-wire) / SM SM MIPI I3C / SPI (3/4-w) For gyro data only LSM6DSRX Aux SPI (3/4-wire) Camera module For XL and gyro data Camera module 100 nF I2C configuration GND Vdd_IO C2 Vdd_IO 100 nF GND Rpu Rpu SCL SDA Pull-up to be added Rpu=10kOhm 1. Leave pin electrically unconnected and soldered to PCB. Note: When Mode 3 and 4 are used, the pull-up on pins 10 and 11 can be disabled (refer to Table 19. Internal pin status). To avoid leakage current, it is recommended to add pull-up resistors on the SPI lines unless the SPI master can be left on while the OIS system is off. The device core is supplied through the Vdd line. Power supply decoupling capacitors (C1, C2 = 100 nF ceramic) should be placed as near as possible to the supply pin of the device (common design practice). The functionality of the device is selectable and accessible through the SPI/I²C/MIPI I3CSM primary interface. Measured acceleration/angular rate data is selectable and accessible through the SPI/I²C/MIPI I3CSM primary interface and auxiliary SPI. The functions, the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user through the SPI/I²C/MIPI I3CSM interface. DS13007 - Rev 3 page 38/171 DS13007 - Rev 3 Table 19. Internal pin status pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function SDO SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) SPI 4-wire interface serial data output (SDO) I²C least significant bit of the device address (SA0) I²C least significant bit of the device address (SA0) I²C least significant bit of the device address (SA0) MIPI I3CSM least significant bit of the static address (SA0) MIPI I3CSM least significant bit of the static address (SA0) MIPI I3CSM least significant bit of the static address (SA0) Connect to Vdd_IO or GND I²C serial data master (MSDA) Auxiliary SPI 3/4-wire interface serial data input (SDI) and SPI 3-wire serial data output (SDO) Auxiliary SPI 3/4-wire interface serial port clock (SPC_Aux) 1 SA0 2 SDx SCx Connect to Vdd_IO or GND 4 INT1 Programmable interrupt 1 / If device is used as MIPI I3CSM pure slave, this pin must be set to ‘1’. Programmable interrupt 1 / If device is used as MIPI I3CSM pure slave, this pin must be set to ‘1’. Programmable interrupt 1 / If device is used as MIPI I3CSM pure slave, this pin must be set to ‘1’. 5 Vdd_IO Power supply for I/O pins Power supply for I/O pins Power supply for I/O pins 6 GND 0 V supply 0 V supply 0 V supply 7 GND 0 V supply 0 V supply 0 V supply 8 Vdd Power supply Power supply Power supply 9 INT2 Programmable interrupt 2 (INT2) / Data enabled (DEN) Programmable interrupt 2 (INT2) / Data enabled (DEN) / I²C master external synchronization signal (MDRDY) Programmable interrupt 2 (INT2) / Data enabled (DEN) 10 OCS_Aux Leave unconnected Leave unconnected Auxiliary SPI 3/4-wire interface enabled 11 SDO_Aux Connect to Vdd_IO or leave unconnected Connect to Vdd_IO or leave unconnected Auxiliary SPI 3wire interface: leave unconnected / Auxiliary SPI 4-wire interface: serial data output (SDO_Aux) I²C/SPI mode selection I²C/SPI mode selection I²C/SPI mode selection (1:SPI idle mode / I²C communication enabled; (1:SPI idle mode / I²C communication enabled; (1:SPI idle mode / I²C communication enabled; 0: SPI communication mode / I²C disabled) 0: SPI communication mode / I²C disabled) 0: SPI communication mode / I²C disabled) 12 CS Pin status Mode 2 Pin status Mode 3/4 (1) Default: input without pull-up. Default: input without pull-up. Default: Input without pull-up. Pull-up is enabled if bit SDO_PU_EN = 1 in reg 02h. Pull-up is enabled if bit SDO_PU_EN = 1 in reg 02h. Pull-up is enabled if bit SDO_PU_EN = 1 in reg 02h. Default: input without pull-up. Default: input without pull-up. Default: input without pull-up. Pull-up is enabled if bit SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up). Pull-up is enabled if bit SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up). Pull-up is enabled if bit SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up). Default: input without pull-up. Default: input without pull-up. Default: input without pull-up. Pull-up is enabled if bit SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up). Pull-up is enabled if bit SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up). Pull-up is enabled if bit SHUB_PU_EN = 1 in reg 14h in sensor hub registers (see Note to enable pull-up) Default: input with pull-down(2) Default: input with pull-down(2) Default: input with pull-down(2) Default: output forced to ground Default: output forced to ground Default: output forced to ground Default: input with pull-up. Default: input with pull-up. Pull-up is disabled if bit OIS_PU_DIS = 1 in reg 02h. Pull-up is disabled if bit OIS_PU_DIS = 1 in reg 02h. Default: input without pull-up (regardless of the value of bit OIS_PU_DIS in reg 02h.) Default: input with pull-up. Default: input with pull-up. Default: input without pull-up. Pull-up is disabled if bit OIS_PU_DIS = 1 in reg 02h. Pull-up is disabled if bit OIS_PU_DIS = 1 in reg 02h. Pull-up is enabled if bit SIM_OIS = 1 (Aux_SPI 3-wire) in reg 70h and bit OIS_PU_DIS = 0 in reg 02h. Default: input with pull-up. Default: input with pull-up. Default: input with pull-up. Pull-up is disabled if bit I2C_disable = 1 in reg 13h and I3C_disable = 1 in reg 18h. Pull-up is disabled if bit I2C_disable = 1 in reg 13h and I3C_disable = 1 in reg 18h. Pull-up is disabled if bit I2C_disable = 1 in reg 13h and I3C_disable = 1 in reg 18h. LSM6DSRX page 39/171 3 I²C serial clock master (MSCL) Pin status Mode 1 DS13007 - Rev 3 pin# Name Mode 1 function Mode 2 function Mode 3 / Mode 4 function Pin status Mode 1 Pin status Mode 2 Pin status Mode 3/4 (1) 13 SCL I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC) I²C/MIPI I3CSM serial clock (SCL) / SPI serial port clock (SPC) Default: input without pull-up Default: input without pull-up Default: input without pull-up SDA I²C/MIPI I3CSM serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO) I²C/MIPI I3CSM serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO) I²C/MIPI I3CSM serial data (SDA) / SPI serial data input (SDI) / 3-wire interface serial data output (SDO) Default: input without pull-up Default: input without pull-up Default:input without pull-up 14 1. Mode 3 is enabled when the OIS_EN_SPI2 bit in the CTRL1_OIS (70h) register is set to 1. Mode 4 is enabled when both the OIS_EN_SPI2 bit and the Mode4_EN bit in the CTRL1_OIS (70h) register are set to 1. 2. INT1 must be set to '0' or left unconnected during power-on if the I²C/SPI interfaces are used. Internal pull-up value is from 30 kΩ to 50 kΩ, depending on Vdd_IO. Note: The procedure to enable the pull-up on pins 2 and 3 is as follows: 1. From the primary I²C/I3C/SPI interface : write 40h in register at address 01h (enable access to the sensor hub registers) 2. From the primary I²C/I3C/SPI interface : write 08h in register at address 14h (enable the pull-up on pins 2 and 3) 3. From the primary I²C/I3C/SPI interface : write 00h in register at address 01h (disable access to the sensor hub registers) LSM6DSRX page 40/171 LSM6DSRX Register mapping 8 Register mapping The table given below provides a list of the 8/16-bit registers embedded in the device and the corresponding addresses. Table 20. Registers address map Name DS13007 - Rev 3 Type Register address Hex Binary Default FUNC_CFG_ACCESS RW 01 00000001 00000000 PIN_CTRL 00000010 00111111 Comment RW 02 RESERVED - 03 S4S_TPH_L RW 04 00000100 00000000 S4S_TPH_H RW 05 00000101 00000000 S4S_RR RW 06 00000110 00000000 FIFO_CTRL1 RW 07 00000111 00000000 FIFO_CTRL2 RW 08 00001000 00000000 FIFO_CTRL3 RW 09 00001001 00000000 FIFO_CTRL4 RW 0A 00001010 00000000 COUNTER_BDR_REG1 RW 0B 00001011 00000000 COUNTER_BDR_REG2 RW 0C 00001100 00000000 INT1_CTRL RW 0D 00001101 00000000 INT2_CTRL RW 0E 00001110 00000000 WHO_AM_I R 0F 00001111 01101011 R (SPI2) CTRL1_XL RW 10 00010000 00000000 R (SPI2) CTRL2_G RW 11 00010001 00000000 R (SPI2) CTRL3_C RW 12 00010010 00000100 R (SPI2) CTRL4_C RW 13 00010011 00000000 R (SPI2) CTRL5_C RW 14 00010100 00000000 R (SPI2) CTRL6_C RW 15 00010101 00000000 R (SPI2) CTRL7_G RW 16 00010110 00000000 R (SPI2) CTRL8_XL RW 17 00010111 00000000 R (SPI2) CTRL9_XL RW 18 00011000 11100000 R (SPI2) CTRL10_C RW 19 00011001 00000000 R (SPI2) ALL_INT_SRC R 1A 00011010 output WAKE_UP_SRC R 1B 00011011 output TAP_SRC R 1C 00011100 output D6D_SRC R 1D 00011101 output STATUS_REG(1)/STATUS_SPIAux(2) R 1E 00011110 output RESERVED - 1F OUT_TEMP_L R 20 00100000 output OUT_TEMP_H R 21 00100001 output page 41/171 LSM6DSRX Register mapping Name DS13007 - Rev 3 Type Register address Hex Binary Default Comment OUTX_L_G R 22 00100010 output OUTX_H_G R 23 00100011 output OUTY_L_G R 24 00100100 output OUTY_H_G R 25 00100101 output OUTZ_L_G R 26 00100110 output OUTZ_H_G R 27 00100111 output OUTX_L_A R 28 00101000 output OUTX_H_A R 29 00101001 output OUTY_L_A R 2A 00101010 output OUTY_H_A R 2B 00101011 output OUTZ_L_A R 2C 00101100 output OUTZ_H_A R 2D 00101101 output RESERVED - 2E-34 EMB_FUNC_STATUS_MAINPAGE R 35 00110101 output FSM_STATUS_A_MAINPAGE R 36 00110110 output FSM_STATUS_B_MAINPAGE R 37 00110111 output MLC_STATUS_MAINPAGE R 38 00111000 output STATUS_MASTER_MAINPAGE R 39 00111001 output FIFO_STATUS1 R 3A 00111010 output FIFO_STATUS2 R 3B 00111011 output RESERVED - 3C-3F TIMESTAMP0 R 40 01000000 output R (SPI2) TIMESTAMP1 R 41 01000001 output R (SPI2) TIMESTAMP2 R 42 01000010 output R (SPI2) TIMESTAMP3 R 43 01000011 output R (SPI2) RESERVED - 44-55 TAP_CFG0 RW 56 01010110 00000000 TAP_CFG1 RW 57 01010111 00000000 TAP_CFG2 RW 58 01011000 00000000 TAP_THS_6D RW 59 01011001 00000000 INT_DUR2 RW 5A 01011010 00000000 WAKE_UP_THS RW 5B 01011011 00000000 WAKE_UP_DUR RW 5C 01011100 00000000 FREE_FALL RW 5D 01011101 00000000 MD1_CFG RW 5E 01011110 00000000 MD2_CFG RW 5F 01011111 00000000 S4S_ST_CMD_CODE RW 60 01100000 00000000 S4S_DT_REG RW 61 01100001 00000000 I3C_BUS_AVB RW 62 01100010 00000000 page 42/171 LSM6DSRX Register mapping Name Type Register address Default Hex Binary 01100011 output Comment INTERNAL_FREQ_FINE R 63 RESERVED - 64-6E INT_OIS R 6F 01101111 00000000 RW (SPI2) CTRL1_OIS R 70 01110000 00000000 RW (SPI2) CTRL2_OIS R 71 01110001 00000000 RW (SPI2) CTRL3_OIS R 72 01110010 00000000 RW (SPI2) X_OFS_USR RW 73 01110011 00000000 Y_OFS_USR RW 74 01110100 00000000 Z_OFS_USR RW 75 01110101 00000000 RESERVED - 76-77 FIFO_DATA_OUT_TAG R 78 01111000 output FIFO_DATA_OUT_X_L R 79 01111001 output FIFO_DATA_OUT_X_H R 7A 01111010 output FIFO_DATA_OUT_Y_L R 7B 01111011 output FIFO_DATA_OUT_Y_H R 7C 01111100 output FIFO_DATA_OUT_Z_L R 7D 01111101 output FIFO_DATA_OUT_Z_H R 7E 01111110 output 1. This register status is read using the primary interface for user interface data. 2. This register status is read using the auxiliary SPI for OIS data. DS13007 - Rev 3 page 43/171 LSM6DSRX Register description 9 Register description The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, made up of 7 bits, are used to identify them and to write the data through the serial interface. 9.1 FUNC_CFG_ACCESS (01h) Enable embedded functions register (r/w) Table 21. FUNC_CFG_ACCESS register FUNC_CFG_ ACCESS SHUB_REG_ ACCESS 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 22. FUNC_CFG_ACCESS register description FUNC_CFG_ACCESS Enable access to the embedded functions configuration registers. Default value: 0(1) SHUB_REG_ACCESS Enable access to the sensor hub (I²C master) registers. Default value: 0(2) 1. Details concerning the embedded functions configuration registers are available in Section 10 Embedded functions register mapping and Section 11 Embedded functions register description. 2. Details concerning the sensor hub registers are available in Section 14 Sensor hub register mapping and Section 15 Sensor hub register description. 9.2 PIN_CTRL (02h) SDO, OCS_AUX, SDO_AUX pins pull-up enable/disable register (r/w) Table 23. PIN_CTRL register OIS_ PU_DIS SDO_ PU_EN 1(1) 1(1) 1(1) 1(1) 1(1) 1(1) 1. This bit must be set to '1' for the correct operation of the device. Table 24. PIN_CTRL register description Disable pull-up on both OCS_Aux and SDO_Aux pins. Default value: 0 OIS_PU_DIS (0: OCS_Aux and SDO_Aux pins with pull-up; 1: OCS_Aux and SDO_Aux pins pull-up disconnected) SDO_PU_EN DS13007 - Rev 3 Enable pull-up on SDO pin. Default value: 0 (0: SDO pin pull-up disconnected (default); 1: SDO pin with pull-up) page 44/171 LSM6DSRX S4S_TPH_L (04h) 9.3 S4S_TPH_L (04h) Sensor synchronization time frame register (r/w) Table 25. S4S_TPH_L register TPH_H_ SEL TPH_L_6 TPH_L_5 TPH_L_4 TPH_L_3 TPH_L_2 TPH_L_1 TPH_L_0 Table 26. S4S_TPH_L register description TPH_H_SEL TPH_L_[6:0] Chooses if the TPH formula must be taken into account (see equation below). S4S timeframe expressed in number of samples as described in the equation below. If TPH_H_SEL=0 and TPH_L_[6:0] = d0, S4S is disabled. When TPH_H_SEL = 0: TPH [#Samples] = 2 x TPHL When TPH_H_SEL = 1: TPH [#Samples] = 2 x (TPH_L + 256 x TPH_H) 9.4 S4S_TPH_H (05h) Sensor synchronization time frame register (r/w) Table 27. S4S_TPH_H register TPH_H_7 TPH_H_6 TPH_H_5 TPH_H_4 TPH_H_3 TPH_H_2 TPH_H_1 TPH_H_0 Table 28. S4S_TPH_H register description TPH_H_[7:0] 9.5 S4S time frame expressed in number of samples. Only if the TPH_H_SEL bit in S4S_TPH_L (04h) is high, is the value of this register taken into account as described in the equation in S4S_TPH_L (04h) S4S_RR (06h) Sensor synchronization resolution ratio register (r/w) Table 29. S4S_RR register 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) RR_1 RR_0 1. This bit must be set to '0' for the correct operation of the device. Table 30. S4S_RR register description (00: S4S, DT resolution 211; RR_[1:0] 01: S4S, DT resolution 212; 10: S4S, DT resolution 213; 11: S4S, DT resolution 214) DS13007 - Rev 3 page 45/171 LSM6DSRX FIFO_CTRL1 (07h) 9.6 FIFO_CTRL1 (07h) FIFO control register 1 (r/w) Table 31. FIFO_CTRL1 register WTM7 WTM6 WTM5 WTM4 WTM3 WTM2 WTM1 WTM0 Table 32. FIFO_CTRL1 register description FIFO watermark threshold, in conjunction with WTM8 in FIFO_CTRL2 (08h). WTM[7:0] 1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO Watermark flag rises when the number of bytes written in the FIFO is greater than or equal to the threshold level. 9.7 FIFO_CTRL2 (08h) FIFO control register 2 (r/w) Table 33. FIFO_CTRL2 register STOP_ON _WTM FIFO_ COMPR_RT_ EN 0(1) ODRCHG _EN 0(1) UNCOPTR _RATE_1 UNCOPTR _RATE_0 WTM8 1. This bit must be set to '0' for the correct operation of the device. Table 34. FIFO_CTRL2 register Sensing chain FIFO stop values memorization at threshold level STOP_ON_WTM (0: FIFO depth is not limited (default); 1: FIFO depth is limited to the threshold level, defined in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h) FIFO_COMPR_RT_EN(1) Enables/Disables compression algorithm runtime ODRCHG_EN Enables ODR CHANGE virtual sensor to be batched in FIFO This field configures the compression algorithm to write non-compressed data at each rate. (0: Non-compressed data writing is not forced; UNCOPTR_RATE_[1:0] 1: Non-compressed data every 8 batch data rate; 2: Non-compressed data every 16 batch data rate; 3: Non-compressed data every 32 batch data rate) FIFO watermark threshold, in conjunction with WTM[7:0] in FIFO_CTRL1 (07h). WTM8 1 LSB = 1 sensor (6 bytes) + TAG (1 byte) written in FIFO Watermark flag rises when the number of bytes written in FIFO is greater than or equal to the threshold level. 1. This bit is effective if the FIFO_COMPR_EN bit of EMB_FUNC_EN_B (05h) is set to 1. DS13007 - Rev 3 page 46/171 LSM6DSRX FIFO_CTRL3 (09h) 9.8 FIFO_CTRL3 (09h) FIFO control register 3 (r/w) Table 35. FIFO_CTRL3 register BDR_GY_3 BDR_GY_2 BDR_GY_1 BDR_GY_0 BDR_XL_3 BDR_XL_2 BDR_XL_1 BDR_XL_0 Table 36. FIFO_CTRL3 register description Selects Batch Data Rate (write frequency in FIFO) for gyroscope data. (0000: Gyro not batched in FIFO (default); 0001: 12.5 Hz; 0010: 26 Hz; 0011: 52 Hz; 0100: 104 Hz; BDR_GY_[3:0] 0101: 208 Hz; 0110: 417 Hz; 0111: 833 Hz; 1000: 1667 Hz; 1001: 3333 Hz; 1010: 6667 Hz; 1011: 6.5 Hz; 1100-1111: not allowed) Selects Batch Data Rate (write frequency in FIFO) for accelerometer data. (0000: Accelerometer not batched in FIFO (default); 0001: 12.5 Hz; 0010: 26 Hz; 0011: 52 Hz; 0100: 104 Hz; BDR_XL_[3:0] 0101: 208 Hz; 0110: 417 Hz; 0111: 833 Hz; 1000: 1667 Hz; 1001: 3333 Hz; 1010: 6667 Hz; 1011: 1.6 Hz; 1100-1111: not allowed) DS13007 - Rev 3 page 47/171 LSM6DSRX FIFO_CTRL4 (0Ah) 9.9 FIFO_CTRL4 (0Ah) FIFO control register 4 (r/w) Table 37. FIFO_CTRL4 register DEC_TS_ BATCH_1 DEC_TS_ BATCH_0 ODR_T_ BATCH_1 ODR_T_ BATCH_0 0(1) FIFO_ MODE2 FIFO_ MODE1 FIFO_ MODE0 1. This bit must be set to '0' for the correct operation of the device. Table 38. FIFO_CTRL4 register description Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder. (00: Timestamp not batched in FIFO (default); DEC_TS_BATCH_[1:0] 01: Decimation 1: max(BDR_XL[Hz],BDR_GY[Hz]) [Hz]; 10: Decimation 8: max(BDR_XL[Hz],BDR_GY[Hz])/8 [Hz]; 11: Decimation 32: max(BDR_XL[Hz],BDR_GY[Hz])/32 [Hz]) Selects batch data rate (write frequency in FIFO) for temperature data (00: Temperature not batched in FIFO (default); ODR_T_BATCH_[1:0] 01: 1.6 Hz; 10: 12.5 Hz; 11: 52 Hz) FIFO mode selection (000: Bypass mode: FIFO disabled; 001: FIFO mode: stops collecting data when FIFO is full; 010: Reserved; FIFO_MODE[2:0] 011: Continuous-to-FIFO mode: Continuous mode until trigger is deasserted, then FIFO mode; 100: Bypass-to-Continuous mode: Bypass mode until trigger is deasserted, then Continuous mode; 101: Reserved; 110: Continuous mode: if the FIFO is full, the new sample overwrites the older one; 111: Bypass-to-FIFO mode: Bypass mode until trigger is deasserted, then FIFO mode.) DS13007 - Rev 3 page 48/171 LSM6DSRX COUNTER_BDR_REG1 (0Bh) 9.10 COUNTER_BDR_REG1 (0Bh) Counter batch data rate register 1 (r/w) Table 39. COUNTER_BDR_REG1 register dataready_ pulsed RST_ COUNTER_BDR TRIG_ COUNTER_BDR 0(1) 0(1) CNT_BDR_ TH_10 CNT_BDR_ TH_9 CNT_BDR_ TH_8 1. This bit must be set to '0' for the correct operation of the device. Table 40. COUNTER_BDR_REG1 register description Enables pulsed data-ready mode dataready_pulsed (0: Data-ready latched mode (returns to 0 only after an interface reading) (default); 1: Data-ready pulsed mode (the data ready pulses are 75 µs long) RST_COUNTER_BDR Resets the internal counter of batch events for a single sensor. This bit is automatically reset to zero if it was set to ‘1’. Selects the trigger for the internal counter of batch events between XL and gyro. TRIG_COUNTER_BDR (0: XL batch event; 1: GYRO batch event) CNT_BDR_TH_[10:8] 9.11 In conjunction with CNT_BDR_TH_[7:0] in COUNTER_BDR_REG2 (0Ch), sets the threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. COUNTER_BDR_REG2 (0Ch) Counter batch data rate register 2 (r/w) Table 41. COUNTER_BDR_REG2 register CNT_BDR_ TH_7 CNT_BDR_ TH_6 CNT_BDR_ TH_5 CNT_BDR_ TH_4 CNT_BDR_ TH_3 CNT_BDR_ TH_2 CNT_BDR_ TH_1 CNT_BDR_ TH_0 Table 42. COUNTER_BDR_REG2 register description In conjunction with CNT_BDR_TH_[10:8] in COUNTER_BDR_REG1 (0Bh), sets the threshold for the CNT_BDR_TH_[7:0] internal counter of batch events. When this counter reaches the threshold, the counter is reset and the COUNTER_BDR_IA flag in FIFO_STATUS2 (3Bh) is set to ‘1’. DS13007 - Rev 3 page 49/171 LSM6DSRX INT1_CTRL (0Dh) 9.12 INT1_CTRL (0Dh) INT1 pin control register (r/w) Each bit in this register enables a signal to be carried over INT1 when the MIPI I3CSM dynamic address is not assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI (In-Band Interrupt) when the MIPI I3CSM interface is used.. The output of the pad will be the OR combination of the signals selected here and in register MD1_CFG (5Eh). Table 43. INT1_CTRL register DEN_DRDY _flag INT1_ CNT_BDR INT1_ FIFO_FULL INT1_ FIFO_OVR INT1_ FIFO_TH INT1_ BOOT INT1_ DRDY_G INT1_ DRDY_XL Table 44. INT1_CTRL register description DEN_DRDY_flag Sends DEN_DRDY (DEN stamped on Sensor Data flag) to INT1 pin. INT1_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT1. INT1_FIFO_FULL INT1_FIFO_OVR INT1_FIFO_TH INT1_BOOT INT1_DRDY_G INT1_DRDY_XL DS13007 - Rev 3 Enables FIFO full flag interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM interface is used. Enables FIFO overrun interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM interface is used. Enables FIFO threshold interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM interface is used. Enables boot status on INT1 pin. Enables gyroscope data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM interface is used. Enables accelerometer data-ready interrupt on INT1 pin. It can be also used to trigger an IBI when the MIPI I3CSM interface is used. page 50/171 LSM6DSRX INT2_CTRL (0Eh) 9.13 INT2_CTRL (0Eh) INT2 pin control register (r/w). Each bit in this register enables a signal to be carried over INT2 when the MIPI I3CSM dynamic address in not assigned (I²C or SPI is used). Some bits can be also used to trigger an IBI when the MIPI I3CSM interface is used.. The output of the pad will be the OR combination of the signals selected here and in register MD2_CFG (5Fh). Table 45. INT2_CTRL register 0(1) INT2_ CNT_BDR INT2_ FIFO_FULL INT2_ FIFO_OVR INT2_ FIFO_TH INT2_ DRDY_TEMP INT2_ DRDY_G INT2_ DRDY_XL 1. This bit must be set to '0' for the correct operation of the device. Table 46. INT2_CTRL register description INT2_CNT_BDR Enables COUNTER_BDR_IA interrupt on INT2 pin. INT2_FIFO_FULL Enables FIFO full flag interrupt on INT2 pin. INT2_FIFO_OVR Enables FIFO overrun interrupt on INT2 pin. INT_FIFO_TH Enables FIFO threshold interrupt on INT2 pin. Enables temperature sensor data-ready interrupt on INT2 pin. INT2_DRDY_TEMP It can be also used to trigger an IBI when the MIPI I3CSM interface is used and INT2_ON_INT1 = ‘1’ in CTRL4_C (13h). 9.14 INT2_DRDY_G Enables gyroscope data-ready interrupt on INT2 pin. INT2_DRDY_XL Enables accelerometer data-ready interrupt on INT2 pin. WHO_AM_I (0Fh) WHO_AM_I register (r). This is a read-only register. Its value is fixed at 6Bh. Table 47. WhoAmI register 0 DS13007 - Rev 3 1 1 0 1 0 1 1 page 51/171 LSM6DSRX CTRL1_XL (10h) 9.15 CTRL1_XL (10h) Accelerometer control register 1 (r/w) Table 48. CTRL1_XL register ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL LPF2_XL_EN 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 49. CTRL1_XL register description ODR_XL[3:0] Accelerometer ODR selection (see Table 50). Accelerometer full-scale selection. Default value: 00 FS[1:0]_XL (00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g) Accelerometer high-resolution selection LPF2_XL_EN (0: output from first stage digital filtering selected (default); 1: output from LPF2 second filtering stage selected) Table 50. Accelerometer ODR selection ODR_XL3 ODR_XL2 ODR_XL1 ODR_XL0 DS13007 - Rev 3 ODR selection [Hz] when ODR selection [Hz] when XL_HM_MODE = 1 in CTRL6_C (15h) XL_HM_MODE = 0 in CTRL6_C (15h) 0 0 0 0 Power-down Power-down 1 0 1 1 1.6 Hz (low power only) N.A. 0 0 0 1 12.5 Hz (low power) 12.5 Hz (high performance) 0 0 1 0 26 Hz (low power) 26 Hz (high performance) 0 0 1 1 52 Hz (low power) 52 Hz (high performance) 0 1 0 0 104 Hz (normal mode) 104 Hz (high performance) 0 1 0 1 208 Hz (normal mode) 208 Hz (high performance) 0 1 1 0 416 Hz (high performance) 416 Hz (high performance) 0 1 1 1 833 Hz (high performance) 833 Hz (high performance) 1 0 0 0 1.66 kHz (high performance) 1.66 kHz (high performance) 1 0 0 1 3.33 kHz (high performance) 3.33 kHz (high performance) 1 0 1 0 6.66 kHz (high performance) 6.66 kHz (high performance) 1 1 x x Not allowed Not allowed page 52/171 LSM6DSRX CTRL2_G (11h) 9.16 CTRL2_G (11h) Gyroscope control register 2 (r/w) Table 51. CTRL2_G register ODR_G3 ODR_G2 ODR_G1 ODR_G0 FS1_G FS0_G FS_125 FS_4000 Table 52. CTRL2_G register description Gyroscope output data rate selection. Default value: 0000 ODR_G[3:0] (Refer to Table 53) Gyroscope chain full-scale selection (00: ±250 dps; FS[1:0]_G 01: ±500 dps; 10: ±1000 dps; 11: ±2000 dps) Selects gyro chain full-scale ±125 dps FS_125 (0: FS selected through bits FS[1:0]_G; 1: FS set to ±125 dps) Selects gyro chain full-scale ±4000 dps FS_4000(1) (0: FS selected through bits FS[1:0]_G or FS_125; 1: FS set to ±4000 dps) 1. This bit has to be set to 0 when the OIS chain is ON (OIS_EN_SPI2 bit =1 in CTRL1_OIS (70h)) Table 53. Gyroscope ODR configuration setting ODR_G3 ODR_G2 ODR_G1 ODR_G0 DS13007 - Rev 3 ODR selection [Hz] when ODR selection [Hz] when G_HM_MODE = 1 in CTRL7_G (16h) G_HM_MODE = 0 in CTRL7_G (16h) 0 0 0 0 Power-down Power-down 0 0 0 1 12.5 Hz (low power) 12.5 Hz (high performance) 0 0 1 0 26 Hz (low power) 26 Hz (high performance) 0 0 1 1 52 Hz (low power) 52 Hz (high performance) 0 1 0 0 104 Hz (normal mode) 104 Hz (high performance) 0 1 0 1 208 Hz (normal mode) 208 Hz (high performance) 0 1 1 0 416 Hz (high performance) 416 Hz (high performance) 0 1 1 1 833 Hz (high performance) 833 Hz (high performance) 1 0 0 0 1.66 kHz (high performance) 1.66 kHz (high performance) 1 0 0 1 3.33 kHz (high performance) 3.33 kHz (high performance) 1 0 1 0 6.66 kHz (high performance) 6.66 kHz (high performance) 1 0 1 1 Not available Not available page 53/171 LSM6DSRX CTRL3_C (12h) 9.17 CTRL3_C (12h) Control register 3 (r/w) Table 54. CTRL3_C register BOOT BDU H_LACTIVE PP_OD SIM IF_INC 0(1) SW_RESET 1. This bit must be set to '0' for the correct operation of the device. Table 55. CTRL3_C register description Reboots memory content. Default value: 0 BOOT (0: normal mode; 1: reboot memory content) Note: the accelerometer must be ON. This bit is automatically cleared. Block Data Update. Default value: 0 BDU (0: continuous update; 1: output registers are not updated until MSB and LSB have been read) H_LACTIVE PP_OD Interrupt activation level. Default value: 0 (0: interrupt output pins active high; 1: interrupt output pins active low Push-pull/open-drain selection on INT1 and INT2 pins. This bit must be set to '0' when H_LACTIVE is set to '1'. Default value: 0 (0: push-pull mode; 1: open-drain mode) SIM IF_INC SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface) Register address automatically incremented during a multiple byte access with a serial interface (I²C or SPI). Default value: 1 (0: disabled; 1: enabled) Software reset. Default value: 0 SW_RESET (0: normal mode; 1: reset device) This bit is automatically cleared. DS13007 - Rev 3 page 54/171 LSM6DSRX CTRL4_C (13h) 9.18 CTRL4_C (13h) Control register 4 (r/w) Table 56. CTRL4_C register 0(1) SLEEP_G INT2_on _INT1 0(1) DRDY_MASK I2C_disable LPF1_SEL_G 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 57. CTRL4_C register description SLEEP_G Enables gyroscope Sleep mode. Default value:0 (0: disabled; 1: enabled) All interrupt signals available on INT1 pin enable. Default value: 0 INT2_on_INT1 (0: interrupt signals divided between INT1 and INT2 pins; 1: all interrupt signals in logic or on INT1 pin) Enables data available DRDY_MASK (0: disabled; 1: mask DRDY on pin (both XL & Gyro) until filter settling ends (XL and Gyro independently masked). I2C_disable LPF1_SEL_G DS13007 - Rev 3 Disables I²C interface. Default value: 0 (0: SPI, I²C and MIPI I3CSM interfaces enabled (default); 1: I²C interface disabled) Enables gyroscope digital LPF1; the bandwidth can be selected through FTYPE[2:0] in CTRL6_C (15h). (0: disabled; 1: enabled) page 55/171 LSM6DSRX CTRL5_C (14h) 9.19 CTRL5_C (14h) Control register 5 (r/w) Table 58. CTRL5_C register 0(1) ROUNDING1 ROUNDING0 0(1) ST1_G ST0_G ST1_XL ST0_XL 1. This bit must be set to '0' for the correct operation of the device. Table 59. CTRL5_C register description Circular burst-mode (rounding) read of the output registers. Default value: 00 (00: no rounding; ROUNDING[1:0] 01: accelerometer only; 10: gyroscope only; 11: gyroscope + accelerometer) Angular rate sensor self-test enable. Default value: 00 ST[1:0]_G (00: Self-test disabled; Other: refer to Table 60) Linear acceleration sensor self-test enable. Default value: 00 ST[1:0]_XL (00: Self-test disabled; Other: refer to Table 61) Table 60. Angular rate sensor self-test mode selection ST1_G ST0_G 0 0 Normal mode 0 1 Positive sign self-test 1 0 Not allowed 1 1 Negative sign self-test Self-test mode Table 61. Linear acceleration sensor self-test mode selection DS13007 - Rev 3 ST1_XL ST0_XL 0 0 Normal mode 0 1 Positive sign self-test 1 0 Negative sign self-test 1 1 Not allowed Self-test mode page 56/171 LSM6DSRX CTRL6_C (15h) 9.20 CTRL6_C (15h) Control register 6 (r/w) Table 62. CTRL6_C register TRIG_EN LVL1_EN LVL2_EN XL_HM_ MODE USR_ OFF_W FTYPE_2 FTYPE_1 FTYPE_0 Table 63. CTRL6_C register description TRIG_EN Enables DEN data edge-sensitive trigger mode. Refer to Table 64. LVL1_EN Enables DEN data level-sensitive trigger mode. Refer to Table 64. LVL2_EN Enables DEN level-sensitive latched mode. Refer to Table 64. Disables high-performance operating mode for accelerometer. Default value: 0 XL_HM_MODE (0: high-performance operating mode enabled; 1: high-performance operating mode disabled) Weight of XL user offset bits of registers X_OFS_USR (73h), Y_OFS_USR (74h), Z_OFS_USR (75h) USR_OFF_W (0 = 2-10 g/LSB; 1 = 2-6 g/LSB) FTYPE[2:0] Gyroscope low-pass filter (LPF1) bandwidth selection. Table 65 shows the selectable bandwidth values. Table 64. Trigger mode selection TRIG_EN, LVL1_EN, LVL2_EN Trigger mode 100 Edge-sensitive trigger mode is selected 010 Level-sensitive trigger mode is selected 011 Level-sensitive latched mode is selected 110 Level-sensitive FIFO enable mode is selected Table 65. Gyroscope LPF1 bandwidth selection FTYPE 12.5 Hz 26 Hz 52 Hz 104 Hz 208 Hz 416 Hz 833 Hz 1.67 kHz 3.33 kHz 6.67 kHz 000 4.3 8.3 16.7 33 67 133 222 274 292 297 001 4.3 8.3 16.7 33 67 128 186 212 220 223 010 4.3 8.3 16.7 33 67 112 140 150 153 154 011 4.3 8.3 16.7 33 67 134 260 390 451 470 100 4.3 8.3 16.7 34 62 86 96 90 NA 101 4.3 8.3 16.9 31 43 48 49 50 NA 110 4.3 8.3 13.4 19 23 24.6 25 25 NA 111 4.3 8.3 9.8 11.6 12.2 12.4 12.6 12.6 NA [2:0] DS13007 - Rev 3 page 57/171 LSM6DSRX CTRL7_G (16h) 9.21 CTRL7_G (16h) Control register 7 (r/w) Table 66. CTRL7_G register G_HM_ MODE HP_EN_G HPM1_G HPM0_G 0(1) OIS_ON_EN USR_OFF_ ON_OUT OIS_ON 1. This bit must be set to '0' for the correct operation of the device. Disables high-performance operating mode for gyroscope. Default: 0 G_HM_MODE (0: high-performance operating mode enabled; 1: high-performance operating mode disabled) HP_EN_G Enables gyroscope digital high-pass filter. The filter is enabled only if the gyro is in HP mode. Default value: 0 (0: HPF disabled; 1: HPF enabled) Gyroscope digital HP filter cutoff selection. Default: 00 (00 = 16 mHz; HPM_G[1:0] 01 = 65 mHz; 10 = 260 mHz; 11 = 1.04 Hz) Selects how to enable and disable the OIS chain, after first configuration and enabling through SPI2. OIS_ON_EN(1) (0: OIS chain is enabled/disabled with SPI2 interface; 1: OIS chain is enabled/disabled with primary interface) Enables accelerometer user offset correction block; it's valid for the low-pass path - see Figure 18. Accelerometer composite filter. Default value: 0 USR_OFF_ON_OUT (0: accelerometer user offset correction block bypassed; 1: accelerometer user offset correction block enabled) OIS_ON Enables/disables the OIS chain from primary interface when the OIS_ON_EN bit is '1'. (0: OIS disabled; 1: OIS enabled) 1. First, enabling OIS and OIS configurations must be done through SPI2, with OIS_ON_EN and OIS_ON set to '0'. DS13007 - Rev 3 page 58/171 LSM6DSRX CTRL8_XL (17h) 9.22 CTRL8_XL (17h) Control register 8 (r/w) Table 67. CTRL8_XL register HPCF_XL_2 HPCF_XL_1 HPCF_XL_0 HP_REF_ MODE_XL FASTSETTL_ MODE_XL HP_SLOPE_ XL_EN LOW_PASS_ ON_6D 0(1) 1. This bit must be set to '0' for the correct operation of the device. HPCF_XL_[2:0] Accelerometer LPF2 and HP filter configuration and cutoff setting. Refer to Table 68. HP_REF_MODE_XL Enables accelerometer high-pass filter reference mode (valid for high-pass path HP_SLOPE_XL_EN bit must be ‘1’). Default value: 0 (0: disabled, 1: enabled(1)) Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the second samples after FASTSETTL_MODE_XL writing this bit. Active only during device exit from power- down mode. Default value: 0 (0: disabled, 1: enabled) HP_SLOPE_XL_EN Accelerometer slope filter / high-pass filter selection. Refer to Figure 26. LPF2 on 6D function selection. Refer to Figure 26. Default value: 0 LOW_PASS_ON_6D (0: ODR/2 low-pass filtered data sent to 6D interrupt function; 1: LPF2 output data sent to 6D interrupt function) 1. When enabled, the first output data have to be discarded. Table 68. Accelerometer bandwidth configurations Filter type Low pass High pass HP_SLOPE_XL_EN 0 1 LPF2_XL_EN HPCF_XL_[2:0] Bandwidth(1) 0 - ODR/2 000 ODR/4 001 ODR/10 010 ODR/20 011 ODR/45 100 ODR/100 101 ODR/200 110 ODR/400 111 ODR/800 000 SLOPE (ODR/4) 001 ODR/10 010 ODR/20 011 ODR/45 100 ODR/100 101 ODR/200 110 ODR/400 111 ODR/800 1 - 1. Typical value for ODR up to 833 Hz. DS13007 - Rev 3 page 59/171 LSM6DSRX CTRL8_XL (17h) Figure 26. Accelerometer block diagram LOW_PASS_ON_6D Free-fall 0 Advanced functions 1 LPF2_XL_EN USR_OFF_ON_OUT HP_SLOPE_XL_EN 0 0 Digital LP Filter 1 LPF1 output (1) 0 USER OFFSET LPF2 1 USR_OFF_W OFS_USR[7:0] FIFO HPCF_XL[2:0] Digital HP Filter 1 1 0 0 Wake-up Activity / Inactivity SPI / I 2C / MIPI I3C SM USR_OFF_ON_WU SLOPE_FDS 001 010 … 111 1 HPCF_XL[2:0] SLOPE FILTER 6D / 4D 000 HPCF_XL[2:0] S/D Tap 1. DS13007 - Rev 3 The cutoff value of the LPF1 output is ODR/2 when the accelerometer is in high-performance mode and ODR up to 833 Hz. This value is equal to 780 Hz when the accelerometer is in low-power or normal mode. page 60/171 LSM6DSRX CTRL9_XL (18h) 9.23 CTRL9_XL (18h) Control register 9 (r/w) Table 69. CTRL9_XL register DEN_X DEN_Y DEN_Z DEN_XL_G DEN_XL_EN DEN_LH I3C_disable 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 70. CTRL9_XL register description DEN_X DEN_Y DEN_Z DEN value stored in LSB of X-axis. Default value: 1 (0: DEN not stored in X-axis LSB; 1: DEN stored in X-axis LSB) DEN value stored in LSB of Y-axis. Default value: 1 (0: DEN not stored in Y-axis LSB; 1: DEN stored in Y-axis LSB) DEN value stored in LSB of Z-axis. Default value: 1 (0: DEN not stored in Z-axis LSB; 1: DEN stored in Z-axis LSB) DEN stamping sensor selection. Default value: 0 DEN_XL_G (0: DEN pin info stamped in the gyroscope axis selected by bits [7:5]; 1: DEN pin info stamped in the accelerometer axis selected by bits [7:5]) DEN_XL_EN DEN_LH Extends DEN functionality to accelerometer sensor. Default value: 0 (0: disabled; 1: enabled) DEN active level configuration. Default value: 0 (0: active low; 1: active high) Disables MIPI I3CSM communication protocol(1) I3C_disable (0: SPI, I²C, MIPI I3CSM interfaces enabled (default); 1: MIPI I3CSM interface disabled) 1. It is recommended to set this bit to '1' during the initial device configuration phase, when the I3C interface is not used. 9.24 CTRL10_C (19h) Control register 10 (r/w) Table 71. CTRL10_C register 0(1) 0(1) TIMESTAMP _EN 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 72. CTRL10_C register description Enables timestamp counter. Default value: 0 TIMESTAMP_EN (0: disabled; 1: enabled) The counter is readable in TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h). DS13007 - Rev 3 page 61/171 LSM6DSRX ALL_INT_SRC (1A) 9.25 ALL_INT_SRC (1A) Source register for all interrupts (r) Table 73. ALL_INT_SRC register TIMESTAMP _ENDCOUNT 0 SLEEP_ CHANGE_IA D6D_IA DOUBLE_ TAP SINGLE_ TAP WU_IA FF_IA Table 74. ALL_INT_SRC register description TIMESTAMP_ENDCOUNT Alerts timestamp overflow within 6.4 ms SLEEP_CHANGE_IA D6D_IA DOUBLE_TAP SINGLE_TAP WU_IA FF_IA DS13007 - Rev 3 Detects change event in activity/inactivity status. Default value: 0 (0: change status not detected; 1: change status detected) Interrupt active for change in position of portrait, landscape, face-up, face-down. Default value: 0 (0: change in position not detected; 1: change in position detected) Double-tap event status. Default value: 0 (0:event not detected, 1: event detected) Single-tap event status. Default value:0 (0: event not detected, 1: event detected) Wake-up event status. Default value: 0 (0: event not detected, 1: event detected) Free-fall event status. Default value: 0 (0: event not detected, 1: event detected) page 62/171 LSM6DSRX WAKE_UP_SRC (1Bh) 9.26 WAKE_UP_SRC (1Bh) Wake-up interrupt source register (r) Table 75. WAKE_UP_SRC register 0 SLEEP_ CHANGE_IA FF_IA SLEEP_ STATE WU_IA X_WU Y_WU Z_WU Table 76. WAKE_UP_SRC register description SLEEP_CHANGE_IA FF_IA SLEEP_STATE WU_IA X_WU Y_WU Z_WU DS13007 - Rev 3 Detects change event in activity/inactivity status. Default value: 0 (0: change status not detected; 1: change status detected) Free-fall event detection status. Default: 0 (0: free-fall event not detected; 1: free-fall event detected) Sleep event status. Default value: 0 (0: sleep event not detected; 1: sleep event detected) Wakeup event detection status. Default value: 0 (0: wakeup event not detected; 1: wakeup event detected.) Wakeup event detection status on X-axis. Default value: 0 (0: wakeup event on X-axis not detected; 1: wakeup event on X-axis detected) Wakeup event detection status on Y-axis. Default value: 0 (0: wakeup event on Y-axis not detected; 1: wakeup event on Y-axis detected) Wakeup event detection status on Z-axis. Default value: 0 (0: wakeup event on Z-axis not detected; 1: wakeup event on Z-axis detected) page 63/171 LSM6DSRX TAP_SRC (1Ch) 9.27 TAP_SRC (1Ch) Tap source register (r) Table 77. TAP_SRC register 0 TAP_IA SINGLE_ TAP DOUBLE_ _TAP TAP_SIGN X_TAP Y_TAP Z_TAP Table 78. TAP_SRC register description TAP_IA SINGLE_TAP DOUBLE_TAP Tap event detection status. Default: 0 (0: tap event not detected; 1: tap event detected) Single-tap event status. Default value: 0 (0: single tap event not detected; 1: single tap event detected) Double-tap event detection status. Default value: 0 (0: double-tap event not detected; 1: double-tap event detected.) Sign of acceleration detected by tap event. Default: 0 TAP_SIGN (0: positive sign of acceleration detected by tap event; 1: negative sign of acceleration detected by tap event) X_TAP Y_TAP Z_TAP DS13007 - Rev 3 Tap event detection status on X-axis. Default value: 0 (0: tap event on X-axis not detected; 1: tap event on X-axis detected) Tap event detection status on Y-axis. Default value: 0 (0: tap event on Y-axis not detected; 1: tap event on Y-axis detected) Tap event detection status on Z-axis. Default value: 0 (0: tap event on Z-axis not detected; 1: tap event on Z-axis detected) page 64/171 LSM6DSRX DRD_SRC (1Dh) 9.28 DRD_SRC (1Dh) Portrait, landscape, face-up and face-down source register (r) Table 79. D6D_SRC register DEN_DRDY D6D_IA ZH ZL YH YL XH XL Table 80. D6D_SRC register description DEN_DRDY D6D_IA ZH ZL YH YL XH XL DEN data-ready signal. It is set high when data output is related to the data coming from a DEN active condition.(1) Interrupt active for change position portrait, landscape, face-up, face-down. Default value: 0 (0: change position not detected; 1: change position detected) Z-axis high event (over threshold). Default value: 0 (0: event not detected; 1: event (over threshold) detected) Z-axis low event (under threshold). Default value: 0 (0: event not detected; 1: event (under threshold) detected) Y-axis high event (over threshold). Default value: 0 (0: event not detected; 1: event (over-threshold) detected) Y-axis low event (under threshold). Default value: 0 (0: event not detected; 1: event (under threshold) detected) X-axis high event (over threshold). Default value: 0 (0: event not detected; 1: event (over threshold) detected) X-axis low event (under threshold). Default value: 0 (0: event not detected; 1: event (under threshold) detected) 1. The DEN data-ready signal can be latched or pulsed depending on the value of the dataready_pulsed bit of the COUNTER_BDR_REG1 (0Bh) register. DS13007 - Rev 3 page 65/171 LSM6DSRX STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) 9.29 STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) The STATUS_REG register is read by the primary interface SPI/I²C & MIPI I3CSM (r) Table 81. STATUS_REG register 0 0 0 0 0 TDA GDA XLDA GDA XLDA Table 82. STATUS_REG register description Temperature new data available. Default: 0 TDA (0: no set of data is available at temperature sensor output; 1: a new set of data is available at temperature sensor output) Gyroscope new data available. Default value: 0 GDA (0: no set of data available at gyroscope output; 1: a new set of data is available at gyroscope output) Accelerometer new data available. Default value: 0 XLDA (0: no set of data available at accelerometer output; 1: a new set of data is available at accelerometer output) The STATUS_SPIAux register is read by the auxiliary SPI. Table 83. STATUS_SPIAux register 0 0 0 0 0 GYRO SETTLING Table 84. STATUS_SPIAux register description DS13007 - Rev 3 GYRO_SETTLING High when the gyroscope output is in the settling phase GDA Gyroscope data available (reset when one of the high parts of the output data is read) XLDA Accelerometer data available (reset when one of the high parts of the output data is read) page 66/171 LSM6DSRX OUT_TEMP_L (20h), OUT_TEMP_H (21h) 9.30 OUT_TEMP_L (20h), OUT_TEMP_H (21h) Temperature data output register (r). L and H registers together express a 16-bit word in two’s complement. Table 85. OUT_TEMP_L register Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 Temp0 Temp10 Temp9 Temp8 Table 86. OUT_TEMP_H register Temp15 Temp14 Temp13 Temp12 Temp11 Table 87. OUT_TEMP register description Temp[15:0] 9.31 Temperature sensor output data The value is expressed as two’s complement sign extended on the MSB. OUTX_L_G (22h) and OUTX_H_G (23h) Angular rate sensor pitch axis (X) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G (11h)) of gyro user interface. If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro. Table 88. OUTX_L_G register D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 Table 89. OUTX_H_G register D15 D14 D13 D12 D11 Table 90. OUTX_H_G register description Pitch axis (X) angular rate value D[15:0] D[15:0] expressed in two’s complement and its value depends on the interface used: SPI1/I²C/MIPI I3CSM: Gyro UI chain pitch axis output SPI2: Gyro OIS chain pitch axis output DS13007 - Rev 3 page 67/171 LSM6DSRX OUTY_L_G (24h) and OUTY_H_G (25h) 9.32 OUTY_L_G (24h) and OUTY_H_G (25h) Angular rate sensor roll axis (Y) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G (11h)) of the gyro user interface. If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro. . Table 91. OUTY_L_G register D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 Table 92. OUTY_H_G register D15 D14 D13 D12 D11 Table 93. OUTY_H_G register description Roll axis (Y) angular rate value D[15:0] D[15:0] expressed in two’s complement and its value depends on the interface used: SPI1/I²C/MIPI I3CSM: Gyro UI chain roll axis output SPI2: Gyro OIS chain roll axis output 9.33 OUTZ_L_G (26h) and OUTZ_H_G (27h) Angular rate sensor yaw axis (Z) angular rate output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full scale and ODR settings (CTRL2_G (11h)) of the gyro user interface. If this register is read by the auxiliary interface, data are according to the full scale and ODR (6.66 kHz) settings of the OIS gyro. Table 94. OUTZ_L_G register D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 Table 95. OUTZ_H_G register D15 D14 D13 D12 D11 Table 96. OUTZ_H_G register description Yaw axis (Z) angular rate value D[15:0] D[15:0] expressed in two’s complement and its value depends on the interface used: SPI1/I²C/MIPI I3CSM: Gyro UI chain yaw axis output SPI2: Gyro OIS chain yaw axis output DS13007 - Rev 3 page 68/171 LSM6DSRX OUTX_L_A (28h) and OUTX_H_A (29h) 9.34 OUTX_L_A (28h) and OUTX_H_A (29h) Linear acceleration sensor X-axis output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface. If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (CTRL3_OIS (72h)). Table 97. OUTX_L_A register D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 Table 98. OUTX_H_A register D15 D14 D13 D12 D11 Table 99. OUTX_H_A register description X-axis linear acceleration value. D[15:0] D[15:0] expressed in two’s complement and its value depends on the interface used: SPI1/I²C/MIPI I3CSM: Accelerometer UI chain X-axis output SPI2: Accelerometer OIS chain X-axis output 9.35 OUTY_L_A (2Ah) and OUTY_H_A (2Bh) Linear acceleration sensor Y-axis output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface. If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (CTRL3_OIS (72h)). Table 100. OUTY_L_A register D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 Table 101. OUTY_H_A register D15 D14 D13 D12 D11 Table 102. OUTY_H_A register description Y-axis linear acceleration value D[15:0] D[15:0] expressed in two’s complement and its value depends on the interface used: SPI1/I²C/MIPI I3CSM: Accelerometer UI chain Y-axis output SPI2: Accelerometer OIS chain Y-axis output DS13007 - Rev 3 page 69/171 LSM6DSRX OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) 9.36 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) Linear acceleration sensor Z-axis output register (r). The value is expressed as a 16-bit word in two’s complement. If this register is read by the primary interface, data are according to the full-scale and ODR settings (CTRL1_XL (10h)) of the accelerometer user interface. If this register is read by the auxiliary interface, data are according to the full-scale and ODR (6.66 kHz) settings of the OIS (CTRL3_OIS (72h)). Table 103. OUTZ_L_A register D7 D6 D5 D4 D3 D2 D1 D0 D10 D9 D8 0 0 Table 104. OUTZ_H_A register D15 D14 D13 D12 D11 Table 105. OUTZ_H_A register description Z-axis linear acceleration value D[15:0] D[15:0] expressed in two’s complement and its value depends on the interface used: SPI1/I²C/MIPI I3CSM: Accelerometer UI chain Z-axis output SPI2: Accelerometer OIS chain Z-axis output 9.37 EMB_FUNC_STATUS_MAINPAGE (35h) Embedded function status register (r) Table 106. EMB_FUNC_STATUS_MAINPAGE register IS_FSM_LC 0 IS_SIGMOT IS_TILT IS_STEP_DET 0 Table 107. EMB_FUNC_STATUS_MAINPAGE register description IS_FSM_LC IS_SIGMOT IS_TILT IS_STEP_DET DS13007 - Rev 3 Interrupt status bit for FSM long counter timeout interrupt event. (1: interrupt detected; 0: no interrupt) Interrupt status bit for significant motion detection (1: interrupt detected; 0: no interrupt) Interrupt status bit for tilt detection (1: interrupt detected; 0: no interrupt) Interrupt status bit for step detection (1: interrupt detected; 0: no interrupt) page 70/171 LSM6DSRX FSM_STATUS_A_MAINPAGE (36h) 9.38 FSM_STATUS_A_MAINPAGE (36h) Finite State Machine status register (r) Table 108. FSM_STATUS_A_MAINPAGE register IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 IS_FSM2 IS_FSM1 Table 109. FSM_STATUS_A_MAINPAGE register description 9.39 IS_FSM8 Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM7 Interrupt status bit for FSM7 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM6 Interrupt status bit for FSM6 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM5 Interrupt status bit for FSM5 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM4 Interrupt status bit for FSM4 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM3 Interrupt status bit for FSM3 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM2 Interrupt status bit for FSM2 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM1 Interrupt status bit for FSM1 interrupt event. (1: interrupt detected; 0: no interrupt) FSM_STATUS_B_MAINPAGE (37h) Finite State Machine status register (r) Table 110. FSM_STATUS_B_MAINPAGE register IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9 Table 111. FSM_STATUS_B_MAINPAGE register description DS13007 - Rev 3 IS_FSM16 Interrupt status bit for FSM16 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM15 Interrupt status bit for FSM15 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM14 Interrupt status bit for FSM14 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM13 Interrupt status bit for FSM13 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM12 Interrupt status bit for FSM12 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM11 Interrupt status bit for FSM11 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM10 Interrupt status bit for FSM10 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM9 Interrupt status bit for FSM9 interrupt event. (1: interrupt detected; 0: no interrupt) page 71/171 LSM6DSRX MLC_STATUS_MAINPAGE (38h) 9.40 MLC_STATUS_MAINPAGE (38h) Machine Learning Core status register (r) Table 112. MLC_STATUS_MAINPAGE register IS_MLC8 IS_MLC7 IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1 0 SENS_HUB_ ENDOP Table 113. MLC_STATUS_MAINPAGE register description 9.41 IS_MLC8 Interrupt status bit for MLC8 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC7 Interrupt status bit for MLC7 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC6 Interrupt status bit for MLC6 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC5 Interrupt status bit for MLC5 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC4 Interrupt status bit for MLC4 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC3 Interrupt status bit for MLC3 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC2 Interrupt status bit for MLC2 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC1 Interrupt status bit for MLC1 interrupt event. (1: interrupt detected; 0: no interrupt) STATUS_MASTER_MAINPAGE (39h) Sensor hub source register (r) Table 114. STATUS_MASTER_MAINPAGE register WR_ONCE_ DONE SLAVE3_ NACK SLAVE2_ NACK SLAVE1_ NACK SLAVE0_ NACK 0 Table 115. STATUS_MASTER_MAINPAGE register description WR_ONCE_DONE When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0 SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0 SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0 SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0 SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0 Sensor hub communication status. Default value: 0 SENS_HUB_ENDOP (0: sensor hub communication not concluded; 1: sensor hub communication concluded) DS13007 - Rev 3 page 72/171 LSM6DSRX FIFO_STATUS1 (3Ah) 9.42 FIFO_STATUS1 (3Ah) FIFO status register 1 (r) Table 116. FIFO_STATUS1 register DIFF_FIFO_7 DIFF_FIFO_6 DIFF_FIFO_5 DIFF_FIFO_4 DIFF_FIFO_3 DIFF_FIFO_2 DIFF_FIFO_1 DIFF_FIFO_0 Table 117. FIFO_STATUS1 register description Number of unread sensor data (TAG + 6 bytes) stored in FIFO DIFF_FIFO_[7:0] 9.43 In conjunction with DIFF_FIFO[9:8] in FIFO_STATUS2 (3Bh). FIFO_STATUS2 (3Bh) FIFO status register 2 (r) Table 118. FIFO_STATUS2 register FIFO_ WTM_IA FIFO_ OVR_IA FIFO_ FULL_IA COUNTER_ BDR_IA FIFO_OVR_ LATCHED 0 DIFF_FIFO_9 DIFF_FIFO_8 Table 119. FIFO_STATUS2 register description FIFO watermark status. Default value: 0 FIFO_WTM_IA (0: FIFO filling is lower than WTM; 1: FIFO filling is equal to or greater than WTM) Watermark is set through bits WTM[8:0] in FIFO_CTRL1 (07h) and FIFO_CTRL2 (08h). FIFO_OVR_IA FIFO_FULL_IA COUNTER_BDR_IA FIFO overrun status. Default value: 0 (0: FIFO is not completely filled; 1: FIFO is completely filled) Smart FIFO full status. Default value: 0 (0: FIFO is not full; 1: FIFO will be full at the next ODR) Counter BDR reaches the CNT_BDR_TH_[10:0] threshold set in COUNTER_BDR_REG1 (0Bh) and COUNTER_BDR_REG2 (0Ch). Default value: 0 This bit is reset when these registers are read. FIFO_OVR_LATCHED DIFF_FIFO_[9:8] DS13007 - Rev 3 Latched FIFO overrun status. Default value: 0 This bit is reset when this register is read. Number of unread sensor data (TAG + 6 bytes) stored in FIFO. Default value: 00 In conjunction with DIFF_FIFO[7:0] in FIFO_STATUS1 (3Ah). page 73/171 LSM6DSRX TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 9.44 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) Timestamp first data output register (r). The value is expressed as a 32-bit word and the bit resolution is 25 µs. Table 120. TIMESTAMP3 register D31 D30 D29 D28 D27 D26 D25 D24 D18 D17 D16 D10 D9 D8 D2 D1 D0 Table 121. TIMESTAMP2 register D23 D22 D21 D20 D19 Table 122. TIMESTAMP1 register D15 D14 D13 D12 D11 Table 123. TIMESTAMP0 register D7 D[31:0] D6 D5 D4 D3 Timestamp output registers: 1LSB = 25 µs The formula below can be used to calculate a better estimation of the actual timestamp resolution: TS_Res = 1 / (40000 + (0.0015 * INTERNAL_FREQ_FINE * 40000)) where INTERNAL_FREQ_FINE is the content of INTERNAL_FREQ_FINE (63h). DS13007 - Rev 3 page 74/171 LSM6DSRX TAP_CFG0 (56h) 9.45 TAP_CFG0 (56h) Activity/inactivity functions, configuration of filtering, and tap recognition functions (r/w) Table 124. TAP_CFG0 register 0(1) INT_CLR_ ON_READ SLEEP_STATUS _ON_INT SLOPE_ FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR 1. This bit must be set to '0' for the correct operation of the device. Table 125. TAP_CFG0 register description This bit allows immediately clearing the latched interrupts of an event detection upon the read of the corresponding status register. It must be set to 1 together with LIR. Default value: 0 INT_CLR_ON_READ (0: latched interrupt signal cleared at the end of the ODR period; 1: latched interrupt signal immediately cleared) Activity/inactivity interrupt mode configuration. SLEEP_STATUS_ON_INT If INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits are enabled, drives the sleep status or sleep change on the INT pins. Default value: 0 (0: sleep change notification on INT pins; 1: sleep status reported on INT pins) SLOPE_FDS TAP_X_EN TAP_Y_EN TAP_Z_EN LIR DS13007 - Rev 3 HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions. Default value: 0 (0: SLOPE filter applied; 1: HPF applied) Enable X direction in tap recognition. Default value: 0 (0: X direction disabled; 1: X direction enabled) Enable Y direction in tap recognition. Default value: 0 (0: Y direction disabled; 1: Y direction enabled) Enable Z direction in tap recognition. Default value: 0 (0: Z direction disabled; 1: Z direction enabled) Latched Interrupt. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) page 75/171 LSM6DSRX TAP_CFG1 (57h) 9.46 TAP_CFG1 (57h) Tap configuration register (r/w) Table 126. TAP_CFG1 register TAP_ PRIORITY_2 TAP_ PRIORITY_1 TAP_ PRIORITY_0 TAP_ THS_X_4 TAP_ THS_X_3 TAP_ THS_X_2 TAP_ THS_X_1 TAP_ THS_X_0 Table 127. TAP_CFG1 register description TAP_PRIORITY_[2:0] Selection of axis priority for TAP detection (see Table 128) X-axis tap recognition threshold. Default value: 0 TAP_THS_X_[4:0] 1 LSB = FS_XL / (25) Table 128. TAP priority decoding 9.47 TAP_PRIORITY_[2:0] Max. priority Mid. priority Min. priority 000 X Y Z 001 Y X Z 010 X Z Y 011 Z Y X 100 X Y Z 101 Y Z X 110 Z X Y 111 Z Y X TAP_CFG2 (58h) Enables interrupt and inactivity functions, and tap recognition functions (r/w) Table 129. TAP_CFG2 register INTERRUPTS _ENABLE INACT_EN1 INACT_EN0 TAP_ THS_Y_4 TAP_ THS_Y_3 TAP_ THS_Y_2 TAP_ THS_Y_1 TAP_ THS_Y_0 Table 130. TAP_CFG2 register description INTERRUPTS_ENABLE Enable basic interrupts (6D/4D, free-fall, wake-up, tap, inactivity). Default value: 0 (0: interrupt disabled; 1: interrupt enabled) Enable activity/inactivity (sleep) function. Default value: 00 (00: stationary/motion-only interrupts generated, XL and gyro do not change; INACT_EN[1:0] 01: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro does not change; 10: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to sleep mode; 11: sets accelerometer ODR to 12.5 Hz (low-power mode), gyro to power-down mode) TAP_THS_Y_[4:0] DS13007 - Rev 3 Y-axis tap recognition threshold. Default value: 0 1 LSB = FS_XL / (25) page 76/171 LSM6DSRX TAP_THS_6D (59h) 9.48 TAP_THS_6D (59h) Portrait/landscape position and tap function threshold register (r/w) Table 131. TAP_THS_6D register D4D_EN SIXD_THS1 TAP_ THS_Z_4 SIXD_THS0 TAP_ THS_Z_3 TAP_ THS_Z_2 TAP_ THS_Z_1 TAP_ THS_Z_0 Table 132. TAP_THS_6D register description Enables detection of 4D orientation. Z-axis position detection is disabled. Default value: 0 D4D_EN (0: disabled; 1: enabled) Threshold for 4D/6D function: (00: 80 degrees (default); SIXD_THS[1:0] 01: 70 degrees; 10: 60 degrees; 11: 50 degrees) TAP_THS_Z_[4:0] 9.49 Z-axis recognition threshold. Default value: 0 1 LSB = FS_XL / (25) INT_DUR2 (5Ah) Tap recognition function setting register (r/w) Table 133. INT_DUR2 register DUR3 DUR2 DUR1 DUR0 QUIET1 QUIET0 SHOCK1 SHOCK0 Table 134. INT_DUR2 register description Duration of maximum time gap for double-tap recognition. Default: 0000 DUR[3:0] When double-tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double-tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time. Expected quiet time after a tap detection. Default value: 00 QUIET[1:0] Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET[1:0] bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. Maximum duration of overthreshold event. Default value: 00 SHOCK[1:0] Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK[1:0] bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. DS13007 - Rev 3 page 77/171 LSM6DSRX WAKE_UP_THS (5Bh) 9.50 WAKE_UP_THS (5Bh) Single/double-tap selection and wake-up configuration (r/w) Table 135. WAKE_UP_THS register SINGLE_ DOUBLE_TAP USR_OFF_ ON_WU WK_THS5 WK_THS4 WK_THS3 WK_THS2 WK_THS1 WK_THS0 Table 136. WAKE_UP_THS register description Single/double-tap event enable. Default: 0 SINGLE_DOUBLE_TAP (0: only single-tap event enabled; 1: both single and double-tap events enabled) 9.51 USR_OFF_ON_WU Sends the low-pass filtered data with user offset correction (instead of high-pass filtered data) to the wakeup function. WK_THS[5:0] Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in WAKE_UP_DUR (5Ch). Default value: 000000 WAKE_UP_DUR (5Ch) Free-fall, wakeup and sleep mode functions duration setting register (r/w) Table 137. WAKE_UP_DUR register FF_DUR5 WAKE_DUR1 WAKE_DUR0 WAKE_ THS_W SLEEP_ DUR3 SLEEP_ DUR2 SLEEP_ DUR1 SLEEP_ DUR0 Table 138. WAKE_UP_DUR register description Free fall duration event. Default: 0 FF_DUR5 For the complete configuration of the free-fall duration, refer to FF_DUR[4:0] in FREE_FALL (5Dh) configuration. 1 LSB = 1 ODR_time WAKE_DUR[1:0] Wake up duration event. Default: 00 1LSB = 1 ODR_time Weight of 1 LSB of wakeup threshold. Default: 0 WAKE_THS_W (0: 1 LSB =FS_XL / (26); 1: 1 LSB = FS_XL / (28)) SLEEP_DUR[3:0] DS13007 - Rev 3 Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512 ODR page 78/171 LSM6DSRX FREE_FALL (5Dh) 9.52 FREE_FALL (5Dh) Free-fall function duration setting register (r/w) Table 139. FREE_FALL register FF_DUR4 FF_DUR3 FF_DUR2 FF_DUR1 FF_DUR0 FF_THS2 FF_THS1 FF_THS0 Table 140. FREE_FALL register description Free-fall duration event. Default: 0 FF_DUR[4:0] For the complete configuration of the free fall duration, refer to FF_DUR5 in WAKE_UP_DUR (5Ch) configuration. Free-fall threshold setting: (000: 156 mg (default); 001: 219 mg; 010: 250 mg; FF_THS[2:0] 011: 312 mg; 100: 344 mg; 101: 406 mg; 110: 469 mg; 111: 500 mg) DS13007 - Rev 3 page 79/171 LSM6DSRX MD1_CFG (5Eh) 9.53 MD1_CFG (5Eh) Functions routing on INT1 register (r/w) Table 141. MD1_CFG register INT1_SLEEP _CHANGE INT1_ SINGLE_TAP INT1_WU INT1_FF INT1_ DOUBLE_TAP INT1_6D INT1_ EMB_FUNC INT1_SHUB Table 142. MD1_CFG register description Routing of activity/inactivity recognition event on INT1. Default: 0 INT1_SLEEP_CHANGE(1) (0: routing of activity/inactivity event on INT1 disabled; 1: routing of activity/inactivity event on INT1 enabled) Routing of single-tap recognition event on INT1. Default: 0 INT1_SINGLE_TAP (0: routing of single-tap event on INT1 disabled; 1: routing of single-tap event on INT1 enabled) Routing of wakeup event on INT1. Default value: 0 INT1_WU (0: routing of wakeup event on INT1 disabled; 1: routing of wakeup event on INT1 enabled) Routing of free-fall event on INT1. Default value: 0 INT1_FF (0: routing of free-fall event on INT1 disabled; 1: routing of free-fall event on INT1 enabled) Routing of tap event on INT1. Default value: 0 INT1_DOUBLE_TAP (0: routing of double-tap event on INT1 disabled; 1: routing of double-tap event on INT1 enabled) Routing of 6D event on INT1. Default value: 0 INT1_6D (0: routing of 6D event on INT1 disabled; 1: routing of 6D event on INT1 enabled) Routing of embedded functions event on INT1. Default value: 0 INT1_EMB_FUNC (0: routing of embedded functions event on INT1 disabled; 1: routing embedded functions event on INT1 enabled) Routing of sensor hub communication concluded event on INT1. Default value: 0 INT1_SHUB (0: routing of sensor hub communication concluded event on INT1 disabled; 1: routing of sensor hub communication concluded event on INT1 enabled) 1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the TAP_CFG0 (56h) register. DS13007 - Rev 3 page 80/171 LSM6DSRX MD2_CFG (5Fh) 9.54 MD2_CFG (5Fh) Functions routing on INT2 register (r/w) Table 143. MD2_CFG register INT2_SLEEP _CHANGE INT2_ SINGLE_TAP INT2_WU INT2_FF INT2_ DOUBLE_TAP INT2_6D INT2_ EMB_FUNC INT2_ TIMESTAMP Table 144. MD2_CFG register description Routing of activity/inactivity recognition event on INT2. Default: 0 INT2_SLEEP_CHANGE(1) (0: routing of activity/inactivity event on INT2 disabled; 1: routing of activity/inactivity event on INT2 enabled) Single-tap recognition routing on INT2. Default: 0 INT2_SINGLE_TAP (0: routing of single-tap event on INT2 disabled; 1: routing of single-tap event on INT2 enabled) Routing of wakeup event on INT2. Default value: 0 INT2_WU (0: routing of wakeup event on INT2 disabled; 1: routing of wake-up event on INT2 enabled) Routing of free-fall event on INT2. Default value: 0 INT2_FF (0: routing of free-fall event on INT2 disabled; 1: routing of free-fall event on INT2 enabled) Routing of tap event on INT2. Default value: 0 INT2_DOUBLE_TAP (0: routing of double-tap event on INT2 disabled; 1: routing of double-tap event on INT2 enabled) Routing of 6D event on INT2. Default value: 0 INT2_6D (0: routing of 6D event on INT2 disabled; 1: routing of 6D event on INT2 enabled) Routing of embedded functions event on INT2. Default value: 0 INT2_EMB_FUNC (0: routing of embedded functions event on INT2 disabled; 1: routing embedded functions event on INT2 enabled) INT2_TIMESTAMP Enables routing on INT2 pin of the alert for timestamp overflow within 6.4 ms. 1. Activity/Inactivity interrupt mode (sleep change or sleep status) depends on the SLEEP_STATUS_ON_INT bit in the TAP_CFG0 (56h) register. DS13007 - Rev 3 page 81/171 LSM6DSRX S4S_ST_CMD_CODE (60h) 9.55 S4S_ST_CMD_CODE (60h) S4S master command register (r/w) Table 145. S4S_ST_CMD_CODE register ST_CMD_ CODE7 ST_CMD_ CODE6 ST_CMD_ CODE5 ST_CMD_ CODE4 ST_CMD_ CODE3 ST_CMD_ CODE2 ST_CMD_ CODE1 ST_CMD_ CODE0 DT1 DT0 0(1) PD_DIS_ INT1 Table 146. S4S_ST_CMD_CODE register description ST_CMD_CODE[7:0] 9.56 Master command code used for S4S. Default value: 0 S4S_DT_REG (61h) S4S DT register (r/w) Table 147. S4S_DT_REG register DT7 DT6 DT5 DT4 DT3 DT2 Table 148. S4S_DT_REG register description DT[7:0] 9.57 DT used for S4S. Default value: 0 I3C_BUS_AVB (62h) I3C_BUS_AVB register (r/w) Table 149. I3C_BUS_AVB register 0(1) 0(1) 0(1) I3C_Bus_ Avb_Sel1 I3C_Bus_ Avb_Sel0 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 150. I3C_BUS_AVB register description These bits are used to select the bus available time when I3C IBI is used. Default value: 00 I3C_Bus_Avb_Sel[1:0] (00: bus available time equal to 50 µsec (default); 01: bus available time equal to 2 µsec; 10: bus available time equal to 1 msec; 11: bus available time equal to 25 msec) This bit allows disabling the INT1 pull-down. PD_DIS_INT1 (0: Pull-down on INT1 enabled (pull-down is effectively connected only when no interrupts are routed to the INT1 pin or when the I3C dynamic address is assigned); 1: Pull-down on INT1 disabled (pull-down not connected)) DS13007 - Rev 3 page 82/171 LSM6DSRX INTERNAL_FREQ_FINE (63h) 9.58 INTERNAL_FREQ_FINE (63h) Internal frequency register (r) Table 151. INTERNAL_FREQ_FINE register FREQ_FINE7 FREQ_FINE6 FREQ_FINE5 FREQ_FINE4 FREQ_FINE3 FREQ_FINE2 FREQ_FINE1 FREQ_FINE0 Table 152. INTERNAL_FREQ_FINE register description FREQ_FINE[7:0] Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.15%. 8-bit format, 2's complement. The formula below can be used to calculate a better estimation of the actual ODR: ODR_Actual = (6667 + ((0.0015 * INTERNAL_FREQ_FINE) * 6667)) / ODR_Coeff Selected_ODR ODR_Coeff 12.5 512 26 256 52 128 104 64 208 32 416 16 833 8 1667 4 3333 2 6667 1 The Selected_ODR parameter has to be derived from the ODR_XL selection (Table 50. Accelerometer ODR selection) in order to estimate the accelerometer ODR and from the ODR_G selection (Table 53. Gyroscope ODR configuration setting) in order to estimate the gyroscope ODR. DS13007 - Rev 3 page 83/171 LSM6DSRX INT_OIS (6Fh) 9.59 INT_OIS (6Fh) OIS interrupt configuration register and accelerometer self-test enable setting. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 153. INT_OIS register INT2_ DRDY_OIS LVL2_OIS DEN_LH_OIS - - 0(1) ST1_XL_OIS ST0_XL_OIS 1. This bit must be set to '0' for the correct operation of the device. Table 154. INT_OIS register description INT2_DRDY_OIS Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2 settings. LVL2_OIS Enables level-sensitive latched mode on the OIS chain. Default value: 0 Indicates polarity of DEN signal on OIS chain DEN_LH_OIS (0: DEN pin is active-low; 1: DEN pin is active-high) Selects accelerometer self-test – effective only if XL OIS chain is enabled. Default value: 00 (00: Normal mode; ST[1:0]_XL_OIS 01: Positive sign self-test; 10: Negative sign self-test; 11: not allowed) DS13007 - Rev 3 page 84/171 LSM6DSRX CTRL1_OIS (70h) 9.60 CTRL1_OIS (70h) OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 155. CTRL1_OIS register 0(1) LVL1_OIS SIM_OIS Mode4_EN FS1_G_OIS FS0_G_OIS FS_125_OIS OIS_EN_SPI2 1. This bit must be set to '0' for the correct operation of the device. Table 156. CTRL1_OIS register description LVL1_OIS Enables level-sensitive trigger mode on OIS chain. Default value: 0 SPI2 3- or 4-wire interface. Default value: 0 SIM_OIS (0: 4-wire SPI2; 1: 3-wire SPI2) Mode4_EN Enables accelerometer OIS chain. OIS outputs are available through SPI2 in registers OUTX_L_A (28h) and OUTX_H_A (29h) - OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh). Note: OIS_EN_SPI2 must be enabled (i.e. set to ‘1’) to enable also XL OIS chain. Selects gyroscope OIS chain full-scale (00: ±250 dps; FS[1:0]_G_OIS 01: ±500 dps; 10: ±1000 dps; 11: ±2000 dps) Selects gyroscope OIS chain full-scale ±125 dps FS_125_OIS (0: FS selected through bits FS[1:0]_OIS_G; 1: ±125 dps) Enables OIS chain data processing for gyro in Mode 3 and Mode 4 (mode4_en = 1) and accelerometer data in Mode 4 (mode4_en = 1). OIS_EN_SPI2 When the OIS chain is enabled, the OIS outputs are available through the SPI2 in registers OUTX_L_G (22h) and OUTX_H_G (23h) through OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) and STATUS_REG (1Eh) / STATUS_SPIAux (1Eh), and LPF1 is dedicated to this chain. DEN mode selection can be done using the LVL1_OIS bit of register CTRL1_OIS (70h) and the LVL2_OIS bit of register INT_OIS (6Fh). DEN mode on the OIS path is active in the gyroscope only. Table 157. DEN mode selection DS13007 - Rev 3 LVL1_OIS, LVL2_OIS DEN mode 10 Level-sensitive trigger mode is selected 11 Level-sensitive latched mode is selected page 85/171 LSM6DSRX CTRL2_OIS (71h) 9.61 CTRL2_OIS (71h) OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 158. CTRL2_OIS register - - HPM1_OIS HPM0_OIS 0(1) FTYPE_1_OIS FTYPE_0_OIS HP_EN_OIS 1. This bit must be set to '0' for the correct operation of the device. Table 159. CTRL2_OIS register description Selects gyroscope OIS chain digital high-pass filter cutoff. Default value: 00 (00: 16 mHz; HPM[1:0]_OIS 01: 65 mHz; 10: 260 mHz; 11: 1.04 Hz) FTYPE_[1:0]_OIS Selects gyroscope digital LPF1 filter bandwidth. Table 160 shows cutoff and phase values obtained with all configurations. HP_EN_OIS Enables gyroscope OIS chain digital high-pass filter. Table 160. Gyroscope OIS chain digital LPF1 filter bandwidth selection ODR [Hz] 6.66 kHz DS13007 - Rev 3 LPF1 FTYPE_[1:0]_OIS Total BW [Hz] (phase delay @20 Hz) 00 297 Hz (7°) 01 222 Hz (9°) 10 154 Hz (12°) 11 470 Hz (5°) page 86/171 LSM6DSRX CTRL3_OIS (72h) 9.62 CTRL3_OIS (72h) OIS configuration register. Primary interface for read-only (r); only Aux SPI can write to this register (r/w). Table 161. CTRL3_OIS register FS1_XL_OIS FS0_XL_OIS FILTER_XL_ FILTER_XL_ FILTER_XL_ CONF_OIS_2 CONF_OIS_1 CONF_OIS_0 ST1_OIS ST0_OIS ST_OIS_ CLAMPDIS Table 162. CTRL3_OIS register description Selects accelerometer OIS channel full-scale. Default value: 00. FS[1:0]_XL_OIS (00: ±2 g; 01: ±16 g; 10: ±4 g; 11: ±8 g) FILTER_XL_CONF_OIS_[2:0] Selects accelerometer OIS channel bandwidth. See Table 163. Selects gyroscope OIS chain self-test. Default value: 00 Table 164 lists the output variation when the self-test is enabled and ST_OIS_CLAMPDIS='1'. (00: Normal mode; ST[1:0]_OIS 01: Positive sign self-test; 10: Normal mode; 11: Negative sign self-test) Disables OIS chain clamp ST_OIS_CLAMPDIS (0: All OIS chain outputs = 8000h during self-test; 1: OIS chain self-test outputs as shown in Table 164. Table 163. Accelerometer OIS channel bandwidth and phase FILTER_XL_CONF_OIS[2:0] Typ. overall bandwidth [Hz] Typ. overall phase [°] 000 631 -4.20 @ 20 Hz 001 295 -6.35 @ 20 Hz 010 140 -10.6 @ 20 Hz 011 68.2 -18.9 @ 20 Hz 100 33.6 -17.8 @ 10 Hz 101 16.7 -32.2 @ 10 Hz 110 8.3 -26.2 @ 4 Hz 111 4.14 -26.0 @ 2 Hz Table 164. Self-test nominal output variation DS13007 - Rev 3 Full scale Output variation [dps] ±2000 ±400 ±1000 ±200 ±500 ±100 ±250 ±50 ±125 ±25 page 87/171 LSM6DSRX X_OFS_USR (73h) 9.63 X_OFS_USR (73h) Accelerometer X-axis user offset correction (r/w). The offset value set in the X_OFS_USR offset register is internally subtracted from the acceleration value measured on the X-axis. Table 165. X_OFS_USR register X_OFS_ USR_7 X_OFS_ USR_6 X_OFS_ USR_5 X_OFS_ USR_4 X_OFS_ USR_3 X_OFS_ USR_2 X_OFS_ USR_1 X_OFS_ USR_0 Table 166. X_OFS_USR register description X_OFS_USR_[7:0] 9.64 Accelerometer X-axis user offset correction expressed in two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127 127]. Y_OFS_USR (74h) Accelerometer Y-axis user offset correction (r/w). The offset value set in the Y_OFS_USR offset register is internally subtracted from the acceleration value measured on the Y-axis. Table 167. Y_OFS_USR register Y_OFS_ USR_7 Y_OFS_ USR_6 Y_OFS_USR_[7:0] 9.65 Y_OFS_ USR_5 Y_OFS_ USR_4 Y_OFS_ USR_3 Y_OFS_ USR_2 Y_OFS_ USR_1 Y_OFS_ USR_0 Accelerometer Y-axis user offset calibration expressed in 2’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127]. Z_OFS_USR (75h) Accelerometer Z-axis user offset correction (r/w). The offset value set in the Z_OFS_USR offset register is internally subtracted from the acceleration value measured on the Z-axis. Table 168. Z_OFS_USR register Z_OFS_ USR_7 Z_OFS_ USR_6 Z_OFS_ USR_5 Z_OFS_ USR_4 Z_OFS_ USR_3 Z_OFS_ USR_2 Z_OFS_ USR_1 Z_OFS_ USR_0 Table 169. Z_OFS_USR register description Z_OFS_USR_[7:0] DS13007 - Rev 3 Accelerometer Z-axis user offset calibration expressed in 2’s complement, weight depends on USR_OFF_W in CTRL6_C (15h). The value must be in the range [-127, +127]. page 88/171 LSM6DSRX FIFO_DATA_OUT_TAG (78h) 9.66 FIFO_DATA_OUT_TAG (78h) FIFO tag register (r) Table 170. FIFO_DATA_OUT_TAG register TAG_ SENSOR_4 TAG_ SENSOR_3 TAG_ SENSOR_2 TAG_ SENSOR_1 TAG_ SENSOR_0 TAG_CNT_1 TAG_CNT_0 TAG_ PARITY Table 171. FIFO_DATA_OUT_TAG register description Identifies the sensor in: TAG_SENSOR_[4:0] FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah), FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch), and FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) For details, refer to Table 172. FIFO tag TAG_CNT_[1:0] 2-bit counter which identifies sensor time slot TAG_PARITY Parity check of TAG content Table 172. FIFO tag DS13007 - Rev 3 TAG_SENSOR_[4:0] Sensor name 0x01 Gyroscope NC 0x02 Accelerometer NC 0x03 Temperature 0x04 Timestamp 0x05 CFG_Change 0x06 Accelerometer NC_T_2 0x07 Accelerometer NC_T_1 0x08 Accelerometer 2xC 0x09 Accelerometer 3xC 0x0A Gyroscope NC_T_2 0x0B Gyroscope NC_T_1 0x0C Gyroscope 2xC 0x0D Gyroscope 3xC 0x0E Sensor Hub Slave 0 0x0F Sensor Hub Slave 1 0x10 Sensor Hub Slave 2 0x11 Sensor Hub Slave 3 0x12 Step Counter 0x19 Sensor Hub Nack page 89/171 LSM6DSRX FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) 9.67 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) FIFO data output X (r) Table 173. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 174. FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description D[15:0] 9.68 FIFO X-axis output FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) FIFO data output Y (r) Table 175. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 176. FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description D[15:0] 9.69 FIFO Y-axis output FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) FIFO data output Z (r) Table 177. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 178. FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description D[15:0] DS13007 - Rev 3 FIFO Z-axis output page 90/171 LSM6DSRX Embedded functions register mapping 10 Embedded functions register mapping The table given below provides a list of the registers for the embedded functions available in the device and the corresponding addresses. Embedded functions registers are accessible when FUNC_CFG_EN is set to '1' in FUNC_CFG_ACCESS (01h). Table 179. Register address map - embedded functions Name DS13007 - Rev 3 Type Register address Hex Binary Default PAGE_SEL RW 02 00000010 RESERVED - 03 00000011 EMB_FUNC_EN_A RW 04 00000100 00000000 EMB_FUNC_EN_B RW 05 00000101 00000000 PAGE_ADDRESS RW 08 00001000 00000000 PAGE_VALUE RW 09 00001001 00000000 EMB_FUNC_INT1 RW 0A 00001010 00000000 FSM_INT1_A RW 0B 00001011 00000000 FSM_INT1_B RW 0C 00001100 00000000 MLC_INT1 RW 0D 00001101 00000000 EMB_FUNC_INT2 RW 0E 00001110 00000000 FSM_INT2_A RW 0F 00001111 01101011 FSM_INT2_B RW 10 00010000 00000000 MLC_INT2 RW 11 00010001 00000000 EMB_FUNC_STATUS R 12 00010010 output FSM_STATUS_A R 13 00010011 output FSM_STATUS_B R 14 00010100 output MLC_STATUS R 15 00010101 output PAGE_RW RW 17 00010111 00000000 RESERVED - 18-43 EMB_FUNC_FIFO_CFG RW 44 01000100 00000000 FSM_ENABLE_A RW 46 01000110 00000000 FSM_ENABLE_B RW 47 01000111 00000000 Comment 00000001 FSM_LONG_COUNTER_L RW 48 01001000 00000000 FSM_LONG_COUNTER_H RW 49 01001001 00000000 FSM_LONG_COUNTER_CLEAR RW 4A 01001010 00000000 FSM_OUTS1 R 4C 01001100 output FSM_OUTS2 R 4D 01001101 output FSM_OUTS3 R 4E 01001110 output FSM_OUTS4 R 4F 01001111 output FSM_OUTS5 R 50 01010000 output FSM_OUTS6 R 51 01010001 output page 91/171 LSM6DSRX Embedded functions register mapping Name Type Register address Hex Binary Default FSM_OUTS7 R 52 01010010 output FSM_OUTS8 R 53 01010011 output FSM_OUTS9 R 54 01010100 output FSM_OUTS10 R 55 01010101 output FSM_OUTS11 R 56 01010110 output FSM_OUTS12 R 57 01010111 output FSM_OUTS13 R 58 01011000 output FSM_OUTS14 R 59 01011001 output FSM_OUTS15 R 5A 01011010 output FSM_OUTS16 R 5B 01011011 output RESERVED - 5C-5E EMB_FUNC_ODR_CFG_B RW 5F 01011111 01001011 EMB_FUNC_ODR_CFG_C RW 60 01100000 00010101 STEP_COUNTER_L R 62 01100010 output STEP_COUNTER_H R 63 01100011 output EMB_FUNC_SRC RW 64 01100100 output EMB_FUNC_INIT_A RW 66 01100110 00000000 EMB_FUNC_INIT_B RW 67 01100111 00000000 MLC0_SRC R 70 01110000 output MLC1_SRC R 71 01110001 output MLC2_SRC R 72 01110010 output MLC3_SRC R 73 01110011 output MLC4_SRC R 74 01110100 output MLC5_SRC R 75 01110101 output MLC6_SRC R 76 01110110 output MLC7_SRC R 77 01110111 output Comment Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. DS13007 - Rev 3 page 92/171 LSM6DSRX Embedded functions register description 11 Embedded functions register description 11.1 PAGE_SEL (02h) Enable advanced features dedicated page (r/w) Table 180. PAGE_SEL register PAGE_SEL3 PAGE_SEL2 PAGE_SEL1 0(1) PAGE_SEL0 0(1) 0(1) 1(2) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device. Table 181. PAGE_SEL register description Select the advanced features dedicated page PAGE_SEL[3:0] 11.2 Default value: 0000 EMB_FUNC_EN_A (04h) Embedded functions enable register (r/w) Table 182. EMB_FUNC_EN_A register 0(1) 0(1) SIGN_ MOTION_EN TILT_EN PEDO_EN 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 183. EMB_FUNC_EN_A register description Enable significant motion detection function. Default value: 0 SIGN_MOTION_EN (0: significant motion detection function disabled; 1: significant motion detection function enabled) Enable tilt calculation. Default value: 0 TILT_EN (0: tilt algorithm disabled; 1: tilt algorithm enabled) Enable pedometer algorithm. Default value: 0 PEDO_EN (0: pedometer algorithm disabled; 1: pedometer algorithm enabled) DS13007 - Rev 3 page 93/171 LSM6DSRX EMB_FUNC_EN_B (05h) 11.3 EMB_FUNC_EN_B (05h) Embedded functions enable register (r/w) Table 184. EMB_FUNC_EN_B register 0(1) 0(1) 0(1) MLC_EN FIFO_ COMPR_EN 0(1) 0(1) FSM_EN PAGE_ ADDR1 PAGE_ ADDR0 1. This bit must be set to '0' for the correct operation of the device. Table 185. EMB_FUNC_EN_B register description Enable Machine Learning Core feature. Default value: 0 MLC_EN (0: Machine Learning Core feature disabled; 1: Machine Learning Core feature enabled) Enable FIFO compression feature. Default value: 0 FIFO_COMPR_EN(1) (0: FIFO compression feature disabled; 1: FIFO compression feature enabled) Enable Finite State Machine (FSM) feature. Default value: 0 FSM_EN (0: FSM feature disabled; 1: FSM feature enabled) 1. This bit is effective if the FIFO_COMPR_RT_EN bit of FIFO_CTRL2 (08h) is set to 1. 11.4 PAGE_ADDRESS (08h) Page address register (r/w) Table 186. PAGE_ADDRESS register PAGE_ ADDR7 PAGE_ ADDR6 PAGE_ ADDR5 PAGE_ ADDR4 PAGE_ ADDR3 PAGE_ ADDR2 Table 187. PAGE_ADDRESS register description After setting the bit PAGE_WRITE / PAGE_READ in register PAGE_RW (17h), this register is used to set PAGE_ADDR[7:0] the address of the register to be written/read in the advanced features page selected through the bits PAGE_SEL[3:0] in register PAGE_SEL (02h). 11.5 PAGE_VALUE (09h) Page value register (r/w) Table 188. PAGE_VALUE register PAGE_ VALUE7 PAGE_ VALUE6 PAGE_ VALUE5 PAGE_ VALUE4 PAGE_ VALUE3 PAGE_ VALUE2 PAGE_ VALUE1 PAGE_ VALUE0 Table 189. PAGE_VALUE register description These bits are used to write (if the bit PAGE_WRITE = 1 in register PAGE_RW (17h)) or read (if the bit PAGE_VALUE[7:0] PAGE_READ = 1 in register PAGE_RW (17h)) the data at the address PAGE_ADDR[7:0] of the selected advanced features page. DS13007 - Rev 3 page 94/171 LSM6DSRX EMB_FUNC_INT1 (0Ah) 11.6 EMB_FUNC_INT1 (0Ah) INT1 pin control register (r/w) Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals. Table 190. EMB_FUNC_INT1 register INT1_ FSM_LC 0(1) INT1_ SIG_MOT INT1_TILT INT1_STEP_ DETECTOR 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 191. EMB_FUNC_INT1 register description INT1_FSM_LC(1) INT1_SIG_MOT(1) INT1_TILT(1) INT1_STEP_DETECTOR(1) Routing of FSM long counter timeout interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of significant motion event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of tilt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of pedometer step recognition event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) 1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1. DS13007 - Rev 3 page 95/171 LSM6DSRX FSM_INT1_A (0Bh) 11.7 FSM_INT1_A (0Bh) INT1 pin control register (r/w). Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals. Table 192. FSM_INT1_A register INT1_FSM8 INT1_FSM7 INT1_FSM6 INT1_FSM5 INT1_FSM4 INT1_FSM3 INT1_FSM2 INT1_FSM1 Table 193. FSM_INT1_A register description INT1_FSM8(1) INT1_FSM7(1) INT1_FSM6(1) INT1_FSM5(1) INT1_FSM4(1) INT1_FSM3(1) INT1_FSM2(1) INT1_FSM1(1) Routing of FSM8 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM7 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM6 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM5 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM4 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM3 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM2 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM1 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) 1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1. DS13007 - Rev 3 page 96/171 LSM6DSRX FSM_INT1_B (0Ch) 11.8 FSM_INT1_B (0Ch) INT1 pin control register (r/w). Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals. Table 194. FSM_INT1_B register INT1_FSM16 INT1_FSM15 INT1_FSM14 INT1_FSM13 INT1_FSM12 INT1_FSM11 INT1_FSM10 INT1_FSM9 Table 195. FSM_INT1_B register description INT1_FSM16(1) INT1_FSM15(1) INT1_FSM14(1) INT1_FSM13(1) INT1_FSM12(1) INT1_FSM11(1) INT1_FSM10(1) INT1_FSM9(1) Routing of FSM16 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM15 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM14 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM13 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM12 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM11 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM10 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of FSM9 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) 1. This bit is effective if the INT1_EMB_FUNC bit of MD1_CFG (5Eh) is set to 1. DS13007 - Rev 3 page 97/171 LSM6DSRX MLC_INT1 (0Dh) 11.9 MLC_INT1 (0Dh) INT1 pin control register (r/w). Each bit in this register enables a signal to be carried over INT1. The pin's output will supply the OR combination of the selected signals. Table 196. MLC_INT1 register INT1_MLC8 INT1_MLC7 INT1_MLC6 INT1_MLC5 INT1_MLC4 INT1_MLC3 INT1_MLC2 INT1_MLC1 Table 197. MLC_INT1 register description INT1_MLC8 INT1_MLC7 INT1_MLC6 INT1_MLC5 INT1_MLC4 INT1_MLC3 INT1_MLC2 INT1_MLC1 DS13007 - Rev 3 Routing of MLC8 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC7 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC6 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC5 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC4 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC3 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC2 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) Routing of MLC1 interrupt event on INT1. Default value: 0 (0: routing on INT1 disabled; 1: routing on INT1 enabled) page 98/171 LSM6DSRX EMB_FUNC_INT2 (0Eh) 11.10 EMB_FUNC_INT2 (0Eh) INT2 pin control register (r/w). Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals. Table 198. EMB_FUNC_INT2 register INT2_ FSM_LC 0(1) INT2_ SIG_MOT INT2_TILT INT2_STEP_ DETECTOR 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 199. EMB_FUNC_INT2 register description INT2_FSM_LC(1) INT2_SIG_MOT(1) INT2_TILT(1) INT2_STEP_DETECTOR(1) Routing of FSM long counter timeout interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of significant motion event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of tilt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of pedometer step recognition event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) 1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1. DS13007 - Rev 3 page 99/171 LSM6DSRX FSM_INT2_A (0Fh) 11.11 FSM_INT2_A (0Fh) INT2 pin control register (r/w). Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals. Table 200. FSM_INT2_A register INT2_FSM8 INT2_FSM7 INT2_FSM6 INT2_FSM5 INT2_FSM4 INT2_FSM3 INT2_FSM2 INT2_FSM1 Table 201. FSM_INT2_A register description INT2_FSM8(1) INT2_FSM7(1) INT2_FSM6(1) INT2_FSM5(1) INT2_FSM4(1) Routing of FSM8 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM7 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM6 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM5 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM4 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM3 interrupt event on INT2. Default value: 0 INT2_FSM3(1) (0: routing on INT2 disabled; 1: routing on INT2 enabled) (0: routing on INT1 disabled; 1: routing on INT1 enabled) INT2_FSM2(1) INT2_FSM1(1) Routing of FSM2 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM1 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) 1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1. DS13007 - Rev 3 page 100/171 LSM6DSRX FSM_INT2_B (10h) 11.12 FSM_INT2_B (10h) INT2 pin control register (r/w). Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals. Table 202. FSM_INT2_B register INT2_FSM16 INT2_FSM15 INT2_FSM14 INT2_FSM13 INT2_FSM12 INT2_FSM11 INT2_FSM10 INT2_FSM9 Table 203. FSM_INT2_B register description INT2_FSM16(1) INT2_FSM15(1) INT2_FSM14(1) INT2_FSM13(1) INT2_FSM12(1) Routing of FSM16 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM15 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM14 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM13 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM12 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM11 interrupt event on INT2. Default value: 0 INT2_FSM11(1) (0: routing on INT2 disabled; 1: routing on INT2 enabled) (0: routing on INT1 disabled; 1: routing on INT1 enabled) INT2_FSM10(1) INT2_FSM9(1) Routing of FSM10 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of FSM9 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) 1. This bit is effective if the INT2_EMB_FUNC bit of MD2_CFG (5Fh) is set to 1. DS13007 - Rev 3 page 101/171 LSM6DSRX MLC_INT2 (11h) 11.13 MLC_INT2 (11h) INT2 pin control register (r/w). Each bit in this register enables a signal to be carried over INT2. The pin's output will supply the OR combination of the selected signals. Table 204. MLC_INT2 register INT2_MLC8 INT2_MLC7 INT2_MLC6 INT2_MLC5 INT2_MLC4 INT2_MLC3 INT2_MLC2 INT2_MLC1 Table 205. MLC_INT2 register description INT2_MLC8 INT2_MLC7 INT2_MLC6 INT2_MLC5 INT2_MLC4 INT2_MLC3 INT2_MLC2 INT2_MLC1 DS13007 - Rev 3 Routing of MLC8 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC7 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC6 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC5 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC4 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC3 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC2 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) Routing of MLC1 interrupt event on INT2. Default value: 0 (0: routing on INT2 disabled; 1: routing on INT2 enabled) page 102/171 LSM6DSRX EMB_FUNC_STATUS (12h) 11.14 EMB_FUNC_STATUS (12h) Embedded function status register (r) Table 206. EMB_FUNC_STATUS register IS_FSM_LC 0 IS_SIGMOT IS_TILT IS_STEP_DET 0 0 0 IS_FSM2 IS_FSM1 Table 207. EMB_FUNC_STATUS register description IS_FSM_LC IS_SIGMOT IS_TILT IS_STEP_DET 11.15 Interrupt status bit for FSM long counter timeout interrupt event. (1: interrupt detected; 0: no interrupt) Interrupt status bit for significant motion detection (1: interrupt detected; 0: no interrupt) Interrupt status bit for tilt detection (1: interrupt detected; 0: no interrupt) Interrupt status bit for step detection (1: interrupt detected; 0: no interrupt) FSM_STATUS_A (13h) Finite State Machine status register (r) Table 208. FSM_STATUS_A register IS_FSM8 IS_FSM7 IS_FSM6 IS_FSM5 IS_FSM4 IS_FSM3 Table 209. FSM_STATUS_A register description DS13007 - Rev 3 IS_FSM8 Interrupt status bit for FSM8 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM7 Interrupt status bit for FSM7 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM6 Interrupt status bit for FSM6 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM5 Interrupt status bit for FSM5 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM4 Interrupt status bit for FSM4 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM3 Interrupt status bit for FSM3 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM2 Interrupt status bit for FSM2 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM1 Interrupt status bit for FSM1 interrupt event. (1: interrupt detected; 0: no interrupt) page 103/171 LSM6DSRX FSM_STATUS_B (14h) 11.16 FSM_STATUS_B (14h) Finite State Machine status register (r) Table 210. FSM_STATUS_B register IS_FSM16 IS_FSM15 IS_FSM14 IS_FSM13 IS_FSM12 IS_FSM11 IS_FSM10 IS_FSM9 Table 211. FSM_STATUS_B register description 11.17 IS_FSM16 Interrupt status bit for FSM16 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM15 Interrupt status bit for FSM15 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM14 Interrupt status bit for FSM14 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM13 Interrupt status bit for FSM13 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM12 Interrupt status bit for FSM12 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM11 Interrupt status bit for FSM11 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM10 Interrupt status bit for FSM10 interrupt event. (1: interrupt detected; 0: no interrupt) IS_FSM9 Interrupt status bit for FSM9 interrupt event. (1: interrupt detected; 0: no interrupt) MLC_STATUS (15h) Machine Learning Core status register (r) Table 212. MLC_STATUS register IS_MLC8 IS_MLC7 IS_MLC6 IS_MLC5 IS_MLC4 IS_MLC3 IS_MLC2 IS_MLC1 Table 213. MLC_STATUS register description DS13007 - Rev 3 IS_MLC8 Interrupt status bit for MLC8 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC7 Interrupt status bit for MLC7 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC6 Interrupt status bit for MLC6 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC5 Interrupt status bit for MLC5 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC4 Interrupt status bit for MLC4 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC3 Interrupt status bit for MLC3 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC2 Interrupt status bit for MLC2 interrupt event. (1: interrupt detected; 0: no interrupt) IS_MLC1 Interrupt status bit for MLC1 interrupt event. (1: interrupt detected; 0: no interrupt) page 104/171 LSM6DSRX PAGE_RW (17h) 11.18 PAGE_RW (17h) Enable read and write mode of advanced features dedicated page (r/w) Table 214. PAGE_RW register EMB_ FUNC_LIR PAGE_ WRITE PAGE_ READ 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 215. PAGE_RW register description Latched Interrupt mode for Embedded Functions. Default value: 0 EMB_FUNC_LIR (0: Embedded Functions interrupt request not latched; 1: Embedded Functions interrupt request latched) Enable writes to the selected advanced features dedicated page.(1) PAGE_WRITE Default value: 0 (1: enable; 0: disable) Enable reads from the selected advanced features dedicated page.(1) PAGE_READ Default value: 0 (1: enable; 0: disable) 1. Page selected by PAGE_SEL[3:0] in register PAGE_SEL (02h). 11.19 EMB_FUNC_FIFO_CFG (44h) Embedded functions batching configuration register (r/w) Table 216. EMB_FUNC_FIFO_CFG register 0(1) PEDO_ FIFO_EN 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 217. EMB_FUNC_FIFO_CFG register description PEDO_FIFO_EN DS13007 - Rev 3 Enable FIFO batching of step counter values. Default value: 0 page 105/171 LSM6DSRX FSM_ENABLE_A (46h) 11.20 FSM_ENABLE_A (46h) FSM enable register (r/w) Table 218. FSM_ENABLE_A register FSM8_EN FSM7_EN FSM6_EN FSM5_EN FSM4_EN FSM3_EN FSM2_EN FSM1_EN FSM10_EN FSM9_EN Table 219. FSM_ENABLE_A register description 11.21 FSM8_EN FSM8 enable. Default value: 0 (0: FSM8 disabled; 1: FSM8 enabled) FSM7_EN FSM7 enable. Default value: 0 (0: FSM7 disabled; 1: FSM7 enabled) FSM6_EN FSM6 enable. Default value: 0 (0: FSM6 disabled; 1: FSM6 enabled) FSM5_EN FSM5 enable. Default value: 0 (0: FSM5 disabled; 1: FSM5 enabled) FSM4_EN FSM4 enable. Default value: 0 (0: FSM4 disabled; 1: FSM4 enabled) FSM3_EN FSM3 enable. Default value: 0 (0: FSM3 disabled; 1: FSM3 enabled) FSM2_EN FSM2 enable. Default value: 0 (0: FSM2 disabled; 1: FSM2 enabled) FSM1_EN FSM1 enable. Default value: 0 (0: FSM1 disabled; 1: FSM1 enabled) FSM_ENABLE_B (47h) FSM enable register (r/w) Table 220. FSM_ENABLE_B register FSM16_EN FSM15_EN FSM14_EN FSM13_EN FSM12_EN FSM11_EN Table 221. FSM_ENABLE_B register description DS13007 - Rev 3 FSM16_EN FSM16 enable. Default value: 0 (0: FSM16 disabled; 1: FSM16 enabled) FSM15_EN FSM15 enable. Default value: 0 (0: FSM15 disabled; 1: FSM15 enabled) FSM14_EN FSM14 enable. Default value: 0 (0: FSM14 disabled; 1: FSM14 enabled) FSM13_EN FSM13 enable. Default value: 0 (0: FSM13 disabled; 1: FSM13 enabled) FSM12_EN FSM12 enable. Default value: 0 (0: FSM12 disabled; 1: FSM12 enabled) FSM11_EN FSM11 enable. Default value: 0 (0: FSM11 disabled; 1: FSM11 enabled) FSM10_EN FSM10 enable. Default value: 0 (0: FSM10 disabled; 1: FSM10 enabled) FSM9_EN FSM9 enable. Default value: 0 (0: FSM9 disabled; 1: FSM9 enabled) page 106/171 LSM6DSRX FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) 11.22 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) FSM long counter status register (r/w). Long counter value is an unsigned integer value (16-bit format); this value can be reset using the LC_CLEAR bit in FSM_LONG_COUNTER_CLEAR (4Ah) register. Table 222. FSM_LONG_COUNTER_L register FSM_LC_7 FSM_LC_6 FSM_LC_5 FSM_LC_4 FSM_LC_3 FSM_LC_2 FSM_LC_1 FSM_LC_0 FSM_LC_9 FSM_LC_8 FSM_LC_ CLEARED FSM_LC_ CLEAR Table 223. FSM_LONG_COUNTER_L register description FSM_LC_[7:0] Long counter current value (LSbyte). Default value: 00000000 Table 224. FSM_LONG_COUNTER_H register FSM_LC_15 FSM_LC_14 FSM_LC_13 FSM_LC_12 FSM_LC_11 FSM_LC_10 Table 225. FSM_LONG_COUNTER_H register description FSM_LC_[15:8] 11.23 Long counter current value (MSbyte). Default value: 00000000 FSM_LONG_COUNTER_CLEAR (4Ah) FSM long counter reset register (r/w) Table 226. FSM_LONG_COUNTER_CLEAR register 0(1) 0(1) 0(1) 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 227. FSM_LONG_COUNTER_CLEAR register description DS13007 - Rev 3 FSM_LC_CLEARED This read-only bit is automatically set to 1 when the long counter reset is done. Default value: 0 FSM_LC_CLEAR Clear FSM long counter value. Default value: 0 page 107/171 LSM6DSRX FSM_OUTS1 (4Ch) 11.24 FSM_OUTS1 (4Ch) FSM1 output register (r) Table 228. FSM_OUTS1 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 229. FSM_OUTS1 register description 11.25 P_X FSM1 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM1 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM1 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM1 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM1 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM1 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM1 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM1 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS2 (4Dh) FSM2 output register (r) Table 230. FSM_OUTS2 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 231. FSM_OUTS2 register description DS13007 - Rev 3 P_X FSM2 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM2 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM2 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM2 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM2 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM2 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM2 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM2 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 108/171 LSM6DSRX FSM_OUTS3 (4Eh) 11.26 FSM_OUTS3 (4Eh) FSM3 output register (r) Table 232. FSM_OUTS3 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 233. FSM_OUTS3 register description 11.27 P_X FSM3 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM3 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM3 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM3 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM3 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM3 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM3 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM3 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS4 (4Fh) FSM4 output register (r) Table 234. FSM_OUTS4 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 235. FSM_OUTS4 register description DS13007 - Rev 3 P_X FSM4 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM4 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM4 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM4 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM4 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM4 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM4 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM4 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 109/171 LSM6DSRX FSM_OUTS5 (50h) 11.28 FSM_OUTS5 (50h) FSM5 output register (r) Table 236. FSM_OUTS5 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 237. FSM_OUTS5 register description 11.29 P_X FSM5 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM5 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM5 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM5 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM5 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM5 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM5 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM5 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS6 (51h) FSM6 output register (r) Table 238. FSM_OUTS6 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 239. FSM_OUTS6 register description DS13007 - Rev 3 P_X FSM6 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM6 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM6 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM6 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM6 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM6 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM6 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM6 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 110/171 LSM6DSRX FSM_OUTS7 (52h) 11.30 FSM_OUTS7 (52h) FSM7 output register (r) Table 240. FSM_OUTS7 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 241. FSM_OUTS7 register description 11.31 P_X FSM7 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM7 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM7 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM7 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM7 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM7 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM7 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM7 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS8 (53h) FSM8 output register (r) Table 242. FSM_OUTS8 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 243. FSM_OUTS8 register description DS13007 - Rev 3 P_X FSM8 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM8 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM8 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM8 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM8 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM8 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM8 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM8 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 111/171 LSM6DSRX FSM_OUTS9 (54h) 11.32 FSM_OUTS9 (54h) FSM9 output register (r) Table 244. FSM_OUTS9 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 245. FSM_OUTS9 register description 11.33 P_X FSM9 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM9 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM9 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM9 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM9 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM9 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM9 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM9 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS10 (55h) FSM10 output register (r) Table 246. FSM_OUTS10 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 247. FSM_OUTS10 register description DS13007 - Rev 3 P_X FSM10 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM10 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM10 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM10 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM10 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM10 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM10 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM10 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 112/171 LSM6DSRX FSM_OUTS11 (56h) 11.34 FSM_OUTS11 (56h) FSM11 output register (r) Table 248. FSM_OUTS11 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 249. FSM_OUTS11 register description 11.35 P_X FSM11 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM11 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM11 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM11 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM11 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM11 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM11 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM11 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS12 (57h) FSM12 output register (r) Table 250. FSM_OUTS12 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 251. FSM_OUTS12 register description DS13007 - Rev 3 P_X FSM12 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM12 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM12 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM12 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM12 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM12 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM12 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM12 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 113/171 LSM6DSRX FSM_OUTS13 (58h) 11.36 FSM_OUTS13 (58h) FSM13 output register (r) Table 252. FSM_OUTS13 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 253. FSM_OUTS13 register description 11.37 P_X FSM13 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM13 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM13 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM13 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM13 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM13 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM13 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM13 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS14 (59h) FSM14 output register (r) Table 254. FSM_OUTS14 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 255. FSM_OUTS14 register description DS13007 - Rev 3 P_X FSM14 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM14 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM14 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM14 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM14 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM14 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM14 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM14 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 114/171 LSM6DSRX FSM_OUTS15 (5Ah) 11.38 FSM_OUTS15 (5Ah) FSM15 output register (r) Table 256. FSM_OUTS15 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 257. FSM_OUTS15 register description 11.39 P_X FSM15 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM15 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM15 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM15 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM15 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM15 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM15 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM15 output: negative event detected on the vector. (0: event not detected; 1: event detected) FSM_OUTS16 (5Bh) FSM16 output register (r) Table 258. FSM_OUTS16 register P_X N_X P_Y N_Y P_Z N_Z P_V N_V Table 259. FSM_OUTS16 register description DS13007 - Rev 3 P_X FSM16 output: positive event detected on the X-axis. (0: event not detected; 1: event detected) N_X FSM16 output: negative event detected on the X-axis. (0: event not detected; 1: event detected) P_Y FSM16 output: positive event detected on the Y-axis. (0: event not detected; 1: event detected) N_Y FSM16 output: negative event detected on the Y-axis. (0: event not detected; 1: event detected) P_Z FSM16 output: positive event detected on the Z-axis. (0: event not detected; 1: event detected) N_Z FSM16 output: negative event detected on the Z-axis. (0: event not detected; 1: event detected) P_V FSM16 output: positive event detected on the vector. (0: event not detected; 1: event detected) N_V FSM16 output: negative event detected on the vector. (0: event not detected; 1: event detected) page 115/171 LSM6DSRX EMB_FUNC_ODR_CFG_B (5Fh) 11.40 EMB_FUNC_ODR_CFG_B (5Fh) Finite State Machine output data rate configuration register (r/w) Table 260. EMB_FUNC_ODR_CFG_B register 0(1) 1(2) 0(1) FSM_ODR1 FSM_ODR0 0(1) 1(2) 1(2) 0(1) 1(2) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device Table 261. EMB_FUNC_ODR_CFG_B register description Finite State Machine ODR configuration: (00: 12.5 Hz; FSM_ODR[1:0] 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) 11.41 EMB_FUNC_ODR_CFG_C (60h) Machine Learning Core output data rate configuration register (r/w) Table 262. EMB_FUNC_ODR_CFG_C register 0(1) 0(1) MLC_ODR1 MLC_ODR0 0(1) 1(2) 1. This bit must be set to '0' for the correct operation of the device. 2. This bit must be set to '1' for the correct operation of the device. Table 263. EMB_FUNC_ODR_CFG_C register description Machine Learning Core ODR configuration: (00: 12.5 Hz; MLC_ODR[1:0] 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) DS13007 - Rev 3 page 116/171 LSM6DSRX STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) 11.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) Step counter output register (r) Table 264. STEP_COUNTER_L register STEP_7 STEP_6 STEP_5 STEP_4 STEP_3 STEP_2 STEP_1 STEP_0 STEP_9 STEP_8 Table 265. STEP_COUNTER_L register description STEP_[7:0] Step counter output (LSbyte) Table 266. STEP_COUNTER_H register STEP_15 STEP_14 STEP_13 STEP_12 STEP_11 STEP_10 Table 267. STEP_COUNTER_H register description STEP_[15:8] DS13007 - Rev 3 Step counter output (MSbyte) page 117/171 LSM6DSRX EMB_FUNC_SRC (64h) 11.43 EMB_FUNC_SRC (64h) Embedded function source register (r/w) Table 268. EMB_FUNC_SRC register PEDO_ RST_STEP 0(1) STEP_ DETECTED STEP_COUNT _DELTA_IA STEP_ OVERFLOW STEPCOUNTER _BIT_SET 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 269. EMB_FUNC_SRC register description Reset pedometer step counter. Read/write bit. PEDO_RST_STEP (0: disabled; 1: enabled) Step detector event detection status. Read-only bit. STEP_DETECTED (0: step detection event not detected; 1: step detection event detected) Pedometer step recognition on delta time status. Read-only bit. STEP_COUNT_DELTA_IA (0: no step recognized during delta time; 1: at least one step recognized during delta time) Step counter overflow status. Read-only bit. STEP_OVERFLOW (0: step counter value < 216; 1: step counter value reached 216) STEPCOUNTER_BIT_SET 11.44 This bit is equal to 1 when the step count is increased. Read-only bit. EMB_FUNC_INIT_A (66h) Embedded functions initialization register (r/w) Table 270. EMB_FUNC_INIT_A register 0(1) 0(1) SIG_MOT _INIT TILT_INIT STEP_DET _INIT 0(1) 0(1) 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 271. EMB_FUNC_INIT_A register description DS13007 - Rev 3 SIG_MOT_INIT Significant Motion Detection algorithm initialization request. Default value: 0 TILT_INIT Tilt algorithm initialization request. Default value: 0 STEP_DET_INIT Pedometer Step Counter/Detector algorithm initialization request. Default value: 0 page 118/171 LSM6DSRX EMB_FUNC_INIT_B (67h) 11.45 EMB_FUNC_INIT_B (67h) Embedded functions initialization register (r/w) Table 272. EMB_FUNC_INIT_B register 0(1) 0(1) 0(1) MLC_INIT FIFO_ COMPR_INIT 0(1) 0(1) FSM_INIT MLC0_ SRC_1 MLC0_ SRC_0 MLC1_ SRC_1 MLC1_ SRC_0 1. This bit must be set to '0' for the correct operation of the device. Table 273. EMB_FUNC_INIT_B register description 11.46 MLC_INIT Machine Learning Core initialization request. Default value: 0 FIFO_COMPR_INIT FIFO compression feature initialization request. Default value: 0 FSM_INIT FSM initialization request. Default value: 0 MLC0_SRC (70h) Machine Learning Core source register (r) Table 274. MLC0_SRC register MLC0_ SRC_7 MLC0_ SRC_6 MLC0_ SRC_5 MLC0_ SRC_4 MLC0_ SRC_3 MLC0_ SRC_2 Table 275. MLC0_SRC register description MLC0_SRC_[7:0] 11.47 Output value of MLC0 decision tree MLC1_SRC (71h) Machine Learning Core source register (r) Table 276. MLC1_SRC register MLC1_ SRC_7 MLC1_ SRC_6 MLC1_ SRC_5 MLC1_ SRC_4 MLC1_ SRC_3 MLC1_ SRC_2 Table 277. MLC1_SRC register description MLC1_SRC_[7:0] DS13007 - Rev 3 Output value of MLC1 decision tree page 119/171 LSM6DSRX MLC2_SRC (72h) 11.48 MLC2_SRC (72h) Machine Learning Core source register (r) Table 278. MLC2_SRC register MLC2_ SRC_7 MLC2_ SRC_6 MLC2_ SRC_5 MLC2_ SRC_4 MLC2_ SRC_3 MLC2_ SRC_2 MLC2_ SRC_1 MLC2_ SRC_0 MLC3_ SRC_1 MLC3_ SRC_0 MLC4_ SRC_1 MLC4_ SRC_0 MLC5_ SRC_1 MLC5_ SRC_0 Table 279. MLC2_SRC register description MLC2_SRC_[7:0] 11.49 Output value of MLC2 decision tree MLC3_SRC (73h) Machine Learning Core source register (r) Table 280. MLC3_SRC register MLC3_ SRC_7 MLC3_ SRC_6 MLC3_ SRC_5 MLC3_ SRC_4 MLC3_ SRC_3 MLC3_ SRC_2 Table 281. MLC3_SRC register description MLC3_SRC_[7:0] 11.50 Output value of MLC3 decision tree MLC4_SRC (74h) Machine Learning Core source register (r) Table 282. MLC4_SRC register MLC4_ SRC_7 MLC4_ SRC_6 MLC4_ SRC_5 MLC4_ SRC_4 MLC4_ SRC_3 MLC4_ SRC_2 Table 283. MLC4_SRC register description MLC4_SRC_[7:0] 11.51 Output value of MLC4 decision tree MLC5_SRC (75h) Machine Learning Core source register (r) Table 284. MLC5_SRC register MLC5_ SRC_7 MLC5_ SRC_6 MLC5_ SRC_5 MLC5_ SRC_4 MLC5_ SRC_3 MLC5_ SRC_2 Table 285. MLC5_SRC register description MLC5_SRC_[7:0] DS13007 - Rev 3 Output value of MLC5 decision tree page 120/171 LSM6DSRX MLC6_SRC (76h) 11.52 MLC6_SRC (76h) Machine Learning Core source register (r) Table 286. MLC6_SRC register MLC6_ SRC_7 MLC6_ SRC_6 MLC6_ SRC_5 MLC6_ SRC_4 MLC6_ SRC_3 MLC6_ SRC_2 MLC6_ SRC_1 MLC6_ SRC_0 MLC7_ SRC_1 MLC7_ SRC_0 Table 287. MLC6_SRC register description MLC6_SRC_[7:0] 11.53 Output value of MLC6 decision tree MLC7_SRC (77h) Machine Learning Core source register (r) Table 288. MLC7_SRC register MLC7_ SRC_7 MLC7_ SRC_6 MLC7_ SRC_5 MLC7_ SRC_4 MLC7_ SRC_3 MLC7_ SRC_2 Table 289. MLC7_SRC register description MLC7_SRC_[7:0] DS13007 - Rev 3 Output value of MLC7 decision tree page 121/171 LSM6DSRX Embedded advanced features pages 12 Embedded advanced features pages The table given below provides a list of the registers for the embedded advanced features page 0. These registers are accessible when PAGE_SEL[3:0] are set to 0000 in PAGE_SEL (02h). Table 290. Register address map - embedded advanced features page 0 Name Type Register address Hex Binary 10111010 Default MAG_SENSITIVITY_L RW BA MAG_SENSITIVITY_H RW BB 10111011 00010110 MAG_OFFX_L RW C0 11000000 00000000 MAG_OFFX_H RW C1 11000001 00000000 MAG_OFFY_L RW C2 11000010 00000000 MAG_OFFY_H RW C3 11000011 00000000 MAG_OFFZ_L RW C4 11000100 00000000 MAG_OFFZ_H RW C5 11000101 00000000 MAG_SI_XX_L RW C6 11000110 00000000 MAG_SI_XX_H RW C7 11000111 00111100 MAG_SI_XY_L RW C8 11001000 00000000 MAG_SI_XY_H RW C9 11001001 00000000 MAG_SI_XZ_L RW CA 11001010 00000000 MAG_SI_XZ_H RW CB 11001011 00000000 MAG_SI_YY_L RW CC 11001100 00000000 MAG_SI_YY_H RW CD 11001101 00111100 MAG_SI_YZ_L RW CE 11001110 00000000 MAG_SI_YZ_H RW CF 11001111 00000000 MAG_SI_ZZ_L RW D0 11010000 00000000 MAG_SI_ZZ_H RW D1 11010001 00111100 MAG_CFG_A RW D4 11010100 00000101 MAG_CFG_B RW D5 11010101 00000010 Comment 00100100 The following table provides a list of the registers for the embedded advanced features page 1. These registers are accessible when PAGE_SEL[3:0] are set to 0001 in PAGE_SEL (02h). DS13007 - Rev 3 page 122/171 LSM6DSRX Embedded advanced features pages Table 291. Register address map - embedded advanced features page 1 Name Type Register address Hex Binary Default FSM_LC_TIMEOUT_L RW 7A 01111010 00000000 FSM_LC_TIMEOUT_H RW 7B 01111011 00000000 FSM_PROGRAMS RW 7C 01111100 00000000 FSM_START_ADD_L RW 7E 01111110 00000000 FSM_START_ADD_H RW 7F 01111111 00000000 PEDO_CMD_REG RW 83 10000011 00000000 PEDO_DEB_STEPS_CONF RW 84 10000100 00001010 PEDO_SC_DELTAT_L RW D0 11010000 00000000 PEDO_SC_DELTAT_H RW D1 11010001 00000000 MLC_MAG_SENSITIVITY_L RW E8 11101000 00000000 MLC_MAG_SENSITIVITY_H RW E9 11101001 00111100 Comment Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. Write procedure example: Example: write value 06h register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1 1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h) // Enable access to embedded functions registers 2. Write bit PAGE_WRITE = 1 in PAGE_RW (17h) register // Select write operation mode 3. Write 0001 in PAGE_SEL[3:0] field of register PAGE_SEL (02h) // Select page 1 4. Write 84h in PAGE_ADDR register (08h) // Set address 5. Write 06h in PAGE_DATA register (09h) // Set value to be written 6. Write bit PAGE_WRITE = 0 in PAGE_RW (17h) register // Write operation disabled 7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h) // Disable access to embedded functions registers Read procedure example: Example: read value of register at address 84h (PEDO_DEB_STEPS_CONF) in Page 1 DS13007 - Rev 3 1. Write bit FUNC_CFG_EN = 1 in FUNC_CFG_ACCESS (01h) // Enable access to embedded functions registers 2. Write bit PAGE_READ = 1 in PAGE_RW (17h) register // Select read operation mode 3. Write 0001 in PAGE_SEL[3:0] field // Select page 1 page 123/171 LSM6DSRX Embedded advanced features pages of register PAGE_SEL (02h) 4. Write 84h in PAGE_ADDR register (08h) // Set address 5. Read value of PAGE_DATA register (09h) // Get register value 6. Write bit PAGE_READ = 0 in PAGE_RW (17h) register // Read operation disabled 7. Write bit FUNC_CFG_EN = 0 in FUNC_CFG_ACCESS (01h) // Disable access to embedded functions registers Note: Steps 1 and 2 of both procedures are intended to be performed at the beginning of the procedure. Steps 6 and 7 of both procedures are intended to be performed at the end of the procedure. If the procedure involves multiple operations, only steps 3, 4 and 5 must be repeated for each operation. If, in particular, multiple operations involve consecutive registers, only step 5 can be performed. DS13007 - Rev 3 page 124/171 LSM6DSRX Embedded advanced features register description 13 Embedded advanced features register description 13.1 Page 0 - Embedded advanced features registers 13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) External magnetometer sensitivity value register for the Finite State Machine (r/w). This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value of MAG_SENS[15:0] is 0x1624, corresponding to 0.0015 gauss/LSB. Table 292. MAG_SENSITIVITY_L register MAG_ SENS_7 MAG_ SENS_6 MAG_ SENS_5 MAG_ SENS_4 MAG_ SENS_3 MAG_ SENS_2 MAG_ SENS_1 MAG_ SENS_0 MAG_ SENS_9 MAG_ SENS_8 Table 293. MAG_SENSITIVITY_L register description MAG_SENS_[7:0] External magnetometer sensitivity (LSbyte). Default value: 00100100 Table 294. MAG_SENSITIVITY_H register MAG_ SENS_15 MAG_ SENS_14 MAG_ SENS_13 MAG_ SENS_12 MAG_ SENS_11 MAG_ SENS_10 Table 295. MAG_SENSITIVITY_H register description MAG_SENS_[15:8] DS13007 - Rev 3 External magnetometer sensitivity (MSbyte). Default value: 00010110 page 125/171 LSM6DSRX Page 0 - Embedded advanced features registers 13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h) Offset for X-axis hard-iron compensation register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 296. MAG_OFFX_L register MAG_ OFFX_7 MAG_ OFFX_6 MAG_ OFFX_5 MAG_ OFFX_4 MAG_ OFFX_3 MAG_ OFFX_2 MAG_ OFFX_1 MAG_ OFFX_0 Table 297. MAG_OFFX_L register description MAG_OFFX_[7:0] Offset for X-axis hard-iron compensation (LSbyte). Default value: 00000000 Table 298. MAG_OFFX_H register MAG_ OFFX_15 MAG_ OFFX_14 MAG_ OFFX_13 MAG_ OFFX_12 MAG_ OFFX_11 MAG_ OFFX_10 MAG_ OFFX_9 MAG_ OFFX_8 Table 299. MAG_OFFX_H register description MAG_OFFX_[15:8] 13.1.3 Offset for X-axis hard-iron compensation (MSbyte). Default value: 00000000 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h) Offset for Y-axis hard-iron compensation register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 300. MAG_OFFY_L register MAG_ OFFY_7 MAG_ OFFY_6 MAG_ OFFY_5 MAG_ OFFY_4 MAG_ OFFY_3 MAG_ OFFY_2 MAG_ OFFY_1 MAG_ OFFY_0 Table 301. MAG_OFFY_L register description MAG_OFFY_[7:0] Offset for Y-axis hard-iron compensation (LSbyte). Default value: 00000000 Table 302. MAG_OFFY_H register MAG_ OFFY_15 MAG_ OFFY_14 MAG_ OFFY_13 MAG_ OFFY_12 MAG_ OFFY_11 MAG_ OFFY_10 MAG_ OFFY_9 MAG_ OFFY_8 Table 303. MAG_OFFY_H register description MAG_OFFY_[15:8] DS13007 - Rev 3 Offset for Y-axis hard-iron compensation (MSbyte). Default value: 00000000 page 126/171 LSM6DSRX Page 0 - Embedded advanced features registers 13.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) Offset for Z-axis hard-iron compensation register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 304. MAG_OFFZ_L register MAG_ OFFZ_7 MAG_ OFFZ_6 MAG_ OFFZ_5 MAG_ OFFZ_4 MAG_ OFFZ_3 MAG_ OFFZ_2 MAG_ OFFZ_1 MAG_ OFFZ_0 Table 305. MAG_OFFZ_L register description MAG_OFFZ_[7:0] Offset for Z-axis hard-iron compensation (LSbyte). Default value: 00000000 Table 306. MAG_OFFZ_H register MAG_ OFFZ_15 MAG_ OFFZ_14 MAG_ OFFZ_13 MAG_ OFFZ_12 MAG_ OFFZ_11 MAG_ OFFZ_10 MAG_ OFFZ_9 MAG_ OFFZ_8 Table 307. MAG_OFFZ_H register description MAG_OFFZ_[15:8] 13.1.5 Offset for Z-axis hard-iron compensation (MSbyte). Default value: 00000000 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) Soft-iron (3x3 symmetric) matrix correction register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 308. MAG_SI_XX_L register MAG_SI_ XX_7 MAG_SI_ XX_6 MAG_SI_ XX_5 MAG_SI_ XX_4 MAG_SI_ XX_3 MAG_SI_ XX_2 MAG_SI_ XX_1 MAG_SI_ XX_0 Table 309. MAG_SI_XX_L register description MAG_SI_XX_[7:0] Soft-iron correction row1 col1 coefficient (LSbyte). Default value: 00000000 Table 310. MAG_SI_XX_H register MAG_SI_ XX_15 MAG_SI_ XX_14 MAG_SI_ XX_13 MAG_SI_ XX_12 MAG_SI_ XX_11 MAG_SI_ XX_10 MAG_SI_ XX_9 MAG_SI_ XX_8 Table 311. MAG_SI_XX_H register description MAG_SI_XX_[15:8] DS13007 - Rev 3 Soft-iron correction row1 col1 coefficient (MSbyte). Default value: 00111100 page 127/171 LSM6DSRX Page 0 - Embedded advanced features registers 13.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) Soft-iron (3x3 symmetric) matrix correction register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 312. MAG_SI_XY_L register MAG_SI_ XY_7 MAG_SI_ XY_6 MAG_SI_ XY_5 MAG_SI_ XY_4 MAG_SI_ XY_3 MAG_SI_ XY_2 MAG_SI_ XY_1 MAG_SI_ XY_0 Table 313. MAG_SI_XY_L register description MAG_SI_XY_[7:0] Soft-iron correction row1 col2 (and row2 col1) coefficient (LSbyte). Default value: 00000000 Table 314. MAG_SI_XY_H register MAG_SI_ XY_15 MAG_SI_ XY_14 MAG_SI_ XY_13 MAG_SI_ XY_12 MAG_SI_ XY_11 MAG_SI_ XY_10 MAG_SI_ XY_9 MAG_SI_ XY_8 Table 315. MAG_SI_XY_H register description MAG_SI_XY_[15:8] 13.1.7 Soft-iron correction row1 col2 (and row2 col1) coefficient (MSbyte). Default value: 00000000 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) Soft-iron (3x3 symmetric) matrix correction register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 316. MAG_SI_XZ_L register MAG_SI_ XZ_7 MAG_SI_ XZ_6 MAG_SI_ XZ_5 MAG_SI_ XZ_4 MAG_SI_ XZ_3 MAG_SI_ XZ_2 MAG_SI_ XZ_1 MAG_SI_ XZ_0 Table 317. MAG_SI_XZ_L register description MAG_SI_XZ_[7:0] Soft-iron correction row1 col3 (and row3 col1) coefficient (LSbyte). Default value: 00000000 Table 318. MAG_SI_XZ_H register MAG_SI_ XZ_15 MAG_SI_ XZ_14 MAG_SI_ XZ_13 MAG_SI_ XZ_12 MAG_SI_ XZ_11 MAG_SI_ XZ_10 MAG_SI_ XZ_9 MAG_SI_ XZ_8 Table 319. MAG_SI_XZ_H register description MAG_SI_XZ_[15:8] DS13007 - Rev 3 Soft-iron correction row1 col3 (and row3 col1) coefficient (MSbyte). Default value: 00000000 page 128/171 LSM6DSRX Page 0 - Embedded advanced features registers 13.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) Soft-iron (3x3 symmetric) matrix correction register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 320. MAG_SI_YY_L register MAG_SI_ YY_7 MAG_SI_ YY_6 MAG_SI_ YY_5 MAG_SI_ YY_4 MAG_SI_ YY_3 MAG_SI_ YY_2 MAG_SI_ YY_1 MAG_SI_ YY_0 Table 321. MAG_SI_YY_L register description MAG_SI_YY_[7:0] Soft-iron correction row2 col2 coefficient (LSbyte). Default value: 00000000 Table 322. MAG_SI_YY_H register MAG_SI_ YY_15 MAG_SI_ YY_14 MAG_SI_ YY_13 MAG_SI_ YY_12 MAG_SI_ YY_11 MAG_SI_ YY_10 MAG_SI_ YY_9 MAG_SI_ YY_8 Table 323. MAG_SI_YY_H register description MAG_SI_YY_[15:8] 13.1.9 Soft-iron correction row2 col2 coefficient (MSbyte). Default value: 00111100 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) Soft-iron (3x3 symmetric) matrix correction register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 324. MAG_SI_YZ_L register MAG_SI_ YZ_7 MAG_SI_ YZ_6 MAG_SI_ YZ_5 MAG_SI_ YZ_4 MAG_SI_ YZ_3 MAG_SI_ YZ_2 MAG_SI_ YZ_1 MAG_SI_ YZ_0 Table 325. MAG_SI_YZ_L register description MAG_SI_YZ_[7:0] Soft-iron correction row2 col3 (and row3 col2) coefficient (LSbyte). Default value: 00000000 Table 326. MAG_SI_YZ_H register MAG_SI_ YZ_15 MAG_SI_ YZ_14 MAG_SI_ YZ_13 MAG_SI_ YZ_12 MAG_SI_ YZ_11 MAG_SI_ YZ_10 MAG_SI_ YZ_9 MAG_SI_ YZ_8 Table 327. MAG_SI_YZ_H register description MAG_SI_YZ_[15:8] DS13007 - Rev 3 Soft-iron correction row2 col3 (and row3 col2) coefficient (MSbyte). Default value: 00000000 page 129/171 LSM6DSRX Page 0 - Embedded advanced features registers 13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) Soft-iron (3x3 symmetric) matrix correction register (r/w). The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Table 328. MAG_SI_ZZ_L register MAG_SI_ ZZ_7 MAG_SI_ ZZ_6 MAG_SI_ ZZ_5 MAG_SI_ ZZ_4 MAG_SI_ ZZ_3 MAG_SI_ ZZ_2 MAG_SI_ ZZ_1 MAG_SI_ ZZ_0 Table 329. MAG_SI_ZZ_L register description MAG_SI_ZZ_[7:0] Soft-iron correction row3 col3 coefficient (LSbyte). Default value: 00000000 Table 330. MAG_SI_ZZ_H register MAG_SI_ ZZ_15 MAG_SI_ ZZ_14 MAG_SI_ ZZ_13 MAG_SI_ ZZ_12 MAG_SI_ ZZ_11 MAG_SI_ ZZ_10 MAG_SI_ ZZ_9 MAG_SI_ ZZ_8 Table 331. MAG_SI_ZZ_H register description MAG_SI_ZZ_[15:8] DS13007 - Rev 3 Soft-iron correction row3 col3 coefficient (MSbyte). Default value: 00111100 page 130/171 LSM6DSRX Page 0 - Embedded advanced features registers 13.1.11 MAG_CFG_A (D4h) External magnetometer coordinates (Z and Y axes) rotation register (r/w) Table 332. MAG_CFG_A register 0(1) MAG_Y_ AXIS2 MAG_Y_ AXIS1 MAG_Y_ AXIS0 0(1) MAG_Z_ AXIS2 MAG_Z_ AXIS1 MAG_Z_ AXIS0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 333. MAG_CFG_A register description Magnetometer Y-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation) (000: Y = Y; (default) 001: Y = -Y; MAG_Y_AXIS[2:0] 010: Y = X; 011: Y = -X; 100: Y = -Z; 101: Y = Z; Others: Y = Y) Magnetometer Z-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation) (000: Z = Y; 001: Z = -Y; MAG_Z_AXIS[2:0] 010: Z = X; 011: Z = -X; 100: Z = -Z; 101: Z = Z; (default) Others: Z = Y) 13.1.12 MAG_CFG_B (D5h) External magnetometer coordinates (X-axis) rotation register (r/w) Table 334. MAG_CFG_B register 0(1) 0(1) 0(1) 0(1) 0(1) MAG_X_ AXIS2 MAG_X_ AXIS1 MAG_X_ AXIS0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 335. MAG_CFG_B register description Magnetometer X-axis coordinates rotation (to be aligned to accelerometer/gyroscope axes orientation) (000: X = Y; 001: X = -Y; MAG_X_AXIS[2:0] 010: X = X; (default) 011: X = -X; 100: X = -Z; 101: X = Z; Others: X = Y) DS13007 - Rev 3 page 131/171 LSM6DSRX Page 1 - Embedded advanced features registers 13.2 13.2.1 Page 1 - Embedded advanced features registers FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh) FSM long counter timeout register (r/w). The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reaches this value, the FSM generates an interrupt. Table 336. FSM_LC_TIMEOUT_L register FSM_LC_ TIMEOUT7 FSM_LC_ TIMEOUT6 FSM_LC_ TIMEOUT5 FSM_LC_ TIMEOUT4 FSM_LC_ TIMEOUT3 FSM_LC_ TIMEOUT2 FSM_LC_ TIMEOUT1 FSM_LC_ TIMEOUT0 Table 337. FSM_LC_TIMEOUT_L register description FSM_LC_TIMEOUT[7:0] FSM long counter timeout value (LSbyte). Default value: 00000000 Table 338. FSM_LC_TIMEOUT_H register FSM_LC_ TIMEOUT15 FSM_LC_ TIMEOUT14 FSM_LC_ TIMEOUT13 FSM_LC_ TIMEOUT12 FSM_LC_ TIMEOUT11 FSM_LC_ TIMEOUT10 FSM_LC_ TIMEOUT9 FSM_LC_ TIMEOUT8 Table 339. FSM_LC_TIMEOUT_H register description FSM_LC_TIMEOUT[15:8] 13.2.2 FSM long counter timeout value (MSbyte). Default value: 00000000 FSM_PROGRAMS (7Ch) FSM number of programs register (r/w) Table 340. FSM_PROGRAMS register FSM_N_ PROG7 FSM_N_ PROG6 FSM_N_ PROG5 FSM_N_ PROG4 FSM_N_ PROG3 FSM_N_ PROG2 FSM_N_ PROG1 FSM_N_ PROG0 Table 341. FSM_PROGRAMS register description FSM_N_PROG[7:0] DS13007 - Rev 3 Number of FSM programs; must be less than or equal to 16. Default value: 00000000 page 132/171 LSM6DSRX Page 1 - Embedded advanced features registers 13.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) FSM start address register (r/w). First available address is 0x033C. Table 342. FSM_START_ADD_L register FSM_ START7 FSM_ START6 FSM_ START5 FSM_ START4 FSM_ START3 FSM_ START2 FSM_ START1 FSM_ START0 FSM_ START9 FSM_ START8 0(1) 0(1) Table 343. FSM_START_ADD_L register description FSM_START[7:0] FSM start address value (LSbyte). Default value: 00000000 Table 344. FSM_START_ADD_H register FSM_ START15 FSM_ START14 FSM_ START13 FSM_ START12 FSM_ START11 FSM_ START10 Table 345. FSM_START_ADD_H register description FSM_START[15:8] 13.2.4 FSM start address value (MSbyte). Default value: 00000000 PEDO_CMD_REG (83h) Pedometer configuration register (r/w) Table 346. PEDO_CMD_REG register 0(1) 0(1) 0(1) 0(1) CARRY_ COUNT_EN 0(1) 1. This bit must be set to '0' for the correct operation of the device. Table 347. PEDO_CMD_REG register description CARRY_COUNT_EN 13.2.5 Set when user wants to generate interrupt only on count overflow event. PEDO_DEB_CONF (84h) Pedometer debounce configuration register (r/w) Table 348. PEDO_DEB_STEPS_CONF register DEB_ STEP7 DEB_ STEP6 DEB_ STEP5 DEB_ STEP4 DEB_ STEP3 DEB_ STEP2 DEB_ STEP1 DEB_ STEP0 Table 349. PEDO_DEB_STEPS_CONF register description DEB_STEP[7:0] DS13007 - Rev 3 Debounce threshold. Minimum number of steps to increment the step counter (debounce). Default value: 00001010 page 133/171 LSM6DSRX Page 1 - Embedded advanced features registers 13.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) Time period register for step detection on delta time (r/w) Table 350. PEDO_SC_DELTAT_L register PD_SC_7 PD_SC_6 PD_SC_5 PD_SC_4 PD_SC_3 PD_SC_2 PD_SC_1 PD_SC_0 PD_SC_9 PD_SC_8 Table 351. PEDO_SC_DELTAT_H register PD_SC_15 PD_SC_14 PD_SC_13 PD_SC_12 PD_SC_11 PD_SC_10 Table 352. PEDO_SC_DELTAT_H/L register description PD_SC_[15:0] 13.2.7 Time period value (1LSB = 6.4 ms) MLC_MAG_SENSITIVITY_L (E8h) and MLC_MAG_SENSITIVITY_H (E9h) External magnetometer sensitivity value register for the Machine Learning Core (r/w). This register corresponds to the LSB-to-gauss conversion value of the external magnetometer sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value of MLC_MAG_S_[15:0] is 0x3C00, corresponding to 1 gauss/ LSB. Table 353. MLC_MAG_SENSITIVITY_L register MLC_ MAG_S_7 MLC_ MAG_S_6 MLC_ MAG_S_5 MLC_ MAG_S_4 MLC_ MAG_S_3 MLC_ MAG_S_2 MLC_ MAG_S_1 MLC_ MAG_S_0 Table 354. MLC_MAG_SENSITIVITY_L register description MLC_MAG_S_[7:0] External magnetometer sensitivity (LSbyte). Default value: 00000000 Table 355. MLC_MAG_SENSITIVITY_H register MLC_ MAG_S_15 MLC_ MAG_S_14 MLC_ MAG_S_13 MLC_ MAG_S_12 MLC_ MAG_S_11 MLC_ MAG_S_10 MLC_ MAG_S_9 MLC_ MAG_S_8 Table 356. MLC_MAG_SENSITIVITY_H register description MLC_MAG_S_[15:8] DS13007 - Rev 3 External magnetometer sensitivity (MSbyte). Default value: 00111100 page 134/171 LSM6DSRX Sensor hub register mapping 14 Sensor hub register mapping The table given below provides a list of the registers for the sensor hub functions available in the device and the corresponding addresses. The sensor hub registers are accessible when bit SHUB_REG_ACCESS is set to '1' in FUNC_CFG_ACCESS (01h). Table 357. Registers address map Name DS13007 - Rev 3 Type Register address Hex Binary Default SENSOR_HUB_1 R 02 00000010 output SENSOR_HUB_2 R 03 00000011 output SENSOR_HUB_3 R 04 00000100 output SENSOR_HUB_4 R 05 00000101 output SENSOR_HUB_5 R 06 00000110 output SENSOR_HUB_6 R 07 00000111 output SENSOR_HUB_7 R 08 00001000 output SENSOR_HUB_8 R 09 00001001 output SENSOR_HUB_9 R 0A 00001010 output SENSOR_HUB_10 R 0B 00001011 output SENSOR_HUB_11 R 0C 00001100 output SENSOR_HUB_12 R 0D 00001101 output SENSOR_HUB_13 R 0E 00001110 output SENSOR_HUB_14 R 0F 00001111 output SENSOR_HUB_15 R 10 00010000 output SENSOR_HUB_16 R 11 00010001 output SENSOR_HUB_17 R 12 00010010 output SENSOR_HUB_18 R 13 00010011 output MASTER_CONFIG RW 14 00010100 00000000 SLV0_ADD RW 15 00010101 00000000 SLV0_SUBADD RW 16 00010110 00000000 SLV0_CONFIG RW 17 00010111 00000000 SLV1_ADD RW 18 00011000 00000000 SLV1_SUBADD RW 19 00011001 00000000 SLV1_CONFIG RW 1A 00011010 00000000 SLV2_ADD RW 1B 00011011 00000000 SLV2_SUBADD RW 1C 00011100 00000000 SLV2_CONFIG RW 1D 00011101 00000000 SLV3_ADD RW 1E 00011110 00000000 SLV3_SUBADD RW 1F 00011111 00000000 SLV3_CONFIG RW 20 00100000 00000000 DATAWRITE_SLV0 RW 21 00100001 00000000 STATUS_MASTER R 22 00100010 output Comment page 135/171 LSM6DSRX Sensor hub register mapping Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. DS13007 - Rev 3 page 136/171 LSM6DSRX Sensor hub register description 15 Sensor hub register description 15.1 SENSOR_HUB_1 (02h) Sensor hub output register (r) First byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 358. SENSOR_HUB_1 register Sensor Hub1_7 Sensor Hub1_6 Sensor Hub1_5 Sensor Hub1_4 Sensor Hub1_3 Sensor Hub1_2 Sensor Hub1_1 Sensor Hub1_0 Table 359. SENSOR_HUB_1 register description SensorHub1[7:0] 15.2 First byte associated to external sensors SENSOR_HUB_2 (03h) Sensor hub output register (r) Second byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 360. SENSOR_HUB_2 register Sensor Hub2_7 Sensor Hub2_6 Sensor Hub2_5 Sensor Hub2_4 Sensor Hub2_3 Sensor Hub2_2 Sensor Hub2_1 Sensor Hub2_0 Table 361. SENSOR_HUB_2 register description SensorHub2[7:0] 15.3 Second byte associated to external sensors SENSOR_HUB_3 (04h) Sensor hub output register (r) Third byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 362. SENSOR_HUB_3 register Sensor Hub3_7 Sensor Hub3_6 Sensor Hub3_5 Sensor Hub3_4 Sensor Hub3_3 Sensor Hub3_2 Sensor Hub3_1 Sensor Hub3_0 Table 363. SENSOR_HUB_3 register description SensorHub3[7:0] DS13007 - Rev 3 Third byte associated to external sensors page 137/171 LSM6DSRX SENSOR_HUB_4 (05h) 15.4 SENSOR_HUB_4 (05h) Sensor hub output register (r) Fourth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 364. SENSOR_HUB_4 register Sensor Hub4_7 Sensor Hub4_6 Sensor Hub4_5 Sensor Hub4_4 Sensor Hub4_3 Sensor Hub4_2 Sensor Hub4_1 Sensor Hub4_0 Table 365. SENSOR_HUB_4 register description SensorHub4[7:0] 15.5 Fourth byte associated to external sensors SENSOR_HUB_5 (06h) Sensor hub output register (r) Fifth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 366. SENSOR_HUB_5 register Sensor Hub5_7 Sensor Hub5_6 Sensor Hub5_5 Sensor Hub5_4 Sensor Hub5_3 Sensor Hub5_2 Sensor Hub5_1 Sensor Hub5_0 Table 367. SENSOR_HUB_5 register description SensorHub5[7:0] 15.6 Fifth byte associated to external sensors SENSOR_HUB_6 (07h) Sensor hub output register (r) Sixth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 368. SENSOR_HUB_6 register Sensor Hub6_7 Sensor Hub6_6 Sensor Hub6_5 Sensor Hub6_4 Sensor Hub6_3 Sensor Hub6_2 Sensor Hub6_1 Sensor Hub6_0 Table 369. SENSOR_HUB_6 register description SensorHub6[7:0] DS13007 - Rev 3 Sixth byte associated to external sensors page 138/171 LSM6DSRX SENSOR_HUB_7 (08h) 15.7 SENSOR_HUB_7 (08h) Sensor hub output register (r) Seventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 370. SENSOR_HUB_7 register Sensor Hub7_7 Sensor Hub7_6 Sensor Hub7_5 Sensor Hub7_4 Sensor Hub7_3 Sensor Hub7_2 Sensor Hub7_1 Sensor Hub7_0 Table 371. SENSOR_HUB_7 register description SensorHub7[7:0] 15.8 Seventh byte associated to external sensors SENSOR_HUB_8 (09h) Sensor hub output register (r) Eighth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 372. SENSOR_HUB_8 register Sensor Hub8_7 Sensor Hub8_6 Sensor Hub8_5 Sensor Hub8_4 Sensor Hub8_3 Sensor Hub8_2 Sensor Hub8_1 Sensor Hub8_0 Table 373. SENSOR_HUB_8 register description SensorHub8[7:0] 15.9 Eighth byte associated to external sensors SENSOR_HUB_9 (0Ah) Sensor hub output register (r) Ninth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 374. SENSOR_HUB_9 register Sensor Hub9_7 Sensor Hub9_6 Sensor Hub9_5 Sensor Hub9_4 Sensor Hub9_3 Sensor Hub9_2 Sensor Hub9_1 Sensor Hub9_0 Table 375. SENSOR_HUB_9 register description SensorHub9[7:0] DS13007 - Rev 3 Ninth byte associated to external sensors page 139/171 LSM6DSRX SENSOR_HUB_10 (0Bh) 15.10 SENSOR_HUB_10 (0Bh) Sensor hub output register (r) Tenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 376. SENSOR_HUB_10 register Sensor Hub10_7 Sensor Hub10_6 Sensor Hub10_5 Sensor Hub10_4 Sensor Hub10_3 Sensor Hub10_2 Sensor Hub10_1 Sensor Hub10_0 Table 377. SENSOR_HUB_10 register description SensorHub10[7:0] 15.11 Tenth byte associated to external sensors SENSOR_HUB_11 (0Ch) Sensor hub output register (r) Eleventh byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 378. SENSOR_HUB_11 register Sensor Hub11_7 Sensor Hub11_6 Sensor Hub11_5 Sensor Hub11_4 Sensor Hub11_3 Sensor Hub11_2 Sensor Hub11_1 Sensor Hub11_0 Table 379. SENSOR_HUB_11 register description SensorHub11[7:0] 15.12 Eleventh byte associated to external sensors SENSOR_HUB_12 (0Dh) Sensor hub output register (r) Twelfth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 380. SENSOR_HUB_12 register Sensor Hub12_7 Sensor Hub12_6 Sensor Hub12_5 Sensor Hub12_4 Sensor Hub12_3 Sensor Hub12_2 Sensor Hub12_1 Sensor Hub12_0 Table 381. SENSOR_HUB_12 register description SensorHub12[7:0] DS13007 - Rev 3 Twelfth byte associated to external sensors page 140/171 LSM6DSRX SENSOR_HUB_13 (0Eh) 15.13 SENSOR_HUB_13 (0Eh) Sensor hub output register (r) Thirteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 382. SENSOR_HUB_13 register Sensor Hub13_7 Sensor Hub13_6 Sensor Hub13_5 Sensor Hub13_4 Sensor Hub13_3 Sensor Hub13_2 Sensor Hub13_1 Sensor Hub13_0 Table 383. SENSOR_HUB_13 register description SensorHub13[7:0] 15.14 Thirteenth byte associated to external sensors SENSOR_HUB_14 (0Fh) Sensor hub output register (r) Fourteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 384. SENSOR_HUB_14 register Sensor Hub14_7 Sensor Hub14_6 Sensor Hub14_5 Sensor Hub14_4 Sensor Hub14_3 Sensor Hub14_2 Sensor Hub14_1 Sensor Hub14_0 Table 385. SENSOR_HUB_14 register description SensorHub14[7:0] 15.15 Fourteenth byte associated to external sensors SENSOR_HUB_15 (10h) Sensor hub output register (r) Fifteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 386. SENSOR_HUB_15 register Sensor Hub15_7 Sensor Hub15_6 Sensor Hub15_5 Sensor Hub15_4 Sensor Hub15_3 Sensor Hub15_2 Sensor Hub15_1 Sensor Hub15_0 Table 387. SENSOR_HUB_15 register description SensorHub15[7:0] DS13007 - Rev 3 Fifteenth byte associated to external sensors page 141/171 LSM6DSRX SENSOR_HUB_16 (11h) 15.16 SENSOR_HUB_16 (11h) Sensor hub output register (r) Sixteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 388. SENSOR_HUB_16 register Sensor Hub16_7 Sensor Hub16_6 Sensor Hub16_5 Sensor Hub16_4 Sensor Hub16_3 Sensor Hub16_2 Sensor Hub16_1 Sensor Hub16_0 Table 389. SENSOR_HUB_16 register description SensorHub16[7:0] 15.17 Sixteenth byte associated to external sensors SENSOR_HUB_17 (12h) Sensor hub output register (r) Seventeenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 390. SENSOR_HUB_17 register Sensor Hub17_7 Sensor Hub17_6 Sensor Hub17_5 Sensor Hub17_4 Sensor Hub17_3 Sensor Hub17_2 Sensor Hub17_1 Sensor Hub17_0 Table 391. SENSOR_HUB_17 register description SensorHub17[7:0] 15.18 Seventeenth byte associated to external sensors SENSOR_HUB_18 (13h) Sensor hub output register (r) Eighteenth byte associated to external sensors. The content of the register is consistent with the SLAVEx_CONFIG number of read operation configurations (for external sensors from x = 0 to x = 3). Table 392. SENSOR_HUB_18 register Sensor Hub18_7 Sensor Hub18_6 Sensor Hub18_5 Sensor Hub18_4 Sensor Hub18_3 Sensor Hub18_2 Sensor Hub18_1 Sensor Hub18_0 Table 393. SENSOR_HUB_18 register description SensorHub18[7:0] DS13007 - Rev 3 Eighteenth byte associated to external sensors page 142/171 LSM6DSRX MASTER_CONFIG (14h) 15.19 MASTER_CONFIG (14h) Master configuration register (r/w) Table 394. MASTER_CONFIG register RST_ MASTER_REGS WRITE_ ONCE START_ CONFIG PASS_ THROUGH_MODE SHUB_ PU_EN MASTER _ON AUX_SENS _ON1 AUX_SENS _ON0 Table 395. MASTER_CONFIG register description RST_MASTER_REGS Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’. Default value: 0 Slave 0 write operation is performed only at the first sensor hub cycle. WRITE_ONCE Default value: 0 (0: write operation for each sensor hub cycle; 1: write operation only for the first sensor hub cycle) Sensor hub trigger signal selection. Default value: 0 START_CONFIG (0: sensor hub trigger signal is the accelerometer/gyro data-ready; 1: sensor hub trigger signal external from INT2 pin) I²C interface pass-through. Default value: 0 PASS_THROUGH_MODE (0: pass-through disabled; 1: pass-through enabled, main I²C line is short-circuited with the auxiliary line) Master I²C pull-up enable. Default value: 0 SHUB_PU_EN (0: internal pull-up on auxiliary I²C line disabled; 1: internal pull-up on auxiliary I²C line enabled) MASTER_ON Sensor hub I²C master enable. Default: 0 (0: master I²C of sensor hub disabled; 1: master I²C of sensor hub enabled) Number of external sensors to be read by the sensor hub. (00: one sensor (default); AUX_SENS_ON[1:0] 01: two sensors; 10: three sensors; 11: four sensors) DS13007 - Rev 3 page 143/171 LSM6DSRX SLV0_ADD (15h) 15.20 SLV0_ADD (15h) I²C slave address of the first external sensor (Sensor 1) register (r/w) Table 396. SLV0_ADD register slave0_ add6 slave0_ add5 slave0_ add4 slave0_ add3 slave0_ add2 slave0_ add1 slave0_ add0 rw_0 slave0_ reg1 slave0_ reg0 Table 397. SLV0_ADD register description I²C slave address of Sensor1 that can be read by the sensor hub. slave0_add[6:0] Default value: 0000000 Read/write operation on Sensor 1. Default value: 0 rw_0 15.21 (0: write operation; 1: read operation) SLV0_SUBADD (16h) Address of register on the first external sensor (Sensor 1) register (r/w) Table 398. SLV0_SUBADD register slave0_ reg7 slave0_ reg6 slave0_ reg5 slave0_ reg4 slave0_ reg3 slave0_ reg2 Table 399. SLV0_SUBADD register description slave0_reg[7:0] 15.22 Address of register on Sensor1 that has to be read/written according to the rw_0 bit value in SLV0_ADD (15h). Default value: 00000000 SLAVE0_CONFIG (17h) First external sensor (Sensor1) configuration and sensor hub settings register (r/w) Table 400. SLAVE0_CONFIG register SHUB_ ODR_1 SHUB_ ODR_0 0(1) 0(1) BATCH_EXT_ SENS_0_EN Slave0_ numop2 Slave0_ numop1 Slave0_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 401. SLAVE0_CONFIG register description Rate at which the master communicates. Default value: 00 (00: 104 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 104 Hz); SHUB_ODR_[1:0] 01: 52 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 52 Hz); 10: 26 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 26 Hz); 11: 12.5 Hz (or at the maximum ODR between the accelerometer and gyro if it is less than 12.5 Hz) DS13007 - Rev 3 BATCH_EXT_SENS_0_EN Enable FIFO data batching of first slave. Default value: 0 Slave0_numop[2:0] Number of read operations on Sensor 1. Default value: 000 page 144/171 LSM6DSRX SLV1_ADD (18h) 15.23 SLV1_ADD (18h) I²C slave address of the second external sensor (Sensor 2) register (r/w) Table 402. SLV1_ADD register Slave1_ add6 Slave1_ add5 Slave1_ add4 Slave1_ add3 Slave1_ add2 Slave1_ add1 Slave1_ add0 r_1 Slave1_ reg1 Slave1_ reg0 Table 403. SLV1_ADD register description I²C slave address of Sensor 2 that can be read by the sensor hub. Slave1_add[6:0] Default value: 0000000 Read operation on Sensor 2 enable. Default value: 0 r_1 15.24 (0: read operation disabled; 1: read operation enabled) SLV1_SUBADD (19h) Address of register on the second external sensor (Sensor 2) register (r/w) Table 404. SLV1_SUBADD register Slave1_ reg7 Slave1_ reg6 Slave1_ reg5 Slave1_ reg4 Slave1_ reg3 Slave1_ reg2 Table 405. SLV1_SUBADD register description Slave1_reg[7:0] 15.25 Address of register on Sensor 2 that has to be read/written according to the r_1 bit value in SLV1_ADD (18h). SLAVE1_CONFIG (1Ah) Second external sensor (Sensor 2) configuration register (r/w) Table 406. SLAVE1_CONFIG register 0(1) 0(1) 0(1) 0(1) BATCH_EXT_ SENS_1_EN Slave1_ numop2 Slave1_ numop1 Slave1_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 407. SLAVE1_CONFIG register description DS13007 - Rev 3 BATCH_EXT_SENS_1_EN Enable FIFO data batching of second slave. Default value: 0 Slave1_numop[2:0] Number of read operations on Sensor 2. Default value: 000 page 145/171 LSM6DSRX SLV2_ADD (1Bh) 15.26 SLV2_ADD (1Bh) I²C slave address of the third external sensor (Sensor 3) register (r/w) Table 408. SLV2_ADD register Slave2_ add6 Slave2_ add5 Slave2_ add4 Slave2_ add3 Slave2_ add2 Slave2_ add1 Slave2_ add0 r_2 Slave2_ reg1 Slave2_ reg0 Table 409. SLV2_ADD register description Slave2_add[6:0] I²C slave address of Sensor 3 that can be read by the sensor hub. Read operation on Sensor 3 enable. Default value: 0 r_2 15.27 (0: read operation disabled; 1: read operation enabled) SLV2_SUBADD (1Ch) Address of register on the third external sensor (Sensor 3) register (r/w) Table 410. SLV2_SUBADD register Slave2_ reg7 Slave2_ reg6 Slave2_ reg5 Slave2_ reg4 Slave2_ reg3 Slave2_ reg2 Table 411. SLV2_SUBADD register description Slave2_reg[7:0] 15.28 Address of register on Sensor 3 that has to be read/written according to the r_2 bit value in SLV2_ADD (1Bh). SLAVE2_CONFIG (1Dh) Third external sensor (Sensor 3) configuration register (r/w) Table 412. SLAVE2_CONFIG register 0(1) 0(1) 0(1) 0(1) BATCH_EXT_ SENS_2_EN Slave2_ numop2 Slave2_ numop1 Slave2_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 413. SLAVE2_CONFIG register description DS13007 - Rev 3 BATCH_EXT_SENS_2_EN Enable FIFO data batching of third slave. Default value: 0 Slave2_numop[2:0] Number of read operations on Sensor 3. Default value: 000 page 146/171 LSM6DSRX SLV3_ADD (1Eh) 15.29 SLV3_ADD (1Eh) I²C slave address of the fourth external sensor (Sensor 4) register (r/w) Table 414. SLV3_ADD register Slave3_ add6 Slave3_ add5 Slave3_ add4 Slave3_ add3 Slave3_ add2 Slave3_ add1 Slave3_ add0 r_3 Slave3_ reg1 Slave3_ reg0 Table 415. SLV3_ADD register description Slave3_add[6:0] I²C slave address of Sensor 4 that can be read by the sensor hub. Read operation on Sensor 4 enable. Default value: 0 r_3 15.30 (0: read operation disabled; 1: read operation enabled) SLV3_SUBADD (1Fh) Address of register on the fourth external sensor (Sensor 4) register (r/w) Table 416. SLV3_SUBADD register Slave3_ reg7 Slave3_ reg6 Slave3_ reg5 Slave3_ reg4 Slave3_ reg3 Slave3_ reg2 Table 417. SLV3_SUBADD register description Slave3_reg[7:0] 15.31 Address of register on Sensor 4 that has to be read according to the r_3 bit value in SLV3_ADD (1Eh). SLAVE3_CONFIG (20h) Fourth external sensor (Sensor 4) configuration register (r/w) Table 418. SLAVE3_CONFIG register 0(1) 0(1) 0(1) 0(1) BATCH_EXT_ SENS_3_EN Slave3_ numop2 Slave3_ numop1 Slave3_ numop0 1. This bit must be set to ‘0’ for the correct operation of the device. Table 419. SLAVE3_CONFIG register description DS13007 - Rev 3 BATCH_EXT_SENS_3_EN Enable FIFO data batching of fourth slave. Default value: 0 Slave3_numop[2:0] Number of read operations on Sensor 4. Default value: 000 page 147/171 LSM6DSRX DATAWRITE_SLV0 (21h) 15.32 DATAWRITE_SLV0 (21h) Data to be written into the slave device register (r/w) Table 420. DATAWRITE_SLV0 register Slave0_ dataw7 Slave0_ dataw6 Slave0_ dataw5 Slave0_ dataw4 Slave0_ dataw3 Slave0_ dataw2 Slave0_ dataw1 Slave0_ dataw0 Table 421. DATAWRITE_SLV0 register description Slave0_dataw[7:0] 15.33 Data to be written into the slave 0 device according to the rw_0 bit in register SLV0_ADD (15h). Default value: 00000000 STATUS_MASTER (22h) Sensor hub source register (r) Table 422. STATUS_MASTER register WR_ONCE _DONE SLAVE3_ NACK SLAVE2_ NACK SLAVE1_ NACK SLAVE0_ NACK 0 0 SENS_HUB _ENDOP Table 423. STATUS_MASTER register description WR_ONCE_DONE When the bit WRITE_ONCE in MASTER_CONFIG (14h) is configured as 1, this bit is set to 1 when the write operation on slave 0 has been performed and completed. Default value: 0 SLAVE3_NACK This bit is set to 1 if Not acknowledge occurs on slave 3 communication. Default value: 0 SLAVE2_NACK This bit is set to 1 if Not acknowledge occurs on slave 2 communication. Default value: 0 SLAVE1_NACK This bit is set to 1 if Not acknowledge occurs on slave 1 communication. Default value: 0 SLAVE0_NACK This bit is set to 1 if Not acknowledge occurs on slave 0 communication. Default value: 0 Sensor hub communication status. Default value: 0 SENS_HUB_ENDOP (0: sensor hub communication not concluded; 1: sensor hub communication concluded) DS13007 - Rev 3 page 148/171 LSM6DSRX Soldering information 16 Soldering information The LGA package is compliant with the ECOPACK, RoHS and "Green" standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Land pattern and soldering recommendations are available at www.st.com/mems. DS13007 - Rev 3 page 149/171 LSM6DSRX Package information 17 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 17.1 LGA-14L package information Figure 27. LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data Pin1 indicator Pin1 indicator H 0.5 4x 1 TOP VIEW (0.1) 14x 0.5 L 1.5 W 14x 0.25±0.05 0.475±0.05 BOTTOM VIEW Dimensions are in millimeter unless otherwise specified General tolerance is +/-0.1mm unless otherwise specified OUTER DIMENSIONS ITEM Length [L] W idth [W ] Height [H] DIMENSION [mm] 2.50 3.00 0.86 TOLERANCE [mm] ±0.1 ±0.1 MA X DM00249496_1 DS13007 - Rev 3 page 150/171 LSM6DSRX LGA-14 packing information 17.2 LGA-14 packing information Figure 28. Carrier tape information for LGA-14 package Figure 29. LGA-14 package orientation in carrier tape DS13007 - Rev 3 page 151/171 LSM6DSRX LGA-14 packing information Figure 30. Reel information for carrier tape of LGA-14 package T 40mm min. Access hole at slot location B C N D A Full radius G measured at hub Tape slot in core for tape start 2.5mm min. width Table 424. Reel dimensions for carrier tape of LGA-14 package Reel dimensions (mm) DS13007 - Rev 3 A (max) 330 B (min) 1.5 C 13 ±0.25 D (min) 20.2 N (min) 60 G 12.4 +2/-0 T (max) 18.4 page 152/171 LSM6DSRX Revision history Table 425. Document revision history Date Version 19-Sep-2019 1 Changes Initial release Updated title of datasheet, Descripton, added Product resources Updated Table 6. I²C slave timing values 12-Mar-2020 2 Updated description of bit 7 in TAP_THS_6D (59h) Updated bit 0 in I3C_BUS_AVB (62h) Updated PEDO_CMD_REG (83h) Updated linear acceleration self-test output change in Table 2. Mechanical characteristics 18-Nov-2020 3 Updated Note below Figure 6 and Figure 7 Updated Table 50. Accelerometer ODR selection Updated description of bits in INT_DUR2 (5Ah) DS13007 - Rev 3 page 153/171 LSM6DSRX Contents Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 Embedded low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Tilt detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Significant Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Finite State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Machine Learning Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1 4 5 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4.2 I²C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6.2 Zero-g and zero-rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 5.1 5.2 I²C/SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 I²C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 SPI bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MIPI I3CSM interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 MIPI I3CSM slave interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.2 MIPI I3CSM CCC supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 I²C/I3C coexistence in LSM6DSRX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 Master I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.5 Auxiliary SPI interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DS13007 - Rev 3 page 154/171 LSM6DSRX Contents 6 7 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 6.1 Operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 Accelerometer power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4 Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.4.1 Block diagrams of the accelerometer filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.4.2 Block diagrams of the gyroscope filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.5 OIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.6 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6.3 Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6.4 Continuous-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6.5 Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6.6 Bypass-to-FIFO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.6.7 FIFO reading procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.1 LSM6DSRX electrical connections in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 LSM6DSRX electrical connections in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 LSM6DSRX electrical connections in Mode 3 and Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 Register mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 9 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 9.1 FUNC_CFG_ACCESS (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2 PIN_CTRL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.3 S4S_TPH_L (04h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.4 S4S_TPH_H (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.5 S4S_RR (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6 FIFO_CTRL1 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.7 FIFO_CTRL2 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.8 FIFO_CTRL3 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.9 FIFO_CTRL4 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DS13007 - Rev 3 page 155/171 LSM6DSRX Contents 9.10 COUNTER_BDR_REG1 (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.11 COUNTER_BDR_REG2 (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.12 INT1_CTRL (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.13 INT2_CTRL (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.14 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.15 CTRL1_XL (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.16 CTRL2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.17 CTRL3_C (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.18 CTRL4_C (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.19 CTRL5_C (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.20 CTRL6_C (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.21 CTRL7_G (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.22 CTRL8_XL (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.23 CTRL9_XL (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.24 CTRL10_C (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.25 ALL_INT_SRC (1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.26 WAKE_UP_SRC (1Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.27 TAP_SRC (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.28 DRD_SRC (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.29 STATUS_REG (1Eh) / STATUS_SPIAux (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.30 OUT_TEMP_L (20h), OUT_TEMP_H (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.31 OUTX_L_G (22h) and OUTX_H_G (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.32 OUTY_L_G (24h) and OUTY_H_G (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.33 OUTZ_L_G (26h) and OUTZ_H_G (27h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.34 OUTX_L_A (28h) and OUTX_H_A (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.35 OUTY_L_A (2Ah) and OUTY_H_A (2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.36 OUTZ_L_A (2Ch) and OUTZ_H_A (2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.37 EMB_FUNC_STATUS_MAINPAGE (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 9.38 FSM_STATUS_A_MAINPAGE (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 9.39 FSM_STATUS_B_MAINPAGE (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DS13007 - Rev 3 page 156/171 LSM6DSRX Contents 9.40 MLC_STATUS_MAINPAGE (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.41 STATUS_MASTER_MAINPAGE (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.42 FIFO_STATUS1 (3Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.43 FIFO_STATUS2 (3Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.44 TIMESTAMP0 (40h), TIMESTAMP1 (41h), TIMESTAMP2 (42h), and TIMESTAMP3 (43h) 74 9.45 TAP_CFG0 (56h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 9.46 TAP_CFG1 (57h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.47 TAP_CFG2 (58h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.48 TAP_THS_6D (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.49 INT_DUR2 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.50 WAKE_UP_THS (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.51 WAKE_UP_DUR (5Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.52 FREE_FALL (5Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.53 MD1_CFG (5Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.54 MD2_CFG (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.55 S4S_ST_CMD_CODE (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.56 S4S_DT_REG (61h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.57 I3C_BUS_AVB (62h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.58 INTERNAL_FREQ_FINE (63h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9.59 INT_OIS (6Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.60 CTRL1_OIS (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.61 CTRL2_OIS (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 9.62 CTRL3_OIS (72h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.63 X_OFS_USR (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.64 Y_OFS_USR (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.65 Z_OFS_USR (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.66 FIFO_DATA_OUT_TAG (78h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 9.67 FIFO_DATA_OUT_X_L (79h) and FIFO_DATA_OUT_X_H (7Ah) . . . . . . . . . . . . . . . . . . . . . 90 9.68 FIFO_DATA_OUT_Y_L (7Bh) and FIFO_DATA_OUT_Y_H (7Ch) . . . . . . . . . . . . . . . . . . . . . 90 9.69 FIFO_DATA_OUT_Z_L (7Dh) and FIFO_DATA_OUT_Z_H (7Eh) . . . . . . . . . . . . . . . . . . . . . 90 DS13007 - Rev 3 page 157/171 LSM6DSRX Contents 10 Embedded functions register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 11 Embedded functions register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.1 PAGE_SEL (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.2 EMB_FUNC_EN_A (04h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.3 EMB_FUNC_EN_B (05h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.4 PAGE_ADDRESS (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.5 PAGE_VALUE (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.6 EMB_FUNC_INT1 (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.7 FSM_INT1_A (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.8 FSM_INT1_B (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.9 MLC_INT1 (0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.10 EMB_FUNC_INT2 (0Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.11 FSM_INT2_A (0Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.12 FSM_INT2_B (10h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.13 MLC_INT2 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.14 EMB_FUNC_STATUS (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.15 FSM_STATUS_A (13h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.16 FSM_STATUS_B (14h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.17 MLC_STATUS (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11.18 PAGE_RW (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.19 EMB_FUNC_FIFO_CFG (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.20 FSM_ENABLE_A (46h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.21 FSM_ENABLE_B (47h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 11.22 FSM_LONG_COUNTER_L (48h) and FSM_LONG_COUNTER_H (49h) . . . . . . . . . . . . . . 107 11.23 FSM_LONG_COUNTER_CLEAR (4Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.24 FSM_OUTS1 (4Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.25 FSM_OUTS2 (4Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 11.26 FSM_OUTS3 (4Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.27 FSM_OUTS4 (4Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 11.28 FSM_OUTS5 (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DS13007 - Rev 3 page 158/171 LSM6DSRX Contents 11.29 FSM_OUTS6 (51h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 11.30 FSM_OUTS7 (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.31 FSM_OUTS8 (53h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 11.32 FSM_OUTS9 (54h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.33 FSM_OUTS10 (55h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 11.34 FSM_OUTS11 (56h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.35 FSM_OUTS12 (57h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 11.36 FSM_OUTS13 (58h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.37 FSM_OUTS14 (59h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 11.38 FSM_OUTS15 (5Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.39 FSM_OUTS16 (5Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 11.40 EMB_FUNC_ODR_CFG_B (5Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.41 EMB_FUNC_ODR_CFG_C (60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 11.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) . . . . . . . . . . . . . . . . . . . . . . . . . 117 11.43 EMB_FUNC_SRC (64h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.44 EMB_FUNC_INIT_A (66h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11.45 EMB_FUNC_INIT_B (67h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.46 MLC0_SRC (70h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.47 MLC1_SRC (71h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11.48 MLC2_SRC (72h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.49 MLC3_SRC (73h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.50 MLC4_SRC (74h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.51 MLC5_SRC (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 11.52 MLC6_SRC (76h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11.53 MLC7_SRC (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 12 Embedded advanced features pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 13 Embedded advanced features register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.1 DS13007 - Rev 3 Page 0 - Embedded advanced features registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 13.1.1 MAG_SENSITIVITY_L (BAh) and MAG_SENSITIVITY_H (BBh) . . . . . . . . . . . . . . . . . . 125 13.1.2 MAG_OFFX_L (C0h) and MAG_OFFX_H (C1h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.1.3 MAG_OFFY_L (C2h) and MAG_OFFY_H (C3h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 page 159/171 LSM6DSRX Contents 13.1.4 MAG_OFFZ_L (C4h) and MAG_OFFZ_H (C5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.1.5 MAG_SI_XX_L (C6h) and MAG_SI_XX_H (C7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.1.6 MAG_SI_XY_L (C8h) and MAG_SI_XY_H (C9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.1.7 MAG_SI_XZ_L (CAh) and MAG_SI_XZ_H (CBh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.1.8 MAG_SI_YY_L (CCh) and MAG_SI_YY_H (CDh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.1.9 MAG_SI_YZ_L (CEh) and MAG_SI_YZ_H (CFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 13.1.10 MAG_SI_ZZ_L (D0h) and MAG_SI_ZZ_H (D1h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 13.1.11 MAG_CFG_A (D4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.1.12 MAG_CFG_B (D5h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 13.2 Page 1 - Embedded advanced features registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.2.1 FSM_LC_TIMEOUT_L (7Ah) and FSM_LC_TIMEOUT_H (7Bh). . . . . . . . . . . . . . . . . . . 132 13.2.2 FSM_PROGRAMS (7Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 13.2.3 FSM_START_ADD_L (7Eh) and FSM_START_ADD_H (7Fh) . . . . . . . . . . . . . . . . . . . . 133 13.2.4 PEDO_CMD_REG (83h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.2.5 PEDO_DEB_CONF (84h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 13.2.6 PEDO_SC_DELTAT_L (D0h) and PEDO_SC_DELTAT_H (D1h) . . . . . . . . . . . . . . . . . . 134 13.2.7 MLC_MAG_SENSITIVITY_L (E8h) and MLC_MAG_SENSITIVITY_H (E9h) . . . . . . . . . 134 14 Sensor hub register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 15 Sensor hub register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.1 SENSOR_HUB_1 (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.2 SENSOR_HUB_2 (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.3 SENSOR_HUB_3 (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 15.4 SENSOR_HUB_4 (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.5 SENSOR_HUB_5 (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.6 SENSOR_HUB_6 (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 15.7 SENSOR_HUB_7 (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.8 SENSOR_HUB_8 (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.9 SENSOR_HUB_9 (0Ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 15.10 SENSOR_HUB_10 (0Bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.11 SENSOR_HUB_11 (0Ch). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 15.12 SENSOR_HUB_12 (0Dh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DS13007 - Rev 3 page 160/171 LSM6DSRX Contents 15.13 SENSOR_HUB_13 (0Eh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.14 SENSOR_HUB_14 (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.15 SENSOR_HUB_15 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 15.16 SENSOR_HUB_16 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.17 SENSOR_HUB_17 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.18 SENSOR_HUB_18 (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 15.19 MASTER_CONFIG (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 15.20 SLV0_ADD (15h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.21 SLV0_SUBADD (16h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.22 SLAVE0_CONFIG (17h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 15.23 SLV1_ADD (18h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 15.24 SLV1_SUBADD (19h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 15.25 SLAVE1_CONFIG (1Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 15.26 SLV2_ADD (1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.27 SLV2_SUBADD (1Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.28 SLAVE2_CONFIG (1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.29 SLV3_ADD (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.30 SLV3_SUBADD (1Fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.31 SLAVE3_CONFIG (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 15.32 DATAWRITE_SLV0 (21h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 15.33 STATUS_MASTER (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 16 Soldering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 17 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 17.1 LGA-14L package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 17.2 LGA-14 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 DS13007 - Rev 3 page 161/171 LSM6DSRX List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI slave timing values (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer when master is writing one byte to slave. . . . . . . . . . . . . . . . . . . . Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . Transfer when master is receiving (reading) one byte of data from slave . . . . Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 12 12 13 14 15 17 17 18 18 18 18 18 Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. MIPI I3CSM CCC commands . . . . . . . . . . . . Master I²C pin details . . . . . . . . . . . . . . . . . Auxiliary SPI pin details . . . . . . . . . . . . . . . Gyroscope LPF2 bandwidth selection . . . . . . Internal pin status . . . . . . . . . . . . . . . . . . . Registers address map . . . . . . . . . . . . . . . . FUNC_CFG_ACCESS register . . . . . . . . . . FUNC_CFG_ACCESS register description . . PIN_CTRL register. . . . . . . . . . . . . . . . . . . PIN_CTRL register description . . . . . . . . . . S4S_TPH_L register . . . . . . . . . . . . . . . . . S4S_TPH_L register description . . . . . . . . . S4S_TPH_H register . . . . . . . . . . . . . . . . . S4S_TPH_H register description . . . . . . . . . S4S_RR register . . . . . . . . . . . . . . . . . . . . S4S_RR register description . . . . . . . . . . . . FIFO_CTRL1 register . . . . . . . . . . . . . . . . . FIFO_CTRL1 register description. . . . . . . . . FIFO_CTRL2 register . . . . . . . . . . . . . . . . . FIFO_CTRL2 register . . . . . . . . . . . . . . . . . FIFO_CTRL3 register . . . . . . . . . . . . . . . . . FIFO_CTRL3 register description. . . . . . . . . FIFO_CTRL4 register . . . . . . . . . . . . . . . . . FIFO_CTRL4 register description. . . . . . . . . COUNTER_BDR_REG1 register . . . . . . . . . COUNTER_BDR_REG1 register description . COUNTER_BDR_REG2 register . . . . . . . . . COUNTER_BDR_REG2 register description . INT1_CTRL register . . . . . . . . . . . . . . . . . . INT1_CTRL register description . . . . . . . . . . INT2_CTRL register . . . . . . . . . . . . . . . . . . INT2_CTRL register description . . . . . . . . . . WhoAmI register . . . . . . . . . . . . . . . . . . . . CTRL1_XL register . . . . . . . . . . . . . . . . . . CTRL1_XL register description . . . . . . . . . . Accelerometer ODR selection . . . . . . . . . . . CTRL2_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 27 27 31 39 41 44 44 44 44 45 45 45 45 45 45 46 46 46 46 47 47 48 48 49 49 49 49 50 50 51 51 51 52 52 52 53 DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 162/171 LSM6DSRX List of tables Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. CTRL2_G register description . . . . . . . . . . . . . . . Gyroscope ODR configuration setting . . . . . . . . . . CTRL3_C register . . . . . . . . . . . . . . . . . . . . . . . CTRL3_C register description . . . . . . . . . . . . . . . CTRL4_C register . . . . . . . . . . . . . . . . . . . . . . . CTRL4_C register description . . . . . . . . . . . . . . . CTRL5_C register . . . . . . . . . . . . . . . . . . . . . . . CTRL5_C register description . . . . . . . . . . . . . . . Angular rate sensor self-test mode selection . . . . . Linear acceleration sensor self-test mode selection CTRL6_C register . . . . . . . . . . . . . . . . . . . . . . . CTRL6_C register description . . . . . . . . . . . . . . . Trigger mode selection . . . . . . . . . . . . . . . . . . . . Gyroscope LPF1 bandwidth selection . . . . . . . . . . CTRL7_G register . . . . . . . . . . . . . . . . . . . . . . . CTRL8_XL register . . . . . . . . . . . . . . . . . . . . . . Accelerometer bandwidth configurations . . . . . . . . CTRL9_XL register . . . . . . . . . . . . . . . . . . . . . . CTRL9_XL register description . . . . . . . . . . . . . . CTRL10_C register . . . . . . . . . . . . . . . . . . . . . . CTRL10_C register description . . . . . . . . . . . . . . ALL_INT_SRC register . . . . . . . . . . . . . . . . . . . . ALL_INT_SRC register description. . . . . . . . . . . . WAKE_UP_SRC register . . . . . . . . . . . . . . . . . . WAKE_UP_SRC register description . . . . . . . . . . TAP_SRC register . . . . . . . . . . . . . . . . . . . . . . . TAP_SRC register description . . . . . . . . . . . . . . . D6D_SRC register . . . . . . . . . . . . . . . . . . . . . . . D6D_SRC register description . . . . . . . . . . . . . . . STATUS_REG register . . . . . . . . . . . . . . . . . . . . STATUS_REG register description . . . . . . . . . . . . STATUS_SPIAux register . . . . . . . . . . . . . . . . . . STATUS_SPIAux register description . . . . . . . . . . OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . OUT_TEMP register description. . . . . . . . . . . . . . OUTX_L_G register . . . . . . . . . . . . . . . . . . . . . . OUTX_H_G register . . . . . . . . . . . . . . . . . . . . . . OUTX_H_G register description. . . . . . . . . . . . . . OUTY_L_G register . . . . . . . . . . . . . . . . . . . . . . OUTY_H_G register . . . . . . . . . . . . . . . . . . . . . . OUTY_H_G register description. . . . . . . . . . . . . . OUTZ_L_G register . . . . . . . . . . . . . . . . . . . . . . OUTZ_H_G register . . . . . . . . . . . . . . . . . . . . . . OUTZ_H_G register description . . . . . . . . . . . . . . OUTX_L_A register . . . . . . . . . . . . . . . . . . . . . . OUTX_H_A register . . . . . . . . . . . . . . . . . . . . . . OUTX_H_A register description . . . . . . . . . . . . . . OUTY_L_A register . . . . . . . . . . . . . . . . . . . . . . OUTY_H_A register . . . . . . . . . . . . . . . . . . . . . . OUTY_H_A register description . . . . . . . . . . . . . . OUTZ_L_A register . . . . . . . . . . . . . . . . . . . . . . OUTZ_H_A register . . . . . . . . . . . . . . . . . . . . . . OUTZ_H_A register description . . . . . . . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 53 54 54 55 55 56 56 56 56 57 57 57 57 58 59 59 61 61 61 61 62 62 63 63 64 64 65 65 66 66 66 66 67 67 67 67 67 67 68 68 68 68 68 68 69 69 69 69 69 69 70 70 70 page 163/171 LSM6DSRX List of tables Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. Table 136. Table 137. Table 138. Table 139. Table 140. Table 141. Table 142. Table 143. Table 144. Table 145. Table 146. Table 147. Table 148. Table 149. Table 150. Table 151. Table 152. Table 153. Table 154. Table 155. Table 156. Table 157. Table 158. Table 159. EMB_FUNC_STATUS_MAINPAGE register . . . . . . . . EMB_FUNC_STATUS_MAINPAGE register description FSM_STATUS_A_MAINPAGE register . . . . . . . . . . . . FSM_STATUS_A_MAINPAGE register description . . . . FSM_STATUS_B_MAINPAGE register . . . . . . . . . . . . FSM_STATUS_B_MAINPAGE register description . . . . MLC_STATUS_MAINPAGE register . . . . . . . . . . . . . . MLC_STATUS_MAINPAGE register description . . . . . . STATUS_MASTER_MAINPAGE register. . . . . . . . . . . STATUS_MASTER_MAINPAGE register description . . FIFO_STATUS1 register . . . . . . . . . . . . . . . . . . . . . . FIFO_STATUS1 register description . . . . . . . . . . . . . . FIFO_STATUS2 register . . . . . . . . . . . . . . . . . . . . . . FIFO_STATUS2 register description . . . . . . . . . . . . . . TIMESTAMP3 register . . . . . . . . . . . . . . . . . . . . . . . TIMESTAMP2 register . . . . . . . . . . . . . . . . . . . . . . . TIMESTAMP1 register . . . . . . . . . . . . . . . . . . . . . . . TIMESTAMP0 register . . . . . . . . . . . . . . . . . . . . . . . TAP_CFG0 register . . . . . . . . . . . . . . . . . . . . . . . . . TAP_CFG0 register description . . . . . . . . . . . . . . . . . TAP_CFG1 register . . . . . . . . . . . . . . . . . . . . . . . . . TAP_CFG1 register description . . . . . . . . . . . . . . . . . TAP priority decoding . . . . . . . . . . . . . . . . . . . . . . . . TAP_CFG2 register . . . . . . . . . . . . . . . . . . . . . . . . . TAP_CFG2 register description . . . . . . . . . . . . . . . . . TAP_THS_6D register . . . . . . . . . . . . . . . . . . . . . . . TAP_THS_6D register description . . . . . . . . . . . . . . . INT_DUR2 register. . . . . . . . . . . . . . . . . . . . . . . . . . INT_DUR2 register description . . . . . . . . . . . . . . . . . WAKE_UP_THS register. . . . . . . . . . . . . . . . . . . . . . WAKE_UP_THS register description . . . . . . . . . . . . . WAKE_UP_DUR register . . . . . . . . . . . . . . . . . . . . . WAKE_UP_DUR register description . . . . . . . . . . . . . FREE_FALL register . . . . . . . . . . . . . . . . . . . . . . . . FREE_FALL register description . . . . . . . . . . . . . . . . MD1_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . MD1_CFG register description. . . . . . . . . . . . . . . . . . MD2_CFG register . . . . . . . . . . . . . . . . . . . . . . . . . . MD2_CFG register description. . . . . . . . . . . . . . . . . . S4S_ST_CMD_CODE register . . . . . . . . . . . . . . . . . S4S_ST_CMD_CODE register description . . . . . . . . . S4S_DT_REG register . . . . . . . . . . . . . . . . . . . . . . . S4S_DT_REG register description . . . . . . . . . . . . . . . I3C_BUS_AVB register . . . . . . . . . . . . . . . . . . . . . . . I3C_BUS_AVB register description. . . . . . . . . . . . . . . INTERNAL_FREQ_FINE register. . . . . . . . . . . . . . . . INTERNAL_FREQ_FINE register description. . . . . . . . INT_OIS register . . . . . . . . . . . . . . . . . . . . . . . . . . . INT_OIS register description . . . . . . . . . . . . . . . . . . . CTRL1_OIS register. . . . . . . . . . . . . . . . . . . . . . . . . CTRL1_OIS register description. . . . . . . . . . . . . . . . . DEN mode selection. . . . . . . . . . . . . . . . . . . . . . . . . CTRL2_OIS register. . . . . . . . . . . . . . . . . . . . . . . . . CTRL2_OIS register description. . . . . . . . . . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 70 71 71 71 71 72 72 72 72 73 73 73 73 74 74 74 74 75 75 76 76 76 76 76 77 77 77 77 78 78 78 78 79 79 80 80 81 81 82 82 82 82 82 82 83 83 84 84 85 85 85 86 86 page 164/171 LSM6DSRX List of tables Table 160. Table 161. Table 162. Table 163. Table 164. Table 165. Table 166. Table 167. Table 168. Table 169. Table 170. Table 171. Table 172. Table 173. Table 174. Table 175. Table 176. Table 177. Table 178. Table 179. Table 180. Table 181. Table 182. Table 183. Table 184. Table 185. Table 186. Table 187. Table 188. Table 189. Table 190. Table 191. Table 192. Table 193. Table 194. Table 195. Table 196. Table 197. Table 198. Table 199. Table 200. Table 201. Table 202. Table 203. Table 204. Table 205. Table 206. Table 207. Table 208. Table 209. Table 210. Table 211. Table 212. Table 213. Gyroscope OIS chain digital LPF1 filter bandwidth selection . . . . . . . . . CTRL3_OIS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTRL3_OIS register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accelerometer OIS channel bandwidth and phase . . . . . . . . . . . . . . . . Self-test nominal output variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . X_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . Y_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z_OFS_USR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z_OFS_USR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO_DATA_OUT_TAG register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO_DATA_OUT_TAG register description . . . . . . . . . . . . . . . . . . . . FIFO tag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L registers . . . . . . . . FIFO_DATA_OUT_X_H and FIFO_DATA_OUT_X_L register description FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L registers . . . . . . . . FIFO_DATA_OUT_Y_H and FIFO_DATA_OUT_Y_L register description FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L registers . . . . . . . . FIFO_DATA_OUT_Z_H and FIFO_DATA_OUT_Z_L register description. Register address map - embedded functions . . . . . . . . . . . . . . . . . . . . PAGE_SEL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAGE_SEL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_EN_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_EN_A register description . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_EN_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_EN_B register description . . . . . . . . . . . . . . . . . . . . . . . PAGE_ADDRESS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAGE_ADDRESS register description . . . . . . . . . . . . . . . . . . . . . . . . PAGE_VALUE register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAGE_VALUE register description . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_INT1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_INT1 register description . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT1_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT1_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT1_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT1_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC_INT1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC_INT1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_INT2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_INT2 register description . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT2_A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT2_A register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT2_B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_INT2_B register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC_INT2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC_INT2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_STATUS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_STATUS register description. . . . . . . . . . . . . . . . . . . . . . FSM_STATUS_A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_STATUS_A register description . . . . . . . . . . . . . . . . . . . . . . . . . FSM_STATUS_B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM_STATUS_B register description . . . . . . . . . . . . . . . . . . . . . . . . . MLC_STATUS register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC_STATUS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 . 87 . 87 . 87 . 87 . 88 . 88 . 88 . 88 . 88 . 89 . 89 . 89 . 90 . 90 . 90 . 90 . 90 . 90 . 91 . 93 . 93 . 93 . 93 . 94 . 94 . 94 . 94 . 94 . 94 . 95 . 95 . 96 . 96 . 97 . 97 . 98 . 98 . 99 . 99 100 100 101 101 102 102 103 103 103 103 104 104 104 104 page 165/171 LSM6DSRX List of tables Table 214. Table 215. Table 216. Table 217. Table 218. Table 219. Table 220. Table 221. Table 222. Table 223. Table 224. Table 225. Table 226. Table 227. Table 228. Table 229. Table 230. Table 231. Table 232. Table 233. Table 234. Table 235. Table 236. Table 237. Table 238. Table 239. Table 240. Table 241. Table 242. Table 243. Table 244. Table 245. Table 246. Table 247. Table 248. Table 249. Table 250. Table 251. Table 252. Table 253. Table 254. Table 255. Table 256. Table 257. Table 258. Table 259. Table 260. Table 261. Table 262. Table 263. Table 264. Table 265. Table 266. Table 267. PAGE_RW register . . . . . . . . . . . . . . . . . . . . . . . . PAGE_RW register description . . . . . . . . . . . . . . . . EMB_FUNC_FIFO_CFG register . . . . . . . . . . . . . . . EMB_FUNC_FIFO_CFG register description . . . . . . . FSM_ENABLE_A register . . . . . . . . . . . . . . . . . . . . FSM_ENABLE_A register description . . . . . . . . . . . . FSM_ENABLE_B register . . . . . . . . . . . . . . . . . . . . FSM_ENABLE_B register description . . . . . . . . . . . . FSM_LONG_COUNTER_L register . . . . . . . . . . . . . FSM_LONG_COUNTER_L register description . . . . . FSM_LONG_COUNTER_H register . . . . . . . . . . . . . FSM_LONG_COUNTER_H register description. . . . . FSM_LONG_COUNTER_CLEAR register. . . . . . . . . FSM_LONG_COUNTER_CLEAR register description. FSM_OUTS1 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS1 register description. . . . . . . . . . . . . . . FSM_OUTS2 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS2 register description. . . . . . . . . . . . . . . FSM_OUTS3 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS3 register description. . . . . . . . . . . . . . . FSM_OUTS4 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS4 register description. . . . . . . . . . . . . . . FSM_OUTS5 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS5 register description. . . . . . . . . . . . . . . FSM_OUTS6 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS6 register description. . . . . . . . . . . . . . . FSM_OUTS7 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS7 register description. . . . . . . . . . . . . . . FSM_OUTS8 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS8 register description. . . . . . . . . . . . . . . FSM_OUTS9 register . . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS9 register description. . . . . . . . . . . . . . . FSM_OUTS10 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS10 register description . . . . . . . . . . . . . . FSM_OUTS11 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS11 register description . . . . . . . . . . . . . . FSM_OUTS12 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS12 register description . . . . . . . . . . . . . . FSM_OUTS13 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS13 register description . . . . . . . . . . . . . . FSM_OUTS14 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS14 register description . . . . . . . . . . . . . . FSM_OUTS15 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS15 register description . . . . . . . . . . . . . . FSM_OUTS16 register . . . . . . . . . . . . . . . . . . . . . . FSM_OUTS16 register description . . . . . . . . . . . . . . EMB_FUNC_ODR_CFG_B register . . . . . . . . . . . . . EMB_FUNC_ODR_CFG_B register description . . . . . EMB_FUNC_ODR_CFG_C register . . . . . . . . . . . . . EMB_FUNC_ODR_CFG_C register description . . . . . STEP_COUNTER_L register. . . . . . . . . . . . . . . . . . STEP_COUNTER_L register description. . . . . . . . . . STEP_COUNTER_H register . . . . . . . . . . . . . . . . . STEP_COUNTER_H register description . . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 105 105 105 106 106 106 106 107 107 107 107 107 107 108 108 108 108 109 109 109 109 .110 .110 .110 .110 .111 .111 .111 .111 .112 .112 .112 .112 .113 .113 .113 .113 .114 .114 .114 .114 .115 .115 .115 .115 .116 .116 .116 .116 .117 .117 .117 .117 page 166/171 LSM6DSRX List of tables Table 268. Table 269. Table 270. Table 271. Table 272. Table 273. Table 274. Table 275. Table 276. Table 277. Table 278. Table 279. Table 280. Table 281. Table 282. Table 283. Table 284. Table 285. Table 286. Table 287. Table 288. Table 289. Table 290. Table 291. Table 292. Table 293. Table 294. Table 295. Table 296. Table 297. Table 298. Table 299. Table 300. Table 301. Table 302. Table 303. Table 304. Table 305. Table 306. Table 307. Table 308. Table 309. Table 310. Table 311. Table 312. Table 313. Table 314. Table 315. Table 316. Table 317. Table 318. Table 319. Table 320. Table 321. EMB_FUNC_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_SRC register description . . . . . . . . . . . . . . . . . EMB_FUNC_INIT_A register . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_INIT_A register description. . . . . . . . . . . . . . . . EMB_FUNC_INIT_B register . . . . . . . . . . . . . . . . . . . . . . . . EMB_FUNC_INIT_B register description. . . . . . . . . . . . . . . . MLC0_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC0_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC1_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC2_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC2_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC3_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC3_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC4_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC4_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC5_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC5_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC6_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC6_SRC register description . . . . . . . . . . . . . . . . . . . . . . MLC7_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MLC7_SRC register description . . . . . . . . . . . . . . . . . . . . . . Register address map - embedded advanced features page 0 . Register address map - embedded advanced features page 1 . MAG_SENSITIVITY_L register . . . . . . . . . . . . . . . . . . . . . . MAG_SENSITIVITY_L register description . . . . . . . . . . . . . . MAG_SENSITIVITY_H register . . . . . . . . . . . . . . . . . . . . . . MAG_SENSITIVITY_H register description . . . . . . . . . . . . . . MAG_OFFX_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_OFFX_L register description. . . . . . . . . . . . . . . . . . . . MAG_OFFX_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_OFFX_H register description . . . . . . . . . . . . . . . . . . . MAG_OFFY_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_OFFY_L register description. . . . . . . . . . . . . . . . . . . . MAG_OFFY_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_OFFY_H register description . . . . . . . . . . . . . . . . . . . MAG_OFFZ_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_OFFZ_L register description . . . . . . . . . . . . . . . . . . . . MAG_OFFZ_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_OFFZ_H register description . . . . . . . . . . . . . . . . . . . MAG_SI_XX_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_XX_L register description . . . . . . . . . . . . . . . . . . . MAG_SI_XX_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_XX_H register description . . . . . . . . . . . . . . . . . . . MAG_SI_XY_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_XY_L register description . . . . . . . . . . . . . . . . . . . MAG_SI_XY_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_XY_H register description . . . . . . . . . . . . . . . . . . . MAG_SI_XZ_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_XZ_L register description . . . . . . . . . . . . . . . . . . . MAG_SI_XZ_H register . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_XZ_H register description . . . . . . . . . . . . . . . . . . . MAG_SI_YY_L register. . . . . . . . . . . . . . . . . . . . . . . . . . . . MAG_SI_YY_L register description . . . . . . . . . . . . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 .118 .118 .118 .119 .119 .119 .119 .119 .119 120 120 120 120 120 120 120 120 121 121 121 121 122 123 125 125 125 125 126 126 126 126 126 126 126 126 127 127 127 127 127 127 127 127 128 128 128 128 128 128 128 128 129 129 page 167/171 LSM6DSRX List of tables Table 322. Table 323. Table 324. Table 325. Table 326. Table 327. Table 328. Table 329. Table 330. Table 331. Table 332. Table 333. Table 334. Table 335. Table 336. Table 337. Table 338. Table 339. Table 340. Table 341. Table 342. Table 343. Table 344. Table 345. Table 346. Table 347. Table 348. Table 349. Table 350. Table 351. Table 352. Table 353. Table 354. Table 355. Table 356. Table 357. Table 358. Table 359. Table 360. Table 361. Table 362. Table 363. Table 364. Table 365. Table 366. Table 367. Table 368. Table 369. Table 370. Table 371. Table 372. Table 373. Table 374. Table 375. MAG_SI_YY_H register . . . . . . . . . . . . . . . . . . MAG_SI_YY_H register description . . . . . . . . . . MAG_SI_YZ_L register. . . . . . . . . . . . . . . . . . . MAG_SI_YZ_L register description . . . . . . . . . . MAG_SI_YZ_H register . . . . . . . . . . . . . . . . . . MAG_SI_YZ_H register description . . . . . . . . . . MAG_SI_ZZ_L register . . . . . . . . . . . . . . . . . . . MAG_SI_ZZ_L register description. . . . . . . . . . . MAG_SI_ZZ_H register . . . . . . . . . . . . . . . . . . MAG_SI_ZZ_H register description . . . . . . . . . . MAG_CFG_A register . . . . . . . . . . . . . . . . . . . MAG_CFG_A register description . . . . . . . . . . . MAG_CFG_B register . . . . . . . . . . . . . . . . . . . MAG_CFG_B register description . . . . . . . . . . . FSM_LC_TIMEOUT_L register . . . . . . . . . . . . . FSM_LC_TIMEOUT_L register description . . . . . FSM_LC_TIMEOUT_H register . . . . . . . . . . . . . FSM_LC_TIMEOUT_H register description . . . . . FSM_PROGRAMS register . . . . . . . . . . . . . . . . FSM_PROGRAMS register description. . . . . . . . FSM_START_ADD_L register . . . . . . . . . . . . . . FSM_START_ADD_L register description . . . . . . FSM_START_ADD_H register . . . . . . . . . . . . . . FSM_START_ADD_H register description. . . . . . PEDO_CMD_REG register . . . . . . . . . . . . . . . . PEDO_CMD_REG register description . . . . . . . . PEDO_DEB_STEPS_CONF register . . . . . . . . . PEDO_DEB_STEPS_CONF register description . PEDO_SC_DELTAT_L register . . . . . . . . . . . . . PEDO_SC_DELTAT_H register . . . . . . . . . . . . . PEDO_SC_DELTAT_H/L register description. . . . MLC_MAG_SENSITIVITY_L register . . . . . . . . . MLC_MAG_SENSITIVITY_L register description . MLC_MAG_SENSITIVITY_H register . . . . . . . . . MLC_MAG_SENSITIVITY_H register description . Registers address map . . . . . . . . . . . . . . . . . . . SENSOR_HUB_1 register. . . . . . . . . . . . . . . . . SENSOR_HUB_1 register description . . . . . . . . SENSOR_HUB_2 register. . . . . . . . . . . . . . . . . SENSOR_HUB_2 register description . . . . . . . . SENSOR_HUB_3 register. . . . . . . . . . . . . . . . . SENSOR_HUB_3 register description . . . . . . . . SENSOR_HUB_4 register. . . . . . . . . . . . . . . . . SENSOR_HUB_4 register description . . . . . . . . SENSOR_HUB_5 register. . . . . . . . . . . . . . . . . SENSOR_HUB_5 register description . . . . . . . . SENSOR_HUB_6 register. . . . . . . . . . . . . . . . . SENSOR_HUB_6 register description . . . . . . . . SENSOR_HUB_7 register. . . . . . . . . . . . . . . . . SENSOR_HUB_7 register description . . . . . . . . SENSOR_HUB_8 register. . . . . . . . . . . . . . . . . SENSOR_HUB_8 register description . . . . . . . . SENSOR_HUB_9 register. . . . . . . . . . . . . . . . . SENSOR_HUB_9 register description . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 129 129 129 129 129 130 130 130 130 131 131 131 131 132 132 132 132 132 132 133 133 133 133 133 133 133 133 134 134 134 134 134 134 134 135 137 137 137 137 137 137 138 138 138 138 138 138 139 139 139 139 139 139 page 168/171 LSM6DSRX List of tables Table 376. Table 377. Table 378. Table 379. Table 380. Table 381. Table 382. Table 383. Table 384. Table 385. Table 386. Table 387. Table 388. Table 389. Table 390. Table 391. Table 392. Table 393. Table 394. Table 395. Table 396. Table 397. Table 398. Table 399. Table 400. Table 401. Table 402. Table 403. Table 404. Table 405. Table 406. Table 407. Table 408. Table 409. Table 410. Table 411. Table 412. Table 413. Table 414. Table 415. Table 416. Table 417. Table 418. Table 419. Table 420. Table 421. Table 422. Table 423. Table 424. Table 425. SENSOR_HUB_10 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_10 register description. . . . . . . . . . SENSOR_HUB_11 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_11 register description . . . . . . . . . . SENSOR_HUB_12 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_12 register description. . . . . . . . . . SENSOR_HUB_13 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_13 register description. . . . . . . . . . SENSOR_HUB_14 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_14 register description. . . . . . . . . . SENSOR_HUB_15 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_15 register description. . . . . . . . . . SENSOR_HUB_16 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_16 register description. . . . . . . . . . SENSOR_HUB_17 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_17 register description. . . . . . . . . . SENSOR_HUB_18 register . . . . . . . . . . . . . . . . . . SENSOR_HUB_18 register description. . . . . . . . . . MASTER_CONFIG register. . . . . . . . . . . . . . . . . . MASTER_CONFIG register description . . . . . . . . . SLV0_ADD register . . . . . . . . . . . . . . . . . . . . . . . SLV0_ADD register description . . . . . . . . . . . . . . . SLV0_SUBADD register . . . . . . . . . . . . . . . . . . . . SLV0_SUBADD register description . . . . . . . . . . . . SLAVE0_CONFIG register . . . . . . . . . . . . . . . . . . SLAVE0_CONFIG register description . . . . . . . . . . SLV1_ADD register . . . . . . . . . . . . . . . . . . . . . . . SLV1_ADD register description . . . . . . . . . . . . . . . SLV1_SUBADD register . . . . . . . . . . . . . . . . . . . . SLV1_SUBADD register description . . . . . . . . . . . . SLAVE1_CONFIG register . . . . . . . . . . . . . . . . . . SLAVE1_CONFIG register description . . . . . . . . . . SLV2_ADD register . . . . . . . . . . . . . . . . . . . . . . . SLV2_ADD register description . . . . . . . . . . . . . . . SLV2_SUBADD register . . . . . . . . . . . . . . . . . . . . SLV2_SUBADD register description . . . . . . . . . . . . SLAVE2_CONFIG register . . . . . . . . . . . . . . . . . . SLAVE2_CONFIG register description . . . . . . . . . . SLV3_ADD register . . . . . . . . . . . . . . . . . . . . . . . SLV3_ADD register description . . . . . . . . . . . . . . . SLV3_SUBADD register . . . . . . . . . . . . . . . . . . . . SLV3_SUBADD register description . . . . . . . . . . . . SLAVE3_CONFIG register . . . . . . . . . . . . . . . . . . SLAVE3_CONFIG register description . . . . . . . . . . DATAWRITE_SLV0 register. . . . . . . . . . . . . . . . . . DATAWRITE_SLV0 register description . . . . . . . . . STATUS_MASTER register . . . . . . . . . . . . . . . . . . STATUS_MASTER register description. . . . . . . . . . Reel dimensions for carrier tape of LGA-14 package Document revision history . . . . . . . . . . . . . . . . . . . DS13007 - Rev 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 140 140 140 140 140 141 141 141 141 141 141 142 142 142 142 142 142 143 143 144 144 144 144 144 144 145 145 145 145 145 145 146 146 146 146 146 146 147 147 147 147 147 147 148 148 148 148 152 153 page 169/171 LSM6DSRX List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. DS13007 - Rev 3 Generic state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . State machine in the LSM6DSRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Machine Learning Core in the LSM6DSRX . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LSM6DSRX connection modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI slave timing diagram (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I²C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read and write protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SPI read protocol (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple byte SPI read protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . SPI write protocol (in mode 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple byte SPI write protocol (2-byte example) (in mode 3) . . . . . . . . . . . . . . . SPI read protocol in 3-wire mode (in mode 3) . . . . . . . . . . . . . . . . . . . . . . . . . . I²C and I3C both active (INT1 pin not connected) . . . . . . . . . . . . . . . . . . . . . . . Only I3C active (INT1 pin connected to Vdd_IO) . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accelerometer UI chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accelerometer composite filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accelerometer chain with Mode 4 enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gyroscope digital chain - Mode 1 (UI/EIS) and Mode 2 . . . . . . . . . . . . . . . . . . . Gyroscope digital chain - Mode 3 / Mode 4 (OIS/EIS) . . . . . . . . . . . . . . . . . . . . Auxiliary SPI full control (a) and enabling primary interface (b) . . . . . . . . . . . . . . LSM6DSRX electrical connections in Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . LSM6DSRX electrical connections in Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . LSM6DSRX electrical connections in Mode 3 and Mode 4 (auxiliary 3/4-wire SPI) . Accelerometer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LGA-14L 2.5 x 3.0 x 0.86 mm package outline and mechanical data . . . . . . . . . . Carrier tape information for LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . LGA-14 package orientation in carrier tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . Reel information for carrier tape of LGA-14 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 .. 5 .. 6 .. 7 .. 8 . 13 . 14 . 20 . 21 . 21 . 22 . 22 . 23 . 26 . 26 . 28 . 29 . 29 . 30 . 30 . 31 . 32 . 36 . 37 . 38 . 60 150 151 151 152 page 170/171 LSM6DSRX IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS13007 - Rev 3 page 171/171