M24128-BWMN3TG

M24128 M24C64 M24C32 128 Kbit, 64 Kbit and 32 Kbit serial I²C bus EEPROM Features ■ ■ Two-wire I2C serial interface supports 400 kHz protocol Single supply voltages (see Table 1 for root part numbers): – 2.5 V to 5.5 V – 1.8 V to 5.5 V – 1.7 V to 5.5 V Write Control input Byte and Page Write Random and Sequential Read modes Self-timed programming cycle Automatic address incrementing Enhanced ESD/latch-up protection More than 1 Million write cycles More than 40-year data retention Packages – ECOPACK® (RoHS compliant) Device summary Part number M24128-BW Supply voltage 2.5 V to 5.5V 1.8 V to 5.5V 1.7 V to 5.5V 2.5 V to 5.5V 1.8 V to 5.5V 1.7 V to 5.5V 2.5 V to 5.5V 1.8 V to 5.5V 1.7 V to 5.5V WLCSP (CS) PDIP8 (BN) ■ ■ ■ ■ ■ ■ ■ ■ ■ SO8 (MN) 150 mil width Table 1. Reference TSSOP8 (DW) 169 mil width M24128 M24128-BR M24128-BF M24C64-W UFDFPN8 (MB) 2 × 3 mm (MLP) M24C64 M24C64-R M24C64-F M24C32-W M24C32 M24C32-R M24C32-F September 2008 Rev 15 1/39 www.st.com 1 Contents M24128, M24C64, M24C32 Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 2.5 2.6 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 2.6.2 2.6.3 2.6.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 4 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/39 M24128, M24C64, M24C32 Contents 5 6 7 8 9 10 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3/39 List of tables M24128, M24C64, M24C32 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics (M24xxx-W, device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC characteristics (M24xxx-W6, M24xxW3, M24xxR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 29 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 31 UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 M24128 WLCSP, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 33 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Available M24C32 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35 Available M24C64 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35 Available M24128 products (package, voltage range, temperature grade) . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4/39 M24128, M24C64, M24C32 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 DIP, SO, TSSOP and UFDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M24128 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Maximum RP value versus bus parasitic capacitance (C) for an I2C bus . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 29 SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 30 TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 31 UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 M24128 WLCSP, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5/39 Description M24128, M24C64, M24C32 1 Description The M24C32, M24C64 and M24128 devices are I2C-compatible electrically erasable programmable memories (EEPROM). They are organized as 4096 × 8 bits, 8192 × 8 bits and 16384 × 8 bits, respectively. Figure 1. Logic diagram VCC 3 E0-E2 SCL WC M24128 M24C64 M24C32 SDA VSS AI01844e I2C uses a two-wire serial interface, comprising a bi-directional data line and a clock line. The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 3), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. 6/39 M24128, M24C64, M24C32 Table 2. Signal names Signal name E0, E1, E2 SDA SCL WC VCC VSS Function Chip Enable Serial Data Serial Clock Write Control Supply voltage Ground Input I/O Input Input Description Direction Figure 2. DIP, SO, TSSOP and UFDFPN connections M24128 M24C64 M24C32 1 8 2 7 3 6 4 5 E0 E1 E2 VSS VCC WC SCL SDA AI01845e 1. See Package mechanical data section for package dimensions, and how to identify pin-1. Figure 3. M24128 WLCSP connections (top view, marking side, with balls on the underside) VCC E1 E0 WC E2 SDA SCL VSS ai14799 7/39 Signal description M24128, M24C64, M24C32 2 2.1 Signal description Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). 2.3 Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC or VSS, to establish the device select code as shown in Figure 4. When not connected (left floating), these inputs are read as low (0,0,0). Figure 4. Device select code VCC VCC M24xxx Ei M24xxx Ei VSS VSS Ai12806 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and Write operations are allowed. When Write Control (WC) is driven high, device select and Address bytes are acknowledged, Data bytes are not acknowledged. 8/39 M24128, M24C64, M24C32 Signal description 2.5 VSS ground VSS is the reference for the VCC supply voltage. 2.6 2.6.1 Supply voltage (VCC) Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 9 and Table 10). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs. 2.6.3 Device reset In order to prevent inadvertent Write operations during power-up, a power on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any instruction until VCC has reached the power on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 9 and Table 10). Until VCC passes over the POR threshold, the device is reset and in Standby Power mode. In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below the POR threshold voltage, the device is reset and stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decay of VCC), the device must be in Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal Write cycle in progress). 9/39 Signal description Figure 5. M24128, M24C64, M24C32 Maximum RP value versus bus parasitic capacitance (C) for an I2C bus Bus line pull-up resistor (k ) 100 fC = 400 kHz, tLOW = 1.3 µs Rbus x Cbus time constant must be less than 500 ns VCC 10 Rbus I²C bus master SCL SDA M24xxx 1 10 100 Bus line capacitor (pF) 1000 Cbus ai14796 Figure 6. I2C bus protocol SCL SDA SDA Input SDA Change Start Condition Stop Condition SCL 1 2 3 7 8 9 SDA MSB ACK Start Condition SCL 1 2 3 7 8 9 SDA MSB ACK Stop Condition AI00792B 10/39 M24128, M24C64, M24C32 Table 3. Device select code Device type identifier(1) b7 Device select code 1 b6 0 b5 1 b4 0 Signal description Chip Enable address(2) b3 E2 b2 E1 b1 E0 RW b0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. Table 4. b15 Address most significant byte b14 b13 b12 b11 b10 b9 b8 Table 5. b7 Address least significant byte b6 b5 b4 b3 b2 b1 b0 11/39 Memory organization M24128, M24C64, M24C32 3 Memory organization The memory is organized as shown in Figure 7. Figure 7. WC E0 E1 E2 SCL Control Logic High Voltage Generator Block diagram SDA I/O Shift Register Address Register and Counter Data Register Y Decoder 1 Page X Decoder AI06899 12/39 M24128, M24C64, M24C32 Device operation 4 Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The M24C32, M24C64 and M24128 devices are always slaves in all communications. 4.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal Write cycle. 4.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 4.4 Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 13/39 Device operation M24128, M24C64, M24C32 4.5 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 3 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4-bit device type identifier is 1010b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Table 6. Mode Current Address Read Random Address Read Sequential Read Byte Write Operating modes RW bit WC(1) 1 0 1 1 0 X X 1 X X VIL VIL ≥1 1 ≤ 32 for M24C64 and M24C32 ≤ 64 for M24128 reStart, device select, RW = 1 Similar to Current or Random Address Read Start, device select, RW = 0 Bytes 1 Initial sequence Start, device select, RW = 1 Start, device select, RW = 0, Address Page Write 0 Start, device select, RW = 0 1. X = VIH or VIL. 14/39 M24128, M24C64, M24C32 Figure 8. WC ACK Byte Write Start Device operation Write mode sequences with WC = 1 (data write inhibited) ACK ACK Data in NO ACK Dev select R/W Byte address Byte address WC ACK Page Write Start ACK ACK NO ACK Data in 1 Data in 2 Dev select R/W Byte address Byte address WC (cont'd) NO ACK Page Write (cont'd) NO ACK Data in N Stop Stop AI01120d 15/39 Device operation M24128, M24C64, M24C32 4.6 Write operations Following a Start condition the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data Byte. Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write instruction with Write Control (WC) driven high (during a period of time from the Start condition until the end of the two address bytes) will not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 8. Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant Byte (Table 4) is sent first, followed by the Least Significant Byte (Table 5). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. 4.7 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 9. 4.8 Page Write The Page Write mode allows up to 32 bytes (for the M24C32 and M24C64) or 64 bytes (for the M24128) to be written in a single Write cycle, provided that they are all located in the same ’row’ in the memory: that is, the most significant memory address bits (b13-b6 for M24128, b12-b5 for M24C64, and b11-b5 for M24C32) are the same. If more bytes are sent than will fit up to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 32 bytes of data (for the M24C32 and M24C64) or 64 bytes of data (for the M24128), each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. 16/39 M24128, M24C64, M24C32 Figure 9. WC ACK Byte Write Dev Select ACK ACK Data in Device operation Write mode sequences with WC = 0 (data write enabled) ACK Byte address R/W Byte address Start WC ACK Page Write Dev Select ACK ACK Data in 1 ACK Data in 2 Byte address R/W Byte address WC (cont'd) Start ACK Page Write (cont'd) Data in N ACK Stop Stop AI01106d 4.9 ECC (error correction code) and write cycling The M24128 and M24C64 in UFDFPN8 (MLP) 2 × 3 mm package and the M24128 in WLCSP package offer an ECC (error correction code) logic which compares each 4-byte word with its six associated EEPROM ECC bits. As a result, if a single bit out of 4 bytes of data happens to be erroneous during a read operation, the ECC detects it and replaces it by the correct value. The read reliability is therefore much improved by the use of this feature. Note however that even if a single byte has to be written, 4 bytes are internally modified (plus the ECC word), that is, the addressed byte is cycled together with the three other bytes making up the word. It is therefore recommended to write by packets of 4 bytes in order to benefit from the larger amount of write cycles. All M24C32, M24C64 and M24128 devices are qualified at 1 million (1 000 000) write cycles; the M24128 and M24C64 in UFDFPN8 (MLP) 2 × 3 mm package and the M24128 in WLCSP package are qualified (at 1 million write cycles), using a cycling routine that writes to the device by multiples of 4-byte words. 17/39 Device operation Figure 10. Write cycle polling flowchart using ACK Write cycle in progress M24128, M24C64, M24C32 Start condition Device select with RW = 0 NO First byte of instruction with RW = 0 already decoded by the device ACK Returned YES NO Next operation is addressing the memory YES ReStart Send address and receive ACK Stop NO Start condition YES Data for the Write operation Device select with RW = 1 Continue the Write operation Continue the Random Read operation AI01847d 4.10 Minimizing system delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 17 and Table 18, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 10, is: 1. 2. 3. Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 18/39 M24128, M24C64, M24C32 Figure 11. Read mode sequences ACK Current Address Read Start Device operation NO ACK Data out Dev select R/W ACK Random Address Read Start ACK Stop ACK Dev select * Start ACK Data out NO ACK Dev select * R/W Byte address Byte address R/W ACK Sequential Current Read Start ACK Data out 1 ACK NO ACK Data out N Stop Dev select R/W ACK Sequential Random Read Start ACK ACK Dev select * Start ACK Data out 1 R/W ACK Dev select * Byte address R/W Byte address ACK NO ACK Data out N Stop AI01105d 1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must be identical. Stop 19/39 Device operation M24128, M24C64, M24C32 4.11 Read operations Read operations are performed independently of the state of the Write Control (WC) signal. After the successful completion of a Read operation, the device’s internal address counter is incremented by one, to point to the next byte address. 4.12 Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 11) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. 4.13 Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 11, without acknowledging the Byte. 4.14 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 11. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. 4.15 Acknowledge in Read mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this time, the device terminates the data transfer and switches to its Standby mode. 20/39 M24128, M24C64, M24C32 Initial delivery state 5 Initial delivery state The device is delivered with all bits in the memory array set to 1 (each byte contains FFh). 6 Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Symbol TA TSTG TLEAD VIO IOL VCC VESD Absolute maximum ratings Parameter Ambient operating temperature Storage temperature Lead temperature during soldering PDIP-specific lead temperature during soldering Input or output range DC output current (SDA = 0) Supply voltage Electrostatic discharge voltage (human body model)(3) –0.50 –0.50 –4000 Min. –40 –65 see note Max. 130 150 (1) (2) Unit °C °C °C °C V mA V V 260 6.5 5 6.5 4000 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. TLEAD max must not be applied for more than 10 s. 3. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500 Ω, R2=500 Ω) 21/39 DC and AC parameters M24128, M24C64, M24C32 7 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 8. Symbol VCC TA Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3) Operating conditions (M24xxx-W) Parameter Min. 2.5 –40 –40 Max. 5.5 85 125 Unit V °C °C Table 9. Symbol VCC TA Operating conditions (M24xxx-R) Parameter Supply voltage Ambient operating temperature Min. 1.8 –40 Max. 5.5 85 Unit V °C Table 10. Symbol VCC TA Operating conditions (M24xxx-F) Parameter Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 5) Min. 1.7 –40 –20 Max. 5.5 85 85 Unit V °C °C Table 11. Symbol CL AC test measurement conditions Parameter Load capacitance Input rise and fall times Input levels Input and output timing reference levels Min. 100 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V Figure 12. AC test measurement I/O waveform Input Levels 0.8VCC Input and Output Timing Reference Levels 0.7VCC 0.3VCC AI00825B 0.2VCC 22/39 M24128, M24C64, M24C32 Table 12. Symbol CIN CIN ZWCL(1) ZWCH(1) tNS(1) DC and AC parameters Input parameters Parameter Input capacitance (SDA) Input capacitance (other pins) WC input impedance WC input impedance Pulse width ignored (Input filter on SCL and SDA) VIN < 0.3VCC VIN > 0.7VCC 50 500 200 Test condition Min. Max. 8 6 200 Unit pF pF kΩ kΩ ns 1. Characterized only. Table 13. Symbol ILI ILO ICC ICC0 DC characteristics (M24xxx-W, device grade 6) Parameter Input leakage current (SCL, SDA, E2, E1, E0) Output leakage current Supply current (Read) Supply current (Write) Standby supply current Test condition (in addition to those in Table 8) VIN = VSS or VCC device in Standby mode SDA in Hi-Z, external voltage applied on SDA: VSS or VCC 2.5 V < VCC < 5.5 V, fc = 400 kHz During tW, 2.5 V < VCC < 5.5 V VIN = VSS or VCC, VCC = 5.5 V VIN = VSS or VCC, VCC = 2.5 V –0.45 Min. Max. ±2 ±2 2 5(1) 5 2 0.3VCC Unit µA µA mA mA µA µA V V V ICC1 Standby supply current VIL VIH VOL Input low voltage (SDA, SCL, WC) Input high voltage (SDA, SCL, WC) Output low voltage 0.7VCC VCC+0.6 IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 0.4 1. Characterized value, not tested in production. 23/39 DC and AC parameters Table 14. Symbol ILI ILO ICC ICC0 ICC1 VIL VIH VOL M24128, M24C64, M24C32 DC characteristics (M24xxx-W, device grade 3) Parameter Test condition (in addition to those in Table 8) VIN = VSS or VCC device in Standby mode SDA in Hi-Z, external voltage applied on SDA: VSS or VCC 2.5 V < VCC < 5.5 V, fc = 400 kHz During tW, 2.5 V < VCC < 5.5 V VIN = VSS or VCC, 2.5 V < VCC < 5.5 V –0.45 Min. Max. ±2 ±2 2 5 (1) Unit µA µA mA mA µA V V V Input leakage current (SCL, SDA, E2, E1, E0) Output leakage current Supply current (Read) Supply current (Write) Standby supply current Input low voltage (SDA, SCL, WC) Input high voltage (SDA, SCL, WC) Output low voltage 10 0.3VCC 0.7VCC VCC+0.6 IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 0.4 1. Characterized value, not tested in production. Table 15. Symbol ILI ILO ICC ICC0 ICC1 VIL DC characteristics (M24xxx-R - device grade 6) Parameter Input leakage current (SCL, SDA, E2, E1, E0) Output leakage current Supply current (Read) Supply current (Write) Standby supply current Input low voltage (SDA, SCL, WC) Input high voltage (SDA, SCL, WC) Output low voltage Test condition (in addition to those in Table 9) VIN = VSS or VCC device in Standby mode SDA Hi-Z, external voltage applied on SDA: VSS or VCC VCC = 1.8 V, fc = 400 kHz During tW, 1.8 V < VCC < 2.5 V VIN = VSS or VCC, 1.8 V < VCC < 2.5 V 1.8 V ≤VCC < 2.5 V 2.5 V ≤VCC < 5.5 V 1.8 V ≤VCC < 2.5 V 2.5 V ≤VCC < 5.5 V IOL = 1 mA, VCC = 1.8 V –0.45 –0.45 0.75VCC 0.7VCC Min. Max. ±2 ±2 0.8 3(1) 1 0.25 VCC 0.3 VCC VCC+1 VCC+1 0.2 Unit µA µA mA mA µA V V V V V VIH VOL 1. Characterized value, not tested in production. 24/39 M24128, M24C64, M24C32 Table 16. Symbol DC and AC parameters DC characteristics (M24xxx-F)(1) Parameter Input leakage current (SCL, SDA, E2, E1, E0) Output leakage current Supply current (Read) Supply current (Write) Standby supply current Input low voltage (SDA, SCL, WC) Input high voltage (SDA, SCL, WC) Output low voltage Test condition (in addition to those in Table 10) VIN = VSS or VCC device in Standby mode SDA Hi-Z, external voltage applied on SDA: VSS or VCC VCC =1.7 V, fc = 400 kHz During tW, 1.7 V < VCC < 2.5 V VIN = VSS or VCC, 1.7 V < VCC < 2.5 V 1.8 V ≤VCC < 2.5 V 2.5 V ≤VCC < 5.5 V 1.8 V ≤VCC < 2.5 V 2.5 V ≤VCC < 5.5 V IOL = 0.7 mA, VCC = 1.7 V –0.45 –0.45 0.75VCC 0.7VCC Min. Max. Unit ILI ILO ICC ICC0 ICC1 VIL ±2 ±2 0.8 3(2) 1 0.25 VCC 0.3 VCC VCC+1 VCC+1 0.2 µA µA mA mA µA V V V V V VIH VOL 1. Preliminary data. 2. Characterized value, not tested in production. 25/39 DC and AC parameters Table 17. M24128, M24C64, M24C32 AC characteristics (M24xxx-W6, M24xxW3, M24xxR6) Test conditions specified in Table 8 and Table 9 Symbol fC tCHCL tCLCH tXH1XH2(1) tXL1XL2(1) tDL1DL2 tDXCX tCLDX tCLQX tCLQV(2)(3) tCHDX(4) tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tR tF tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF Clock frequency Parameter Min. Max. 400 Unit kHz ns ns Clock pulse width high Clock pulse width low Input signal rise time Input signal fall time SDA (out) fall time Data in set up time Data in hold time Data out hold time Clock low to next data valid (access time) Start condition set up time Start condition hold time Stop condition set up time Time between Stop condition and next Start condition Write time 600 1300 20 20 20 100 0 200 200 600 600 600 1300 5(5) 900 300 300 100 ns ns ns ns ns ns ns ns ns ns ns ms 1. Values recommended by the I²C-bus Fast-Mode specification. 2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus × Cbus time constant is less than 500 ns (as specified in Figure 5). 4. For a reStart condition, or following a Write cycle. 5. For production lots assembled from 1st July 2007 (data code 727: week27, year 2007), the M24xxx-R (1.8 V to 5.5 V range) memories are specified with tW = 5 ms (instead of 10ms). 26/39 M24128, M24C64, M24C32 Table 18. AC characteristics (M24xxx-F) Test conditions specified in Table 10 Symbol fC tCHCL tCLCH tXH1XH2(1) tXL1XL2(1) tDL1DL2 tDXCX tCLDX tCLQX tCLQV(2)(3) tCHDX(4) tDLCL tCHDH tDHDL tW Alt. fSCL tHIGH tLOW tR tF tF tSU:DAT tHD:DAT tDH tAA tSU:STA tHD:STA tSU:STO tBUF Clock frequency Clock pulse width high Clock pulse width low Input signal rise time Input signal fall time SDA (out) fall time Data in set up time Data in hold time Data out hold time Clock low to next data valid (access time) Start condition set up time Start condition hold time Stop condition set up time Time between Stop condition and next Start condition Write time Parameter DC and AC parameters Min. Max. 400 Unit kHz ns ns 600 1300 20 20 20 100 0 200 200 600 600 600 1300 10(5) 900 300 300 100 ns ns ns ns ns ns ns ns ns ns ns ms 1. Values recommended by the I²C-bus Fast-Mode specification. 2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach 0.8VCC in a compatible way with the I2C specification (which specifies tSU:DAT (min) = 100 ns), assuming that the Rbus × Cbus time constant is less than 500 ns (as specified in Figure 5). 4. For a reStart condition, or following a Write cycle. 5. For temperature range 6: tW(max) = 5 ms. For temperature range 5: tW(max) = 10 ms. 27/39 DC and AC parameters Figure 13. AC waveforms tXL1XL2 tXH1XH2 SCL tDLCL SDA In tCHDX Start condition tXH1XH2 SDA Input tCLDX SDA tDXCX Change tXL1XL2 tCHCL tCLCH M24128, M24C64, M24C32 tCHDH tDHDL Start Stop condition condition SCL SDA In tW tCHDH Stop condition Write cycle tCHDX Start condition tCHCL SCL tCLQV SDA Out Data valid tCLQX Data valid AI00795e tDL1DL2 28/39 M24128, M24C64, M24C32 Package mechanical data 8 Package mechanical data In order to meet environmental requirements, ST offers the M24C32, M24C64 and M24128 in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 14. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline b2 A2 A1 b e eA D 8 E A L c eB E1 1 PDIP-B 1. Drawing is not to scale. Table 19. Symbol PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data millimeters Typ. Min. Max. 5.33 0.38 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 2.92 0.36 1.14 0.20 9.02 7.62 6.10 – – 4.95 0.56 1.78 0.36 10.16 8.26 7.11 – – 10.92 3.30 2.92 3.81 0.1299 0.1150 0.1299 0.0181 0.0598 0.0098 0.3650 0.3098 0.2500 0.1000 0.3000 0.0150 0.1150 0.0142 0.0449 0.0079 0.3551 0.3000 0.2402 – – 0.1949 0.0220 0.0701 0.0142 0.4000 0.3252 0.2799 – – 0.4299 0.1500 Typ. inches(1) Min. Max. 0.2098 A A1 A2 b b2 c D E E1 e eA eB L 1. Values in inches are converted from mm and rounded to 4 decimal digits. 29/39 Package mechanical data M24128, M24C64, M24C32 Figure 15. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 b e 0.25 mm GAUGE PLANE k 8 A ccc c D E1 1 E A1 L L1 SO-A 1. Drawing is not to scale. Table 20. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package mechanical data millimeters inches(1) Max 1.75 0.10 1.25 0.28 0.17 0.48 0.23 0.10 4.90 6.00 3.90 1.27 4.80 5.80 3.80 – 0.25 0° 0.40 1.04 5.00 6.20 4.00 – 0.50 8° 1.27 0.0410 0° 0.0157 8° 0.0500 0.1929 0.2362 0.1535 0.0500 0.1890 0.2283 0.1496 – 0.25 0.0039 0.0492 0.0110 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 – Typ Min Max 0.0689 0.0098 Symbol Typ A A1 A2 b c ccc D E E1 e h k L L1 Min 1. Values in inches are converted from mm and rounded to 4 decimal digits. 30/39 M24128, M24C64, M24C32 Package mechanical data Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline D 8 5 c E1 E 1 4 α A1 A CP b e A2 L L1 TSSOP8AM 1. Drawing is not to scale. Table 21. Symbol TSSOP8 – 8 lead thin shrink small outline, package mechanical data millimeters Typ. Min. Max. 1.200 0.050 1.000 0.800 0.190 0.090 0.150 1.050 0.300 0.200 0.100 3.000 0.650 6.400 4.400 0.600 1.000 0° 8° 2.900 – 6.200 4.300 0.450 3.100 – 6.600 4.500 0.750 0.1181 0.0256 0.2520 0.1732 0.0236 0.0394 0° 8° 0.1142 – 0.2441 0.1693 0.0177 0.0394 0.0020 0.0315 0.0075 0.0035 Typ. inches(1) Min. Max. 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.1220 – 0.2598 0.1772 0.0295 A A1 A2 b c CP D e E E1 L L1 α 1. Values in inches are converted from mm and rounded to 4 decimal digits. 31/39 Package mechanical data M24128, M24C64, M24C32 Figure 17. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline D L3 e b L1 E E2 L A D2 ddd A1 UFDFPN-01 1. Drawing is not to scale. Table 22. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package mechanical data millimeters inches(1) Max 0.60 0.05 0.30 2.10 1.70 0.08 3.00 0.20 0.50 0.45 2.90 0.10 – 0.40 3.10 0.30 – 0.50 0.15 0.30 0.0118 0.1181 0.0079 0.0197 0.0177 0.1142 0.0039 – 0.0157 Typ 0.0217 0.0008 0.0098 0.0787 0.0630 Min 0.0197 0 0.0079 0.0748 0.0591 Max 0.0236 0.0020 0.0118 0.0827 0.0669 0.0031 0.1220 0.0118 – 0.0197 0.0059 Symbol Typ A A1 b D D2 ddd E E2 e L L1 L3 0.55 0.02 0.25 2.00 1.60 Min 0.50 0.00 0.20 1.90 1.50 1. Values in inches are converted from mm and rounded to 4 decimal digits. 32/39 M24128, M24C64, M24C32 Figure 18. M24128 WLCSP, 0.5 mm pitch, package outline Package mechanical data Orientation references 5 4 D 3 2 1 A B e3 C E e1 B F G e e2 A A1 A2 1. Drawing is not to scale. Table 23. Symbol M24128 WLCSP, 0.5 mm pitch, package mechanical data millimeters Typ. Min. 0.535 0.205 0.330 0.290 1.785 1.380 Max. 0.635 0.255 0.380 0.350 1.825 1.420 Typ. 0.0230 0.0091 0.0140 0.0126 0.0711 0.0551 0.0197 0.0349 0.0098 0.0174 0.0101 0.0158 8 8 inches(1) Min. 0.0211 0.0081 0.0130 0.0114 0.0703 0.0543 Max. 0.0250 0.0100 0.0150 0.0138 0.0719 0.0559 A A1 A2 B D E e e1 e2 e3 F G N(2) 0.585 0.230 0.355 0.320 1.805 1.400 0.5 0.886 0.250 0.443 0.257 0.4025 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. N is the total number of terminals. 33/39 Part numbering M24128, M24C64, M24C32 9 Part numbering Table 24. Example: Device type M24 = I2C serial access EEPROM Device function 128–B = 128 Kbit (16384 x 8) C64– = 64 Kbit (8192 x 8) C32– = 32 Kbit (4096 x 8) Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MB = UFDFPN8 (MLP8) CS = WLCSP Device grade 6 = Industrial: device tested with standard test flow over –40 to 85 °C 3 = Automotive: device tested with high reliability certified flow(1) over –40 to 125°C. 5 = Consumer: device tested with standard test flow over –20 to 85°C Option blank = standard packing T = Tape and reel packing Plating technology P or G = ECOPACK® (RoHS compliant) Process(2) P = F6DP26% Chartered A = F8L Rousset (only for the WLCSP package) 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 2. Used only for device grade 3 and WLCSP packages. Ordering information scheme M24C32– W MN 6 T P /P For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 34/39 M24128, M24C64, M24C32 Table 25. Part numbering Available M24C32 products (package, voltage range, temperature grade) M24C32-F 1.7 V to 5.5 V Grade 5 Grade 5 M24C32-R 1.8 V to 5.5 V Grade 6 Grade 6 Grade 6 M24C32-W 2.5 V to 5.5 V Grade6 Grade 3 Grade 6 Grade 6 - Package DIP8 (BN) SO8N (MN) TSSOP8 (DW) MLP8 (MB) Table 26. Available M24C64 products (package, voltage range, temperature grade) M24C64-F 1.7 V to 5.5 V Grade 5 Grade 6 M24C64-R 1.8 V to 5.5 V Grade 6 Grade 6 M24C64-W 2.5 V to 5.5 V Grade6 Grade 3 Grade 6 Grade 6 - Package DIP8 (BN) SO8N (MN) TSSOP8 (DW) MLP8 (MB) Table 27. Available M24128 products (package, voltage range, temperature grade) M24128-BF 1.7 V to 5.5 V Grade 6 Grade 6 M24128-BR 1.8 V to 5.5 V Grade 6 Grade 6 M24128-BW 2.5 V to 5.5 V Grade 3 Grade 6 Grade 6 - Package DIP8 (BN) SO8N (MN) TSSOP8 (DW) MLP8 (MB) WLCSP (CS) 35/39 Revision history M24128, M24C64, M24C32 10 Revision history Table 28. Date 22-Dec-1999 28-Jun-2000 31-Oct-2000 Document revision history Revision 2.3 2.4 2.5 Changes TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo, PackageMechData). TSSOP8 package data corrected References to Temperature Range 3 removed from Ordering Information Voltage range -S added, and range -R removed from text and tables throughout. Lead Soldering Temperature in the Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using ACK illustration updated References to PSDIP changed to PDIP and Package Mechanical data updated Test condition for ILI made more precise, and value of ILI for E2-E0 and WC added -R voltage range added Document reformatted using new template. TSSOP8 (3x3mm² body size) package (MSOP8) added. 5ms write time offered for 5V and 2.5V devices SO8W package removed. -S voltage range removed TSSOP8 (3x3mm² body size) package (MSOP8) removed Table of contents, and Pb-free options added. Minor wording changes in Summary Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations. VIL(min) improved to -0.45V. Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. Device Grade clarified Product List summary table added. Device Grade 3 added. 4.5-5.5V range is Not for New Design. Some minor wording changes. AEC-Q100002 compliance. tNS(max) changed. VIL(min) is the same on all input pins of the device. ZWCL changed. UFDFPN8 package added. Small text changes. 20-Apr-2001 2.6 16-Jan-2002 2.7 02-Aug-2002 04-Feb-2003 27-May-2003 22-Oct-2003 2.8 2.9 2.10 3.0 01-Jun-2004 4.0 04-Nov-2004 5.0 05-Jan-2005 6.0 36/39 M24128, M24C64, M24C32 Table 28. Date Revision history Document revision history (continued) Revision Changes Document converted to new ST template. M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed. M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added. Section 2.3: Chip Enable (E0, E1, E2) and Section 2.4: Write Control (WC) modified, Section 2.6: Supply voltage (VCC) added and replaces Power On Reset: VCC Lock-Out Write Protect section. TA added, Note 1 updated and TLEAD specified for PDIP packages in Table 7: Absolute maximum ratings. ICC0 added, ICC voltage conditions changed and ICC1 specified over the whole voltage range in Table 13: DC characteristics (M24xxx-W, device grade 6). ICC0 added, ICC frequency conditions changed and ICC1 specified over the whole voltage range in Table 15: DC characteristics (M24xxx-R device grade 6). tW modified in Table 17: AC characteristics (M24xxx-W6, M24xxW3, M24xxR6). SO8N package specifications updated (see Figure 15 and Table 20). Device grade 5 added, B and P Process letters added to Table 24: Ordering information scheme. Small text changes. ICC1 modified in Table 13: DC characteristics (M24xxx-W, device grade 6). Note 1 added to Table 16: DC characteristics (M24xxx-F) and table title modified. UFDFPN8 package specifications updated (see Table 22). M24128-BWand M24128-BR part numbers added. Generic part number corrected in Features on page 1. ICC0 corrected in Table 14 and Table 13. Packages are ECOPACK® compliant. Available packages and temperature ranges by product specified in Table 25, Table 26 and Table 27. Notes modified below Table 12: Input parameters. VIH max modified in DC characteristics tables (see Table 13, Table 14, Table 15 and Table 16). C process code added to Table 24: Ordering information scheme. For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007 on, tW will be 5 ms (see Table 17: AC characteristics (M24xxx-W6, M24xxW3, M24xxR6). Small text changes. Section 2.5: VSS ground and Section 4.9: ECC (error correction code) and write cycling added. VIL and VIH modified in Table 15: DC characteristics (M24xxx-R - device grade 6). JEDEC standard reference updated below Table 7: Absolute maximum ratings. Package mechanical data inch values calculated from mm and rounded to 4 decimal digits (see Section 8: Package mechanical data). 29-Jun-2006 7 03-Jul-2006 8 17-Oct-2006 9 27-Apr-2007 10 27-Nov-2007 11 37/39 Revision history Table 28. Date M24128, M24C64, M24C32 Document revision history (continued) Revision Changes Added Section 2.6.2: Power-up conditions, updated Section 2.6.3: Device reset, and Section 2.6.4: Power-down conditions in Section 2.6: Supply voltage (VCC). Updated Figure 5: Maximum RP value versus bus parasitic capacitance (C) for an I2C bus. Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6, respectively, in Section 4.9: ECC (error correction code) and write cycling. Added temperature grade 6 in Table 10: Operating conditions (M24xxxF). Updated test conditions for ILO and VLO in Table 13: DC characteristics (M24xxx-W, device grade 6), Table 14: DC characteristics (M24xxx-W, device grade 3), and Table 15: DC characteristics (M24xxx-R - device grade 6). Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤ VCC < 2.5 V and 2.5 V ≤VCC < 5.5 V in Table 16: DC characteristics (M24xxx-F). Updated Table 17: AC characteristics (M24xxx-W6, M24xxW3, M24xxR6), and Table 18: AC characteristics (M24xxx-F). Updated Figure 13: AC waveforms. Added M24128-BF in Table 27: Available M24128 products (package, voltage range, temperature grade). Process B removed fromTable 24: Ordering information scheme. Small text changes. C Process option and Blank Plating technology option removed from Table 24: Ordering information scheme. WLCSP package added (see Figure 3: M24128 WLCSP connections (top view, marking side, with balls on the underside) and Section 8: Package mechanical data). Section 4.9: ECC (error correction code) and write cycling updated. IOL added to Table 7: Absolute maximum ratings. Table 26: Available M24C64 products (package, voltage range, temperature grade) and Table 27: Available M24128 products (package, voltage range, temperature grade) updated. 18-Dec-2007 12 30-May-2008 13 15-Jul-2008 14 16-Sep-2008 15 38/39 M24128, M24C64, M24C32 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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