M24128X-FCU6T/TF

M24128X-FCU Datasheet 128-Kbit serial I²C bus EEPROM with configurable device address and software write protection, delivered in 4-ball CSP Features • • • WLCSP (CU) • • • • • • • • • • Product status link Compatible with the 400 kHz I²C protocol High speed 1 MHz transfer rate Memory array: – 128 Kbit (16 Kbyte) of EEPROM – Page size: 32 byte Supply voltage range: – 1.7 V to 5.5 V over –40 °C / +85 °C – 1.6 V to 5.5 V over 0 °C / +85 °C Write – Byte write within 5 ms – Page write within 5 ms Random and sequential read modes Configurable device address Software write protection ESD protection – Human body model: 4 kV Enhanced ESD / Latch-Up protection More than 4 million write cycles More than 200-year data retention Package – RoHS and halogen free (ECOPACK2) M24128X-FCU DS12680 - Rev 2 - October 2019 For further information contact your local STMicroelectronics sales office. www.st.com M24128X-FCU Description 1 Description This EEPROM device supports standard I²C instruction set. The M24128X-FCU is a 128-Kbit I2C-compatible EEPROM (electrically erasable PROgrammable memory) organized as 16 K × 8 bits and delivered in a 4-ball WLCSP package. The M24128X-FCU can operate with a supply voltage of 1.7 V to 5 V, over an ambient temperature range of -40 °C/+85 °C. It can also operate down to 1.6 V, under some restricting conditions The M24128X-FCU additionally offers an 8-bit chip enable register for the configurable device address (CDA), to configure by software up to eight possibilities of chip enable address, and the memory write protection, enabled by setting, always through software, the write protection bit. Figure 1. Logic diagram VCC SCL M24128X-FCU SDA VSS Table 1. Signal names DS12680 - Rev 2 Signal name Function Direction SDA Serial Data I/O SCL Serial Clock Input VCC Supply voltage - VSS Ground - page 2/35 M24128X-FCU Description Figure 2. 4-bump WLCSP connections 1 2 2 1 A VCC SCL SCL VCC A B SDA VSS VSS SDA B Marking side (top view) Bump side (bottom view) Table 2. Signals vs. bump position DS12680 - Rev 2 Position A B 1 VCC SDA 2 SCL VSS page 3/35 M24128X-FCU Signal description 2 Signal description 2.1 Serial Clock (SCL) SCL is an input. The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 VSS (ground) VSS is the reference for the VCC supply voltage. 2.4 Supply voltage (VCC) 2.4.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually from 10 to 100 nF) close to the VCC / VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.4.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Table 9 in Section 9 DC and AC parameters). 2.4.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 9 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 9 DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.4.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). DS12680 - Rev 2 page 4/35 M24128X-FCU Memory organization 3 Memory organization The memory is organized as shown below. Figure 3. Block diagram SENSE AMPLIFIERS DATA REGISTER SCL ARRAY I/O X DECODER Y DECODER PAGE LATCHES SDA START & STOP DETECT CONTROL LOGIC HV GENERATOR + SEQUENCER ADDRESS REGISTER DS12680 - Rev 2 page 5/35 M24128X-FCU Features 4 Features 4.1 Chip enable register As the M24128X is delivered in 4-ball WLCSP without chip enable inputs, the device provides a non-volatile 8-bit register allowing the user to define a configurable device address (CDA) and a software write protection. This register can be written and read with the device type identifier (1010b) and with a specific address.The description of the chip enable register is given Table 3. Table 3. Chip enable register values bit 7 bit 6 bit 5 bit 4 x (1) x(1) x(1) x(1) bit 3 bit 2 bit 1 bit 0 C2 C1 C0 b0 Configurable device address bit Configurable device address bit Configurable device address bit SWP: Write protection activation bit 1. x = Don’t care bits. Factory delivery of the register is X0b Bit 7:4 Don’t care bits Bits 3:1 Chip enable address configuration: Bit 0 4.2 • (b3,b2,b1) = (0,0,0): the chip enable address is 000 (factory delivery value) • (b3,b2,b1) = (0,0,1): the chip enable address is 001 • (b3,b2,b1) = (0,1,0): the chip enable address is 010 • (b3,b2,b1) = (1,0,0): the chip enable address is 100 • (b3,b2,b1) = (1,1,0): the chip enable address is 110 • (b3,b2,b1) = (1,1,1): the chip enable address is 111 • (b3,b2,b1) = (0,1,1): the chip enable address is 011 • (b3,b2,b1) = (1,0,1): the chip enable address is 101 Enables or disables the write protection of the memory array: • b0 = 0: the whole memory array can be written and read (factory delivery value) • b0 = 1: the whole memory array is write protected and is in read-only mode Configurable device address C2, C1 and C0 are defining the chip enable address in the Device Select Code. These bits can be written and reconfigured with a Write command. Factory delivery value is 000b. At power up or after reprogramming, the device will load the last configuration of C2, C1 and C0 values. 4.3 Software write protect In order to prevent unwanted write sequence, the M24128X offers the SWP feature, which makes it possible to protect the whole memory content. write operations are disabled (read-only memory) when the SWP is set to 1 (SWP=1b). In the same way, the write operations are enabled when the SWP is set to 0 (SWP=0b). Factory default values is 0b. At power up, the device will load the last configuration of the SWP value. Updating the SWP to a new value is a reversible action: the SWP bit can be updated from 0 to 1 and from 1 to 0. When SWP is set to '1', device select and address bytes are acknowledged, data bytes are not acknowledged. DS12680 - Rev 2 page 6/35 M24128X-FCU Device operation 5 Device operation The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data is defined to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. Figure 4. I2C bus protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition DS12680 - Rev 2 page 7/35 M24128X-FCU Start condition 5.1 Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 5.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 5.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 5.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 5.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a start condition. Following this, the bus master sends the device select code, shown in Table 4 on serial data (SDA), most significant bit first. Table 4. Device select code Chip enable address (2) Device type identifier (1) RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 C2 C1 C0 RW 1. The most significant bit, b7, is sent first. 2. b3, b2 and b1 are compared with the C2, C1 and C0 values programmed in the chip enable register. When the device select code is received, the device responds only if the b3, b2 and b1 values match the values of the C2, C1 and C0 bits programmed in the chip enable register. If a match occurs, the corresponding device gives an acknowledgment on serial data (SDA) during the 9th bit time. If the device does not acknowledge the device select code, the device de-selects itself from the bus, and goes into standby mode (therefore will not acknowledge the device select code). The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. DS12680 - Rev 2 page 8/35 M24128X-FCU Instructions 6 Instructions 6.1 Write operations on memory array Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 5, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 5. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 Table 6. Least significant address byte A7 A6 A5 A4 A3 A2 A1 A0 When the bus master generates a stop condition immediately after a data byte ACK bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. After the stop condition and the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. If the software write protection is enabled with the SWP bit set to '1', the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 5. DS12680 - Rev 2 page 9/35 M24128X-FCU Write operations on memory array 6.1.1 Byte write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected, with the SWP bit set to '1', the device replies with NoACK, and the location is not modified, as shown in Figure 6. If, instead, the addressed location is not Write-protected, the device replies with ACK. The bus master terminates the transfer by generating a stop condition, as shown in Figure 5. Figure 5. Write mode sequence SWP bit = 0 (data write enabled) ACK Byte addr Start Dev sel ACK Byte addr Data in ACK Byte addr ACK Data in 1 Data in 2 R/W ACK ACK Data in N Stop Page Write (cont'd) Byte addr ACK R/W ACK Page Write ACK Stop Dev sel Start Byte Write ACK DS12680 - Rev 2 page 10/35 M24128X-FCU Write operations on memory array 6.1.2 Page write The page write mode allows up to 32 bytes to be written in a single write cycle, provided they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A5, are the same. If more bytes than those that will fit up to the end of the page are sent, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 32 bytes of data, each one is acknowledged by the device if the software write protection is disabled with the SWP bit set to '0'. If the software write protection is enabled with the SWP bit set to '1', the contents of the addressed memory location are not modified, and each data byte is followed by a NoACK, as shown in Figure 6. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 6. Write mode sequence with SWP bit = 1 (data write inhibited) ACK Byte addr Start Byte addr NO ACK Data in R/W ACK Page Write Start ACK Byte addr Dev sel ACK Byte addr NO ACK Data in 1 Data in 2 R/W NO ACK NO ACK Data in N Stop Page Write (cont'd) ACK Stop Dev sel Byte Write ACK DS12680 - Rev 2 page 11/35 M24128X-FCU Write operations on memory array 6.1.3 Minimizing write delays by polling on ACK During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum write time (tw) is shown in AC characteristics tables in Section 9 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: • Initial condition: a write cycle is in progress. • Step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal write cycle, no ACK will be returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an ACK, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). Note: In case of write to chip enable register when C2, C1 and C0 are re-configured, the device will return ACK only if: - chip enable address of the device select code is equal to the new C2, C1 and C0 values - an internal write cycle is completed (new C2, C1 and C0 values have been programmed in the chip enable register). Figure 7. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop 1. DS12680 - Rev 2 NO StartCondition YES Data for the write operation Device select with RW = 1 Continue the write operation Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the figure) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the figure). page 12/35 M24128X-FCU Write operations on chip enable register 6.2 Write operations on chip enable register Write operations on chip enable register are performed independently of the state software write protect bit (SWP) . Following a start condition the bus master sends a device select code with the R/W bit (RW) set to 0. The device acknowledges this, as shown in Figure 8, and waits for the address bytes where the register is located. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. In order to write the chip enable register, address bytes must have A15 bit set to 1, all other bits A14 to A0 being don't care. Table 7. Address of the chip enable register A15 (1) A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 X (2) X X X X X X X X X X X X X X 1. MSB A15 is sent first. 2. X means Don’t Care bits. When the bus master generates a stop condition immediately after the data byte ACK bit (in the “10th bit” time slot), the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests (NoACK). If the three bits C2, C1 and C0 have been re-configured with a correct write command, the device will acknowledge if the chip enable address of the device select code is equal to the new values of C2, C1 and C0, otherwise NoACK. Sending more than one byte will abort the write cycle (chip enable register content will not be changed). Figure 8. Write on chip enable register Byte addr Dev sel Start Byte Write ACK RW ACK Byte addr ACK Data in Stop ACK MSv45963V1 DS12680 - Rev 2 page 13/35 M24128X-FCU Read operations on memory array 6.3 Read operations on memory array Read operations are performed independently of the state of the software write protect bit (SWP). After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its Standby mode. Figure 9. Read mode sequences ACK Data out Stop Start Dev sel RW ACK Random Address Read Byte addr Dev sel * ACK ACK Data out 1 ACK NO ACK Data out N ACK Byte addr ACK Byte addr RW ACK Dev sel * Start Dev sel * Start Data out RW RW ACK NO ACK Stop Start Dev sel Sequential Random Read ACK Byte addr RW ACK Sequential Current Read ACK Start Start Dev sel * ACK Stop Current Address Read NO ACK ACK Data out1 RW NO ACK Stop Data out N DS12680 - Rev 2 page 14/35 M24128X-FCU Read operations on memory array 6.3.1 Random address read A dummy write is first performed to load the address into this address counter (as shown in Figure 8) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 6.3.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 8, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the identification page. When accessing the identification page, the address counter value is loaded with the identification page byte location, therefore the next current address read in the memory uses this new address counter value. When accessing the memory, it is safer to use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the current address read instruction. 6.3.3 Sequential read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. DS12680 - Rev 2 page 15/35 M24128X-FCU Read operations on chip enable register 6.4 Read operations on chip enable register Read operations are performed independently of the state software write protect bit (SWP). Following a start condition the bus master sends a device select code with the R/W bit (RW) set to 0. The device acknowledges this and waits for the address bytes where the register is located. The device responds to each address byte with an acknowledge. Then, the bus master sends another start condition, and repeats the device select code with the RW bit set to 1. The device acknowledges this, and outputs the contents of the chip enable register. To terminate the stream of data byte, the bus master must not acknowledge the byte, and must generate a stop condition, as shown in Figure 10. After the successful completion of a random address read operation, the device internal address counter is not incremented by one, to point to the next byte address. Reading more than one byte will loop on reading the chip enable register value. Reading the chip enable register is performed with a random read instruction at address 1xxx.xxxx.xxxx.xxxxb: • Bits b7, b6, b5, b4 of the chip enable register content are read as 0, 0, 0, 0. • The configurable device address bits b3, b2, b1 are described in Section 4.1 Chip enable register. • The software write protection bit b0 is defined in Section 4.1 Chip enable register. The chip enable register cannot be read while a write cycle (tw) is ongoing. The chip enable address value can be checked by sending the device select code. • If the chip enable address b3, b2, b1 sent in the device select code is matching with the C2, C1 and C0 values, device will send an acknowledge. • Otherwise, device will answer NoACK. Figure 10. Read on chip enable register Start Dev sel(1) 1. DS12680 - Rev 2 ACK Byte addr R/W ACK ACK Byte addr Dev sel(1) NO ACK Data out R/W Stop ACK The seven most significant bits of the device select code of a random read (in the first and fourth bytes) must be identical. page 16/35 M24128X-FCU Initial delivery state 7 Initial delivery state The device is delivered with all the memory array bits set to 1 (each byte contains FFh). The chip enable register is set to 0 (00h). DS12680 - Rev 2 page 17/35 M24128X-FCU Maximum ratings 8 Maximum ratings Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol Min. Max. Unit Ambient operating temperature –40 130 °C TSTG Storage temperature –65 150 °C TLEAD Lead temperature during soldering see note (1) IOL DC output current (SDA = 0) - 5 mA VIO Input or output range –0.50 6.5 V VCC Supply voltage –0.50 6.5 V VESD Electrostatic pulse (human body model)(2) - 4000 V - Parameter °C 1. Compliant with JEDEC standard J-STD-020D (for small-body, Sn-Pb or Pb free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to AECQ100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012, C1=100 pF, R1=1500 Ω). DS12680 - Rev 2 page 18/35 M24128X-FCU DC and AC parameters 9 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 9. Operating conditions Symbol VCC TA fC Parameter Min. Supply voltage 1.6 1.7 Ambient operating temperature: Read –40 -40 Ambient operating temperature: Write 0 -40 Max. Unit 5.5 V 85 °C Operating clock frequency VCC = 1.6 V - 400 Operating clock frequency VCC ≥ 1.7 V - 1000 kHz Table 10. AC measurement conditions Symbol Min. Max. Unit Load capacitance - 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V Cbus Parameter Figure 11. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3V CC 0.2VCC Table 11. Input parameters Symbol Parameter (1) Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF 1. Characterized only, not tested in production. DS12680 - Rev 2 page 19/35 M24128X-FCU DC and AC parameters Table 12. Cycling performance Symbol Ncycle Parameter Write cycle endurance (1) Test condition Max. Unit TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85°C, VCC(min) < VCC < VCC(max) 1.200.000 Write cycles (2) 1. The Write cycle endurance is defined by characterization and qualification. 2. A Write cycle is executed when either a page write, or a byte write or a write chip enable register instruction is decoded. Table 13. Memory cell data retention Parameter Test condition Min. Unit Data retention (1) TA = 55 °C 200 Year Cycling TA = 25 °C 4 million Cycle 1. The data retention behaviour is checked in production, while the data retention limit defined in this table is extracted from characterization and qualification results. Table 14. DC characteristics Symbol ILI ILO ICC ICC0 Parameter Test conditions (in addition to those in Table 9) VIL VIH VOL Max. Unit - ±2 µA µA Input leakage current VIN = VSS or VCC (SCL, SDA) device in Standby mode Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 VCC < 1.7 V, fC = 400 kHz - 0.8 VCC ≥ 1.7 V, fC = 400 kHz - 2 VCC ≥ 1.7 V, fC = 1 MHz - 2.5 During tW - 2 - 1 Device not selected, 6VIN = VSS or VCC, VCC = 2.5 V - 2 Device not selected, 6VIN = VSS or VCC, VCC = 5.5 V - 3 - –0.45 0.25 VCC V - 0.75 VCC VCC + 1 V IOL = 1 mA, VCC < 1.8 V - 0.2 V IOL = 2.1 mA, VCC = 2.5 V - 0.4 V IOL = 3 mA, VCC = 5.5 V - 0.4 V Supply current (Read) Supply current (Write)(1) Device not selected, 6 ICC1 Min. VIN = VSS or VCC, VCC = 1.7 V Standby supply current Input low voltage (SCL, SDA) Input high voltage (SCL, SDA) Output low voltage mA mA µA 1. Characterized value, not tested in production 2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). DS12680 - Rev 2 page 20/35 M24128X-FCU DC and AC parameters Table 15. 400 kHz AC characteristics (fast mode); Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tQL1QL2 (1) tF SDA (out) fall time 20 (2) 300 ns tXH1XH2 tR Input signal rise time (3) (3) ns tXL1XL2 tF Input signal fall time (3) (3) ns tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns 50 - ns - 900 ns (4) tDH Data out hold time tCLQV (5) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tW tWR Write time - 5 ms tNS (1) - Pulse width ignored (input filter on SCL and SDA) - single glitch - 50 ns tCLQX 1. Characterized only, not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. value for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12. DS12680 - Rev 2 page 21/35 M24128X-FCU DC and AC parameters Table 16. 1 MHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency 0 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 700 - ns tXH1XH2 tR Input signal rise time (1) (1) ns tXL1XL2 tF Input signal fall time (1) (1) ns 120 ns (2) Parameter tF SDA (out) fall time tDXCH tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns 50 - ns - 650 ns tQL1QL2 20 (3) (4) tDH Data out hold time tCLQV (5) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tW tWR Write time - 5 ms tNS (2) - Pulse width ignored (input filter on SCL and SDA) - 50 ns tCLQX 1. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when fC < 1 MHz. 2. Characterized only, not tested in production. 3. With CL = 10 pF. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13. DS12680 - Rev 2 page 22/35 M24128X-FCU DC and AC parameters Figure 12. Maximum Rbus value vs. bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (kΩ) 100 10 4k R bu s × C bu s= 40 Here Rbus x Cbus = 120 ns 0 The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left. VCC Rbus ns I²C bus master SCL M24xxx SDA 1 10 30 100 1000 Cbus Bus line capacitor (pF) Figure 13. Maximum Rbus value vs. bus parasitic capacitance (Cbus) for an I2C bus at fC = 1MHz VCC Bus line pull-up resistor (kΩ ) 10 0 Rbus 10 4 xC bus The Rbus x Cbus time constant Must be below the 150 ns Time constant line I²C bus SCL represented on the left master SDA = 15 0 ns Here, Rbus x Cbus = 120 ns Rbus M24xxx Cbus 1 10 30 100 Bus line capacitor (pF) DS12680 - Rev 2 page 23/35 M24128X-FCU DC and AC parameters Figure 14. AC waveforms Start condition Stop condition tXL1XL2 tXH1XH2 tCHCL Start condition tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX tDXCH SDA Change tCHDH Stop condition tDHDL Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS12680 - Rev 2 tCLQX Data valid tQL1QL2 Data valid page 24/35 M24128X-FCU Package information 10 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 10.1 Ultra thin WLCSP4 package information Figure 15. Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale package outline bbb Z D X Orientation reference Detail A Y e1 F E e F Orientation reference aaa (4X) A A2 Wafer back side G G Side view Bump A1 eee Z Z b (4X) Ø ccc M Z X Y Øddd M Z 1. 2. DS12680 - Rev 2 Seating plane Detail A Rotated 90 ° Drawing is not to scale. Primary datum Z and seating plane are defined by the spherical crowns of the bump. page 25/35 M24128X-FCU Ultra thin WLCSP4 package information Table 17. Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.240 0.270 0.300 0.0094 0.0106 0.0118 A1 - 0.095 - - 0.0037 - A2 - 0.175 - - 0.0079 - b(2)(3) - 0.185 - - 0.0073 - D - 0.851 0.871 - 0.0335 0.0343 E - 0.851 0.871 - 0.0335 0.0343 e - 0.400 - - 0.0157 - e1 - 0.500 - - 0.0197 - F - 0.226 - - 0.0089 - G - 0.176 - - 0.0069 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. DS12680 - Rev 2 page 26/35 M24128X-FCU Ultra thin WLCSP4 package information Figure 16. Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, with BSC, wafer level chip scale package outline Back side coating thickness 0.025 mm D X bbb Z Orientation reference Detail A Y e1 F E e F Orientation reference aaa (4X) A3 Wafer back side A A2 G G Side view Bump A1 eee Z Z b (4X) Ø ccc M Z X Y Øddd M Z 1. 2. DS12680 - Rev 2 Seating plane Detail A Rotated 90 ° Drawing is not to scale. Primary datum Z and seating plane are defined by the spherical crowns of the bump. page 27/35 M24128X-FCU Ultra thin WLCSP4 package information Table 18. Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, with BSC, wafer level chip scale package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.265 0.295 0.330 0.0104 0.0116 0.0130 A1 - 0.095 - - 0.0037 - A2 - 0.175 - - 0.0079 - A3 (BSC) - 0.025 - - 0.0010 - b(2)(3) - 0.185 - - 0.0073 - D - 0.851 0.871 - 0.0335 0.0343 E - 0.851 0.871 - 0.0335 0.0343 e - 0.400 - - 0.0157 - e1 - 0.500 - - 0.0197 - F - 0.226 - - 0.0089 - G - 0.176 - - 0.0069 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Figure 17. Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale recommended footprint 4 bumps x Ø 0.185 mm e1 e DS12680 - Rev 2 page 28/35 M24128X-FCU Ordering information 11 Ordering information Table 19. Ordering information scheme Example: M24 128X - F CU 6 T /T F Device type M24 = I2C serial access EEPROM Device function 128X = 128 Kbit (16384 x 8 bit) Operating voltage F = VCC = 1.7 V to 5.5 V Package (1) CU = 4-bump WLCSP ultra-thin Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 °C Option T = Tape and reel packing blank = tube packing Process technology(2) /T =Process letter Option Blank = No back side coating F = Back side coating 1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants). 2. The process letter appears on the device package (marking) and on the shipment box. Contact your nearest ST Sales Office for further information. Note: DS12680 - Rev 2 Parts marked as “ES” or “E” are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. page 29/35 M24128X-FCU Revision history Table 20. Document revision history DS12680 - Rev 2 Date Revision Changes 16-Nov-2018 1 Initial release 01-Oct-2019 2 Updated: Figure 3. Block diagram, Section 6.4 Read operations on chip enable register, Figure 10. Read on chip enable register page 30/35 M24128X-FCU Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 5 6 4.1 Chip enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.2 Configurable device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4.3 Software Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 6.1 Write operations on memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1.3 Minimizing write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 Write operations on chip enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.3 Read operations on memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3.1 DS12680 - Rev 2 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 page 31/35 M24128X-FCU Contents 6.4 6.3.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read operations on chip enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 10.1 11 Ultra thin WLCSP4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 DS12680 - Rev 2 page 32/35 M24128X-FCU List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signals vs. bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chip enable register values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Most significant address byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Address of the chip enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 kHz AC characteristics (fast mode); . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale package mechanical data . . . . . . . . Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, with BSC, wafer level chip scale package mechanical data . Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS12680 - Rev 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 6 . 8 . 9 . 9 13 18 19 19 19 20 20 20 21 22 26 28 29 30 page 33/35 M24128X-FCU List of figures List of figures Figure 1. Figure 2. Figure 3. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4-bump WLCSP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequence SWP bit = 0 (data write enabled) . . . . Write mode sequence with SWP bit = 1 (data write inhibited) Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . Write on chip enable register . . . . . . . . . . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . Read on chip enable register . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . Figure 12. Maximum Rbus value vs. bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . 23 Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Maximum Rbus value vs. bus parasitic capacitance (Cbus) for an I2C bus at fC = 1MHz. . . . . . . . AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale package outline. . . . . . . . Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, with BSC, wafer level chip scale package outline Ultra thin WLCSP- 4-bump, 0.851 x 0.851 mm, wafer level chip scale recommended footprint . . DS12680 - Rev 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 10 11 12 13 14 16 19 23 24 25 27 28 page 34/35 M24128X-FCU IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2019 STMicroelectronics – All rights reserved DS12680 - Rev 2 page 35/35