M24256-BWMN6T

M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Datasheet 256-Kbit serial I²C bus EEPROM Features • SO8N (MN) TSSOP8 (DW) 150 mil width 169 mil width • • UFDFPN8 (MC) DFN8 - 2x3 mm • • WLSCP (CS) WLSCP (CU) Unsawn wafer Product status link M24256-BF M24256-DF M24256-BR M24256-DR M24256-BW • • • • • Compatible with following I2C bus modes: – 1 MHz – 400 kHz – 100 kHz Memory array: – 256 Kbit (32 Kbyte) of EEPROM – Page size: 64 byte – Additional write lockable page (M24256-D order codes) Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.5 V Write: – Byte write within 5 ms – Page write within 5 ms Operating temperature range: – from -40 °C up to +85 °C Random and sequential read modes Write protect of the whole memory array Enhanced ESD/latch-Up protection More than 4 million write cycles More than 200-years data retention Packages • • • • • • RoHS-compliant and Halogen-free (ECOPACK2) SO8 ECOPACK2 TSSOP8 ECOPACK2 UFDFPN8 ECOPACK2 WLCSP ECOPACK2 Unsawn wafer (each die is tested) DS1766 - Rev 35 - November 2020 For further information contact your local STMicroelectronics sales office. www.st.com M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Description 1 Description The M24256 is a 256-Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 32 K × 8 bits. The M24256-BW can operate with a supply voltage from 2.5 V to 5.5 V, the M24256-BR AND M24256-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M24256-BF and M24256-DF can operate with a supply voltage from 1.7 V to 5.5 V. All these devices operate with a clock frequency of 1 MHz (or less), over an ambient temperature range of –40 °C / +85 °C. The M24256-D offers an additional page, named the identification page (64 byte). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. Figure 1. Logic diagram VCC 3 E0-E2 SDA M24xxx SCL WC VSS Table 1. Signal names Signal name Function Direction E2, E1, E0 Chip enable Input SDA Serial data I/O SCL Serial clock Input WC Write control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections, top view 1. DS1766 - Rev 35 E0 1 8 VCC E1 2 7 WC E2 3 6 SCL VSS 4 5 SDA See Section 9 Package information for package dimensions, and how to identify pin 1 page 2/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Description Figure 3. WLCSP connections 1 A 2 WC E1 E1 2 A WC VSS SDA B VCC C SDA E2 SCL 1 E0 VSS VCC D E 3 E0 B C 3 E2 Marking side (top view) D SCL E Bump side (bottom view) Table 2. Signal vs. bump position DS1766 - Rev 35 Position A B C D E 1 WC - VCC - SCL 2 - E0 - SDA - 3 E1 - VSS - E2 page 3/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Signal description 2 Signal description 2.1 Serial clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from serial data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor). 2.3 Chip enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 3). These inputs must be tied to VCC or VSS, as shown in Figure 4. When not connected (left floating), these inputs are read as low (0). Figure 4. Chip enable inputs connection VCC VCC M24xxx M24xxx Ei Ei VSS 2.4 VSS Write control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for the VCC supply voltage. DS1766 - Rev 35 page 4/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Supply voltage (VCC) 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8 DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). DS1766 - Rev 35 page 5/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Memory organization 3 Memory organization The memory is organized as shown below. Figure 5. Block diagram SENSE AMPLIFIERS PAGE LATCHES ARRAY SCL I/O X DECODER Y DECODER DATA REGISTER + ECC SDA WC START & STOP DETECT Ei CONTROL LOGIC IDENTIFICATION PAGE HV GENERATOR + SEQUENCER ADDRESS REGISTER DS1766 - Rev 35 page 6/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Device operation 4 Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. Figure 6. I2C bus protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition DS1766 - Rev 35 page 7/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Start condition 4.1 Start condition Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition. 4.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable and driven high. A stop condition terminates communication between the device and the bus master. A read instruction that is followed by NoAck can be followed by a stop condition to force the device into the standby mode. A stop condition at the end of a write instruction triggers the internal write cycle. 4.3 Data input During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. DS1766 - Rev 35 page 8/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Device addressing 4.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 3 (most significant bit first). Table 3. Device select code Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2 E1 E0 RW Device select code when accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2. When the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (E2, E1, E0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgement on serial data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. DS1766 - Rev 35 page 9/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Instructions 5 Instructions 5.1 Write operations Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 4. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 Table 5. Least significant address byte A7 A6 A5 A4 A3 A2 A1 A0 When the bus master generates a stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. After the stop condition and the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 8. DS1766 - Rev 35 page 10/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Write operations 5.1.1 Byte write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected, by write control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not write-protected, the device replies with Ack. The bus master terminates the transfer by generating a stop condition, as shown in Figure 7. Figure 7. Write mode sequences with WC = 0 (data write enabled) WC ACK Byte addr ACK ACK Data in Byte addr Stop Dev sel Start Byte Write ACK RW WC ACK Dev sel Start Page Write ACK Byte addr ACK Byte addr ACK Data in 1 Data in 2 RW WC (cont’d) ACK Data in N Stop Page Write (cont’d) ACK DS1766 - Rev 35 page 11/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Write operations 5.1.2 Page write The page write mode allows up to 64 byte to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 64 byte of data, each of which is acknowledged by the device if write control (WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 8. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 8. Write mode sequences with WC = 1 (data write inhibited) WC Byte write WC Page write WC (cont’d) Page write (cont’d) DS1766 - Rev 35 page 12/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Write operations 5.1.3 Write identification page (M24256-D only) The identification page (64 byte) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences: • Device type identifier = 1011b • MSB address bits A15/A6 are don't care except for address bit A10 which must be ‘0’. LSB address bits A5/A0 define the byte address inside the Identification page. If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoAck). 5.1.4 Lock identification page (M24256-D only) The lock identification page instruction (Lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions: • Device type identifier = 1011b • Address bit A10 must be ‘1’; all other address bits are don't care • The data byte must be equal to the binary value xxxx xx1x, where x is don't care 5.1.5 ECC (error correction code) and write cycling The error correction code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 11. DS1766 - Rev 35 page 13/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Write operations 5.1.6 Minimizing write delays by polling on ACK The maximum write time (tw) is shown in AC characteristics tables in Section 8 , but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: • Initial condition: a write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 9. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop 1. DS1766 - Rev 35 NO StartCondition YES Data for the write operation Device select with RW = 1 Continue the write operation Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the figure) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the figure). page 14/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Read operations 5.2 Read operations Read operations are performed independently of the state of the write control (WC) signal. After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its standby mode. Figure 10. Read mode sequences ACK Data out Stop Start Dev sel NO ACK RW ACK Random Address Read Byte addr Dev sel * ACK ACK Data out 1 ACK NO ACK Data out N ACK Byte addr ACK Byte addr RW ACK Dev sel * Start Dev sel * Start Data out RW RW ACK NO ACK Stop Start Dev sel Sequential Random Read ACK Byte addr RW ACK Sequential Current Read ACK Start Start Dev sel * ACK Stop Current Address Read ACK Data out1 RW NO ACK Stop Data out N DS1766 - Rev 35 page 15/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Read identification page (M24256-D only) 5.2.1 Random address read A dummy write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1 Random address read) instead of the current address Read instruction. 5.2.3 Sequential read This operation can be used after a current address read or a random address read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. 5.3 Read identification page (M24256-D only) The identification page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The identification page can be read by issuing an read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. The MSB address bits A15/A6 are don't care, the LSB address bits A5/A0 define the byte address inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the identification page from location 10d, the number of bytes should be less than or equal to 54, as the ID page boundary is 64 bytes). DS1766 - Rev 35 page 16/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Read the lock status (M24256-D only) 5.4 Read the lock status (M24256-D only) The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit if the identification page is unlocked, otherwise a NoAck bit if the identification page is locked. Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: • Start: the truncated command is not executed because the start condition resets the device internal logic, • Stop: the device is then set back into standby mode by the stop condition. DS1766 - Rev 35 page 17/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Initial delivery state 6 Initial delivery state The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh). DS1766 - Rev 35 page 18/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Parameter Min. Max. Unit - Ambient operating temperature -40 130 °C TSTG Storage temperature –65 150 °C TLEAD Lead temperature during soldering IOL DC output current (SDA = 0) – 5 mA VIO Input or output range –0.50 6.5 V VCC Supply voltage -0.50 6.5 V VESD Electrostatic pulse (Human Body model)(2) – 4000 V see note (1) °C 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω). DS1766 - Rev 35 page 19/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 7. Operating conditions (voltage range W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.8 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.7 5.5 V TA Ambient operating temperature -40 85 °C fC Operating clock frequency - 1 MHz VCC Parameter Table 8. Operating conditions (voltage range R) Symbol VCC Parameter Table 9. Operating conditions (voltage range F) Symbol VCC Parameter Table 10. AC measurement conditions Symbol Min. Max. Unit Load capacitance - 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V Cbus DS1766 - Rev 35 Parameter page 20/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Figure 11. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3V CC 0.2VCC Table 11. Input parameters Parameter(1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - kΩ VIN > 0.7 VCC 500 - kΩ ZL ZH Input impedance (E2, E1, E0, WC)(2) 1. Characterized only, not tested in production. 2. E2, E1, E0 input impedance when the memory is selected (after a Start condition). Table 12. Cycling performance by groups of four bytes Symbol Ncycle Parameter Write cycle endurance(1) Test condition Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(2) 1. The write cycle endurance is defined by characterization and qualification. For devices embedding the ECC functionality (see ECC (error correction code) and write cycling), the write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. 2. A Write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. When using the byte write, the page write or the write identification page, refer also to Section 5.1.5 ECC (error correction code) and write cycling Table 13. Memory cell data retention Parameter Data retention(1) Test condition TA = 55 °C Min. Unit 200 Year 1. The data retention behaviour is checked in production, while the data retention limit defined in this table is extracted from characterization and qualification results. DS1766 - Rev 35 page 21/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Table 14. DC characteristics (M24256-BW, device grade 6) Symbol ILI ILO Parameter Input leakage current (SCL, SDA, E2, E1, E0) Output leakage current Test conditions (in addition to those in Table 7) Min. Max. Unit VIN = VSS or VCC, device in Standby mode - ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA - 1 - 2 - 2.5 - 2(1) mA - 2 μA - 3 μA - –0.45 0.3 VCC V - 0.7 VCC 6.5 V - 0.7 VCC VCC+0.6 VCC = 2.5 V, fC = 400 kHz (rise/fall time < 50 ns) ICC Supply current (Read) VCC = 5.5 V, fC = 400 kHz (rise/fall time < 50 ns) 2.5 V ≤VCC ≤ 5.5 V, fC = 1 MHz (rise/fall time < 50 ns) ICC0 Supply current (Write) During tW, 2.5 V ≤ VCC ≤ 5.5 V Device not selected(2), ICC1 Standby supply current VIN = VSS or VCC, VCC = 2.5 V Device not selected(2), VIN = VSS or VCC, VCC = 5.5 V VIL Input low voltage(3) (SCL, SDA, WC, E2, E1, E0) Input high voltage VIH (SCL, SDA) Input high voltage (WC, E2, E1, E0)(4) VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V - mA 0.4 V V 1. Characterized value, not tested in production. 2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 3. Ei inputs should be tied to Vss (see Section 2.3 Chip enable (E2, E1, E0)). 4. Ei inputs should be tied to Vcc (see Section 2.3 Chip enable (E2, E1, E0)). DS1766 - Rev 35 page 22/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Table 15. DC characteristics (M24256-BR, M24256-DR device grade 6) Symbol ILI Parameter Input leakage current ( E0, E1, E2, SCL, SDA) ILO Output leakage current ICC Supply current (Read) ICC0 Supply current (Write) ICC1 Standby supply current VIL Input low voltage (SCL, SDA, WC,E2, E1, E0)(4) Input high voltage VIH (SCL, SDA) Input high voltage (WC, E2, E1, E0(5)) VOL Output low voltage Test conditions (1)(in addition to those in Table 8) Min. Max. Unit VIN = VSS or VCC, device in Standby mode - ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 0.8 mA fc= 1 MHz - 2.5 mA - 2(2) mA - 1 µA 1.8 V ≤ VCC < 2.5 V -0.45 0.25 VCC V 1.8 V ≤ VCC < 2.5 V 0.75 VCC 6.5 V 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC+0.6 During tW 1.8 V ≤ VCC ≤ 2.5 V Device not selected,(3) VIN = VSS or VCC, VCC = 1.8 V IOL = 1 mA, VCC = 1.8 V - 0.2 V V 1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 14 instead of this table. 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 4. Ei inputs should be tied to VSS (see Section 2.3 Chip enable (E2, E1, E0)). 5. Ei inputs should be tied to VCC (see Section 2.3 Chip enable (E2, E1, E0)). DS1766 - Rev 35 page 23/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Table 16. DC characteristics (M24256-BF, M24256-DF, device grade 6) Symbol Parameter Test conditions(1) (in addition to those in Table 9) Min. Max. Unit - ±2 µA µA Input leakage current VIN = VSS or VCC (E0, E1, E2, SCL, SDA) device in Standby mode ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 ICC Supply current (Read) VCC = 1.7 V, fc= 400 kHz - 0.8 fc= 1 MHz - 2.5 ICC0 Supply current (Write) - 2(2) mA ICC1 Standby supply current - 1 µA VIL Input low voltage (SCL, SDA, WC,E2, E1, E0)(4) 1.7 V ≤ VCC < 2.5 V -0.45 0.25 VCC V 1.7 V ≤ VCC < 2.5 V 0.75 VCC 6.5 V 1.7 V ≤ VCC < 2.5 V 0.75 VCC VCC+0.6 ILI Input high voltage VIH (SCL, SDA) Input high voltage (WC, E2, E1, E0)(5) VOL Output low voltage During tW 1.7 V < VCC < 2.5 V Device not selected,(3) VIN = VSS or VCC, VCC = 1.7 V IOL = 1 mA, VCC = 1.7 V - mA 0.2 V V 1. If the application uses the voltage range F device with 2.5 V < VCC < 5.5 V and -40 °C < TA < +85 °C, please refer to Table 14 instead of this table. 2. Characterized value, not tested in production. 3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 4. Ei inputs should be tied to VSS (see Section 2.3 Chip enable (E2, E1, E0)). 5. Ei inputs should be tied to VCC (see Section 2.3 Chip enable (E2, E1, E0)). DS1766 - Rev 35 page 24/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Table 17. 400 kHz AC characteristics Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tQL1QL2(1) tF SDA (out) fall time 20(2) 300 ns tXH1XH2 tR Input signal rise time (3) (3) ns tXL1XL2 tF Input signal fall time (3) (3) ns tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns 100 - ns - 900 ns tCLQX (4) tDH Data out hold time tCLQV(5) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns (1)(6) tSU:WC WC set up time (before the Start condition) 0 - µs tDHWH(1)(7) tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Internal Write cycle duration - 5 ms tNS(1) - Pulse width ignored (input filter on SCL and SDA) - single glitch - 80 ns tWLDL 1. Characterized only, not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12. 6. WC=0 set up time condition to enable the execution of a WRITE command. 7. WC=0 hold time condition to enable the execution of a WRITE command. DS1766 - Rev 35 page 25/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Table 18. 1 MHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency 0 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 500 - ns tXH1XH2 tR Input signal rise time (1) (1) ns tXL1XL2 tF Input signal fall time (1) (1) ns 120 ns (2) Parameter tF SDA (out) fall time 20(3) tDXCH tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns 100 - ns - 450 ns tQL1QL2 tCLQX (4) tDH Data out hold time tCLQV(5) tAA Clock low to next data valid (access time) tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns (2)(6) tSU:WC WC set up time (before the Start condition) 0 - µs tDHWH(2)(7) tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Write time - 5 ms tNS(2) - Pulse width ignored (input filter on SCL and SDA) - 50 ns tWLDL 1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. 2. Characterized only, not tested in production. 3. With CL = 10 pF. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13. 6. WC=0 set up time condition to enable the execution of a WRITE command. 7. WC=0 hold time condition to enable the execution of a WRITE command. DS1766 - Rev 35 page 26/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (kΩ) 100 10 4k R bu s × C bu s= 40 Here Rbus x Cbus = 120 ns 0 The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left. VCC Rbus ns I²C bus master SCL M24xxx SDA 1 10 30 100 1000 Cbus Bus line capacitor (pF) Figure 13. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz VCC Bus line pull-up resistor (kΩ ) 10 0 Rbus 10 4 xC bus The Rbus x Cbus time constant Must be below the 150 ns Time constant line I²C bus SCL represented on the left master SDA = 15 0 ns Here, Rbus x Cbus = 120 ns Rbus M24xxx Cbus 1 10 30 100 Bus line capacitor (pF) DS1766 - Rev 35 page 27/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF DC and AC parameters Figure 14. AC waveforms Start condition Start Stop condition condition tXL1XL2 tXH1XH2 tCHCL tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX SDA tDXCH Change tCHDH tDHDL WC tDHWH tWLDL Stop condition Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS1766 - Rev 35 tCLQX Data valid tQL1QL2 Data valid page 28/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. For die information concerning the M24256-BF delivered in unsawn wafer, please contact your nearest ST Sales Office. 9.1 UFDFPN8 (DFN8) package information UFDFPN8 is an 8-lead, 2 × 3 mm, 0.55 mm thickness ultra thin profile fine pitch dual flat package. Figure 15. UFDFPN8 - Outline D N A B A ccc C Pin #1 ID marking E A1 C eee C Seating plane A3 Side view 2x aaa C 1 aaa C 2x 2 Top view D2 e 1 2 L3 Datum A b L1 L L3 Pin #1 ID marking E2 K L e/2 L1 e Terminal tip Detail “A” Even terminal ND-1 x e Bottom view 1. 2. 3. 4. DS1766 - Rev 35 See Detail “A” Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. page 29/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF UFDFPN8 (DFN8) package information Table 19. UFDFPN8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - 0.0197 K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee(3) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Figure 16. UFDFPN8 - Recommended footprint 1.400 0.500 0.300 0.600 1.200 1.300 1. DS1766 - Rev 35 Dimensions are expressed in millimeters. page 30/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF TSSOP8 package information 9.2 TSSOP8 package information TSSOP8 is an 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package. Figure 17. TSSOP8 – Outline D 8 5 c E1 1 E 4 α A1 CP A2 A b 1. L L1 e Drawing is not to scale. Table 20. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 CP - - 0.100 - - 0.0039 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DS1766 - Rev 35 page 31/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF TSSOP8 package information Figure 18. TSSOP8 – Recommended footprint 2.3 1.0 7.0 0.65 0.35 1. DS1766 - Rev 35 Dimensions are expressed in millimeters. page 32/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF SO8N package information 9.3 SO8N package information SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 19. SO8N – Outline h x 45˚ A2 A c ccc b e 0.25 mm GAUGE PLANE D k 8 E1 E 1 A1 L L1 1. Drawing is not to scale. Table 21. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. DS1766 - Rev 35 page 33/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF SO8N package information Figure 20. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS1766 - Rev 35 Dimensions are expressed in millimeters. page 34/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF WLCSP8 (CS) package information 9.4 WLCSP8 (CS) package information WLCSP8 is a 8 bumps, 1.289 x 1.379 mm, 0.4 mm pitch wafer level chip scale package Figure 21. WLCSP8 - Outline bbb Z D X e2 Y e Detail A E e3 aaa Reference F Wafer back side H A A2 (4X) e1 G Orientation Bump side Side view Bump A1 eee Z b Ø ccc M Ø ddd M Z Z X Y Z Detail A Rotated 90 ° 1. 2. 3. DS1766 - Rev 35 Seating plane Drawing is not to scale Primary datum Z and seating plane are defined by the spherical crowns of the bump. Bump position designation per JESD 95-1, SPP-010. page 35/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF WLCSP8 (CS) package information Table 22. WLCSP8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.500 0.540 0.580 0.0197 0.0213 0.0228 A1 - 0.190 - - 0.0075 - A2 - 0.350 - - 0.0138 - b(2) - 0.270 - - 0.0106 - D - 1.289 1.309 - 0.0507 0.0515 E - 1.379 1.399 - 0.0542 0.0550 e - 0.800 - - 0.0315 - e1 - 0.693 - - 0.0273 - e2 - 0.400 - - 0.0157 - e3 - 0.400 - - 0.0157 - F - 0.342 - - 0.0135 - G - 0.245 - - 0.0096 - H - 0.245 - - 0.0096 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 22. WLCSP8 - Recommended footprint 0.400 0.800 0.693 0.400 8 bumps x Ø 0.270 1. DS1766 - Rev 35 Dimensions are expressed in millimeters. page 36/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF WLCSP8 (CU) package information 9.5 WLCSP8 (CU) package information This WLCSP is a 8 balls, 1.289 x 1.376 mm, 0.4 mm pitch, with BSC, wafer level chip scale package Figure 23. WLCSP8 - Outline e1 X Y E aaa TOP VIEW 1 A1 b e3 F E D C B A A A2 Orientation reference SIDE VIEW BOTTOM VIEW A1 ccc M ddd M DS1766 - Rev 35 e2 2 bbb Z 1. 2. 3. 4. e G 3 A3 (2X) Orientation reference Detail A Backside protection D bbb Z aaa (2X) b Z XY Z Z Detail A Rotated 90 Seating plane Drawing is not to scale. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Bump position designation per JESD 95-1, SPP-010. page 37/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF WLCSP8 (CU) package information Table 23. WLCSP8 - Mechanical data inches(1) Millimeters Min Typ Max Min Typ Max A 0.255 0.295 0.335 A1 - 0.095 - 0.0100 0.0116 0.0132 - 0.0037 - A2 - 0.175 - - 0.0069 - A3 - 0.025 - - 0.0010 - b - 0.185 - - 0.0073 - D - 1.289 1.309 - 0.0507 0.0515 E - 1.376 1.396 - 0.0542 0.0550 e - 0.400 - - 0.0157 - e1 - 0.800 - - 0.0315 - e2 - 0.346 - - 0.0136 - e3 - 0.693 - - 0.0273 - F - 0.342 - - 0.0135 - G - 0.245 - - 0.0096 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to the 4rd decimal place Figure 24. WLCSP8 - Recommended footprint 0.800 0.400 0.346 0.693 8 bumps x 1. DS1766 - Rev 35 0.185 Dimensions are expressed in millimeters. page 38/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Ordering information 10 Ordering information Table 24. Ordering information scheme Example: M24 256 -D W MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function 256 = 256 Kbit (32 K x 8 bit) Device family B = Without identification page D = With identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V Package(1) MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MC = UFDFPN8 (DFN8) CS = WLCSP (chip scale package) CU = WLCSP Ultra-thin Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = ECOPACK2 Process(2) /K = Manufacturing technology code 1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants). 2. These process letters appear on the device package (marking) and on the shipment box. Contact your nearest ST Sales Office for further information DS1766 - Rev 35 page 39/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Ordering information Table 25. Ordering information scheme (unsawn wafer) Example: M24 256 - B F K W 20 I /90 Device type(1) M24 = I2C serial access EEPROM Device function 256 = 256 Kbit (32 K x 8 bit) Device family B = Without identification page Operating voltage F = VCC = 1.7 V to 5.5 V Process K = F8H Delivery form W =Unsawn wafer Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C 1. For all information concerning the M24256 delivered in unsawn wafer, please contact your nearest ST Sales Office. Note: DS1766 - Rev 35 Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. page 40/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Revision history Table 26. Document revision history Date Revision Changes Datasheet revision 25 split into: – M24256-125 datasheet for automotive products (range 3), – M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF (this datasheet) for standard products (range 6). Added: – Reference M24256-DF – Table 1: Signal names, Table 12: Memory cell data retention 22-Jun-2012 26 Updated: – Table 17: 400 kHz AC characteristics and Table 18: 1 MHz AC characteristics: added set up and hold timing conditions on WC (tWLDL and tDHWH) – Figure 18: M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline and Table 21: M24256-DFCS6TP/K, WLCSP 8- bump waferlevel chip scale package mechanical data – Cycling and data retention limits Deleted: – UFDFPN8, package revision MB 01-Aug-2012 27 18-Sep-2012 28 20-Nov-2012 29 Updated Figure 3: WLCSP connections and Figure 18: M24256-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline. Changed title of Figure 3: WLCSP connections. Updated Section 5.2.2: Current Address Read. Corrected “Device family” data in Table 24: Ordering information scheme. Deleted note (3) under Table 3: Device select code. 17-Dec-2012 30 Modified ICCO condition in Table 15: DC characteristics (M24256-BR, M24256-DR device grade 6). Deleted incorrect table (Table 15. DC characteristics (M24256-R, device grade 6)). Updated package list in Table 24: Ordering information scheme. Updated Figure 3: WLCSP connections. 21-Feb-2014 31 Added notes 4. and 5. in Table 14 and notes 5. and 6. in Table 15 and Table 16 Updated 17-Jun-2014 32 – Figure 3, – note 1 on Table 12 – In Table 24 note 1 on Package and blank reference on Option. Added: – Unsawn wafer reference on cover page and Table 25: Ordering information scheme (unsawn wafer) 01-Jun-2015 33 – Figure 20: WLCSP (CS) - 8-bump, 1.289 x 1.376 mm, 0.4 mm pitch wafer level chip scale package recommended footprint – reference to Engineering samples Updated: – Section 2.6.2, Section 4.5 DS1766 - Rev 35 page 41/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Date Revision Changes – Note 2 on Table 6 – Table 18 – Note 2 on Figure 15 – Table 21 – Note 2 on Table 24 Removed: – Note on tNS max value on Table 18 Added WLCSP (CU) package in cover page and in Section 9: Package information, Table 2: Signals vs. bump position. 14-Mar-2018 34 Updated Table 10: AC measurement conditions, Table 22: WLCSP (CS)8-bump, 1.289 x 1.376 mm, 0.4 mm pitch wafer level chip scale package mechanical data, Table 24: Ordering information scheme Updated: 19-Nov-2020 35 • Figure 5. Block diagram, • Table 6. Absolute maximum ratings, Table 12. Cycling performance by groups of four bytes, Table 14. DC characteristics (M24256-BW, device grade 6), Table 15. DC characteristics (M24256-BR, M24256-DR device grade 6), Table 16. DC characteristics (M24256-BF, M24256-DF, device grade 6), Table 18. 1 MHz AC characteristics, • note 1 in Table 13. Memory cell data retention • title of Figure 17. TSSOP8 – Outline andTable 20. TSSOP8 – Mechanical data; Figure 19. SO8N – Outline, Table 21. SO8N – Mechanical data and Figure 20. SO8N - Recommended footprint; Figure 21. WLCSP8 - Outline, Table 22. WLCSP8 Mechanical data and Figure 22. WLCSP8 - Recommended footprint; Figure 23. WLCSP8 - Outline, Table 23. WLCSP8 - Mechanical data and Figure 24. WLCSP8 - Recommended footprint Added: • DS1766 - Rev 35 , Figure 18. TSSOP8 – Recommended footprint page 42/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.1 5.2 DS1766 - Rev 35 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 Write identification page (M24256-D only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 Lock identification page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 page 43/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF Contents 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3 Read identification page (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.4 Read the lock status (M24256-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 10 9.1 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.2 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.3 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.4 WLCSP8 (CS) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.5 WLCSP8 (CU) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DS1766 - Rev 35 page 44/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal vs. bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Most significant address byte. . . . . . . . . . . . . . . . . . . . . . . . Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . Operating conditions (voltage range W) . . . . . . . . . . . . . . . . Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . Input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cycling performance by groups of four bytes . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics (M24256-BW, device grade 6). . . . . . . . . . DC characteristics (M24256-BR, M24256-DR device grade 6) . DC characteristics (M24256-BF, M24256-DF, device grade 6) . 400 kHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . Ordering information scheme (unsawn wafer) . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . DS1766 - Rev 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 9 10 10 19 20 20 20 20 21 21 21 22 23 24 25 26 30 31 33 36 38 39 40 41 page 45/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Logic diagram. . . . . . . . . . . . . . . . . 8-pin package connections, top view . WLCSP connections . . . . . . . . . . . . Chip enable inputs connection . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequences with WC = 0 (data write enabled) . Write mode sequences with WC = 1 (data write inhibited). Write cycle polling flowchart using ACK . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 12 14 15 21 Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS1766 - Rev 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 4 6 27 28 29 30 31 32 33 34 35 36 37 38 page 46/47 M24256-BW M24256-BR M24256-BF M24256-DR M24256-DF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2020 STMicroelectronics – All rights reserved DS1766 - Rev 35 page 47/47