M24256-DRDW8TP/K

M24256-DRE 256-Kbit serial I²C bus EEPROM - 105°C operation Datasheet - production data Features • Compatible with all I2C bus modes – 1 MHz – 400 kHz – 100 kHz TSSOP8 (DW) 169 mil width • Memory array – 256 Kbits (32 Kbytes) of EEPROM – Page size: 64 bytes – Additional Write lockable page (Identification page) • Extended temperature and voltage range – -40 °C to 105 °C; 1.7 V to 5.5 V • Schmitt trigger inputs for noise filtering SO8 (MN) 150 mil width • Short Write cycle time – Byte Write within 4 ms – Page Write within 4 ms • Write cycle endurance – 4 million Write cycles at 25 °C – 1.2 million Write cycles at 85 °C – 900 k Write cycles at 105 °C WFDFPN8 (MF) DFN8 - 2 x 3 mm • Data retention – more than 50 years at 105 °C – 200 years at 55 °C • ESD Protection (Human Body Model) – 4000 V • Packages – RoHS compliant and halogen-free (ECOPACK2®) January 2017 This is information on a product in full production. DocID027418 Rev 2 1/42 www.st.com Contents M24256-DRE Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 2/42 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.4 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.5 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID027418 Rev 2 M24256-DRE 5 Contents Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3 WFDFPN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID027418 Rev 2 3/42 List of tables M24256-DRE List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. 4/42 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Significant address bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DocID027418 Rev 2 M24256-DRE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO8N – 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package outline . 35 SO8N – 8-lead 4.9 x 6 mm, plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DocID027418 Rev 2 5/42 Description 1 M24256-DRE Description The M24256-DRE is a 256-Kbit serial EEPROM device operating up to 105 °C. The M24256-DRE is compliant with the level of reliability defined by the AEC-Q100 grade 2. The device is accessed by a simple serial I2C compatible interface running up to 1 MHz. The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory). The M24256-DRE is a byte-alterable memory (32 K × 8 bits) organized as 512 pages of 64 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M24256-DRE offers an additional Identification Page (64 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode. Figure 1. Logic diagram 7# % % (IGHVOLTAGE GENERATOR #ONTROLLOGIC 3#, 3$! )/SHIFTREGISTER $ATA REGISTER 9DECODER !DDRESSREGISTER ANDCOUNTER PAGE )DENTIFICATIONPAGE 8DECODER -36 6/42 DocID027418 Rev 2 M24256-DRE Description Table 1. Signal names Signal name Function Direction E2, E1, E0 Chip enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connection (   9&& (   :& (   6&/ 966   6'$ $,I 1. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1. DocID027418 Rev 2 7/42 Signal description M24256-DRE 2 Signal description 2.1 Serial Clock (SCL) The signal applied on this input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected between SDA and VCC (Figure 10 and Figure 11 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs are read as low (0). Figure 3. Device select code 6## 6## -XXX -XXX %I %I 633 633 !I 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/42 DocID027418 Rev 2 M24256-DRE 2.5 Signal description VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) VCC is the supply voltage pin. DocID027418 Rev 2 9/42 Device operation 3 M24256-DRE Device operation The device supports the I2C protocol (see Figure 4). The I2C bus is controlled by the bus master and the device is always a slave in all communications. The device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data. Figure 4. I2C bus protocol 3#, 3$! 3$! )NPUT 34!24 #ONDITION 3#,  3$! -3"  3$! #HANGE 34/0 #ONDITION     !#+ 34!24 #ONDITION 3#,  3$! -3"      !#+ 34/0 #ONDITION !)" 10/42 DocID027418 Rev 2 M24256-DRE 3.1 Device operation Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 3.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 3.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 3.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. DocID027418 Rev 2 11/42 Device operation 3.5 M24256-DRE Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, as shown in Table 2. The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable address (E2, E1, E0). A device select code handling any value other than 1010b (to select the memory) or 1011b (to select the Identification page) is not acknowledged by the memory device. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is received, the memory device only responds if the Chip Enable Address is the same as the value decoded on the E2, E1, E0 inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. Table 2. Device select code Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 When accessing the memory 1 0 1 0 E2 E1 E0 RW When accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2. If a match occurs on the device select code, the corresponding memory device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Once the memory device has acknowledged the device select code (Table 2), the memory device waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The memory device responds to each address byte with an acknowledge bit. 12/42 DocID027418 Rev 2 M24256-DRE Device operation Address byte Most significant address bits Table 3. Significant address bits Note: Memory Identification page (Device type identifier = 1010b) (Device type identifier = 1011b) Read Write Lock Identification Identification Identification page page page Random Address Read Write Read lock status b15 X X X X X X b14 A14 A14 X X X X b13 A13 A13 X X X X b12 A12 A12 X X X X b11 A11 A11 X X X X b10 A10 A10 X 0 1 0 b9 A9 A9 X X X X b8 A8 A8 X X X X b7 A7 A7 X X X X b6 A6 A6 X X X X b5 A5 A5 A5 A5 X X b4 A4 A4 A4 A4 X X b3 A3 A3 A3 A3 X X b2 A2 A2 A2 A2 X X b1 A1 A1 A1 A1 X X b0 A0 A0 A0 A0 X X A: significant address bit. X: bit is Don’t Care. DocID027418 Rev 2 13/42 Device operation 3.6 M24256-DRE Identification page The M24256-DRE offers an Identification Page (64 bytes) in addition to the 256-Kbit memory. The Identification page contains two fields: Note: • Device identification code: the first three bytes are programmed by STMicroelectronics with the Device identification code, as shown in Table 4. • Application parameters: the bytes after the Device identification code are available for application specific data. If the end application does not need to read the Device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode. The instructions Read, Write and Lock Identification Page are detailed in Section 4: Instructions. Table 4. Device identification code Address in Identification page 00h 14/42 Content ST manufacturer code 2C family code 01h I 02h Memory density code DocID027418 Rev 2 Value 20h E0h 0Fh (256-Kbit) M24256-DRE 4 Instructions 4.1 Write operations Instructions For a Write operation, the bus master sends a Start condition followed by a device select code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The device responds to each address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. After the successful completion of an internal Write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 6. DocID027418 Rev 2 15/42 Instructions 4.1.1 M24256-DRE Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified (see Figure 6). If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 5. Figure 5. Write mode sequences with WC = 0 (data write enabled) 7# !#+ !#+ "YTEADDR "YTEADDR !#+ $ATAIN 3TOP $EVSEL 3TART "YTE7RITE !#+ 27 7# !#+ "YTEADDR $EVSEL 3TART 0AGE7RITE !#+ !#+ "YTEADDR !#+ $ATAIN $ATAIN 27 7#CONTgD !#+ $ATAIN. 3TOP 0AGE7RITECONTgD !#+ 16/42 DocID027418 Rev 2 !)D M24256-DRE 4.1.2 Instructions Page Write The Page Write mode allows up to N(1) bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A6, are the same. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the page are overwritten. Note: The bus master sends from 1 to N(1) bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 6. Write mode sequences with WC = 1 (data write inhibited) 7# !#+ "YTEADDR !#+ "YTEADDR ./!#+ $ATAIN 3TOP $EVSEL 3TART "YTE7RITE !#+ 27 7# !#+ $EVSEL 3TART 0AGE7RITE !#+ "YTEADDR !#+ "YTEADDR ./!#+ $ATAIN $ATAIN 27 7#CONTgD ./!#+ $ATAIN. 3TOP 0AGE7RITECONTgD ./!#+ !)D 1. N is the number of bytes in a page. DocID027418 Rev 2 17/42 Instructions 4.1.3 M24256-DRE Write Identification Page The Identification Page (64 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: • Device type identifier = 1011b • Most significant address bits A15/A6 are don't care, except for address bit A10 which must be “0”. Least significant address bits A5/A0 define the byte location inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). 4.1.4 Lock Identification Page The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: 18/42 • Device type identifier = 1011b • Address bit A10 must be ‘1’; all other address bits are don't care • The data byte must be equal to the binary value xxxx xx1x, where x is don't care DocID027418 Rev 2 M24256-DRE 4.1.5 Instructions Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: • Initial condition: a Write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 7. Write cycle polling flowchart using ACK :ULWHF\FOH LQSURJUHVV 6WDUWFRQGLWLRQ 'HYLFHVHOHFW ZLWK5:  12 $&. UHWXUQHG