M24512-R
M24512-W M24512-DR
512 Kbit serial I²C bus EEPROM
with three Chip Enable lines
Features
■
Compatible with all I²C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■
Memory array:
– 512 Kb (64 Kbytes) of EEPROM
– Page size: 128 bytes
■
M24512- DR: additional Write lockable Page
(Identification page)
■
Noise suppression
– Schmitt trigger inputs
– Input noise filter
■
Write
– Byte Write within 5 ms
– Page Write within 5 ms
■
Random and Sequential Read modes
■
Write protect of the whole memory array
■
Single supply voltage:
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V
■
Enhanced ESD/Latch-Up protection
■
More than 1 million Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK2® (RoHS compliant and
Halogen-free)
SO8 (MW)
208 mils width
SO8 (MN)
150 mils width
TSSOP8 (DW)
UFDFPN8 (MB)
2 × 3 mm (MLP)
WLCSP (CS)
December 2010
Doc ID 16459 Rev 21
1/41
www.st.com
1
Contents
M24512-R, M24512-W, M24512-DR
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
3
2/41
2.6.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5
Addressing the memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.6
Addressing the Identification page (M24512-DR only) . . . . . . . . . . . . . . . 14
3.7
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9
Page Write (memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10
Write Identification Page (M24512-DR only) . . . . . . . . . . . . . . . . . . . . . . 16
3.11
Lock Identification Page (M24512-DR only) . . . . . . . . . . . . . . . . . . . . . . . 17
3.12
ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . 17
3.13
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
3.14
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15
Random Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16
Current Address Read (in memory array) . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
Contents
3.18
Read Identification Page (M24512-D only) . . . . . . . . . . . . . . . . . . . . . . . 21
3.19
Read the lock status (M24512-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.20
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 16459 Rev 21
3/41
List of tables
M24512-R, M24512-W, M24512-DR
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
4/41
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Device select code (for memory array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device select code to access the Identification page (M24512-DR only) . . . . . . . . . . . . . . 11
Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SO8W – 8-lead plastic small outline, 208 mils body width, package data . . . . . . . . . . . . . 30
SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . 31
TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 32
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WLCSP-R 8 bumps, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Available M24512-W and M24512-R products (package, voltage range,
temperature grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Available M24512-DR products (package, voltage range, temperature grade) . . . . . . . . . 36
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO, UFDFPN and TSSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WLCSP connections (top view, marking side, with balls on the underside) . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SO8W – 8-lead plastic small outline, 208 mils body width, package outline . . . . . . . . . . . 30
SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 31
TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 32
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
WLCSP-R 8 bumps, outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Doc ID 16459 Rev 21
5/41
Description
1
M24512-R, M24512-W, M24512-DR
Description
The M24512-x devices are I2C-compatible electrically erasable programmable memories
(EEPROM). They are organized as 64 Kb × 8 bits.
The M24512-D also offers an additional page, named the Identification Page (128 bytes)
which can be written and (later) permanently locked in Read-only mode. This Identification
Page offers flexibility in the application board production line, as it can be used to store
unique identification parameters and/or parameters specific to the production line.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a device select code and Read/Write
bit (RW) terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1.
Logic diagram
6##
%
%
3$!
-XXX
3#,
7#
633
Table 1.
Signal names
Signal name
6/41
!)G
Function
Direction
E0, E1, E2
Chip Enable
Inputs
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
Figure 2.
Description
SO, UFDFPN and TSSOP connections
E0
E1
E2
8
7
6
5
1
2
3
4
VSS
VCC
WC
SCL
SDA
AI04035e
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
WLCSP connections (top view, marking side, with balls on the underside)
VCC
SDA
SCL
E2
WC
E1
VSS
E0
ai17507
Caution:
As EEPROM cells loose their charge (and so their binary value) when exposed to ultra violet
(UV) light, EEPROM dice delivered in wafer form or in WLCSP package by
STMicroelectronics must never be exposed to UV light.
Doc ID 16459 Rev 21
7/41
Signal description
M24512-R, M24512-W, M24512-DR
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 6 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 6 indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code. When not connected (left floating), these inputs
are read as Low (0,0,0).
Figure 4.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven High. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven High, device select and address bytes are
acknowledged, Data bytes are not acknowledged.
8/41
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
2.5
Signal description
VSS ground
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 8, Table 9). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with
a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
VCC has to rise continuously from 0 V up to VCC(min) (see Table 8, Table 9), and the rise
time must not vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included. At power-up, the device does not respond to any instruction until VCC
reaches an internal reset threshold voltage. This threshold is lower than the minimum VCC
operating voltage defined in Table 8, Table 9.
When VCC passes over the POR threshold, the device is reset and enters the Standby
Power mode. However, the device must not be accessed until VCC reaches a valid and
stable VCC voltage within the specified [VCC(min), VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power on reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4
Power-down conditions
During power-down (where VCC decreases continuously), the device must be in the Standby
Power mode (mode reached after decoding a Stop condition, assuming that there is no
internal Write cycle in progress).
Doc ID 16459 Rev 21
9/41
Signal description
M24512-R, M24512-W, M24512-DR
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
Figure 5.
Bus line pull-up resistor
(k )
100
10
4 kΩ
When tLOW = 1.3 µs (min value for
fC = 400 kHz), the Rbus × Cbus
time constant must be below the
400 ns time constant line
represented on the left.
R
bu
s ×
C
bu
s =
Here Rbus × Cbus = 120 ns
40
VCC
Rbus
0n
s
I²C bus
master
SCL
M24xxx
SDA
1
30 pF
10
100
Bus line capacitor (pF)
Cbus
1000
ai14796b
Bus line pull-up resistor (k )
Figure 6.
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
100
VCC
When tLOW = 700 ns
(max possible value for
fC = 1 MHz), the Rbus × Cbus
time constant must be below
the 270 ns time constant line
represented on the left.
R
bus ×
C
bus =
270
10
5
ns
R
bus ×
C
bus =
10
0 ns
Here,
Rbus × Cbus = 150 ns
When tLOW = 400 ns
(min value for fC = 1 MHz),
the Rbus × Cbus time constant
must be below the 100 ns
time constant line represented
on the left.
Rbus
I²C bus
master
SCL
M24xxx
SDA
Cbus
1
10
100
30
Bus line capacitor (pF)
ai14795d
10/41
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
Figure 7.
Signal description
I2C bus protocol
SCL
SDA
SDA
Input
Start
condition
SCL
1
2
SDA
MSB
SDA
Change
Stop
condition
3
7
8
9
ACK
Start
condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
Stop
condition
AI00792c
Table 2.
Device select code (for memory array)
Device type identifier(1)
Device select code
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
0
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Table 3.
Device select code to access the Identification page (M24512-DR only)
Device type identifier(1)
Device select code
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
Doc ID 16459 Rev 21
11/41
Signal description
Table 4.
b15
Table 5.
b7
12/41
M24512-R, M24512-W, M24512-DR
Most significant address byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Least significant address byte
b6
b5
b4
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
3
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always slave in all
communications.
3.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the High state. A Start condition must precede any data transfer instruction. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
3.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven High. A Stop condition terminates communication between the device and the
bus master. A Read instruction that is followed by NoAck can be followed by a Stop
condition to force the device into the Standby mode. A Stop condition at the end of a Write
instruction triggers the internal Write cycle.
3.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to
acknowledge the receipt of the eight data bits.
3.4
Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven Low.
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Device operation
3.5
M24512-R, M24512-W, M24512-DR
Addressing the memory array
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 6.
Operating modes
RW bit
WC(1)
Bytes
1
X
1
Random Address
Read
0
X
1
X
Sequential Read
1
X
1
Byte Write
0
VIL
1
Start, device select, RW = 0
Page Write
0
VIL
128
Start, device select, RW = 0
Mode
Current Address
Read
Initial sequence
Start, device select, RW = 1
Start, device select, RW = 0, Address
1
re-Start, device select, RW = 1
Similar to Current or Random Address
Read
1. X = VIH or VIL.
3.6
Addressing the Identification page (M24512-DR only)
The M24512-DR features an additional memory page, referred to as Identification page.
Read and write operations can be performed on this page, except if a Lock instruction has
been issued to permanently write protect it.
The M24512-DR Identification page is addressed in the same way as the memory array,
except that the 4-bit device type identifier of the device select code is 1011b (see Table 3).
14/41
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M24512-R, M24512-W, M24512-DR
Figure 8.
Device operation
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
NO ACK
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
Data in N
Stop
Page Write
(cont'd)
NO ACK
AI01120d
Doc ID 16459 Rev 21
15/41
Device operation
3.7
M24512-R, M24512-W, M24512-DR
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The most significant
byte (Table 4) is sent first, followed by the least significant byte (Table 5). Bits b15 to b0 form
the address of the byte in memory.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
3.8
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven High, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
3.9
Page Write (memory array)
The Page Write mode allows up to or 128 bytes to be written in a single Write cycle,
provided that they are all located in the same ‘row’ in the memory: that is, the most
significant memory address bits (b15-b7) are the same. If more bytes are sent than will fit up
to the end of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as
data starts to become overwritten in an implementation dependent way.
The bus master sends from 1 to or 128 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is Low. If Write Control (WC) is High, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (the 7 least significant
address bits only) is incremented. The transfer is terminated by the bus master generating a
Stop condition.
3.10
Write Identification Page (M24512-DR only)
The Identification Page (128 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. The identification page is written by issuing an
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M24512-R, M24512-W, M24512-DR
Device operation
Write Identification Page instruction. This instruction uses the same protocol and format as
Page Write (into memory array), except for the following differences:
●
Device type identifier = 1011b
●
MSB address bits A15/A7 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A6/A0 define the byte address inside the identification page.
If the Identification page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
3.11
Lock Identification Page (M24512-DR only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification page
in read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●
Device Type Identifier = 1011b
●
Address bit A10 must be ‘1’; all other address bits are don't care
●
The data byte must be equal to the binary value xxxx xx1x, where x is don't care.
If the Identification Page is locked, the data bytes transferred during the ID Write instruction
are not acknowledged (NoAck).
3.12
ECC (error correction code) and write cycling
The M24512-x devices offer an ECC (error correction code) logic which compares each 4byte word with its six associated ECC EEPROM bits. As a result, if a single bit out of 4 bytes
of data happens to be erroneous during a Read operation, the ECC detects it and replaces
it by the correct value. The read reliability is therefore much improved by the use of this
feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the other three bytes
making up the word. It is therefore recommended to write by word (4 bytes) at address 4*N
(where N is an integer) in order to benefit from the larger amount of Write cycles.
The M24512-x devices are qualified at 1 million (1 000 000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-bytes.
Doc ID 16459 Rev 21
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Device operation
Figure 9.
M24512-R, M24512-W, M24512-DR
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
ACK
Byte addr
Byte addr
ACK
Data in
Stop
Dev sel
Start
Byte Write
ACK
R/W
WC
ACK
Dev sel
Start
Page Write
ACK
Byte addr
ACK
Byte addr
ACK
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write
(cont'd)
ACK
AI01106d
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Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
Device operation
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
Send Address
and Receive ACK
ReStart
NO
Stop
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
3.13
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 14, but the typical time is shorter. To make use of this, a polling sequence
can be used by the bus master.
The sequence, as shown in Figure 10, is:
●
Initial condition: a Write cycle is in progress.
●
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Doc ID 16459 Rev 21
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Device operation
3.14
M24512-R, M24512-W, M24512-DR
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
Figure 11. Read mode sequences
ACK
Data out
Stop
Start
Dev sel
R/W
ACK
Random
Address
Read
Byte addr
Dev sel *
ACK
NO ACK
Data out N
R/W
ACK
ACK
Byte addr
ACK
Byte addr
ACK
Dev sel *
Start
Start
Dev sel *
R/W
ACK
Data out
R/W
ACK
Data out 1
NO ACK
Stop
Start
Dev sel
Sequential
Random
Read
ACK
Byte addr
R/W
ACK
Sequential
Current
Read
ACK
Start
Start
Dev sel *
ACK
Stop
Current
Address
Read
NO ACK
ACK
Data out 1
R/W
NO ACK
Stop
Data out N
AI01105d
3.15
Random Address Read (in memory array)
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
20/41
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M24512-R, M24512-W, M24512-DR
3.16
Device operation
Current Address Read (in memory array)
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the byte.
3.17
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.18
Read Identification Page (M24512-D only)
The Identification Page (128 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A7 are don't
care, the LSB address bits A6/A0 define the byte address inside the Identification Page.The
number of bytes to read in the ID page must not exceed the page boundary (e.g.: when
reading the Identification Page from location 100d, the number of bytes should be less than
or equal to 28, as the ID page boundary is 128 bytes).
If the Identification Page is locked, the data bytes are read as FFh.
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Device operation
3.19
M24512-R, M24512-W, M24512-DR
Read the lock status (M24512-D only)
The locked/unlocked status of the Identification page can be checked by issuing a specific
truncated instruction consisting of the Identification Page Write instruction (see
Section 3.10) followed by one data byte. The data byte will be acknowledged if the
Identification page is unlocked, while it will not be acknowledged if the Identification page is
locked.
Once the acknowledge bit of this data byte is read, it is recommended to generate a Start
condition followed by a Stop condition, so that:
3.20
●
The instruction is truncated and not executed as the Start condition resets the device
internal logic.
●
The device is set to Standby mode by the Stop condition.
Acknowledge in Read mode
For all Read instructions, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this
time, the device terminates the data transfer and switches to its Standby mode.
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Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
4
Initial delivery state
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5
Maximum rating
Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Absolute maximum ratings
Symbol
TSTG
TLEAD
Parameter
Min.
Max.
Unit
Ambient temperature with power applied
–55
130
°C
Storage temperature
–65
150
°C
Lead temperature during soldering
See
note (1)
°C
VIO
Input or output range
–0.50
6.5
V
VCC
Supply voltage
–0.50
6.5
V
IOL
DC output current (SDA = 0)
5
mA
3000
V
VESD
Electrostatic discharge voltage (human body model)
(2)
–3000
ECOPACK®
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST
7191395 specification, and the European directive on the restriction of the use of certain hazardous
substances in electrical and electronic equipment (RoHS) 2002/95/EC.
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 , R2 = 500 )
Doc ID 16459 Rev 21
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DC and AC parameters
6
M24512-R, M24512-W, M24512-DR
DC and AC parameters
This section summarizes the operating and measurement conditions, and the dc and ac
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 8.
Operating conditions (voltage range W)
Symbol
VCC
TA
Table 9.
Parameter
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
Operating conditions (voltage range R)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
Ambient operating temperature
–40
85
°C
AC test measurement conditions
Symbol
Cbus
Parameter
Min.
Load capacitance
Max.
100
SCL input rise/fall time, SDA input fall time
pF
50
ns
Input levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 12. AC test measurement I/O waveform
Input Levels
0.8VCC
Input and Output
Timing Reference Levels
0.7VCC
0.3VCC
0.2VCC
AI00825B
24/41
Unit
Doc ID 16459 Rev 21
M24512-R, M24512-W, M24512-DR
Table 11.
DC and AC parameters
Input parameters
Parameter(1)
Symbol
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
ZL(2)
Input impedance
(E2, E1, E0, WC)
VIN < 0.3VCC
30
k
ZH(2)
Input impedance
(E2, E1, E0, WC)
VIN > 0.7VCC
500
k
1. Sampled only, not 100% tested.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 12.
DC characteristics (voltage range W)
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA, E0, E1,
E2)
ILO
Output leakage
current
ICC
Test conditions (see Table 8 and
Table 10)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
±2
µA
VCC = 2.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
1.5
mA
2
mA
2.5
mA
5(1)
mA
VCC = 5.5 V, fc = 400 kHz
Supply current (Read) (rise/fall
time < 50 ns)
2.5 V < VCC < 5.5 V, fc = 1 MHz
(rise/fall time < 50 ns)
ICC0
ICC1
VIL
VIH
VOL
Supply current (Write) During tW, 2.5 V < VCC < 5.5 V
Standby supply
current
Device not selected(2), Device grade 3
VIN = VSS or VCC, VCC
Device grade 6
= 2.5 V
5
VIN = VSS or VCC, VCC = 5.5 V
3
µA
V
µA
2
Input low voltage
(SCL, SDA, WC)
–0.45
0.3VCC
Input high voltage
(SCL, SDA)
0.7VCC
6.5
V
Input high voltage
(WC, E0, E1, E2)
Output low voltage
0.7VCC VCC+0.6
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
0.4
V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 16459 Rev 21
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DC and AC parameters
Table 13.
Symbol
M24512-R, M24512-W, M24512-DR
DC characteristics (voltage range R)
Test conditions (in addition to
those in Table 9 and
Table 10)(1)
Parameter
ILI
Input leakage current
(E1, E2, SCL, SDA)
ILO
Output leakage current
ICC
ICC0
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc= 400 kHz
(rise/fall time < 50 ns)
1.5
mA
VCC = 1.8 V, fc= 1 MHz
(rise/fall time < 50 ns)
2.5
mA
During tW, VCC = 1.8 V,
5(2)
mA
1
µA
Supply current (Read)
Supply current (Write)
(3),
Device not selected
VIN = VSS or VCC, VCC = 1.8 V
ICC1
Standby supply current
VIL
Input low voltage
(SCL, SDA, WC)
1.8 V VCC < 2.5 V
–0.45
0.25 VCC
V
VIH
Input high voltage
(SCL, SDA)
1.8 V VCC < 2.5 V
0.75VCC
6.5
V
Input high voltage
(WC, E0, E1, E2)
1.8 V VCC < 2.5 V
0.75VCC
VCC+0.6
V
Output low voltage
IOL = 1 mA, VCC = 1.8 V
0.2
V
VOL
1. If the application uses the voltage range R device within 2.5
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