M24C16-DRMN3TP/K

M24C16-A125 Datasheet Automotive 16-Kbit serial I²C bus EEPROM with 1 MHz clock Features TSSOP8 (DW) • AEC-Q100 qualified • Compatible with all I2C bus modes – 1 MHz – 400 kHz – 100 kHz Memory array – 16 Kbits (2 Kbytes) of EEPROM – Page size: 16 bytes – Additional write lockable page (identification page) Extended temperature and voltage ranges – -40 °C to 125 °C; 1.7 V to 5.5 V Schmitt trigger inputs for noise filtering Short write cycle time – Byte write within 4 ms – Page write within 4 ms Write cycle endurance – 4 million write cycles at 25 °C – 1.2 million write cycles at 85 °C – 600 k write cycles at 125 °C Data retention – 50 years at 125 °C – 100 years at 25 °C ESD protection (human body model) – 4000 V Packages – RoHS compliant and halogen-free (ECOPACK2) 169 mil width • SO8N (MN) 150 mil width • WFDFPN8 (MF) • • DFN8 - 2 x 3 mm • Product status link • M24C16-A125 • • DS10068 - Rev 7 - September 2022 For further information contact your local STMicroelectronics sales office. www.st.com M24C16-A125 Description 1 Description The M24C16-A125 is a 16-Kbit serial EEPROM automotive grade device operating up to 125 °C. The M24C16A125 is compliant with the very high level of reliability defined by the automotive standard AEC-Q100 grade 1. The device is accessed by a simple serial I2C compatible interface running up to 1 MHz. The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory). The M24C16-A125 is a byte-alterable memory (2048 × 8 bits) organized as 128 pages of 16 bytes in which the data integrity is significantly improved with an embedded error correction code logic. The M24C16-A125 offers an additional identification page (16 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode. Figure 1. Logic diagram SENSE AMPLIFIERS DATA REGISTER + ECC ARRAY SCL I/O X DECODER Y DECODER PAGE LATCHES SDA START & STOP DETECT WC CONTROL LOGIC IDENTIFICATION PAGE HV GENERATOR + SEQUENCER ADDRESS REGISTER Table 1. Signal names Signal name Function Direction SDA Serial data I/O SCL Serial clock Input WC Write control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections NC 1 8 V CC NC 2 7 WC NC 3 6 SCL 4 5 SDA V SS 1. DS10068 - Rev 7 See Section 9 Package mechanical data for package dimensions, and how to identify pin 1. page 2/36 M24C16-A125 Signal description 2 Signal description 2.1 Serial clock (SCL) The signal applied on this input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial data (SDA) SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that may be wired-AND with other open drain or open collector signals on the bus. A pull up resistor must be connected between SDA and VCC (Figure 9 and Figure 10 indicate how to calculate the value of the pull-up resistor). 2.3 Write control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 2.4 VSS (ground) VSS is the reference for the VCC supply voltage. 2.5 Supply voltage (VCC) VCC is the supply voltage pin. DS10068 - Rev 7 page 3/36 M24C16-A125 Device operation 3 Device operation The device supports the I2C protocol (see Figure 3). The I2C bus is controlled by the bus master and the device is always a slave in all communications. The device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data. Figure 3. I2C bus protocol STOP Condition DS10068 - Rev 7 page 4/36 M24C16-A125 Start condition 3.1 Start condition Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) serial data (SDA) and serial clock (SCL) for a start condition. 3.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable and driven high. A stop condition terminates communication between the device and the bus master. A stop condition at the end of a write instruction triggers the internal write cycle. 3.3 Data input During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low. 3.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. DS10068 - Rev 7 page 5/36 M24C16-A125 Device addressing 3.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a start condition. Following this, the bus master sends the device select code, as shown in Table 2 (on serial data (SDA), most significant bit first). Table 2. Device select code Device type identifier (1) When accessing the memory When accessing the identification page Chip enable address RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 A10 A9 A8 RW 1 X(2) X(2) X(2) RW 1 0 1 1. The most significant bit, b7, is sent first. 2. X bit is a don’t care bit. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations. If a match occurs on the device select code, the corresponding memory device gives an acknowledgment on serial data (SDA) during the 9th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into standby mode. Table 3. Significant address bits Memory Identification page (Device type identifier = 1010b) Most significant address bits Address byte (Device type identifier = 1011b) Random address read Write Read identification page Write identification page Lock identification page b3(1) A10 A10 X X X b2(1) A9 A9 X X X b1(1) A8 A8 X X X b7 A7 A7 0 0 1 b6 A6 A6 X X X b5 A5 A5 X X X b4 A4 A4 X X X b3 A3 A3 A3 A3 X b2 A2 A2 A2 A2 X b1 A1 A1 A1 A1 X b0 A0 A0 A0 A0 X Read lock status see Section 4.2.5 1. Address bits defined inside the device select code (see Table 2) Note: DS10068 - Rev 7 A: significant address bit. X: bit is Don’t Care. page 6/36 M24C16-A125 Identification page 3.6 Identification page The M24C16-A125 offers an identification page (16 bytes) in addition to the 16-Kbit memory. The identification page contains two fields: • • Note: Device identification code: the first three bytes are programmed by STMicroelectronics with the device identification code, as shown in Table 4. Application parameters: the bytes after the device identification code are available for application specific data. If the end application does not need to read the device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the identification page, the whole identification page should be permanently locked in read-only mode. The instructions read, write and lock identification page are detailed in Section 4 Instructions. Table 4. Device identification code Address in identification page DS10068 - Rev 7 Content Value 00h ST manufacturer code 20h 01h I2C E0h 02h Memory density code family code 0Bh (16-Kbit) page 7/36 M24C16-A125 Instructions 4 Instructions 4.1 Write operations For a write operation, the bus master sends a start condition followed by a device select code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 4, and waits for the master to send the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a stop condition immediately after a data byte ACK bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is then triggered. A stop condition at any other time slot does not trigger the internal write cycle. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. After the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 5. DS10068 - Rev 7 page 8/36 M24C16-A125 Write operations 4.1.1 Byte write After the device select code and the address byte, the bus master sends one data byte. If the addressed location is Write-protected, by write control (WC) being driven high, the device replies with NoACK on the received data byte, and the location is not modified (see Figure 5). If, instead, the addressed location is not write-protected, the device replies with ACK. The bus master terminates the transfer by generating a stop condition, as shown in Figure 4. Figure 4. Write mode sequences with WC = 0 (data write enabled) WC ACK ACK Data in Stop Byte address Dev Select Start Byte Write ACK R/W WC ACK Dev Select Start Page Write ACK Byte address ACK Data in 1 ACK Data in 2 Data in 3 R/W WC (cont'd) ACK Data in N Stop Page Write(cont'd) ACK DS10068 - Rev 7 page 9/36 M24C16-A125 Write operations 4.1.2 Page write The page write mode allows up to N (N is the number of bytes in a page) bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A10/A4, are the same. If more bytes are sent than fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the page are overwritten. Note: The bus master sends from 1 to N bytes of data, each of which is acknowledged by the device if write control (WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is not acknowledged, as shown in Figure 5. After each byte is transferred, the internal byte address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 5. Write mode sequences with WC = 1 (data write inhibited) WC ACK Byte address NO ACK Data in Stop Dev select Start Byte Write ACK R/W WC ACK Dev select Start Page Write ACK Byte address NO ACK Data in 1 NO ACK Data in 2 Data in 3 R/W WC (cont'd) NO ACK Data in N Stop Page Write(cont'd) NO ACK DS10068 - Rev 7 page 10/36 M24C16-A125 Write operations 4.1.3 Write identification page The identification page (16 bytes) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences: • • Device type identifier = 1011b Most significant address bits A10/A4 are don't care, except for address bit A7 which must be “0”. Least significant address bits A3/A0 define the byte location inside the identification page. If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoACK). 4.1.4 Lock identification page The lock identification page instruction (lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions: • • • DS10068 - Rev 7 Device type identifier = 1011b Address bit A7 must be ‘1’; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care page 11/36 M24C16-A125 Write operations 4.1.5 Minimizing write delays by polling on ACK The maximum write time (tw) is shown in AC characteristics tables in Section 8 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 6, is: • • • Initial condition: a write cycle is in progress. Step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal write cycle, no ACK is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an ACK, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). Figure 6. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop NO Data for the write operation Continue the write operation 1. DS10068 - Rev 7 StartCondition YES Device select with RW = 1 Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the Figure 6) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the Figure 6). page 12/36 M24C16-A125 Read operations 4.2 Read operations Read operations are performed independently of the state of the write control (WC) signal. After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. Figure 7. Read mode sequences ACK Data out Stop Start Dev select R/W ACK Byte address Start Dev select * R/W ACK Sequential Current Read Dev select * NO ACK Data out R/W ACK ACK Data out 1 NO ACK Data out N Stop Start Dev select R/W ACK Start Dev select * ACK Byte address R/W ACK ACK Dev select * Start Sequential Random Read ACK Start Random Address Read ACK Stop Current Address Read NO ACK ACK Data out 1 R/W NO ACK Stop Data out N 4.2.1 Random address read The random address read is a sequence composed of a truncated write sequence (to define a new address pointer value, see Table 3) followed by a current read. The random address read sequence is therefore the sum of [start + device select code with R/W=0 + address byte] (without stop condition, as shown in Figure 7) and [start condition + device select code with R/W=1]. The memory device acknowledges the sequence and then outputs the contents of the addressed byte. To terminate the data transfer, the bus master does not acknowledge the last data byte and then issues a stop condition. DS10068 - Rev 7 page 13/36 M24C16-A125 Read operations 4.2.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte pointed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 7, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the identification page, the address counter value is loaded with the identification page byte location, when accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the current address read instruction. 4.2.3 Sequential read A sequential read can be used after a current address read or a random address read. After a read instruction, the device can continue to output the next byte(s) in sequence if the bus master sends additional clock pulses and if the bus master does acknowledge each transmitted data byte. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in Figure 7. The sequential read is controlled with the device internal address counter which is automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. 4.2.4 Read identification page The identification page can be read by issuing a read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. The most significant address bits A10/A4 are don't care except bit A7 which must be 0, the least significant address bits A3/A0 define the byte location inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary. 4.2.5 Read the lock status The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit after the data byte if the identification page is unlocked, otherwise a NoACK bit if the identification page is locked. Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: • • 4.2.6 Start: the truncated command is not executed because the start condition resets the device internal logic, Stop: the device is then set back into standby mode by the stop condition. Acknowledge in read mode For all read instructions, the device waits, after each byte sent out, for an acknowledgement from the bus master during the “9th bit” time slot. If the bus master does not send the acknowledge (the master drives SDA high during the 9th bit time), the device terminates the data transfer and enters its standby mode. DS10068 - Rev 7 page 14/36 M24C16-A125 Application design recommendations 5 Application design recommendations 5.1 Supply voltage 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 6). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. 5.1.2 Power-up conditions When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 6. In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal threshold voltage (this threshold is defined in the DC characteristic Table 10 as VRES). When VCC passes over the POR threshold, the device is reset and in the following state: • • in the standby power mode deselected As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)] range (defined in Table 6), the device is ready for operation. 5.1.3 Power-down During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 6), the device must be in standby power mode (that is after a stop condition or after the completion of the write cycle tW if an internal write cycle is in progress). 5.2 Error correction code (ECC x 1) The error correction code (ECC x 1) is an internal logic function which is transparent for the I2C communication protocol. The ECC x 1 logic is implemented on each byte of the memory array. If a single bit out of the byte happens to be erroneous during a read operation, the ECC x 1 detects this bit and replaces it with the correct value. The read reliability is therefore much improved. DS10068 - Rev 7 page 15/36 M24C16-A125 Delivery state 6 Delivery state The device is delivered as follows: • • DS10068 - Rev 7 The memory array is set to all 1s (each byte = FFh). Identification page: the first three bytes define the Device identification code (value defined in Table 4). The content of the following bytes is Don’t Care. page 16/36 M24C16-A125 Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Min. Max. Unit Ambient operating temperature –40 130 °C TSTG Storage temperature –65 150 °C TLEAD Lead temperature during soldering - Parameter VIO Input or output range IOL DC output current (SDA = 0) VCC Supply voltage VESD Electrostatic pulse (Human Body model) (2) see note (1) °C –0.50 6.5 V - 5 mA –0.50 6.5 V - 4000 V 1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001, C1=100 pF, R1=1500 Ω, R2=500 Ω). DS10068 - Rev 7 page 17/36 M24C16-A125 DC and AC parameters 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Operating conditions (voltage range R) Symbol Parameter VCC TA Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature –40 125 °C Table 7. AC measurement conditions Symbol Min. Max. Unit Load capacitance - 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V Cbus Parameter Figure 8. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3V CC 0.2VCC Table 8. Input parameters Parameter (1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - kΩ VIN > 0.7 VCC 500 - kΩ ZL Input impedance (WC) ZH 1. Evaluated by characterization, not tested in production. Table 9. Cycling performance Symbol Ncycle Parameter Write cycle endurance Test condition Min. Max. TA ≤ 25 °C, 1.7 V < VCC < 5.5 V - 4,000,000 TA = 85 °C, 1.7 V < VCC < 5.5 V - 1,200,000 TA = 125 °C, 1.7 V < VCC < 5.5 V - 600,000 Unit Write cycle (1) 1. A Write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. DS10068 - Rev 7 page 18/36 M24C16-A125 DC and AC parameters Table 10. DC characteristics Symbol ILI ILO ICC in Table 6 and Table 7) - ±2 µA fC = 400 kHz, VCC = 5.5 V - 2 mA fC = 400 kHz, VCC = 2.5 V - 2 mA fC = 400 kHz, VCC = 1.7 V - 1 mA fC = 1 MHz, VCC = 5.5 V - 2 mA fC = 1 MHz, VCC = 2.5 V - 2 mA fC = 1 MHz, VCC = 1.7 V - 2 mA During tW - 2 mA - 1 µA - 2 µA - 3 µA - 15 µA - 15 µA - 20 µA Supply current (Write) Standby supply current VIN = VSS or VCC, VCC = 5.5 V Device not selected(1), t° = 125 °C, VIN = VSS or VCC, VCC = 1.7 V Device not selected(1), t° = 125 °C, VIN = VSS or VCC, VCC = 2.5 V Device not selected(1), t° = 125 °C, VIN = VSS or VCC, VCC = 5.5 V Input low voltage (SCL, SDA, WC) - –0.45 0.3 VCC V Input high voltage (SCL, SDA) - 0.7 VCC 6.5 V Input high voltage (WC) - 0.7 VCC VCC +0.6 V - 0.4 V - 0.3 V 0.5 1.5 V IOL = 2.1 mA, VCC = 2.5 V or Output low voltage IOL = 3 mA, VCC = 5.5 V IOL = 1 mA, VCC = 1.7 V VRES µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC Device not selected(1), t° = 85 °C, (2) ±2 Output leakage current VIN = VSS or VCC, VCC = 2.5 V VOL - device in standby mode Device not selected(1), t° = 85 °C VIH Unit (SCL, SDA) VIN = VSS or VCC, VCC = 1.7 V VIL Max. VIN = VSS or VCC, Device not selected(1), t° = 85 °C, ICC1 Min. Input leakage current Supply current (Read) ICC0 Test conditions (in addition to those Parameter Internal reset threshold voltage - 1. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 2. Evaluated by characterization, not tested in production. DS10068 - Rev 7 page 19/36 M24C16-A125 DC and AC parameters Table 11. 400 kHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tQL1QL2 (1) tF SDA (out) fall time (2) 20 120 ns tXH1XH2 tR Input signal rise time (3) (3) ns tXL1XL2 tF Input signal fall time (3) (3) ns tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX (4) tDH Data out hold time 100 - ns tCLQV (5) tAA Clock low to next data valid (access time) - 900 ns tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tWLDL(1)(6) tSU:WC WC set up time (before the start condition) 0 - µs (1)(7) tHD:WC WC hold time (after the stop condition) 1 - µs Write time - 4 ms Pulse width ignored (input filter on SCL and SDA) - single glitch - 80 ns tDHWH tW tWR tNS (1) - Parameter 1. Evaluated by characterization, not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious start and stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 9. 6. WC=0 set up time condition to enable the execution of a write command. 7. WC=0 hold time condition to enable the execution of a write command. DS10068 - Rev 7 page 20/36 M24C16-A125 DC and AC parameters Table 12. 1 MHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency 0 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 500 - ns tXH1XH2 tR Input signal rise time (1) (1) ns tXL1XL2 tF Input signal fall time (1) (1) ns tQL1QL2 (2) tF SDA (out) fall time 20 120 ns tDXCH tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX (3) tDH Data out hold time 100 - ns tCLQV (4) tAA Clock low to next data valid (access time) - 450 ns tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tWLDL (2)(5) tSU:WC WC set up time (before the Start condition) 0 - µs (2)(6) tHD:WC WC hold time (after the Stop condition) 1 - µs Write time - 4 ms Pulse width ignored (input filter on SCL and SDA) - 80 ns tDHWH tW tWR tNS (2) - Parameter 1. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when fC < 1 MHz. 2. Evaluated by characterization, not tested in production. 3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 4. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 10. 5. WC=0 set up time condition to enable the execution of a WRITE command. 6. WC=0 hold time condition to enable the execution of a WRITE command. DS10068 - Rev 7 page 21/36 M24C16-A125 Figure 9. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line Pull up resistor (kΩ) 100 VCC The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left Rb us 10 xC bu s 00 Here Rbus x Cbus= 120 ns 4 =4 Rbus I²C bus master SCL M24xxx SDA ns Cbus 1 10 30 100 1000 Bus line capacitor (pF) Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz Bus line pull-up resistor (kΩ ) 100 10 Rbu s xC bus The Rbus x Cbus time constant must be below the 150 ns time constant line represented on the left = 15 0 ns 4 VCC Rbus I²C bus master SCL M24xxx SDA Here Rbus x Cbus = 120 ns Cbus 1 10 30 100 Bus line capacitor (pF) DS10068 - Rev 7 page 22/36 M24C16-A125 Figure 11. AC waveforms Start condition Start Stop condition condition tXL1XL2 tXH1XH2 tCHCL tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX SDA tDXCH Change tCHDH tDHDL WC tDHWH tWLDL Stop condition Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS10068 - Rev 7 tCLQX Data valid tQL1QL2 Data valid page 23/36 M24C16-A125 Package mechanical data 9 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 12. TSSOP8 – Outline D 8 Package TSSOP8 (package code 6P) 5 k E1 E A1 1 L L1 4 A2 A c b 1. DS10068 - Rev 7 e 6P_TSSOP8_ME_V3 Drawing is not to scale. page 24/36 M24C16-A125 TSSOP8 package information Table 13. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1(3) 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. Figure 13. TSSOP8 – Recommended footprint 1.55 0.65 0.40 2.35 5.80 7.35 1. DS10068 - Rev 7 6P_TSSOP8_FP_V2 Dimensions are expressed in millimeters. page 25/36 M24C16-A125 SO8N package information 9.2 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 14. SO8N – Outline Package SO8N (package code O7) A2 h x 45˚ A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 E 1 L A1 L1 1. Drawing is not to scale. Table 14. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0039 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS10068 - Rev 7 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 26/36 M24C16-A125 SO8N package information Figure 15. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS10068 - Rev 7 Dimensions are expressed in millimeters. page 27/36 M24C16-A125 WFDFPN8 (DFN8) package information 9.3 WFDFPN8 (DFN8) package information This WFDFPN is a 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package. Figure 16. WFDFPN8 (DFN8) – Outline Package WFDFPN8 (package code A0Y3) D A B E Pin #1 laser marking 0.20 DIA TYP 2x aaa C 2x aaa C Top view // ccc C eee C Seating plane Datum A C A A1 Side view L L3 D2 D2/2 Datum A e e e/2 L1 Terminal tip Detail “A” Pin #1 E2/2 E2 See Detail A A0Y3_WFDFPN8_ME_V4 K NX b (ND-1) x e bbb ddd M M CAB C Bottom view 1. 2. DS10068 - Rev 7 Drawing is not to scale. Exposed copper is not systematic and can appear partially or totally according to the cross section. page 28/36 M24C16-A125 WFDFPN8 (DFN8) package information Table 15. WFDFPN8 (DFN8) – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A 0.700 0.750 0.800 0.0276 0.0295 0.0315 A1 0.025 0.045 0.065 0.0010 0.0018 0.0026 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.500 - - 0.0197 - L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - D2 1.400 - 1.600 0.0551 - 0.0630 E2 1.200 - 1.400 0.0472 - 0.0551 K 0.400 - - 0.0157 - - 0.300 - 0.500 0.0118 - 0.0197 L NX (3) 8 ND (3) 4 aaa - - 0.150 - - 0.0059 bbb(4) - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee (5) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. N is the number of terminals, ND is the number of terminals on “D” sides. 4. Max package warpage is 0.05 mm. 5. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Figure 17. WFDFPN8 (DFN8) – Recommended footprint 1.200 0.300 0.500 1.400 1.300 Note: DS10068 - Rev 7 0.600 The central pad (the area E2 by D2 in the Figure 16) must be either connected to VSS or left floating (not connected) in the end application. page 29/36 M24C16-A125 Ordering information 10 Ordering information Table 16. Ordering information schene Example: M24 C16-D R MN 3 T P /K Device type M24 = I2C serial access EEPROM Device function C16-D = 16 Kbits (2048 x 8 bits) plus identification page Operating voltage R = VCC = 1.7 V to 5.5 V Package(1) MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MF = WFDFPN8 (DFN8) Device grade 3 = -40 to 125 °C. Automotive grade. Device tested with high reliability certified flow(2) Option T = Tape and reel packing blank = tube packing Plating technology P or G = ECOPACK2 Process /K = Manufacturing technology code 1. All packages are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimonyoxide flame retardants). 2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest ST sales office for a copy. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS10068 - Rev 7 page 30/36 M24C16-A125 Revision history Table 17. Document revision history Date Revision 08-Jan-2014 1 Changes Initial release. Updated: Table 2, Table 3and Table 16 10-Feb-2014 2 Replaced A10 with A7 in Section 4.1.3and in Section 4.1.4 Updated Section4.2.4 13-Aug-2014 3 Changed product maturity from Target spec to Preliminary data Changed product maturity from Preliminary to Production data. Updated Package information on Cover page. 11-Sep-2014 4 Added Footnote 2toFigure 14: WFDFPN8 (MLP8) – 8-lead thin fine pitch dual flat package no lead 2 x 3 mm, package outline. Updated Table 16:Orderinginformationscheme. Updated: 07-Jan-2015 5 • Note 2on Table 5 • Figure6 • Table12 Added sentence about Engineering sample on Section 10. Updated: 24-Feb-2016 6 • Features • Table9,Table 10, Table 16 Updated: • 01-Sep-2022 DS10068 - Rev 7 7 Figure 1. Logic diagram, • Section 2.2 Serial data (SDA) • note 1 and 2 inTable 5. Absolute maximum ratings; note in Table 1 and Table 4; note 2 in Table 3 and Table 5 • Table 16. Ordering information schene • Section 9.1 TSSOP8 package information, Section 9.2 SO8N package information, Section 9.3 WFDFPN8 (DFN8) package information page 31/36 M24C16-A125 Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3 4 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 Write control (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.4 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.5 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.6 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 4.2 5 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1.3 Write identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.4 Lock identification page. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.5 Minimizing write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.1 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.4 Read identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2.6 Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.1 5.2 DS10068 - Rev 7 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Error correction code (ECC x 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 page 32/36 M24C16-A125 Contents 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 10 9.1 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3 WFDFPN8 (DFN8) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 DS10068 - Rev 7 page 33/36 M24C16-A125 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal names . . . . . . . . . . . . . . . . . . Device select code . . . . . . . . . . . . . . . Significant address bits . . . . . . . . . . . . Device identification code . . . . . . . . . . Absolute maximum ratings . . . . . . . . . Operating conditions (voltage range R) . AC measurement conditions . . . . . . . . Input parameters . . . . . . . . . . . . . . . . Cycling performance . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . 400 kHz AC characteristics . . . . . . . . . 1 MHz AC characteristics . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . SO8N – Mechanical data . . . . . . . . . . WFDFPN8 (DFN8) – Mechanical data . Ordering information schene . . . . . . . . Document revision history . . . . . . . . . DS10068 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 6 . 6 . 7 17 18 18 18 18 19 20 21 25 26 29 30 31 page 34/36 M24C16-A125 List of figures List of figures Figure 1. Figure 2. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequences with WC = 0 (data write enabled) . Write mode sequences with WC = 1 (data write inhibited). Write cycle polling flowchart using ACK . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . Figure 9. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WFDFPN8 (DFN8) – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WFDFPN8 (DFN8) – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS10068 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 9 10 12 13 18 22 23 24 25 26 27 28 29 page 35/36 M24C16-A125 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS10068 - Rev 7 page 36/36