M24C32-DRDW3TP/K

M24C32-A125 Datasheet Automotive 32-Kbit serial I²C bus EEPROM with 1 MHz clock Features SO8N (MN) TSSOP8 • AEC-Q100 qualified • Compatible with all I2C bus modes – 1 MHz – 400 kHz – 100 kHz Memory array – 32 Kbit (4 Kbyte) of EEPROM – Page size: 32 byte – Additional write lockable page (identification page) Extended temperature and voltage ranges – -40 °C to 125 °C; 1.7 V to 5.5 V Schmitt trigger inputs for noise filtering. Short write cycle time – Byte write within 4 ms – Page write within 4 ms Write cycle endurance – 4 million write cycles at 25 °C – 1.2 million write cycles at 85 °C – 600 k write cycles at 125 °C Data retention – 50 years at 125 °C – 100 years at 25 °C ESD protection (human body model) – 4000 V Packages – RoHS compliant and halogen-free (ECOPACK2 ) 150 mil width 169 mil width • WFDFPN8 (MF) • DFN8 2 x 3 mm • • • Product status link • M24C32-A125 • • DS9133 - Rev 8 - June 2022 For further information contact your local STMicroelectronics sales office. www.st.com M24C32-A125 Description 1 Description The M24C32-A125 is a 32-Kbit serial EEPROM automotive grade device operating up to 125 °C. The M24C32A125 is compliant with the very high level of reliability defined by the automotive standard AEC-Q100 grade 1. The device is accessed by a simple serial I2C compatible interface running up to 1 MHz. The memory array is based on advanced true EEPROM technology (electrically erasable programmable memory). The M24C32-A125 is byte-alterable memories (4096 K × 8 bits) organized as 128 pages of 32 byte in which the data integrity is significantly improved with an embedded error correction code logic. The M24C32-A125 offers an additional identification page (32 byte) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode. Figure 1. Logic diagram SENSE AMPLIFIERS DATA REGISTER + ECC PAGE LATCHES X DECODER SDA ARRAY I/O Y DECODER SCL WC START and STOP DETECT Ei CONTROL LOGIC IDENTIFICATION PAGE HV GENERATOR + SEQUENCER ADDRESS REGISTER Table 1. Signal names DS9133 - Rev 8 Signal name Function Direction E2, E1, E0 Chip enable Input SDA Serial data I/O SCL Serial clock Input WC Write control Input VCC Supply voltage - VSS Ground - page 2/39 M24C32-A125 Description Figure 2. 8-pin package connections 1. DS9133 - Rev 8 E0 1 8 VCC E1 2 7 WC E2 3 6 SCL VSS 4 5 SDA See Section 9 Package information for package dimensions, and how to identify pin 1. page 3/39 M24C32-A125 Signal description 2 Signal description 2.1 Serial clock (SCL) The signal applied on this input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial data (SDA) SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that may be wired-AND with other open drain or open collector signals on the bus. A pull up resistor must be connected between SDA and VCC (Figure 10 and Figure 11 indicate how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs are read as low (0). Figure 3. Device select code VCC VCC M24xxx M24xxx Ei Ei VSS 2.4 VSS Write control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) VCC is the supply voltage pin. DS9133 - Rev 8 page 4/39 M24C32-A125 Device operation 3 Device operation The device supports the I2C protocol (see Figure 4). The I2C bus is controlled by the bus master and the device is always a slave in all communications. The device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data. Figure 4. I2C bus protocol STOP Condition DS9133 - Rev 8 page 5/39 M24C32-A125 Start condition 3.1 Start condition Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition. 3.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A stop condition terminates communication between the device and the bus master. A stop condition at the end of a write instruction triggers the internal write cycle. 3.3 Data input During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low. 3.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. DS9133 - Rev 8 page 6/39 M24C32-A125 Device addressing 3.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a start condition. Following this, the bus master sends the device select code, as shown in Table 2. The device select code consists of a 4-bit device type identifier and a 3-bit chip enable address (E2, E1, E0). A device select code handling any value other than 1010b (to select the memory) or 1011b (to select the identification page) is not acknowledged by the memory device. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the chip enable (E2, E1, E0) inputs. When the device select code is received, the memory device only responds if the chip enable address is the same as the value decoded on the E2, E1, E0 inputs. The 8th bit is the read/write bit (RW). This bit is set to 1 for read and 0 for write operations. Table 2. Device select code Device type identifier (1) Chip Enable address (2) RW - b7 b6 b5 b4 b3 b2 b1 b0 When accessing the memory 1 0 1 0 E2 E1 E0 RW When accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 bits are compared with the value read on input pins E0,E1,E2. If a match occurs on the device select code, the corresponding memory device gives an acknowledgement on serial data (SDA) during the 9th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into standby mode. Once the memory device has acknowledged the device select code (Table 2), the memory device waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The memory device responds to each address byte with an acknowledge bit. DS9133 - Rev 8 page 7/39 M24C32-A125 Device addressing Table 3. Significant bits within the two address bytes address byte address byte Least significant Most significant Memory Note: DS9133 - Rev 8 Identification page Random Address Read Write Read identification page Write identification page Lock identification page Read lock status b15 X X X X X X b14 X X X X X X b13 X X X X X X b12 X X X X X X b11 A11 A11 X X X X b10 A10 A10 X 0 1 0 b9 A9 A9 X X X X b8 A8 A8 X X X X b7 A7 A7 X X X X b6 A6 A6 X X X X b5 A5 A5 X X X X b4 A4 A4 A4 A4 X X b3 A3 A3 A3 A3 X X b2 A2 A2 A2 A2 X X b1 A1 A1 A1 A1 X X b0 A0 A0 A0 A0 X X A: significant address bit. X: bit is don’t Care. page 8/39 M24C32-A125 Identification page 3.6 Identification page The M24C32-A125 offers an identification page (32 byte) in addition to the 32 Kbit memory. The identification page contains two fields: • Device identification code: the first three bytes are programmed by STMicroelectronics with the device identification code, as shown in Table 4. • Application parameters: the bytes after the device identification code are available for application specific data. Note: If the end application does not need to read the device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the identification page, the whole identification page should be permanently locked in read-only mode. The instructions read, write and lock identification page are detailed in Section 4 Instructions. Table 4. Device identification code Address in Content identification page DS9133 - Rev 8 Value 00h ST manufacturer code 20h 01h I2C family code E0h 02h Memory density code 0Ch (32 Kbit) page 9/39 M24C32-A125 Instructions 4 Instructions 4.1 Write operations For a write operation, the bus master sends a start condition followed by a device select code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The device responds to each address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a stop condition immediately after a data byte ACK bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is then triggered. A stop condition at any other time slot does not trigger the internal write cycle. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. After the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. If the Write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 6. DS9133 - Rev 8 page 10/39 M24C32-A125 Write operations 4.1.1 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected, by write control (WC) being driven high, the device replies with NoACK, and the location is not modified (see Figure 6). If, instead, the addressed location is not write-protected, the device replies with ACK. The bus master terminates the transfer by generating a stop condition, as shown in Figure 5. Figure 5. Write mode sequences with WC = 0 (data write enabled) WC ACK Byte addr ACK ACK Data in Byte addr Stop Dev sel Start Byte Write ACK RW WC ACK Dev sel Start Page Write ACK Byte addr ACK Byte addr ACK Data in 1 Data in 2 RW WC (cont’d) ACK Data in N Stop Page Write (cont’d) ACK DS9133 - Rev 8 page 11/39 M24C32-A125 Write operations 4.1.2 Page Write The page write mode allows up to N (N is the number of bytes in a page) bytes to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the page are overwritten. The bus master sends from 1 to N bytes of data, each of which is acknowledged by the device if write control (WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 6. Write mode sequences with WC = 1 (data write inhibited) WC Byte write WC Page write WC (cont’d) Page write (cont’d) 4.1.3 Write identification page The identification page (32 byte) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences: • Device type identifier = 1011b • Most significant address bits A15/A5 are don't care, except for address bit A10 which must be “0”. Least significant address bits A4/A0 define the byte location inside the identification page. DS9133 - Rev 8 page 12/39 M24C32-A125 Write operations If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoACK). 4.1.4 Lock identification page The lock identification page instruction (lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions: • Device type identifier = 1011b • Address bit A10 must be ‘1’; all other address bits are don't care • The data byte must be equal to the binary value xxxx xx1x, where x is don't care 4.1.5 Minimizing write delays by polling on ACK The maximum write time (tw) is shown in AC characteristics of Table 11 and Table 12 in Section 8 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: • Initial condition: a write cycle is in progress. • Step 1: the bus master issues a start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal write cycle, noACK is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an ACK, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during step 1). DS9133 - Rev 8 page 13/39 M24C32-A125 Write operations Figure 7. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop 1. DS9133 - Rev 8 NO StartCondition YES Data for the write operation Device select with RW = 1 Continue the write operation Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the Figure 7) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the Figure 7). page 14/39 M24C32-A125 Read operations 4.2 Read operations Read operations are performed independently of the state of the write control (WC) signal. After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. Figure 8. Read mode sequences ACK NO ACK Current address read Data out Stop Start Dev sel R/W ACK ACK ACK ACK NO ACK Random address read Byte addr Dev sel * R/W ACK ACK ACK Data out Stop Byte addr Start Start Dev sel * R/W NO ACK Sequential current read Data out 1 Data out N Stop Start Dev sel R/W ACK ACK ACK ACK ACK Sequential random read Byte addr R/W ACK Byte addr Dev sel * Start Start Dev sel * Data out1 R/W NO ACK Stop Data out N Note: The seven most significant bits of the first device select code of a random read must be identical to the seven most significant bits of the device select code of the write. 4.2.1 Random address read The random address read is a sequence composed of a truncated write sequence (to define a new address pointer value, see Table 3) followed by a current read. The random address read sequence is therefore the sum of [start + device select code with RW=0 + two address bytes] (without stop condition, as shown in Figure 8)] and [start condition + device select code with RW=1]. The memory device acknowledges the sequence and then outputs the contents of the addressed byte. To terminate the data transfer, the bus master does not acknowledge the last data byte and then issues a stop condition. DS9133 - Rev 8 page 15/39 M24C32-A125 Read operations 4.2.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte pointed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 8, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the identification page. When accessing the identification page, the address counter value is loaded with the identification page byte location, when accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory) instead of the current address read instruction. 4.2.3 Sequential read A sequential read can be used after a current address read or a random address read. After a read instruction, the device can continue to output the next byte(s) in sequence if the bus master sends additional clock pulses and if the bus master does acknowledge each transmitted data byte. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a stop condition, as shown in Figure 8. The sequential read is controlled with the device internal address counter which is automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. 4.2.4 Read identification page The identification page can be read by issuing a read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. The most significant address bits A15/A5 are don't care and the least significant address bits A4/A0 define the byte location inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary. 4.2.5 Read the lock status The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit after the data byte if the identification page is unlocked, otherwise a NoACK bit if the identification page is locked. Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: • Start: the truncated command is not executed because the start condition resets the device internal logic, • Stop: the device is then set back into standby mode by the stop condition. 4.2.6 Acknowledge in read mode For all read instructions, the device waits, after each byte sent out, for an acknowledgement during the 9th bit time. If the bus master does not send the ACK (the master drives SDA high during the 9th bit time), the device terminates the data transfer and enters its standby mode. DS9133 - Rev 8 page 16/39 M24C32-A125 Application design recommendations 5 Application design recommendations 5.1 Supply voltage 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. 5.1.2 Power-up conditions When the power supply is turned on, the VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage. In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the internal threshold voltage. When VCC passes over the POR threshold, the device is reset and in the following state: • • in the standby power mode deselected As soon as the VCC voltage has reached a stable value within the [VCC(min), VCC(max)] range, the device is ready for operation. 5.1.3 Power-down During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage, the device must be in standby power mode (that is after a stop condition or after the completion of the write cycle tW if an internal write cycle is in progress). 5.2 Cycling with error correction code (ECC) The error correction code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (a group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (a group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four byte of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Table 6. Example 1: maximum cycling limit reached with 1 million cycles per byte Each byte of a group can be equally cycled 1 million times (at 25 °C) so that the group cycling budget is 4 million cycles. Example 2: maximum cycling limit reached with unequal byte cycling Inside a group, byte0 can be cycled 2 million times, byte1 can be cycled 1 million times, byte2 and byte3 can be cycled 500,000 times, so that the group cycling budget is 4 million cycles. DS9133 - Rev 8 page 17/39 M24C32-A125 Delivery state 6 Delivery state The device is delivered as follows: • The memory array is set to all 1s (each byte = FFh). • Identification page: the first three bytes define the device identification code (value defined in Table 4). The content of the following bytes is "Don’t Care". DS9133 - Rev 8 page 18/39 M24C32-A125 Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 5 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol Parameter Min. Max. Unit - Ambient operating temperature –40 130 °C TSTG Storage temperature –65 150 °C TLEAD Lead temperature during soldering VIO Input or output range IOL DC output current (SDA = 0) VCC Supply voltage VESD Electrostatic pulse (Human Body model) (2) see note (1) °C –0.50 6.5 V - 5 mA –0.50 6.5 V - 4000 V 1. Compliant with JEDEC Standard J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on pin pairs, according to AEC-Q100-002 (compliant with ANSI/ESDA/JEDEC JS-001, C1=100 pF, R1=1500 Ω, R2=500 Ω). DS9133 - Rev 8 page 19/39 M24C32-A125 DC and AC parameters 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 6. Cycling performance by groups of four bytes Symbol Ncycle Parameter Write cycle endurance (1) Test condition Min. Max. Unit TA ≤ 25 °C, 1.7 V < VCC < 5.5 V - 4,000,000 TA = 85 °C, 1.7 V < VCC < 5.5 V - 1,200,000 TA = 125 °C, 1.7 V < VCC < 5.5 V - 600,000 Write cycle (2) 1. The write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer, or for the status register byte (refer also to Section 5.2 Cycling with error correction code (ECC)). The write cycle endurance is defined by characterization and qualification. 2. A write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. When using those write instructions, refer also to Section 5.2 Cycling with error correction code (ECC). Table 7. Operating conditions (voltage range R, device grade 3) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature –40 125 °C Table 8. AC measurement conditions Symbol Min. Max. Unit Load capacitance - 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V Cbus Parameter Figure 9. AC measurement I/O waveform Input voltage levels 0.8VCC 0.2VCC DS9133 - Rev 8 Input and output Timing reference levels 0.7VCC 0.3V CC page 20/39 M24C32-A125 DC and AC parameters Table 9. Input parameters Symbol Parameter (1) Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - kΩ VIN > 0.7 VCC 500 - kΩ ZL ZH Input impedance (E2, E1, E0, WC) (2) 1. Evaluated by characterization - not tested in production. 2. E2, E1, E0 input impedance when the memory is selected (after a Start condition). DS9133 - Rev 8 page 21/39 M24C32-A125 Table 10. DC characteristics Symbol ILI ILO ICC ICC0 Parameter Test conditions (in addition to those in Table 7 and Table 8) ±2 µA µA device in Standby mode Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 fC = 400 kHz, VCC = 5.5 V - 2 fC = 400 kHz, VCC = 2.5 V - 2 fC = 400 kHz, VCC = 1.7 V - 1 fC = 1 MHz, VCC = 5.5 V - 2 fC = 1 MHz, VCC = 2.5 V - 2 fC = 1 MHz, VCC = 1.7 V - 2 During tW - 2 - 1 - 2 - 3 - 15 - 15 - 20 Supply current (Read) Supply current (Write) VIN = VSS or VCC, VCC = 2.5 V Device not selected(1), t° = 85 °C, Standby supply current VIN = VSS or VCC, VCC = 5.5 V Device not selected(1), t° = 125 °C, VIN = VSS or VCC, VCC = 1.7 V Device not selected(1), t° = 125 °C, VIN = VSS or VCC, VCC = 2.5 V Device not selected(1), t° = 125 °C, VIN = VSS or VCC, VCC = 5.5 V VOL - (SCL, SDA, E2, E1, E0) Device not selected(1), t° = 85 °C, VIH Unit VIN = VSS or VCC, VIN = VSS or VCC, VCC = 1.7 V VIL Max. Input leakage current Device not selected(1), t° = 85 °C, ICC1 Min. mA mA μA μA Input low voltage (SCL, SDA, WC ) - –0.45 0.3 VCC V Input high voltage (SCL, SDA) - 0.7 VCC 6.5 V Input high voltage (WC , E2, E1, E0) - 0.7 VCC VCC +0.6 Output low voltage VRES (2) Internal reset threshold voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V - 0.4 IOL = 1 mA, VCC = 1.7 V - 0.3 0.5 1.5 - V V V 1. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 2. Evaluated by characterization - not tested in production. DS9133 - Rev 8 page 22/39 M24C32-A125 Table 11. 400 kHz AC characteristics Parameter (1) Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tQL1QL2 (2) tF SDA (out) fall time (3) 20 120 ns tXH1XH2 tR Input signal rise time (4) (4) ns tXL1XL2 tF Input signal fall time (4) (4) ns tDXCX tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX (5) tDH Data out hold time 100 - ns tCLQV (6) tAA Clock low to next data valid (access time) - 900 ns tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tWLDL (2)(7) tSU:WC WC set up time (before the Start condition) 0 - µs tW(2) (8) tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Write time - 4 ms tNS (2) - Pulse width ignored (input filter on SCL and SDA) - single glitch - 80 ns 1. Test conditions (in addition to those in Table 7 and Table 8). 2. Evaluated by characterization - not tested in production. 3. With CL = 10 pF. 4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 10. 7. WC =0 set up time condition to enable the execution of a WRITE command. 8. WC=0 hold time condition to enable the execution of a WRITE command. DS9133 - Rev 8 page 23/39 M24C32-A125 Table 12. 1 MHz AC characteristics Parameter (1) Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 400 - ns tXH1XH2 tR Input signal rise time (2) (2) ns tXL1XL2 tF Input signal fall time (2) (2) ns tQL1QL2 (3) tF SDA (out) fall time - 120 ns tDXCX tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX (4) tDH Data out hold time 100 - ns tCLQV (5) tAA Clock low to next data valid (access time) - 450 ns tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tWLDL (6) (3) tSU:WC WC set up time (before the Start condition) 0 - µs tDHWH (7) (3) tHD:WC WC hold time (after the Stop condition) 1 - µs tW tWR Write time - 4 ms tNS (3) - Pulse width ignored (input filter on SCL and SDA) - 80 ns 1. Test conditions (in addition to those in Table 7 and Table 8). 2. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 120 ns when fC < 1 MHz. 3. Evaluated by characterization - not tested in production. 4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 11. 6. WC =0 set up time condition to enable the execution of a WRITE command. 7. WC =0 hold time condition to enable the execution of a WRITE command. DS9133 - Rev 8 page 24/39 M24C32-A125 Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line Pull up resistor (kΩ) 100 VCC The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left Rb us 10 xC bu s 00 Here Rbus x Cbus= 120 ns 4 =4 Rbus I²C bus master SCL M24xxx SDA ns Cbus 1 10 30 100 1000 Bus line capacitor (pF) Figure 11. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz Bus line pull-up resistor (kΩ ) 100 10 Rbu s xC bus The Rbus x Cbus time constant must be below the 150 ns time constant line represented on the left = 15 0 ns 4 VCC Rbus I²C bus master SCL M24xxx SDA Here Rbus x Cbus = 120 ns Cbus 1 10 30 100 Bus line capacitor (pF) DS9133 - Rev 8 page 25/39 M24C32-A125 Figure 12. AC waveforms Start condition Start Stop condition condition tXL1XL2 tXH1XH2 tCHCL tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX SDA tDXCH Change tCHDH tDHDL WC tDHWH tWLDL Stop condition Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS9133 - Rev 8 tCLQX Data valid tQL1QL2 Data valid page 26/39 M24C32-A125 Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 13. TSSOP8 – Outline D 8 Package TSSOP8 (package code 6P) 5 k E1 E A1 1 L L1 4 A2 A c b 1. DS9133 - Rev 8 e 6P_TSSOP8_ME_V3 Drawing is not to scale. page 27/39 M24C32-A125 TSSOP8 package information Table 13. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 0.0177 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. Figure 14. TSSOP8 – Recommended footprint 1.55 0.65 0.40 2.35 5.80 7.35 1. DS9133 - Rev 8 6P_TSSOP8_FP_V2 Dimensions are expressed in millimeters. page 28/39 M24C32-A125 SO8N package information 9.2 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 15. SO8N – Outline Package SO8N (package code O7) A2 h x 45˚ A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 E 1 L A1 L1 1. Drawing is not to scale. Table 14. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0030 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS9133 - Rev 8 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 29/39 M24C32-A125 SO8N package information Figure 16. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS9133 - Rev 8 Dimensions are expressed in millimeters. page 30/39 M24C32-A125 WFDFPN8 (DFN8) package information 9.3 WFDFPN8 (DFN8) package information This WFDFPN is a 8 lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package. Figure 17. WFDFPN8 (DFN8) – Outline D2 Package WFDFPN8 (package code A0Y3) D2/2 Datum Y D Pin #1 ID marking e A B Pin #1 E2/2 E2 E See Z Detail 2x K aaa C 2x (ND-1) x e aaa C Top view // ccc C eee C A Seating plane L L3 e/2 Detail “Z” 1. 2. DS9133 - Rev 8 bbb M C A B ddd M C Bottom view Datum Y e NX b L1 C A1 Side view Terminal tip A0Y3_WFDFPN8_ME_V4 Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to Vss or left floating (not connected) in the end application. page 31/39 M24C32-A125 WFDFPN8 (DFN8) package information Table 15. WFDFPN8 (DFN8) – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A 0.700 0.750 0.800 0.0276 0.0295 0.0315 A1 0.025 0.045 0.065 0.0010 0.0018 0.0026 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.500 - - 0.0197 - L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - D2 1.400 - 1.600 0.0551 - 0.0630 E2 1.200 - 1.400 0.0472 - 0.0551 K 0.400 - - 0.0157 - - L 0.300 - 0.500 0.0118 - 0.0197 NX (2) 8 ND (3) 4 aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 - - 0.080 - - 0.0031 eee (4) 1. Values in inches are converted from mm and rounded to four decimal digits. 2. NX is the number of terminals. 3. ND is the number of terminals on “D” sides. 4. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. Figure 18. WFDFPN8 (DFN8) – Recommended footprint 1.200 0.300 0.500 1.400 1.300 DS9133 - Rev 8 0.600 page 32/39 M24C32-A125 Ordering information 10 Ordering information Table 16. Ordering information scheme Example: M24 C32-D R MN 3 T P /K Device type M24 = I2C serial access EEPROM Device function C32-D = 32 Kbit (4096 K x 8 bits) plus identification page Operating voltage R = VCC = 1.7 V to 5.5 V Package(1) MN = SO8N (150 mil width) DW = TSSOP8 (169 mil width) MF = WFDFPN8 (DFN8) (2 x3 mm) Device grade 3 = -40 to 125 °C. Automotive grade. Device tested with high reliability certified flow(2) Option T = Tape and reel packing blank = tube packing Planting technology P or G = ECOPACK2 Process /K = Manufacturing technology code 1. All packages are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimonyoxide flame retardants). 2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest ST sales office for a copy. Note: For a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS9133 - Rev 8 page 33/39 M24C32-A125 Revision history Table 17. Document revision history Date Revision 03-Aug-2012 1 Changes Initial release. Document reformatted. Document status changed from “Preliminary data” to “Production data”. 05-Mar-2013 25-Mar-2013 2 3 Updated: • Section 3.6: Identification page • Section 6: Delivery state • ICC, VIL and VRES values in Table 10: DC characteristics Updated ICC1 and VIL rows in Table 10: DC characteristics. Added WFDFPN8 (MF) package. Removed UFDFPN8 (MLP8) package. 05-Sep-2013 4 Updated: • Note (1) under Table 5: Absolute maximum ratings. • Third waveform in Figure 12: AC waveforms. Changed Data retention from “40 years at 55 °C” to “50 years at 10-Feb-2014 5 125 °C” in Features. Updated Figure 15: WFDFPN8 (MLP8) – 8-lead, 2 x 3 mm, 0.5 mm pitch very very thin fine pitch dual flat package outline. Updated: 08-Jan-2015 6 • note 2 on Table 5. • Figure 5 • Table 20 and Table 16 Added sentence related Engineering Sample on Section 10 and note 2 on Figure 5 Updated: 23-Feb-2016 7 • Features • Table 6, Table 10, Figure 15, Table 16 Updated: 06-Jun-2022 8 • Section Features, Section 2.2 Serial data (SDA), Section 9.1 TSSOP8 package information, Section 9.2 SO8N package information • Figure 1. Logic diagram • Table 5. Absolute maximum ratings, Table 3. Significant bits within the two address bytes, Table 6. Cycling performance by groups of four bytes, Section 9.3 WFDFPN8 (DFN8) package information, Table 16. Ordering information scheme Added note in Figure 7 and in Figure 8 DS9133 - Rev 8 page 34/39 M24C32-A125 Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3 4 2.1 Serial Clock (SCL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Write Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.6 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.1 4.2 5 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.3 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.1.4 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.5 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.1 Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.4 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2.6 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 DS9133 - Rev 8 page 35/39 M24C32-A125 Contents 5.1 5.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 10 9.1 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.3 WFDFPN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DS9133 - Rev 8 page 36/39 M24C32-A125 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . Significant bits within the two address bytes . . . . . . . . Device identification code . . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . Cycling performance by groups of four bytes . . . . . . . . Operating conditions (voltage range R, device grade 3) AC measurement conditions . . . . . . . . . . . . . . . . . . . Input parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 400 kHz AC characteristics . . . . . . . . . . . . . . . . . . . . 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . . . . . . . . WFDFPN8 (DFN8) – Mechanical data . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . DS9133 - Rev 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 7 . 8 . 9 19 20 20 20 21 22 23 24 28 29 32 33 34 page 37/39 M24C32-A125 List of figures List of figures Figure 1. Figure 2. Figure 3. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8-pin package connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequences with WC = 0 (data write enabled) . Write mode sequences with WC = 1 (data write inhibited). Write cycle polling flowchart using ACK . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . Figure 10. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WFDFPN8 (DFN8) – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WFDFPN8 (DFN8) – Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS9133 - Rev 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 11 12 14 15 20 25 26 27 28 29 30 31 32 page 38/39 M24C32-A125 IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS9133 - Rev 8 page 39/39