M24C32-DF
M24C32-W M24C32-R M24C32-F
32 Kbit serial I²C bus EEPROM
Features
■
Compatible with all I2C bus modes:
– 1 MHz Fast-mode Plus
– 400 kHz Fast mode
– 100 kHz Standard mode
■
Memory array:
– 32 Kb (4 Kbytes) of EEPROM
– Page size: 32 bytes
PDIP8 (BN)
■
M24C32-DF: additional Write lockable Page
(Identification page)
■
Write
– Byte Write within 5 ms
– Page Write within 5 ms
■
Random and Sequential Read modes
■
Write protect of the whole memory array
■
Single supply voltage:
– M24C32-W: 2.5 V to 5.5 V
– M24C32-R: 1.8 V to 5.5 V
– M24C32-xF: 1.7 V to 5.5 V
■
Enhanced ESD/Latch-Up protection
■
More than 1 million Write cycles
■
More than 40-year data retention
■
Packages
– ECOPACK2® (RoHS-compliant and
halogen-free)
– PDIP8 package: ECOPACK1® (RoHScompliant)
September 2011
SO8 (MN)
150 mil width
TSSOP8 (DW)
169 mil width
Doc ID 4578 Rev 19
UFDFPN8
(MB, MC)
1/42
www.st.com
1
Contents
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3
Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6
Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1
2.6.2
Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3
Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4
Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4
Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/42
4.1
Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2
Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3
Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.5
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7
Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.9
Write Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . . 17
4.10
Lock Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11
ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . . . 18
4.12
Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19
4.13
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.15
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Contents
4.16
Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.17
Read Identification Page (M24C32-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.18
Read the lock status (M24C32-D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.19
Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3/42
List of tables
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
4/42
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions (M24xxx-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (M24xxx-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Operating conditions (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC characteristics (M24xxx-W, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC characteristics (M24xxx-W - device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC characteristics (M24xxx-R - device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DC characteristics (M24xxx-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 33
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TSSOP8 – 8 lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 35
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus
parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 15
Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 33
SO8 narrow – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . 34
TSSOP8 – 8 lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 35
UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 4578 Rev 19
5/42
Description
1
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Description
M24C32-x devices are I2C-compatible EEPROM (electrically erasable programmable
memories) organized as 4096 × 8 bits.
The M24C32-W operates with a supply voltage range of 2.5 V/5.5 V, the M24C32-R with a
supply voltage range of 1.8 V/5.5 V and the M24C32-F and M24C32-DF with a supply
voltage range of 1.7 V/5.5 V.
The M24C32-DF offers an additional page, named the Identification Page (32 bytes) which
can be written and (later) permanently locked in Read-only mode. This Identification Page
offers flexibility in the application board production line, as it can be used to store unique
identification parameters and/or parameters specific to the production line.
Figure 1.
Logic diagram
6##
%
%
3$!
-XXX
3#,
7#
633
6/42
Doc ID 4578 Rev 19
!)F
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 1.
Description
Signal names
Signal name
Function
Direction
E2, E1, E0
Chip Enable
Input
SDA
Serial Data
I/O
SCL
Serial Clock
Input
WC
Write Control
Input
VCC
Supply voltage
VSS
Ground
Figure 2.
8-pin package connections
%
%
%
633
6##
7#
3#,
3$!
!)F
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Doc ID 4578 Rev 19
7/42
Signal description
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
2
Signal description
2.1
Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 4 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2
Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 4 indicates how
the value of the pull-up resistor can be calculated).
2.3
Chip Enable (E2, E1, E0)
(E2,E1,E0) input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code as shown in Figure 3. When not connected (left
floating), these inputs are read as low (0).
Figure 3.
Device select code
VCC
VCC
M24xxx
M24xxx
Ei
Ei
VSS
VSS
Ai12806
2.4
Write Control (WC)
This input signal is useful for protecting the entire contents of the memory from inadvertent
write operations. Write operations are disabled to the entire memory array when Write
Control (WC) is driven high. When unconnected, the signal is internally read as VIL, and
Write operations are allowed.
When Write Control (WC) is driven high, device select and Address bytes are
acknowledged, Data bytes are not acknowledged.
8/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
2.5
Signal description
VSS ground
VSS is the reference for the VCC supply voltage.
2.6
Supply voltage (VCC)
2.6.1
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Table 7, Table 8 and
Table 9). In order to secure a stable DC supply voltage, it is recommended to decouple the
VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the
VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2
Power-up conditions
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined in Table 7, Table 8 and Table 9. The rise time must not vary faster than 1 V/µs.
2.6.3
Device reset
In order to prevent inadvertent Write operations during power-up, a power on reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power on reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Table 8 and Table 9). Until VCC
passes over the POR threshold, the device is reset and in Standby Power mode.
In a similar way, during power-down (continuous decay of VCC), as soon as VCC drops below
the POR threshold voltage, the device is reset and stops responding to any instruction sent
to it.
2.6.4
Power-down conditions
During power-down (continuous decay of VCC), the device must be in Standby Power mode
(mode reached after decoding a Stop condition, assuming that there is no internal Write
cycle in progress).
Doc ID 4578 Rev 19
9/42
Signal description
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic
capacitance (Cbus)
"USLINEPULL
UPRESISTOR
K
Figure 4.
2
BU
S §
(ERE2BUS §#BUS NS
4HE2X#TIMECONSTANT
BUS
BUS
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
6##
#
BU
S
2BUS
N
K½
S
)£#BUS
MASTER
3#,
-XXX
3$!
P&
"USLINECAPACITORP&
#BUS
AIB
I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus
parasitic capacitance (Cbus)
Figure 5.
"USLINEPULL
UPRESISTORK
6##
4HE2BUS§#BUSTIMECONSTANT
MUSTBEBELOWTHENS
TIMECONSTANTLINEREPRESENTED
ONTHELEFT
2
BUS §
#
BUS
NS
2BUS
)£#BUS
MASTER
3#,
-XXX
3$!
(ERE
2 BUS § #BUS NS
#BUS
"USLINECAPACITORP&
-36
10/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 6.
Signal description
I2C bus protocol
SCL
SDA
SDA
Input
Start
Condition
SCL
1
SDA
MSB
2
SDA
Change
Stop
Condition
3
7
8
9
ACK
Start
Condition
SCL
1
SDA
MSB
2
3
7
8
9
ACK
Stop
Condition
AI00792B
Table 2.
b15
Table 3.
b7
Address most significant byte
b14
b13
b12
b11
b10
b9
b8
b3
b2
b1
b0
Address least significant byte
b6
b5
b4
Doc ID 4578 Rev 19
11/42
Memory organization
3
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Memory organization
The memory is organized as shown in Figure 7.
Figure 7.
Block diagram
WC
E0
E1
High Voltage
Generator
Control Logic
E2
SCL
SDA
I/O Shift Register
Data
Register
Y Decoder
Address Register
and Counter
1 Page
X Decoder
AI06899
12/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
4
Device operation
Device operation
The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends
data on to the bus is defined to be a transmitter, and any device that reads the data to be a
receiver. The device that controls the data transfer is known as the bus master, and the
other as the slave device. A data transfer can only be initiated by the bus master, which will
also provide the serial clock for synchronization. The device is always a slave in all
communications.
4.1
Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition.
4.2
Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal Write cycle.
4.3
Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
4.4
Data Input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
Doc ID 4578 Rev 19
13/42
Device operation
4.5
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 2 (on Serial Data (SDA), most significant bit first).
Table 4.
Device select code
Device type identifier(1)
Chip Enable address(2)
RW
b7
b6
b5
b4
b3
b2
b1
b0
Device select code
when addressing the
memory array
1
0
1
0
E2
E1
E0
RW
Device select code
when accessing the
Identification page
1
0
1
1
E2
E1
E0
RW
1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
The device select code consists of a 4-bit device type identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). The 4-bit device type identifier 1010b addresses the memory array
(M24C32 and M24C32-D), and the 4-bit device type identifier 1011b addresses the
Identification page (M24C32-D only). A device select code handling a value other than
1010b or 1011b is not acknowledged by the device.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E2, E1, E0) inputs. When the device select code is
received, the device only responds if the Chip Enable Address is the same as the value on
the Chip Enable (E2, E1, E0) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into Standby mode.
Table 5.
Operating modes
Mode
Current Address
Read
RW bit WC(1)
1
X
0
X
Bytes
1
Start, device select, RW = 1
Start, device select, RW = 0, Address
Random Address
Read
1
X
Sequential Read
1
X
≥1
Byte Write
0
VIL
1
Start, device select, RW = 0
Page Write
0
VIL
≤ 32
Start, device select, RW = 0
1
reStart, device select, RW = 1
1. X = VIH or VIL.
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Initial sequence
Doc ID 4578 Rev 19
Similar to Current or Random Address
Read
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 8.
Device operation
Write mode sequences with WC = 1 (data write inhibited)
WC
ACK
Byte address
ACK
Byte address
NO ACK
Data in
Stop
Dev select
Start
Byte Write
ACK
R/W
WC
ACK
Dev select
Start
Page Write
ACK
Byte address
ACK
Byte address
NO ACK
Data in 1
Data in 2
R/W
WC (cont'd)
NO ACK
Data in N
Stop
Page Write
(cont'd)
NO ACK
AI01120d
Doc ID 4578 Rev 19
15/42
Device operation
4.6
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 9, and waits for two
address bytes. The device responds to each address byte with an acknowledge bit, and
then waits for the data Byte.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Table 2) is sent first, followed by the Least Significant Byte (Table 3). Bits b15 to b0
form the address of the byte in memory.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
After the Stop condition, the delay tW, and the successful completion of a Write operation,
the device’s internal address counter is incremented automatically, to point to the next byte
address after the last one that was modified.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
If the Write Control input (WC) is driven High, the Write instruction is not executed and the
accompanying data bytes are not acknowledged, as shown in Figure 8.
4.7
Byte Write
After the device select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected, by Write Control (WC) being driven high, the
device replies with NoAck, and the location is not modified. If, instead, the addressed
location is not Write-protected, the device replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown in Figure 9.
4.8
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same ‘row’ in the memory: that is, the most significant
memory address bits (b11-b5) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck.
After each byte is transferred, the internal byte address counter (inside the page) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
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Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 9.
Device operation
Write mode sequences with WC = 0 (data write enabled)
WC
ACK
Byte address
ACK
Byte address
ACK
Data in
Stop
Dev Select
Start
Byte Write
ACK
R/W
WC
ACK
Dev Select
Start
Page Write
ACK
Byte address
ACK
Byte address
ACK
Data in 1
Data in 2
R/W
WC (cont'd)
ACK
Data in N
Stop
Page Write
(cont'd)
ACK
4.9
AI01106d
Write Identification Page (M24C32-D only)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode. The Identification Page is written by issuing an
Write Identification Page instruction. This instruction uses the same protocol and format as
Page Write (into memory array), except for the following differences:
●
Device type identifier = 1011b
●
MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’.
LSB address bits A4/A0 define the byte address inside the Identification Page.
If the Identification Page is locked, the data bytes transferred during the Write Identification
Page instruction are not acknowledged (NoAck).
Doc ID 4578 Rev 19
17/42
Device operation
4.10
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Lock Identification Page (M24C32-D only)
The Lock Identification Page instruction (Lock ID) permanently locks the Identification Page
in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with
the following specific conditions:
●
Device type identifier = 1011b
●
Address bit A10 must be ‘1’; all other address bits are don't care
●
The data byte must be equal to the binary value xxxx xx1x, where x is don't care
If the Identification Page is locked, the data bytes transferred during the Lock Identification
Page instruction are not acknowledged (NoAck).
4.11
ECC (Error Correction Code) and Write cycling
The M24C32 devices identified with the process letter K offer an ECC (Error Correction
Code) logic which compares each 4-byte word with its associated 6 EEPROM bits of ECC.
As a result, if a single bit out of 4 bytes of data happens to be erroneous during a Read
operation, the ECC detects it and replaces it by the correct value. The read reliability is
therefore much improved by the use of this feature.
Note however that even if a single byte has to be written, 4 bytes are internally modified
(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes
making up the word. It is therefore recommended to write by word (4 bytes) at address 4*N
(where N is an integer) in order to benefit from the larger amount of Write cycles.
The M24C32 devices are qualified as 1 million (1,000,000) Write cycles, using a cycling
routine that writes to the device by multiples of 4-byte words.
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M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Device operation
Figure 10. Write cycle polling flowchart using ACK
Write cycle
in progress
Start condition
Device select
with RW = 0
NO
First byte of instruction
with RW = 0 already
decoded by the device
ACK
Returned
YES
NO
Next
operation is
addressing the
memory
YES
Send address
and receive ACK
ReStart
NO
Stop
Start
condition
YES
Data for the
Write operation
Device select
with RW = 1
Continue the
Write operation
Continue the
Random Read operation
AI01847d
4.12
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 17, but the typical time is shorter. To make use of this, a polling sequence can
be used by the bus master.
The sequence, as shown in Figure 10, is:
1.
Initial condition: a Write cycle is in progress.
2.
Step 1: the bus master issues a Start condition followed by a device select code (the
first byte of the new instruction).
3.
Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Doc ID 4578 Rev 19
19/42
Device operation
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 11. Read mode sequences
ACK
Data out
Stop
Start
Dev select
NO ACK
R/W
ACK
Start
Dev select *
Byte address
Dev select *
ACK
ACK
Data out 1
ACK
NO ACK
Data out N
Byte address
ACK
Byte address
ACK
Dev select *
Start
Start
ACK
R/W
ACK
Data out
R/W
R/W
Dev select *
NO ACK
Stop
Start
Dev select
Sequential
Random
Read
ACK
Byte address
R/W
ACK
Sequential
Current
Read
ACK
Start
Random
Address
Read
ACK
Stop
Current
Address
Read
ACK
Data out 1
R/W
NO ACK
Stop
Data out N
AI01105d
1. The seven most significant bits of the device select code of a Random Read (in the 1st and 4th bytes) must
be identical.
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M24C32-DF, M24C32-W, M24C32-R, M24C32-F
4.13
Device operation
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device’s internal address counter is
incremented by one, to point to the next byte address.
4.14
Random Address Read
A dummy Write is first performed to load the address into this address counter (as shown in
Figure 11) but without sending a Stop condition. Then, the bus master sends another Start
condition, and repeats the device select code, with the Read/Write bit (RW) set to 1. The
device acknowledges this, and outputs the contents of the addressed byte. The bus master
must not acknowledge the byte, and terminates the transfer with a Stop condition.
4.15
Current Address Read
For the Current Address Read operation, following a Start condition, the bus master only
sends a device select code with the Read/Write bit (RW) set to 1. The device acknowledges
this, and outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a Stop condition, as shown in
Figure 11, without acknowledging the Byte.
4.16
Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 11.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory
address 00h.
4.17
Read Identification Page (M24C32-D)
The Identification Page (32 bytes) is an additional page which can be written and (later)
permanently locked in Read-only mode.
The Identification Page can be read by issuing an Read Identification Page instruction. This
instruction uses the same protocol and format as the Random Address Read (from memory
array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't
care, the LSB address bits A4/A0 define the byte address inside the Identification Page. The
number of bytes to read in the ID page must not exceed the page boundary, otherwise
unexpected data is read (e.g.: when reading the Identification Page from location 10d, the
number of bytes should be less than or equal to 22, as the ID page boundary is 32 bytes).
Doc ID 4578 Rev 19
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Device operation
4.18
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Read the lock status (M24C32-D)
The locked/unlocked status of the Identification page can be checked by issuing a specific
truncated command [Identification Page Write instruction + one data byte]: this data byte will
be acknowledged if the Identification page is unlocked, while it will not be acknowledged if
the Identification page is locked.
Once the acknowledge bit of this data byte is read, it is recommended to generate a Start
condition followed by a Stop condition, so that:
4.19
●
Start: the truncated command is not executed because the Start condition resets the
device internal logic,
●
Stop: the device is then set back into Standby mode by the Stop condition.
Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
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Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
5
Initial delivery state
Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
6
Maximum rating
Stressing the device outside the ratings listed in Table 6 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the Operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Refer also to the STMicroelectronics SURE Program and other relevant
quality documents.
Table 6.
Absolute maximum ratings
Symbol
TSTG
Parameter
Min.
Max.
Unit
Ambient operating temperature
–40
130
°C
Storage temperature
–65
150
°C
(1)
°C
Lead temperature during soldering
TLEAD
(2)
PDIP-specific lead temperature during soldering
VIO
Input or output range
IOL
DC output current (SDA = 0)
VCC
Supply voltage
VESD
see note
Electrostatic pulse (human body
model)(3)
260
°C
–0.50
6.5
V
-
5
mA
–0.50
6.5
V
4000
V
1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. TLEAD max must not be applied for more than 10 s.
3.
Positive and negative pulses applied on pin pairs, according to the AEC-Q100-002 (compliant with JEDEC
Std JESD22-A114, C1=100pF, R1=1500Ω, R2=500Ω)
Doc ID 4578 Rev 19
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DC and AC parameters
7
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
DC and AC parameters
Table 7.
Operating conditions (M24xxx-W)
Symbol
Min.
Max.
Unit
Supply voltage
2.5
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 3)
–40
125
°C
-
1
MHz
Min.
Max.
Unit
Supply voltage
1.8
5.5
V
TA
Ambient operating temperature
–40
85
°C
fC
Operating clock frequency
-
1
MHz
VCC
TA
fC
Table 8.
Parameter
Operating clock frequency
Operating conditions (M24xxx-R)
Symbol
VCC
Table 9.
Parameter
Operating conditions (M24xxx-F)
Symbol
VCC
TA
Table 10.
Parameter
Min.
Max.
Unit
Supply voltage
1.7
5.5
V
Ambient operating temperature (device grade 6)
–40
85
°C
Ambient operating temperature (device grade 5)
–20
85
°C
Max.
Unit
AC test measurement conditions
Symbol
Cbus
Parameter
Load capacitance
Min.
100
SCL input rise/fall time, SDA input fall time
pF
50
ns
Input voltage levels
0.2VCC to 0.8VCC
V
Input and output timing reference levels
0.3VCC to 0.7VCC
V
Figure 12. AC test measurement I/O waveform
Input voltage levels
Input and output
timing reference
levels
0.8VCC
0.7VCC
0.3VCC
0.2VCC
MS19844V1
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Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 11.
Symbol
DC and AC parameters
Input parameters
Parameter(1)
Test condition
Min.
Max.
Unit
CIN
Input capacitance (SDA)
8
pF
CIN
Input capacitance (other pins)
6
pF
ZL(2)
Input impedance
(E2, E1, E0, WC)
VIN < 0.3VCC
30
kΩ
ZH(2)
Input impedance
(E2, E1, E0, WC)
VIN > 0.7VCC
500
kΩ
1. Characterized value, not tested in production.
2. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).
Table 12.
Symbol
Ncycle
Note:
Memory cell characteristics
Parameter
Endurance
Test condition
Min.
TA = 25°C, 1.8 V < Vcc < 5.5 V 1,000,000
Max.
Unit
-
Write cycle
This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please refer to AN2014.
Doc ID 4578 Rev 19
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DC and AC parameters
Table 13.
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
DC characteristics (M24xxx-W, device grade 6)
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
ILO
Output leakage
current
ICC
ICC0
ICC1
VIL
VIH
VOL
Supply current (Read)
Test conditions (see Table 7 and
Table 10)
Min.
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
±2
µA
2.5 V < VCC < 5.5 V, fc = 400 kHz
(rise/fall time < 50 ns)
2
mA
2.5 V < VCC < 5.5 V, fc = 1 MHz(1)
(rise/fall time < 50 ns)
2.5
mA
5(2)
mA
Device not selected(3), VIN = VSS or
VCC, VCC = 2.5 V
2
µA
Device not selected(3), VIN = VSS or
VCC, VCC = 5.5 V
5(4)
µA
V
Supply current (Write) During tW, 2.5 V < VCC < 5.5 V
Standby supply
current
Input low voltage
(SCL, SDA, WC)
–0.45
0.3VCC
Input high voltage
(SCL, SDA)
0.7VCC
6.5
V
Input high voltage
(WC, E2, E1, E0)
Output low voltage
0.7VCC
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
VCC+0.6
0.4
1. Only for devices operating at fC max = 1 MHz (see Table 18)
2. Characterized value, not tested in production.
3. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
4. The new M24C32-W devices (identified by the process letter K) offer ICC1 = 3µA (max)
26/42
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V
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 14.
DC and AC parameters
DC characteristics (M24xxx-W - device grade 3)
Symbol
Parameter
ILI
Input leakage current
(SCL, SDA, E2, E1,
E0)
ILO
Test conditions (in addition to those
in Table 7 and Table 10)
Max.
Unit
VIN = VSS or VCC
device in Standby mode
±2
µA
Output leakage
current
SDA in Hi-Z, external voltage applied
on SDA: VSS or VCC
±2
µA
ICC
Supply current (Read)
fc = 400 kHz
2
mA
ICC0
Supply current (Write) During tW
5(1)
mA
10
µA
ICC1
Standby supply
current
VIL
Input low voltage
(SCL, SDA, WC)
–0.45
0.3VCC
V
Input high voltage
(SCL, SDA)
0.7VCC
6.5
V
Input high voltage
(WC, E2, E1, E0)
0.7VCC
VCC+0.6
VIH
VOL
Output low voltage
Device not
VCC
selected(2),
Min.
VIN = VSS or
IOL = 2.1 mA, VCC = 2.5 V or
IOL = 3 mA, VCC = 5.5 V
0.4
V
V
1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
Doc ID 4578 Rev 19
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DC and AC parameters
Table 15.
Symbol
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
DC characteristics (M24xxx-R - device grade 6)
Test conditions(1) (in addition
to those in Table 8 and
Table 10)
Parameter
Min.
Max.
Unit
ILI
Input leakage current
(E1, E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode
±2
µA
ILO
Output leakage current
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.8 V, fc= 400 kHz
0.8
mA
fc= 1 MHz(2)
2.5
mA
During tW, 1.8 V < VCC < 2.5 V
3(3)
mA
1
µA
ICC
ICC0
Supply current (Read)
Supply current (Write)
selected(4),
ICC1
Standby supply current
Device not
VIN = VSS or VCC, VCC = 1.8 V
VIL
Input low voltage
(SCL, SDA, WC)
1.8 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
V
Input high voltage
(SCL, SDA)
1.8 V ≤ VCC < 2.5 V
0.75VCC
6.5
V
Input high voltage
(WC, E2, E1, E0)
1.8 V ≤ VCC < 2.5 V
0.75VCC
VCC+0.6
V
Output low voltage
IOL = 1 mA, VCC = 1.8 V
0.2
V
VIH
VOL
1. If the application uses the voltage range R device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see Table 18).
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
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M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 16.
Symbol
DC and AC parameters
DC characteristics (M24xxx-F)
Test conditions(1) (in addition
to those in Table 9 and
Table 10)
Parameter
Min.
Max.
Unit
ILI
Input leakage current
(E1, E2, SCL, SDA)
VIN = VSS or VCC
device in Standby mode
±2
µA
ILO
Output leakage current
SDA in Hi-Z, external voltage
applied on SDA: VSS or VCC
±2
µA
VCC = 1.7 V, fc= 400 kHz
0.8
mA
fc= 1 MHz(2)
2.5
mA
During tW, 1.7 V < VCC < 2.5 V
3(3)
mA
1
µA
ICC
ICC0
Supply current (Read)
Supply current (Write)
selected(4),
ICC1
Standby supply current
Device not
VIN = VSS or VCC, VCC = 1.7 V
VIL
Input low voltage
(SCL, SDA, WC)
1.7 V ≤ VCC < 2.5 V
–0.45
0.25 VCC
V
Input high voltage
(SCL, SDA)
1.7 V ≤ VCC < 2.5 V
0.75VCC
6.5
V
Input high voltage
(WC, E2, E1, E0)
1.7 V ≤ VCC < 2.5 V
0.75VCC
VCC+0.6
V
Output low voltage
IOL = 1 mA, VCC = 1.7 V
0.2
V
VIH
VOL
1. If the application uses the voltage range F device with 2.5 V < Vcc < 5.5 V and -40 °C < TA < +85 °C,
please refer to Table 13 instead of this table.
2. Only for devices operating at fC max = 1 MHz (see Table 18).
3. Characterized value, not tested in production.
4. The device is not selected after power-up, after a Read instruction (after the Stop condition), or after the
completion of the internal write cycle tW (tW is triggered by the correct decoding of a Write instruction).
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DC and AC parameters
Table 17.
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
400 kHz AC characteristics
Parameter(1)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tLOW
tQL1QL2(2)
tF
tXH1XH2
tR
Min.
Max.
Unit
-
400
kHz
Clock pulse width high
600
-
ns
Clock pulse width low
1300
SDA (out) fall time
20(3)
120
ns
Input signal rise time
(4)
(4)
ns
(4)
ns
ns
tXL1XL2
tF
Input signal fall time
(4)
tDXCX
tSU:DAT
Data in set up time
100
-
ns
tCLDX
tHD:DAT
Data in hold time
0
-
ns
Data out hold time
100(5)
-
ns
Clock low to next data valid (access time)
100(5)
900
ns
tCLQX
tDH
tCLQV(6)(7)
tAA
tCHDL
tSU:STA
Start condition setup time
600
-
ns
tDLCL
tHD:STA
Start condition hold time
600
-
ns
tCHDH
tSU:STO
Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tWLDL(8)(2)
tSU:WC
WC set up time (before the Start condition)
0
-
µs
tDHWH(9)(2)
tHD:WC
WC hold time (after the Stop condition)
1
-
µs
tW
tWR
Write time
-
5
ms
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-
80(10)
ns
tNS(2)
1. Test conditions (in addition to those in Table 7, Table 8, Table 9 and Table 10).
2. Characterized value, not tested in production.
3. With CL = 10 pF.
4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz.
5. The new M24C32 device (identified by the process letter K) offers tCLQX = 100 ns (min) and tCLQV = 100 ns
(min), while the current device offers tCLQX = 200 ns (min) and tCLQV = 200 ns (min). Both series offer a
safe margin compared to the I2C specification which recommends tCLQV = 0 ns (min).
6. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
7. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 4.
8. WC=0 set up time condition to enable the execution of a WRITE command.
9. WC=0 hold time condition to enable the execution of a WRITE command.
10. The current M24C32 device offers tNS=100 ns (max), the new M24C32 device (identified by the process
letter K) offers tNS=80 ns (max). Both products offer a safe margin compared to the 50 ns minimum value
recommended by the I2C specification.
30/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 18.
1 MHz AC characteristics(1)
Parameter(2)
Symbol
Alt.
fC
fSCL
Clock frequency
tCHCL
tHIGH
tCLCH
tXH1XH2
tXL1XL2
tQL1QL2
(9)
DC and AC parameters
Min.
Max.
Unit
0
1
MHz
Clock pulse width high
260
-
ns
tLOW
Clock pulse width low
500
-
ns
tR
Input signal rise time
(3)
(3)
ns
Input signal fall time
(3)
(3)
ns
120
ns
tF
tF
SDA (out) fall time
20
(4)
tDXCX
tSU:DAT Data in setup time
50
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
100
-
ns
450
ns
tCLQX
tCLQV
(5)(6)
tDH
Data out hold time
tAA
Clock low to next data valid (access time)
tCHDL
tSU:STA Start condition setup time
250
-
ns
tDLCL
tHD:STA Start condition hold time
250
-
ns
tCHDH
tSU:STO Stop condition setup time
250
-
ns
500
-
ns
tSU:WC WC set up time (before the Start condition)
0
-
µs
tHD:WC WC hold time (after the Stop condition)
1
-
µs
Write time
-
5
ms
Pulse width ignored (input filter on SCL and
SDA)
-
80
ns
tDHDL
tWLDL(7)(9)
tDHWH
(8)(9)
tW
tBUF
tWR
tNS(9)
Time between Stop condition and next Start
condition
1. Only M24C32 and M24C64-D devices identified by the process letter K are qualified at 1 MHz.
2. Test conditions (in addition to those in Table 7, Table 8, Table 9 and Table 10).
3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the
I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when
fC < 400 kHz, or less than 120 ns when fC < 1 MHz.
4. With CL = 10 pF
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or
0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 5.
7. WC=0 set up time condition to enable the execution of a WRITE command.
8. WC=0 hold time condition to enable the execution of a WRITE command.
9. Characterized only, not tested in production.
Doc ID 4578 Rev 19
31/42
DC and AC parameters
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 13. AC waveforms
3TART
CONDITION
3TART
3TOP
CONDITION CONDITION
T8,8,
T8(8(
T#(#,
T#,#(
3#,
T$,#,
T8,8,
3$!)N
T#($,
T8(8(
3$!
)NPUT
T#,$8
3$! T$8#(
#HANGE
T#($(
T$($,
7#
T$(7(
T7,$,
3TOP
CONDITION
3TART
CONDITION
3#,
3$!)N
T7
T#($(
T#($,
7RITECYCLE
3#,
T#,16
3$!/UT
T#,18
$ATAVALID
T1,1,
$ATAVALID
!)G
32/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
8
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 14. PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package outline
E
b2
A2
A1
b
A
L
c
e
eA
eB
D
8
E1
1
PDIP-B
1. Drawing is not to scale.
Table 19.
PDIP8 – 8 pin plastic DIP, 0.25 mm lead frame, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
A
Max.
Typ.
Min.
5.33
A1
Max.
0.2098
0.38
0.0150
A2
3.30
2.92
4.95
0.1299
0.1150
0.1949
b
0.46
0.36
0.56
0.0181
0.0142
0.0220
b2
1.52
1.14
1.78
0.0598
0.0449
0.0701
c
0.25
0.20
0.36
0.0098
0.0079
0.0142
D
9.27
9.02
10.16
0.3650
0.3551
0.4000
E
7.87
7.62
8.26
0.3098
0.3000
0.3252
E1
6.35
6.10
7.11
0.2500
0.2402
0.2799
e
2.54
–
–
0.1000
–
–
eA
7.62
–
–
0.3000
–
–
eB
L
10.92
3.30
2.92
3.81
0.4299
0.1299
0.1150
0.1500
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 4578 Rev 19
33/42
Package mechanical data
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 15. SO8 narrow – 8 lead plastic small outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
GAUGE PLANE
D
k
8
E1
E
1
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 20.
SO8 narrow – 8 lead plastic small outline, 150 mils body width,
package mechanical data
inches(1)
millimeters
Symbol
Typ
Min
A
Max
Typ
1.75
Max
0.0689
A1
0.10
A2
1.25
b
0.28
0.48
0.0110
0.0189
c
0.17
0.23
0.0067
0.0091
ccc
0.25
0.0039
0.0098
0.0492
0.10
0.0039
D
4.90
4.80
5.00
0.1929
0.1890
0.1969
E
6.00
5.80
6.20
0.2362
0.2283
0.2441
E1
3.90
3.80
4.00
0.1535
0.1496
0.1575
e
1.27
–
–
0.0500
–
–
h
0.25
0.50
k
0°
8°
0°
8°
L
0.40
1.27
0.0157
0.0500
L1
1.04
0.0410
1. Values in inches are converted from mm and rounded to four decimal digits.
34/42
Min
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Package mechanical data
Figure 16. TSSOP8 – 8 lead thin shrink small outline, package outline
D
8
5
c
E1
1
E
4
α
A1
A
L
A2
L1
CP
b
e
TSSOP8AM
1. Drawing is not to scale.
Table 21.
TSSOP8 – 8 lead thin shrink small outline, package mechanical data
inches(1)
millimeters
Symbol
Typ.
Min.
A
Max.
Min.
1.200
A1
0.050
0.150
0.800
1.050
b
0.190
c
0.090
A2
Typ.
1.000
CP
Max.
0.0472
0.0020
0.0059
0.0315
0.0413
0.300
0.0075
0.0118
0.200
0.0035
0.0079
0.0394
0.100
0.0039
D
3.000
2.900
3.100
0.1181
0.1142
0.1220
e
0.650
–
–
0.0256
–
–
E
6.400
6.200
6.600
0.2520
0.2441
0.2598
E1
4.400
4.300
4.500
0.1732
0.1693
0.1772
L
0.600
0.450
0.750
0.0236
0.0177
0.0295
L1
1.000
0°
8°
α
0.0394
0°
8°
1. Values in inches are converted from mm and rounded to four decimal digits.
Doc ID 4578 Rev 19
35/42
Package mechanical data
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Figure 17. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead
2 × 3mm, package outline
-"
E
$
-#
E
B
,
,
%
B
,
,
%
0IN
%
+
+
,
,
!
$
$
EEE
!
:7?-%E
1. Drawing is not to scale.
2. The central pad (E2 × D2 area in the above illustration) is internally pulled to VSS. It must not be allowed to
be connected to any other voltage or signal line on the PCB, for example during the soldering process.
3. The circle in the top view of the package indicates the position of pin 1.
Table 22.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead
2 x 3 mm, data
inches(1)
millimeters
Symbol
Typ
Min
Max
Typ
Min
Max
A
0.550
0.450
0.600
0.0217
0.0177
0.0236
A1
0.020
0.000
0.050
0.0008
0.0000
0.0020
b
0.250
0.200
0.300
0.0098
0.0079
0.0118
D
2.000
1.900
2.100
0.0787
0.0748
0.0827
D2 (rev MB)
1.600
1.500
1.700
0.0630
0.0591
0.0669
1.200
1.600
0.0472
0.0630
D2 (rev MC)
E
3.000
2.900
3.100
0.1181
0.1142
0.1220
E2 (rev MB)
0.200
0.100
0.300
0.0079
0.0039
0.0118
1.200
1.600
0.0472
0.0630
E2 (rev MC)
e
0.500
0.0197
K
0.300
L
0.300
L1
L3
eee
(2)
0.0118
0.500
0.0118
0.150
0.0197
0.0059
0.300
0.0118
0.080
0.0031
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from
measuring.
36/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
9
Part numbering
Part numbering
Table 23.
Ordering information scheme
Example:
M24C32-D
W MN 6
T
P /P
Device type
M24 = I2C serial access EEPROM
Device function
C32– = 32 Kbit (4096 x 8)
Device family
Blank: Without Identification page
-D: With additional Identification page
Operating voltage
W = VCC = 2.5 V to 5.5 V
R = VCC = 1.8 V to 5.5 V
F = VCC = 1.7 V to 5.5 V
Package
BN = PDIP8(1)
MN = SO8 (150 mil width)(2)
DW = TSSOP8 (169 mil width)(2)
MB or MC = UFDFPN8 (MLP8)
Device grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
3 = Automotive: device tested with high-reliability certified flow over -40 to 125°C
5 = Consumer: device tested with standard test flow over –20 to 85°C
Option
blank = standard packing
T = Tape and reel packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(3)
P = F6DP26% Chartered (process letter used only when ordering a device grade 3)
K = F8H process
1. ECOPACK1® (RoHS-compliant).
2. ECOPACK2® (RoHS-compliant and halogen-free).
3. Process letter is used only for device grade 3.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Doc ID 4578 Rev 19
37/42
Revision history
10
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Revision history
Table 24.
38/42
Document revision history
Date
Revision
Changes
22-Dec-1999
2.3
TSSOP8 package in place of TSSOP14 (pp 1, 2, OrderingInfo,
PackageMechData).
28-Jun-2000
2.4
TSSOP8 package data corrected
31-Oct-2000
2.5
References to Temperature Range 3 removed from Ordering Information
Voltage range -S added, and range -R removed from text and tables
throughout.
20-Apr-2001
2.6
Lead Soldering Temperature in the Absolute Maximum Ratings table
amended
Write Cycle Polling Flow Chart using ACK illustration updated
References to PSDIP changed to PDIP and Package Mechanical data
updated
16-Jan-2002
2.7
Test condition for ILI made more precise, and value of ILI for E2-E0 and
WC added
-R voltage range added
02-Aug-2002
2.8
Document reformatted using new template.
TSSOP8 (3x3mm² body size) package (MSOP8) added.
5ms write time offered for 5V and 2.5V devices
04-Feb-2003
2.9
SO8W package removed. -S voltage range removed
27-May-2003
2.10
TSSOP8 (3x3mm² body size) package (MSOP8) removed
22-Oct-2003
3.0
Table of contents, and Pb-free options added. Minor wording changes in
Summary Description, Power-On Reset, Memory Addressing, Write
Operations, Read Operations. VIL(min) improved to -0.45V.
01-Jun-2004
4.0
Absolute Maximum Ratings for VIO(min) and VCC(min) improved.
Soldering temperature information clarified for RoHS compliant devices.
Device Grade clarified
04-Nov-2004
5.0
Product List summary table added. Device Grade 3 added. 4.5-5.5V
range is Not for New Design. Some minor wording changes. AEC-Q100002 compliance. tNS(max) changed. VIL(min) is the same on all input
pins of the device. ZWCL changed.
05-Jan-2005
6.0
UFDFPN8 package added. Small text changes.
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 24.
Revision history
Document revision history (continued)
Date
29-Jun-2006
03-Jul-2006
17-Oct-2006
27-Apr-2007
27-Nov-2007
Revision
Changes
7
Document converted to new ST template.
M24C32 and M24C64 products (4.5 to 5.5V supply voltage) removed.
M24C64 and M24C32 products (1.7 to 5.5V supply voltage) added.
Section 2.3: Chip Enable (E2, E1, E0) and Section 2.4: Write Control
(WC) modified, Section 2.6: Supply voltage (VCC) added and replaces
Power On Reset: VCC Lock-Out Write Protect section.
TA added, Note 1 updated and TLEAD specified for PDIP packages in
Table 6: Absolute maximum ratings.
ICC0 added, ICC voltage conditions changed and ICC1 specified over the
whole voltage range in Table 13: DC characteristics (M24xxx-W, device
grade 6).
ICC0 added, ICC frequency conditions changed and ICC1 specified over
the whole voltage range in Table 15: DC characteristics (M24xxx-R device grade 6).
tW modified in Table 16: AC characteristics.
SO8N package specifications updated (see Figure 15 and Table 20).
Device grade 5 added, B and P Process letters added to Table 23:
Ordering information scheme. Small text changes.
8
ICC1 modified in Table 13: DC characteristics (M24xxx-W, device grade
6).
Note 1 added to Table 16: DC characteristics (M24xxx-F) and table title
modified.
9
UFDFPN8 package specifications updated (see Table 21). M24128-BWand M24128-BR part numbers added.
Generic part number corrected in Features on page 1.
ICC0 corrected in Table 13 and Table 14.
Packages are ECOPACK® compliant.
10
Available packages and temperature ranges by product specified in
Table 22, Table 24 and Table 25.
Notes modified below Table 11: Input parameters.
VIH max modified in DC characteristics tables (see Table 14, Table 15,
Table 15 and Table 16).
C process code added to Table 23: Ordering information scheme.
For M24xxx-R (1.8 V to 5.5 V range) products assembled from July 2007
on, tW will be 5 ms (see Table 16: AC characteristics.
11
Small text changes. Section 2.5: VSS ground and Section 4.11: ECC
(Error Correction Code) and Write cycling added.
VIL and VIH modified in Table 15: DC characteristics (M24xxx-R - device
grade 6).
JEDEC standard reference updated below Table 6: Absolute maximum
ratings.
Package mechanical data inch values calculated from mm and rounded
to 4 decimal digits (see Section 8: Package mechanical data).
Doc ID 4578 Rev 19
39/42
Revision history
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 24.
Document revision history (continued)
Date
Revision
Changes
18-Dec-2007
12
Added Section 2.6.2: Power-up conditions, updated Section 2.6.3:
Device reset, and Section 2.6.4: Power-down conditions in Section 2.6:
Supply voltage (VCC).
Updated Figure 4: I2C Fast mode (fC = 400 kHz): maximum Rbus value
versus bus parasitic capacitance (Cbus).
Replace M24128 and M24C64 by M24128-BFMB6 and M24C64-FMB6,
respectively, in Section 4.11: ECC (Error Correction Code) and Write
cycling.
Added temperature grade 6 in Table 9: Operating conditions (M24xxxF).
Updated test conditions for ILO and VLO in Table 13: DC characteristics
(M24xxx-W, device grade 6), Table 14: DC characteristics (M24xxx-W device grade 3), and Table 15: DC characteristics (M24xxx-R - device
grade 6).
Test condition updated for ILO, and VIH and VIL differentiate for 1.8 V ≤
VCC < 2.5 V and 2.5 V ≤VCC < 5.5 V in Table 16: DC characteristics
(M24xxx-F).
Updated Table 16: AC characteristics, and Table 17: AC characteristics
(M24xxx-F).
Updated Figure 13: AC waveforms.
Added M24128-BF in Table 25: Available M24C32 products (package,
voltage range, temperature grade).
Process B removed fromTable 23: Ordering information scheme.
30-May-2008
13
Small text changes.
C Process option and Blank Plating technology option removed from
Table 23: Ordering information scheme.
14
WLCSP package added (see Figure 3: WLCSP connections (top view,
marking side, with balls on the underside) and Section 8: Package
mechanical data). Section 4.11: ECC (Error Correction Code) and Write
cycling updated.
16-Sep-2008
15
IOL added to Table 6: Absolute maximum ratings.
Table 24: Available M24C32 products (package, voltage range,
temperature grade) and Table 25: Available M24C32 products (package,
voltage range, temperature grade) updated.
05-Jan-2009
16
I2C modes supported specified in Features on page 1.
Note removed from Table 16: DC characteristics (M24xxx-F). Small text
changes.
15-Jul-2008
40/42
Doc ID 4578 Rev 19
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Table 24.
Revision history
Document revision history (continued)
Date
30-Nov-2009
18-Mar-2011
14-Sep-2011
Revision
Changes
17
64 and 128 Kbit densities removed.
Section 2.6.2: Power-up conditions updated.
Figure 4: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus) updated.
ICC1 and VIH updated in Table 13: DC characteristics (M24xxx-W, device
grade 6), Table 14: DC characteristics (M24xxx-W - device grade 3),
Table 15: DC characteristics (M24xxx-R - device grade 6) and Table 16:
DC characteristics (M24xxx-F).
Table 16: AC characteristics modified.
Figure 13: AC waveforms modified.
Note added below Figure 17: UFDFPN8 (MLP8) – 8-lead ultra thin fine
pitch dual flat package no lead 2 × 3mm, package outline.
Small text changes.
18
Added:
– M24C32-DF and all information concerning the Identification Page:
sections 4.9, 4.10, 4.17, 4.18
– ECC section 4.11
– AC table with clock frequency of 1 MHz (Table 18)
– Table 4: Device select code
Updated:
– Section 1: Description
– Section 4.5: Memory addressing
– Section 4.18: Read the lock status (M24C32-D)
– Table 6: Absolute maximum ratings
– AC/DC tables 13, 17 with values specific to the device identified with
process letter K
Deleted:
– Table 2: Device select code
– Table 23: Available M24C32 products (package, voltage range,
temperature grade)
19
Updated:
– Figure 4: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus
bus parasitic capacitance (Cbus)
– Figure 5: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value
versus bus parasitic capacitance (Cbus)
Added tWLDL and tDHWH in:
– Table 17: 400 kHz AC characteristics
– Table 18: 1 MHz AC characteristics
– Figure 13: AC waveforms
Minor text changes.
Doc ID 4578 Rev 19
41/42
M24C32-DF, M24C32-W, M24C32-R, M24C32-F
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
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