M24C32-WMN6P

M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 32-Kbit serial I²C bus EEPROM Datasheet - production data Features • Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz   PDIP8 (BN) TSSOP8 (DW) 169 mil width • Memory array: – 32 Kbit (4 Kbyte) of EEPROM – Page size: 32 byte – Additional Write lockable page (M24C32-D order codes) SO8 (MN) 150 mil width • Single supply voltage: – 1.7 V to 5.5 V over –40 °C / +85 °C – 1.6 V to 5.5 V over –20 °C / +85 °C • Write: – Byte Write within 5 ms – Page Write within 5 ms • Random and sequential Read modes UFDFPN8 (MC) DFN8 - 2x3 mm UFDFPN5 (MH) DFN5 - 1.7x1.4 mm • Write protect of the whole memory array • Enhanced ESD/Latch-Up protection • More than 4 million Write cycles • More than 200-years data retention Packages WLCSP (CU) • PDIP8 ECOPACK2® • SO8 ECOPACK2® • TSSOP8 ECOPACK2® • UFDFPN8 ECOPACK2® • WLCSP ECOPACK2® • UFDFPN5 ECOPACK2® • Unsawn wafer (each die is tested) Unsawn wafer September 2017 This is information on a product in full production. DocID4578 Rev 30 1/51 www.st.com Contents M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 5.2 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.3 Write Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.4 Lock Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 17 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 17 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 2/51 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.4 Read Identification Page (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . 20 5.2.5 Read the lock status (M24C32-D only) . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 UFDFPN5 (DFN5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 UFDFPN8 (DFN8) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.5 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.6 Ultra Thin WLCSP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID4578 Rev 30 3/51 3 List of tables M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. 4/51 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signals vs. bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC characteristics (M24C32-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics (M24C32-R device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M24C32-F, device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M24C32-X, device grade 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 40 Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, with BSC, wafer level chip scale package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 UFDFPN5 (DFN5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP 4 bump Ultra thin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 14. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline . 38 SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 40 Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, with BSC, wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID4578 Rev 30 5/51 5 Description 1 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Description The M24C32 is a 32-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 4 K × 8 bits. The M24C32-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24C32-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24C32-F and M24C32-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C; while the M24C32-X can operate with a supply voltage from 1.6 V to 5.5 V over an ambient temperature range of -20 °C / +85 °C. The M24C32-D offers an additional page, named the Identification Page (32 byte). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. Figure 1. Logic diagram 9&&  (( 6'$ 0[[[ 6&/ :& 966 $,I Table 1. Signal names Signal name Function Direction E2, E1, E0 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections, top view (   9&& (   :& (   6&/ 966   6'$ $,I 6/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Description Figure 3. UFDFPN5 (DFN5) package connections 6 ##  6 33  3$!  !"#$ 89:7  7#   6 33  3#,      4OPVIEW MARKINGSIDE "OTTOMVIEW PADSSIDE -36 1. Inputs E2, E1, E0 are not connected, therefore read as (000). Please refer to Section 2.3 for further explanations. Figure 4. WLCSP 4 bump Ultra thin package connections     $ 9&& 966 966 9&& $ % 6&/ 6'$ 6'$ 6&/ % 0DUNLQJVLGH WRSYLHZ %XPSVLGH ERWWRPYLHZ 06Y9 1. Inputs E2, E1, E0 are read as (000). Please refer to Section 2.3 for further explanations. Table 2. Signals vs. bump position Position A B 1 VCC SCL 2 VSS SDA DocID4578 Rev 30 7/51 50 Signal description M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 2 Signal description 2.1 Serial Clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC (Figure 13 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1, E0) (E2,E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 3). These inputs must be tied to VCC or VSS, as shown in Figure 5. When not connected (left floating), these inputs are read as low (0). For the UFDFPN5 package, the (E2,E1,E0) inputs are not connected, therefore read as (0,0,0). For the 4-balls WLCSP package (see Figure 4), the (E2,E1,E0) inputs are internally connected to (0, 0, 0). Figure 5. Chip enable inputs connection 9&& 9&& 0[[[ 0[[[ (L (L 966 2.4 966 $L Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 2.5 Signal description VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8: DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8: DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8: DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the internal reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the Standby Power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). DocID4578 Rev 30 9/51 50 Memory organization 3 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Memory organization The memory is organized as shown below. Figure 6. Block diagram 7# % % % (IGHVOLTAGE GENERATOR #ONTROLLOGIC 3#, 3$! )/SHIFTREGISTER $ATA REGISTER 9DECODER !DDRESSREGISTER ANDCOUNTER PAGE )DENTIFICATIONPAGE 8DECODER -36 10/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 4 Device operation Device operation The device supports the I2C protocol. This is summarized in Figure 7. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The device is always a slave in all communications. Figure 7. I2C bus protocol DocID4578 Rev 30 11/51 50 Device operation 4.1 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 4.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read instruction that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 4.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. 12/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 4.5 Device operation Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 3 (most significant bit first). Table 3. Device select code Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2 E1 E0 RW Device select code when accessing the Identification page 1 0 1 1 E2 E1 E0 RW 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2. When the device select code is received, the device only responds if the Chip Enable address is the same as the value on its Chip Enable E2,E1,E0 inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the device select code, the device deselects itself from the bus, and goes into Standby mode. DocID4578 Rev 30 13/51 50 Instructions M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 5 Instructions 5.1 Write operations Following a Start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 4. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 A1 A0 Table 5. Least significant address byte A7 A6 A5 A4 A3 A2 When the bus master generates a Stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle tW is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. After the Stop condition and the successful completion of an internal Write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 9. 14/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 5.1.1 Instructions Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 8. Figure 8. Write mode sequences with WC = 0 (data write enabled) DocID4578 Rev 30 15/51 50 Instructions 5.1.2 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Page Write The Page Write mode allows up to 32 byte to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, b16-b5, are the same. If more bytes are sent than will fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 32 byte of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 9. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 9. Write mode sequences with WC = 1 (data write inhibited) 16/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 5.1.3 Instructions Write Identification Page (M24C32-D only) The Identification Page (32 byte) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: • Device type identifier = 1011b • MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’. LSB address bits A4/A0 define the byte address inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). 5.1.4 Lock Identification Page (M24C32-D only) The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: 5.1.5 • Device type identifier = 1011b • Address bit A10 must be ‘1’; all other address bits are don't care • The data byte must be equal to the binary value xxxx xx1x, where x is don't care ECC (Error Correction Code) and Write cycling The ECC is offered only in devices identified with process letter K, all other devices (identified with a different process letter) do not embed the ECC logic. The Error Correction Code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(1). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(1). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 13: Cycling performance. 1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. DocID4578 Rev 30 17/51 50 Instructions 5.1.6 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 10, is: • Initial condition: a Write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 10. Write cycle polling flowchart using ACK :ULWHF\FOH LQSURJUHVV 6WDUWFRQGLWLRQ 'HYLFHVHOHFW ZLWK5:  12 $&. UHWXUQHG ϭ >ϯ WŝŶϭ  Ϯ < >  Ϯ ĞĞĞ ϭ =:B0(H9 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. Table 22. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - eee(2) 0.080 - - 0.0031 - - 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 36/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 9.3 Package information TSSOP8 package information Figure 19.TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package outline  ϴ ϱ Đ ϭ ϭ  ϰ ɲ > ϭ W Ϯ  >ϭ ď Ğ 76623$0B9 1. Drawing is not to scale. Table 23. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 CP - - 0.100 - - 0.0039 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DocID4578 Rev 30 37/51 50 Package information 9.4 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF SO8N package information Figure 20. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline HXƒ ! ! C CCC B E PP *$8*(3/$1( $ K  % %  ! , , 62$B9 1. Drawing is not to scale. Table 24. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol inches(1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 38/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Package information Figure 21. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint   [  2B621B)3B9 1. Dimensions are expressed in millimeters. DocID4578 Rev 30 39/51 50 Package information 9.5 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF PDIP8 package information Figure 22. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline % B ! ! B ! , C E E! E" $  %  0$)0 " 1. Drawing is not to scale. 2. Not recommended for new designs. Table 25. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 5.33 - - 0.2098 A1 0.38 - - 0.0150 - - A2 2.92 3.30 4.95 0.1150 0.1299 0.1949 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 b2 1.14 1.52 1.78 0.0449 0.0598 0.0701 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 D 9.02 9.27 10.16 0.3551 0.3650 0.4000 E 7.62 7.87 8.26 0.3000 0.3098 0.3252 E1 6.10 6.35 7.11 0.2402 0.2500 0.2799 e - 2.54 - - 0.1000 - eA - 7.62 - - 0.3000 - eB - - 10.92 - - 0.4299 L 2.92 3.30 3.81 0.1150 0.1299 0.1500 1. Values in inches are converted from mm and rounded to four decimal digits. 40/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 9.6 Package information Ultra Thin WLCSP package information Figure 23. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package outline EEE = ' 2ULHQWDWLRQ UHIHUHQFH 'HWDLO$ ; < H ) ( H ) DDD ; 2ULHQWDWLRQ UHIHUHQFH $ $ :DIHUEDFNVLGH * 6LGHYLHZ * %XPSVLGH %XPS $ HHH = = E; T FFF0 = ; < TGGG0 = 6HDWLQJSODQH 'HWDLO$ 5RWDWHGƒ $=B:/&63B0(B9 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 3. Side view Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.260 0.290 0.320 0.0102 0.0114 0.0126 A1 - 0.115 - - 0.0045 - A2 - 0.175 - - 0.0069 - b(2) - 0.160 - - 0.0063 - D - 0.795 0.815 - 0.0313 0.0321 E - 0.674 0.694 - 0.0265 0.0273 e - 0.400 - - 0.0157 - F - 0.137 - - 0.0054 - G - 0.198 - - 0.0078 - aaa - - 0.110 - - 0.0043 DocID4578 Rev 30 41/51 50 Package information M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package mechanical data (continued) bbb - - 0.110 - - 0.0043 ccc - - 0.110 - - 0.0043 ddd - - 0.060 - - 0.0024 eee - - 0.060 - - 0.0024 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 24. Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package recommended footprint   [ E $=B:/&63B)3B9 1. Dimensions are expressed in millimeters. 42/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Package information Figure 25. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, with BSC, wafer level chip scale package outline %DFNVLGHFRDWLQJ WKLFNQHVVPP ; ' EEE = 2ULHQWDWLRQ UHIHUHQFH 'HWDLO$ < H ) ( H ) DDD ; 2ULHQWDWLRQ UHIHUHQFH $ $ * $ :DIHUEDFNVLGH 6LGHYLHZ * %XPS6LGH %XPS $ HHH = = E; T FFF0 = ; < TGGG0 = 6HDWLQJSODQH 'HWDLO$ 5RWDWHGƒ $=%6&B0(B9 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Table 27. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, with BSC, wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.285 0.315 0.345 0.0112 0.0124 0.0136 A1 - 0.115 - - 0.0045 - A2 - 0.175 - - 0.0069 - A3 (BSC) - 0.025 - - 0.0010 - b(2) (3) - 0.160 - - 0.0063 - D - 0.795 0.815 - 0.0313 0.0321 E - 0.674 0.694 - 0.0265 0.0273 e - 0.400 - - 0.0157 - F - 0.137 - - 0.0054 - G - 0.198 - - 0.0078 - aaa - - 0.110 - - 0.0043 bbb - - 0.110 - - 0.0043 DocID4578 Rev 30 43/51 50 Package information M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Table 27. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, with BSC, wafer level chip scale package mechanical data (continued) ccc - - 0.110 - - 0.0043 ddd - - 0.060 - - 0.0024 eee - - 0.060 - - 0.0024 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Figure 26. Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package recommended footprint H H [ E $=%6&B)3B9 1. Dimensions are expressed in millimeters. 44/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF 10 Ordering information Ordering information Table 28. Ordering information scheme Example: M24C32 -D W MC 6 T P /T F Device type M24 = I2C serial access EEPROM Device function C32 = 32 Kbit (4096 x 8 bit) Device family Blank = Without Identification page D = With Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V X = VCC = 1.6 V to 5.5 V Package BN = PDIP8(1) MN = SO8 (150 mil width)(2) DW = TSSOP8 (169 mil width)(2) MC = UFDFPN8 (DFN8)(2) MH = UFDFPN5 (DFN5)(2) CU = Ultra-thin 4 bump WLCSP(2) Device grade 5 = Consumer: device tested with standard test flow over –20 to 85°C 6 = Industrial: device tested with standard test flow over –40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = ECOPACK2® Process(3) (4) /P or /K or /T= Manufacturing technology code Option Blank = No Back Side Coating F = Back Side Coating (WLCSP height = 0.345mm) 1. RoHS-compliant (ECOPACK1®) 2. RoHS compliant and free of brominated, chlorinated and antimony-oxide flame retardants 3. These process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. 4. Part numbering for WLCSP DocID4578 Rev 30 45/51 50 Ordering information M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Table 29. Ordering information scheme (unsawn wafer)(1) Example: M24C32 - F T W 20 I /90 Device type M24 = I2C serial access EEPROM Device function C32 = 32 Kbit (4096 x 8 bit) Operating voltage F = VCC = 1.7 V to 5.5 V Process T = F8H Delivery form W = Wafer (bare die) Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C 1. For all information concerning the M24C32 delivered in unsawn wafer, please contact your nearest ST Sales Office. 46/51 DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Ordering information Engineering samples Parts marked as ES or E are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences deriving from such use. In no event, will ST be liable for the customer using of these engineering samples in production. ST’s quality department must be contacted prior to any decision to use these engineering samples to run qualification activity. DocID4578 Rev 30 47/51 50 Revision history 11 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Revision history Table 30. Document revision history Date 18-Mar-2011 14-Sep-2011 21-May-2012 25-Jul-2012 48/51 Revision Changes 18 Added: – M24C32-DF and all information concerning the Identification Page: sections 4.9, 4.10, 4.17, 4.18 – ECC section 4.11 – AC table with clock frequency of 1 MHz (Table 18) – Table 4: Device select code Updated: – Section 1: Description – Section 4.5: Memory addressing – Section 4.18: Read the lock status (M24C32-D) – Table 6: Absolute maximum ratings – AC/DC tables 13, 17 with values specific to the device identified with process letter K Deleted: – Table 2: Device select code – Table 23: Available M24C32 products (package, voltage range, temperature grade) 19 Updated: – Figure 4: I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) – Figure 5: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus) Added tWLDL and tDHWH in: – Table 17: 400 kHz AC characteristics – Table 18: 1 MHz AC characteristics – Figure 13: AC waveforms Minor text changes. 20 Datasheet split into: – M24C32-DF, M24C32-W, M24C32-R,M24C32-F (this datasheet) for standard products (range 6), – M24C32-125 datasheet for automotive products (range 3). 21 Added reference M24C32-X. Updated: – AC and DC tables in Section 8: DC and AC parameters. – Figure 56.: M24C16-FCS5TP/S WLCSP 5 bumps package outline. DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Revision history Table 30. Document revision history (continued) Date Revision Changes 19-May-2014 22 Add new package UFDFPN5, description onFigure 51 and Table 20. Updated: – Figure 30: Block diagram – VESD value on Table 14 – Icc1 values on Table 32 – Icc and Icc0 test conditions on Table 40 – VIH(max) values on Table 32, Table 33 – Icc, Icc0 ,Icc1, VIL, VOL and VIH test conditions onTable 40 – Note on Table 29, Table 31, Table 32, Table 40, Table 41 and Table 48 – Table 76 – Section numbering for Section 5.2.5 and Section 5.2.6. 28-Jul-2014 23 Updated Table 21. 24 Updated – Section 5.1.6. – Note 1 on Table 29 – Section 9, added reference to unsawn wafer availability. – note 3 on Table 76. Added: – Note 1 on Table 21 – Note 2 on Table 31 – Note 2 on Figure 58 – Table 90. Removed notes 1 and 2 on Section 5.1.6 25 Updated: – Section 2.4 – Section 6 – Table 76 – note 2 on Table 76 Added: – WLCSP package in cover page. – Section 9.7: Ultra Thin WLCSP package information 27-Aug-2015 26 Updated: – Table 14 Added: – Note 3 in Figure 59. – Note 1 in Table 60. – Note 2 Table 76 12-Feb-2016 27 Updated Figure 17, Figure 51. Added Table 2. 05-May-2016 28 Updated Table 14: Absolute maximum ratings. 02-Sept-2014 23-Jul-2015 DocID4578 Rev 30 49/51 50 Revision history M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF Table 30. Document revision history (continued) Date Revision 10-Jul-2017 29 Updated Section 9.6: Ultra Thin WLCSP package information 30 Added reference to DFN8 and DFN5 in: cover page figure, Figure 3: UFDFPN5 (DFN5) package connections, Section 9.1: UFDFPN5 (DFN5) package information, Section 9.2: UFDFPN8 (DFN8) package information and Table 28: Ordering information scheme 11-Sep-2017 50/51 Changes DocID4578 Rev 30 M24C32-W M24C32-R M24C32-F M24C32-X M24C32-DF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID4578 Rev 30 51/51 51