M24C64-DFMC6TG

M24C64-W M24C64-R M24C64-F M24C64-DF Datasheet 64-Kbit serial I²C bus EEPROMs Features • WLCSP (CS) WLCSP (CU) • SO8N (MN) UFDFPN5 (MH) 150 mil width DFN5 - 1.7 x 1.4 mm • • TSSOP8 (DW) UFDFPN8 (MC) 169 mil width DFN8 - 2 x 3 mm Thin WLCSP (CT) Unsawn wafer Product status link M24C64-W • • • • • Compatible with following I2C bus modes: – 1 MHz – 400 kHz – 100 kHz Memory array: – 64 Kbit (8 Kbyte) of EEPROM – Page size: 32 byte – Additional Write lockable page (M24C64-D order codes) Single supply voltage: – 1.7 V to 5.5 V over –40 °C / +85 °C – 1.6 V to 5.5 V over 0 °C / +85 °C Write: – Byte write within 5 ms – Page write within 5 ms Random and sequential read modes Write protect of the whole memory array Enhanced ESD/latch-Up protection More than 4 million write cycles More than 200-years data retention Packages Packages RoHS-compliant and Halogen-free • SO8N (ECOPACK2) • TSSOP8 (ECOPACK2) • UFDFPN (ECOPACK2) • WLCSP (ECOPACK2) • Unsawn wafer (each die is tested) M24C64-R M24C64-F M24C64-DF DS6638 - Rev 37 - July 2022 For further information contact your local STMicroelectronics sales office. www.st.com M24C64-W M24C64-R M24C64-F M24C64-DF Description 1 Description The M24C64 is a 64-Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 8K × 8 bits. Over an ambient temperature range of -40 °C / +85 °C, the M24C64-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24C64-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24C64-F and M24C64-DF can operate with a supply voltage from 1.7 V to 5.5 V ( the M24C64-F can also operate down to 1.6 V, under some restricting conditions). The M24C64-D offers an additional page, named the identification page (32 byte). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. Figure 1. Logic diagram VCC 3 E0-E2 SDA M24xxx SCL WC VSS Table 1. Signal names Signal name Function Direction E2, E1, E0 Chip enable Input SDA Serial data I/O SCL Serial clock Input WC Write control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections, top view 1. DS6638 - Rev 37 E0 1 8 VCC E1 2 7 WC E2 3 6 SCL VSS 4 5 SDA See Section 9 Package information for package dimensions, and how to identify pin 1 page 2/51 M24C64-W M24C64-R M24C64-F M24C64-DF Description Figure 3. UFDFPN5 (DFN5) package connections 1. VCC 1 VSS 2 SDA 3 ABCD XYZW 5 WC 5 1 2 VSS 2 2 4 SCL 4 3 Top view Bottom view (marking side) (pads side) Inputs E2, E1 and E0 are not connected, therefore read as (000). Refer to Section 2.3 Chip enable (E2, E1, E0) for further explanations. Figure 4. WLCSP 4-bump ultra thin package connections 1 2 2 1 A VCC VSS VSS VCC A B SCL SDA SDA SCL B Marking side (top view) 1. Bump side (bottom view) MS57081 Inputs E2, E1, E0 are read as (000). Refer to Section 2.3 Chip enable (E2, E1, E0) for further explanations. Table 2. WLCSP 4-bump signal vs. bump position Position A B 1 VCC SCL 2 VSS SDA Figure 5. WLCSP 5-bump connections 1 A VCC 3 3 VSS VSS WC SCL Marking side (top view) 1. DS6638 - Rev 37 2 1 VCC SCL A B SDA SDA B C 2 WC Bump side (bottom view) C MS35045V2 Inputs E2, E1, E0 are internally connected to (001). Refer to Section 2.3 Chip enable (E2, E1, E0) for further explanations. page 3/51 M24C64-W M24C64-R M24C64-F M24C64-DF Description Table 3. WLCSP 5-bump signals vs. bump position Position A B C 1 VCC - WC 2 - SDA - 3 VSS - SCL Figure 6. WLCSP 8-bump connections 1 2 3 4 5 A B C VCC WC SDA SCL E1 5 4 3 2 1 E1 VCC E0 VSS E0 E2 Marking side (top view) E2 WC B SDA VSS A SCL C Bump side (bottom view) MS35046V2 Table 4. WLCSP 8-bump signals vs. bump position DS6638 - Rev 37 Position A B C 1 WC - SCL 2 - SDA - 3 VCC - VSS 4 - E0 - 5 E1 - E2 page 4/51 M24C64-W M24C64-R M24C64-F M24C64-DF Signal description 2 Signal description 2.1 Serial clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wired-AND with other open drain or open collector signals on the bus. A pull-up resistor must be connected from serial data (SDA) to VCC (Figure 15 and Figure 16 indicates how to calculate the value of the pull-up resistor). 2.3 Chip enable (E2, E1, E0) (E2, E1,E0) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select code (see Table 5. These inputs must be tied to VCC or VSS to establish the device select code as shown in Figure 7. When not connected (left floating), these inputs are read as low (0, 0, 0). For the 4-balls WLCSP package (see Figure 4), the (E2,E1,E0) inputs are internally connected to (0, 0, 0). For the 5-balls WLCSP package (see Figure 5), the (E2,E1,E0) inputs are internally connected to (0,0,1). Figure 7. Chip enable inputs connection VCC VCC M24xxx M24xxx Ei Ei VSS 2.4 VSS Write control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for all signals, including the VCC supply voltage. DS6638 - Rev 37 page 5/51 M24C64-W M24C64-R M24C64-F M24C64-DF Supply voltage (VCC) 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8 DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). DS6638 - Rev 37 page 6/51 M24C64-W M24C64-R M24C64-F M24C64-DF Block diagram 3 Block diagram The block diagram of the device is described below. Figure 8. Block diagram SENSE AMPLIFIERS PAGE LATCHES ARRAY SCL I/O X DECODER Y DECODER DATA REGISTER + ECC SDA WC START & STOP DETECT Ei CONTROL LOGIC IDENTIFICATION PAGE HV GENERATOR + SEQUENCER ADDRESS REGISTER DS6638 - Rev 37 page 7/51 M24C64-W M24C64-R M24C64-F M24C64-DF Device operation 4 Device operation The device supports the I2C protocol. This is summarized in Figure 9. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The device is always a slave in all communications. Figure 9. I2C bus protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition DS6638 - Rev 37 page 8/51 M24C64-W M24C64-R M24C64-F M24C64-DF Start condition 4.1 Start condition Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition. 4.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A stop condition terminates communication between the device and the bus master. A read instruction that is followed by NoAck can be followed by a stop condition to force the device into the standby mode. A stop condition at the end of a write instruction triggers the internal write cycle. 4.3 Data input During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. DS6638 - Rev 37 page 9/51 M24C64-W M24C64-R M24C64-F M24C64-DF Device addressing 4.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 5 (most significant bit first). Table 5. Device select code Device type identifier(1) Chip Enable address(2) RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2 E1 E0 RW Device select code when accessing the identification page 1 0 1 1 E2 E1 E0 RW 1. The MSB, b7, is sent first. 2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2. When the device select code is received, the device only responds if the chip enable address is the same as the value on its chip enable E2,E1,E0 inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgement on serial data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. DS6638 - Rev 37 page 10/51 M24C64-W M24C64-R M24C64-F M24C64-DF Instructions 5 Instructions 5.1 Write operations Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 10, and waits for two address byte. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 6. Most significant address byte A7 A6 A5 A4 A3 A2 A1 A0 A1 A0 Table 7. Least significant address byte A7 A6 A5 A4 A3 A2 When the bus master generates a stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. After the stop condition and the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 11. DS6638 - Rev 37 page 11/51 M24C64-W M24C64-R M24C64-F M24C64-DF Write operations 5.1.1 Byte write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected, by write control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not write-protected, the device replies with Ack. The bus master terminates the transfer by generating a stop condition, as shown in Figure 10. Figure 10. Write mode sequences with WC = 0 (data write enabled) WC ACK ACK Data in Stop Byte address Dev Select Start Byte Write ACK R/W WC ACK Dev Select Start Page Write ACK Byte address ACK Data in 1 ACK Data in 2 Data in 3 R/W WC (cont'd) ACK Data in N Stop Page Write(cont'd) ACK DS6638 - Rev 37 page 12/51 M24C64-W M24C64-R M24C64-F M24C64-DF Write operations 5.1.2 Page write The page write mode allows up to 32 byte to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A15/A5, are the same. If more bytes are sent than fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 32 byte of data, each of which is acknowledged by the device if write control (WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 11. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 11. Write mode sequences with WC = 1 (data write inhibited) WC ACK Byte address NO ACK Data in Stop Dev select Start Byte Write ACK R/W WC ACK Dev select Start Page Write ACK Byte address NO ACK Data in 1 NO ACK Data in 2 Data in 3 R/W WC (cont'd) NO ACK Data in N Stop Page Write(cont'd) NO ACK AI02803d_dita DS6638 - Rev 37 page 13/51 M24C64-W M24C64-R M24C64-F M24C64-DF Write operations 5.1.3 Write identification page (M24C64-D only) The identification page (32 byte) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences: • • Device type identifier = 1011b MSB address bits A15/A5 are don't care except for address bit A10 which must be ‘0’. LSB address bits A4/A0 define the byte address inside the identification page. If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoAck). 5.1.4 Lock identification page (M24C64-D only) The lock identification page instruction (Lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions: • • • 5.1.5 Device type identifier = 1011b Address bit A10 must be ‘1’; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care ECC (error correction code) and write cycling The ECC is offered only in devices identified with process letter K, all other devices (identified with a different process letter) do not embed the ECC logic. The error correction code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 14. DS6638 - Rev 37 page 14/51 M24C64-W M24C64-R M24C64-F M24C64-DF Write operations 5.1.6 Minimizing write delays by polling on ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum write time (tw) is shown in AC characteristics tables in Section 8 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 12, is: • • • Initial condition: a write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 12. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop 1. DS6638 - Rev 37 NO StartCondition YES Data for the write operation Device select with RW = 1 Continue the write operation Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the Figure 12) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the Figure 12). page 15/51 M24C64-W M24C64-R M24C64-F M24C64-DF Read operations 5.2 Read operations Read operations are performed independently of the state of the write control (WC) signal. After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its standby mode after a stop condition. Figure 13. Read mode sequences ACK Data out Stop Start Dev select R/W ACK Start Dev select * Byte address R/W ACK Sequential Current Read Dev select * NO ACK Data out R/W ACK ACK Data out 1 NO ACK Data out N Stop Start Dev select R/W ACK Start Dev select * ACK Byte address R/W ACK ACK Dev select * Start Sequential Random Read ACK Start Random Address Read ACK Stop Current Address Read NO ACK ACK Data out 1 R/W NO ACK Stop Data out N Note: DS6638 - Rev 37 The seven most significant bits of the first device select code of a random read must be identical to the seven most significant bits of the device select code of the write. page 16/51 M24C64-W M24C64-R M24C64-F M24C64-DF Read operations 5.2.1 Random address read A dummy write is first performed to load the address into this address counter (as shown in Figure 13) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 13, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the Identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the Identification page, therefore the next Current Address Read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the Random Address Read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1 Random address read) instead of the Current Address Read instruction. 5.2.3 Sequential read This operation can be used after a current address read or a random address read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 13. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. 5.2.4 Read identification page (M24C64-D only) The Identification Page (32 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The identification page can be read by issuing an read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. The MSB address bits A15/A5 are don't care, the LSB address bits A4/A0 define the byte address inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the identification page from location 10d, the number of bytes should be less than or equal to 22, as the ID page boundary is 32 bytes). 5.2.5 Read the lock status (M24C64-D only) The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit if the identification page is unlocked, otherwise a NoAck bit if the identification page is locked. Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: • • DS6638 - Rev 37 Start: the truncated command is not executed because the start condition resets the device internal logic, Stop: the device is then set back into standby mode by the stop condition. page 17/51 M24C64-W M24C64-R M24C64-F M24C64-DF Initial delivery state 6 Initial delivery state The device is delivered with all the memory array bits and identification page bits set to 1 (each byte contains FFh). When delivered in unsawn wafer, all memory bits are set to 1 (each memory byte contains FFh) except the last byte located at address 1FFFh which is written with the value 22h. DS6638 - Rev 37 page 18/51 M24C64-W M24C64-R M24C64-F M24C64-DF Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol Min. Max. Unit Ambient operating temperature -40 130 °C TSTG Storage temperature -65 150 °C TLEAD Lead temperature during soldering - Parameter IOL DC output current (SDA = 0) VIO see note (1) °C – 5 mA Input or output range -0.50 6.5 V VCC Supply voltage -0.50 6.5 V VESD Electrostatic pulse (human body model)(2) – 3000(3) V 1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to ANSI/ESDA/JEDEC JS-001 (C1=100 pF, R1=1500 Ω). 3. 4000 V for devices identified with process letter K. DS6638 - Rev 37 page 19/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 9. Operating conditions (voltage range W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz Min. Max. Unit Supply voltage 1.8 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 1 MHz VCC Parameter Table 10. Operating conditions (voltage range R) Symbol VCC Parameter Table 11. Operating conditions (voltage range F) Symbol VCC TA fC Parameter Min. Max. Unit 1.7 5.5 V -40 -40 85 0 -40 85 1.6(1) Ambient operating temperature: READ Ambient operating temperature: WRITE Supply voltage Operating clock frequency, VCC ≥ 1.6 V(1) - 400 Operating clock frequency, VCC ≥ 1.7 V - 1000 °C kHz 1. Only for devices identified with process letter T. Table 12. AC measurement conditions Symbol Min. Max. Unit Load capacitance - 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V Cbus DS6638 - Rev 37 Parameter page 20/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Figure 14. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3V CC 0.2VCC Table 13. Input parameters Parameter(1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - kΩ VIN > 0.7 VCC 500 - kΩ ZL ZH Input impedance (E2, E1, E0,WC)(2) 1. Evaluated by characterization – Not tested in production. 2. Input impedance when the memory is selected (after a start condition). Table 14. Cycling performance Symbol Ncycle Parameter Write cycle endurance(1) Test condition Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(2) 1. The Write cycle endurance is evaluated by characterization and qualification. For devices embedding the ECC functionality (see Section 5.1.5 ECC (error correction code) and write cycling), the write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. 2. A Write cycle is executed when either a page write, a byte write, a write Identification Page or a lock identification page instruction is decoded. When using the byte write, the Page Write or the write identification page, refer also to Section 5.1.5 ECC (error correction code) and write cycling Table 15. Memory cell data retention Parameter Data retention(1) Test condition TA = 55 °C Min. Unit 200 Year 1. The data retention behavior is checked in production, while the data retention limit defined in this table is extracted from characterization and qualification results. DS6638 - Rev 37 page 21/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Table 16. DC characteristics (M24C64-W) Symbol ILI Parameter Input leakage current (Ei, SCL, SDA) Test conditions (in addition to those in Table 9 and Table 12) VIN = VSS or VCC, device in standby mode Min. Max. Unit - ±2 µA µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 ICC Supply current (Read) fC = 400 kHz, 2.5 V ≤ VCC ≤ 5.5 V - 2 fC = 1 MHz, 2.5 V ≤ VCC ≤ 5.5 V - 2.5 ICC0(1) Supply current (Write) - 2.5 mA - 2 μA - 3 μA - –0.45 0.3 VCC V - 0.7 VCC 6.5 During tW, 2.5 V ≤ VCC ≤ 5.5 V Device not selected(2), ICC1 Standby supply current VIN = VSS or VCC, VCC = 2.5 V Device not selected(2), VIN = VSS or VCC, VCC = 5.5 V mA Input low voltage VIL (SCL, SDA, WC,Ei) (3) Input high voltage (SCL, SDA) VIH V Input high voltage (WC, Ei) - 0.7 VCC VCC+ 0.6 (4) VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V - 0.4 V 1. Evaluated by characterization - Not tested in production. 2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 3. Ei inputs should be tied to VSS (see Section 2.3 Chip enable (E2, E1, E0)). 4. Ei inputs should be tied to VCC (see Section 2.3 Chip enable (E2, E1, E0)) DS6638 - Rev 37 page 22/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Table 17. DC characteristics (M24C64-R) Symbol ILI Parameter Input leakage current (Ei, SCL, SDA) ILO Output leakage current ICC Supply current (Read) ICC0(2) Supply current (Write) ICC1 Standby supply current Test conditions(1) (in addition to those in Table 10) Min. Max. Unit VIN = VSS or VCC, device in standby mode - ±2 µA SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA VCC = 1.8 V, fc= 400 kHz - 0.8 fc= 1 MHz - 2.5 - 1.5 mA - 1 µA 1.8 V ≤ VCC ≤ 2.5 V -0.45 0.25 VCC V 1.8 V ≤ VCC < 2.5 V 0.75 VCC 6.5 V 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 0.6 During tW, 1.8 V ≤ VCC ≤ 2.5 V Device not selected,(3) VIN = VSS or VCC, VCC = 1.8 V mA Input low voltage VIL (SCL, SDA, WC, Ei) (4) Input high voltage (SCL, SDA) VIH Input high voltage (WC, Ei) V (5) VOL Output low voltage IOL = 1 mA, VCC = 1.8 V - 0.2 V 1. If the application uses the voltage range R device with 2.5 V ≤ Vcc ≤ 5.5 V and -40 °C < TA < +85 °C, refer to Table 16 instead of this table. 2. Evaluated by characterization - Not tested in production. 3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 4. Ei inputs should be tied to VSS (see Section 2.3 Chip enable (E2, E1, E0)) 5. Ei inputs should be tied to VCC (see Section 2.3 Chip enable (E2, E1, E0)) DS6638 - Rev 37 page 23/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Table 18. DC characteristics (M24C64-F, M24C64-DF) Symbol Parameter Test conditions(1) (in addition to those in Table 11) Min. Max. Unit - ±2 µA µA Input leakage current VIN = VSS or VCC (Ei, SCL, SDA) device in Standby mode ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 ICC Supply current (Read) VCC = 1.6 V or 1.7 V, fc= 400 kHz - 0.8 fC = 1 MHz - 2.5 ICC0(2) Supply current (Write) - 1.5 mA ICC1 Standby supply current - 1 µA VCC < 2.5 V -0.45 0.25 VCC V VCC < 2.5 V 0.75 VCC 6.5 V VCC < 2.5 V 0.75 VCC VCC + 0.6 ILI During tW, VCC ≤ 1.8 V Device not selected(3), VIN = VSS or VCC, VCC = 1.6 V or 1.7 V mA Input low voltage VIL (SCL, SDA, WC, Ei) (4) Input high voltage (SCL, SDA) VIH Input high voltage (WC, Ei) V (5) VOL Output low voltage IOL = 1 mA, VCC = 1.6 V or 1.7 V - 0.2 V 1. If the application uses the voltage range F device with 2.5 V ≤ VCC ≤ 5.5 V and -40 °C < TA < +85 °C, refer to Table 16 instead of this table. 2. Evaluated by characterization - Not tested in production. 3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). 4. Ei inputs should be tied to VSS (see Section 2.3 Chip enable (E2, E1, E0)) 5. Ei inputs should be tied to VCC (see Section 2.3 Chip enable (E2, E1, E0)) DS6638 - Rev 37 page 24/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Table 19. 400 kHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tQL1QL2(1) tF SDA (out) fall time 20(2) 300 ns tXH1XH2 tR Input signal rise time (3) (3) ns tXL1XL2 tF Input signal fall time (3) (3) ns tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(4) tDH Data out hold time 50 - ns tCLQV(5) tAA Clock low to next data valid (access time) - 900 ns tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tWLDL(1)(6) tSU:WC WC set up time (before the start condition) 0 - (1)(7) tHD:WC WC hold time (after the stop condition) 1 - Write time - 5 ms Pulse width ignored (input filter on SCL and SDA) - single glitch - 50 ns tDHWH Parameter μs tW tWR tNS(1) - 1. Evaluated by characterization - Not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. To avoid spurious start and stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 15. 6. WC=0 set up time condition to enable the execution of a WRITE command 7. WC=0 hold time condition to enable the execution of a WRITE command. DS6638 - Rev 37 page 25/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Table 20. 1 MHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 500 - ns tXH1XH2 tR Input signal rise time (1) (1) ns tXL1XL2 tF Input signal fall time (1) (1) ns tQL1QL2(2) tF SDA (out) fall time 20(3) 120 ns tDXCH tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(4) tDH Data out hold time 50 - ns tCLQV(5) tAA Clock low to next data valid (access time) - 450 ns tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tWLDL(2)(6) tSU:WC WC set up time (before the Start condition) 0 - µs (2)(7) tHD:WC WC hold time (after the Stop condition) 1 - µs Write time - 5 ms Pulse width ignored (input filter on SCL and SDA) - 50 ns tDHWH tW tWR tNS(2) - Parameter 1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. 2. Evaluated by characterization - Not tested in production. 3. With CL = 10 pF. 4. To avoid spurious start and stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 16. 6. WC=0 set up time condition to enable the execution of a WRITE command. 7. WC=0 hold time condition to enable the execution of a WRITE command. DS6638 - Rev 37 page 26/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Figure 15. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line Pull up resistor (kΩ) 100 VCC The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left Rb us 10 xC bu s 00 Here Rbus x Cbus= 120 ns 4 =4 Rbus I²C bus master SCL M24xxx SDA ns Cbus 1 10 30 100 1000 Bus line capacitor (pF) Figure 16. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz Bus line pull-up resistor (kΩ ) 100 10 Rbu s xC bus The Rbus x Cbus time constant must be below the 150 ns time constant line represented on the left = 15 0 ns 4 VCC Rbus I²C bus master SCL M24xxx SDA Here Rbus x Cbus = 120 ns Cbus 1 10 30 100 Bus line capacitor (pF) DS6638 - Rev 37 page 27/51 M24C64-W M24C64-R M24C64-F M24C64-DF DC and AC parameters Figure 17. AC waveforms Start condition Start Stop condition condition tXL1XL2 tXH1XH2 tCHCL tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX SDA tDXCH Change tCHDH tDHDL WC tDHWH tWLDL Stop condition Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS6638 - Rev 37 tCLQX Data valid tQL1QL2 Data valid page 28/51 M24C64-W M24C64-R M24C64-F M24C64-DF Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 WLCSP4 (CU) ultra thin package information This WLCSP4 is a 4-bump, 0.795 x 0.674 mm, 0.400 mm pitch, ultra thin wafer level chip scale package. Figure 18. WLCSP4 (CU) - Outline WLCSP4 package (package code A0Z7_c) bbb Z Back side coating thickness 0.025 mm Orientation reference Detail A D X e Y F E e F aaa Orientation reference (4X) A3 Wafer back side A A2 G Side view G Bump Side Bump A1 eee Z Z b (4X) Ø ccc M Z X Y Ø ddd M Z Seating plane Detail A Rotated 90 ° A0Z7_PTc_WLCSP4_ME_V1 1. 2. 3. DS6638 - Rev 37 Drawing is not to scale. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Bump position designation per JESD 95-1, SPP-010. page 29/51 M24C64-W M24C64-R M24C64-F M24C64-DF WLCSP4 (CU) ultra thin package information Table 21. WLCSP4 (CU) - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.285 0.315 0.345 0.0112 0.0124 0.0136 A1 - 0.115 - - 0.0045 - A2 - 0.175 - - 0.0069 - A3 (BSC) - 0.025 - - 0.0010 - b(2)(3) - 0.160 - - 0.0063 - D - 0.795 0.815 - 0.0313 0.0321 E - 0.674 0.694 - 0.0265 0.0273 e - 0.400 - - 0.0157 - F - 0.137 - - 0.0054 - G - 0.198 - - 0.0078 - aaa - - 0.110 - - 0.0043 bbb - - 0.110 - - 0.0043 ccc - - 0.110 - - 0.0043 ddd - - 0.060 - - 0.0024 eee - - 0.060 - - 0.0024 1. 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 9.1.1 WLCSP4 (CU) package footprint Figure 19. WLCSP4 (CU) - Recommended footprint 0.400 0.400 4x 0.160 A0Z7_PTc_WLCSP4_FP_V2 1. DS6638 - Rev 37 Dimensions are expressed in millimeters. page 30/51 M24C64-W M24C64-R M24C64-F M24C64-DF WLCSP5 (CS) package information 9.2 WLCSP5 (CS) package information This WLCSP is a 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale package. Figure 20. WLCSP5 - Outline Package WLCSP5 (package code 1C_d) bbb D Z e1 X Y 1 2 3 C Detail A E e2 e B A (4x) Orientation reference Wafer back side Orientation reference aaa A2 A Side view F G Bump side Bump Detail A rotated by 90° eee Ø ccc M Ø ddd M 1. 2. 3. DS6638 - Rev 37 A1 Z b (5X) Z X Y Z Z Seating plane 1Cd_WLCSP5_ME_V3 Drawing is not to scale. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Primary datum Z and seating plane are defined by the spherical crowns of the bump. page 31/51 M24C64-W M24C64-R M24C64-F M24C64-DF WLCSP5 (CS) package information Table 22. WLCSP5 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.455 0.545 0.635 0.0179 0.0215 0.0250 A1 - 0.190 - - 0.0075 - A2 - 0.355 - - 0.0140 - b(2) - 0.270 - - 0.0106 - D - 0.959 1.074 - 0.0378 0.0423 E - 1.073 1.168 - 0.0422 0.0460 e - 0.693 - - 0.0273 - e1 - 0.400 - - 0.0157 - e2 - 0.3465 - - 0.0136 - F - 0.280 - - 0.0110 - G - 0.190 - - 0.0075 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 9.2.1 WLCSP5 (CS) recommended footprint Figure 21. WLCSP5 - Recommended footprint 0.3465 0.693 0.400 1. DS6638 - Rev 37 1Cd_WLCSP_FP_V2 Dimensions are expressed in millimeters. page 32/51 M24C64-W M24C64-R M24C64-F M24C64-DF UFDFPN5 (DFN5) package information 9.3 UFDFPN5 (DFN5) package information UFDFPN5 is a 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package. Figure 22. UFDFPN5 - Outline Package UFDFN5 (package code A0UK) D k L Pin 1 Pin 1 b X E E1 Y D1 Top view (marking side) e L1 Bottom view (pads side) A A1 Side view 1. 2. 3. 4. A0UK_UFDFN5_ME_V3 Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from the orientation of the marking. When reading the marking, pin 1 is below the upper left package corner. Table 23. UFDFPN5 - Mechanical data Symbol millimeters inches Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 - 0.050 0.0000 - 0.0020 b(1) 0.175 0.200 0.225 0.0069 0.0079 0.0089 D 1.600 1.700 1.800 0.0630 0.0669 0.0709 D1 1.400 1.500 1.600 0.0551 0.0591 0.0630 E 1.300 1.400 1.500 0.0512 0.0551 0.0591 E1 0.175 0.200 0.225 0.0069 0.0079 0.0089 X - 0.200 - - 0.0079 - Y - 0.200 - - 0.0079 - e - 0.400 - - 0.0157 - L 0.500 0.550 0.600 0.0197 0.0217 0.0236 L1 - 0.100 - - 0.0039 - k - 0.400 - - 0.0157 - 1. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. DS6638 - Rev 37 page 33/51 M24C64-W M24C64-R M24C64-F M24C64-DF UFDFPN5 (DFN5) package information 9.3.1 UFDFPN5 recommended footprint Figure 23. UFDFPN5 - Recommended footprint Pin 1 0.400 0.600 0.200 0.200 0.200 0.200 0.400 1.600 1. DS6638 - Rev 37 Dimensions are expressed in millimeters. page 34/51 M24C64-W M24C64-R M24C64-F M24C64-DF UFDFPN8 (DFN8) package information 9.4 UFDFPN8 (DFN8) package information This UFDFPN is a 8-lead, 2 x 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package. Figure 24. UFDFPN8 - Outline D N A B Package UFDFN8 (package code ZW) A ccc C Pin #1 ID marking E A1 C eee C Seating plane Side view 2x aaa C 1 aaa C 2x 2 Top view D2 e 1 2 L3 Datum A b L1 L L3 Pin #1 ID marking E2 K e/2 L1 e Terminal tip L Detail “A” Even terminal ND-1 x e See Detail “A” Bottom view 1. 2. 3. 4. DS6638 - Rev 37 Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. page 35/51 M24C64-W M24C64-R M24C64-F M24C64-DF UFDFPN8 (DFN8) package information Table 24. UFDFPN8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee(3) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 9.4.1 UFDFPN8 recommended footprint Figure 25. UFDFPN8 - Recommended footprint 1.600 0.500 0.300 0.600 1.600 1.400 1. DS6638 - Rev 37 Dimensions are expressed in millimeters. page 36/51 M24C64-W M24C64-R M24C64-F M24C64-DF TSSOP8 package information 9.5 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 26. TSSOP8 – Outline D 8 Package TSSOP8 (package code 6P) 5 k E1 E A1 1 L L1 4 A2 A c 1. 6P_TSSOP8_ME_V3 e b Drawing is not to scale. Table 25. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1(3) 4.300 4.400 0.0177 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0181 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS6638 - Rev 37 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 37/51 M24C64-W M24C64-R M24C64-F M24C64-DF TSSOP8 package information 9.5.1 TSSOP8 recommended footprint Figure 27. TSSOP8 – Recommended footprint 1.55 0.65 0.40 2.35 5.80 7.35 1. DS6638 - Rev 37 6P_TSSOP8_FP_V2 Dimensions are expressed in millimeters. page 38/51 M24C64-W M24C64-R M24C64-F M24C64-DF SO8N package information 9.6 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 28. SO8N – Outline Package SO8N (package code O7) A2 h x 45˚ A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 E 1 L A1 L1 1. Drawing is not to scale. Table 26. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0030 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS6638 - Rev 37 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 39/51 M24C64-W M24C64-R M24C64-F M24C64-DF SO8N package information 9.6.1 SO8N recommended footprint Figure 29. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS6638 - Rev 37 Dimensions are expressed in millimeters. page 40/51 M24C64-W M24C64-R M24C64-F M24C64-DF WLCSP8 (CT) package information 9.7 WLCSP8 (CT) package information WLCSP8 is a 8 balls, 1.073 x 0.959 mm, 0.4 mm pitch, wafer level chip scale package. Figure 30. WLCSP8 - Outline Package WLCSP8 (package code “(V_d”) bbb Z D X e1 Y Detail A E Reference e e2 aaa A A2 (4X) Wafer back side Side view F Orientation G reference Bumps side Bump A1 eee Z Z b Ø ccc M Ø ddd M 1. 2. DS6638 - Rev 37 Z X Y Z Seating plane Detail A Rotated 90° (Vd_WLCSP8_ME_V1 Drawing is not to scale. Primary datum Z and seating plane are defined by the spherical crowns of the bump. page 41/51 M24C64-W M24C64-R M24C64-F M24C64-DF WLCSP8 (CT) package information Table 27. WLCSP8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.300 0.315 0.330 0.0118 0.0124 0.0130 A1 - 0.115 - - 0.0045 - A2 - 0.200 - - 0.0079 - b(2) - 0.160 - - 0.0063 - D - 1.073 1.093 - 0.0422 0.0430 E - 0.959 0.979 - 0.0378 0.0385 e - 0.693 - - 0.0273 - e1 - 0.800 - - 0.0315 - e2 - 0.400 - - 0.0157 - F - 0.133 - - 0.0052 - G - 0.137 - - 0.0054 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 9.7.1 WLCSP8 recommended footprint Figure 31. WLCSP8 - Recommended footprint 0.400 0.800 0.693 0.400 8 bumps x Ø 0.160 Orientation reference 1. DS6638 - Rev 37 Dimensions are expressed in millimetres. page 42/51 M24C64-W M24C64-R M24C64-F M24C64-DF Ordering information 10 Ordering information Table 28. Ordering information scheme Example: M24 C64 -D W MC 6 T P /T F Device type M24 = I2C serial access EEPROM Device function C64 = 64 Kbit (8192 x 8 bit) Device family Blank = Without identification page D = With identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.6 V or 1.7 V to 5.5 V Package(1) MN = SO8N (150 mil width) DW = TSSOP8 (169 mil width) MC = UFDFPN8 (DFN8) CT = 8-bump WLCSP MH = UFDFPN5 (DFN5) CS = 5-bump WLCSP CU = 4-bump WLCSP Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = RoHS compliant and halogen-free (ECOPACK2) Process(2) or Packing option /K or /T = Manufacturing technology code /12 = Packing 12 mm tape Option Blank = No back side coating F = Back side coating 1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants). 2. These process letters appear on the device package (marking) and on the shipment box. Contact your nearest ST Sales Office for further information. DS6638 - Rev 37 page 43/51 M24C64-W M24C64-R M24C64-F M24C64-DF Ordering information Table 29. Ordering information scheme (unsawn wafer) Example:(1) M24 C64 - F T W 20 I /90 Device type M24 = I2C serial access EEPROM Device function C64 = 64 Kbit (8192 x 8 bit) Operating voltage F = VCC = 1.7 V to 5.5 V Process T = F8H+ Delivery form W =Wafer (bare die) Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C 1. For all information concerning the M24C64 delivered in unsawn wafer, contact your nearest ST Sales Office. Note: For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS6638 - Rev 37 page 44/51 M24C64-W M24C64-R M24C64-F M24C64-DF Revision history Table 30. Document revision history Date Revision Changes Updated information concerning E2, E1, E0 for the WLCSP package: 14-Mar-2011 07-Apr-2011 22 23 • note under Figure 3: UFDFPN5 package connections • comment under Figure 7:Chip enableinputs connection • note 3 under Table 2: Device select code Updated MLP8 package data and Section 10: Part numberingAdded footnote (a) in Section 4.5: Memory addressing. Updated: 18-May-2011 24 • Figure3:UFDFPN5 package connections • Table 6:Absolute maximum ratings • Smalltextchanges Added: • Figure12:Memory cellcharacteristics Updated: 08-Sep-2011 • Table22: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dualflat no lead, 2 x 3 mm, data • Figure16:MaximumRbusvalueversus busparasitic capacitance Cbus) for an I2Cbus at maximumfrequencyfC= 1MHz • Figure6: I2CFastmode Plus (fC =1 MHz): maximumRbus value versus busparasiticcapacitance(Cbus). 25 Added tWLDL and tDHWH in: • Table17: 400 kHz ACcharacteristics • Table18: 1 MHzAC characteristics • Figure: Minor text changes. 16-Dec-2011 26 Updated Adimension in Table 25: WLCSP- 5-bump, 0.959 x1.073 mm, 0.4mmpitch wafer level chipscale packagemechanicaldata. Datasheet split into: • M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this datasheet) forstandard products (range 6), • M24C64-125 datasheet for automotive products (range 3). Added 8bump thin WLCSP. Updated • 28-Aug-2012 27 single supply voltage and number of Write cycles on cover page. • Section 2.1: Serial Clock (SCL) and Section 2.2: Serial Data (SDA). • Figure 8, Figure 11 • Section 5.1.5: ECC (Error Correction Code)and Write cycling and Section 5.1.6: Minimizing Write delays by polling on ACK. Section 5.1.2: Page Write. Section 5.1.4: Lock Identification Page (M24C64-D only). Section 5.1: Write operations • Table 13, Table 27 Added: • Table12 • note 1in Table 7 and Table 8: • Section 4.5: Device addressing, Moved Figure 10 to Section 5.1.1: Byte Write Removed note 2 in Table 17 18-Nov-2013 DS6638 - Rev 37 28 Updated: • Chapter 5.2.2: Current Address Read, page 45/51 M24C64-W M24C64-R M24C64-F M24C64-DF Date Revision Changes • Table14, Table 15, Table 25 • Figure 19, Figure 24., Figure 26 Added note (1) under Table 6. Removed note (3) in Table 3. Updated Figure 3, Figure 6, Table 15, Table 9, Table 17, Table 18 and Table 27. Table 18 and Figure 18 related to UFDFPN5 package. Section 5.1.5 Updated ECOPACK info on front page. Updated notes: 21-Jul-2014 29 • (1) on Table 7, Table 8, Table 14, Table 18, (8) on Table 15, (2) on Table 16, (3) on Table 27, (2) merged with (3) on Table 15, (1) on Table 9 Added: • supply voltage level specification on Cover page • package UFDFPN5 on Cover page Added: 12-Nov-2014 30 • note 2 on Table 14, note 2 on DW, MC and CS package on Table 27, note 1 on BN package on Table 27 • Figure 3 Updated: • Section1: Description, Chapter5.1.5, Table 14, Table 15, Table 16 • note 3 on Table 6, note 1 on Table 9, note 1 on Table 12, note 1 on Table 13, note 2 on Table 27 30-Jul-2015 31 Added WLCSP package. Updated Table 27. 18-Feb-2016 32 Updated Figure 4, Figure 18,Table 19 and added Table 2 22-Jun-2016 33 Added Reference to unsawn wafer inside cover page and added Table 28: Ordering information scheme (unsawn wafer) Added reference to DFN8 and DFN5 in: 13-Sep-2017 34 cover page figure, Figure 3, Section 9.1: UFDFPN5 (DFN5) package information, Section 9.2: UFDFPN8 (DFN8) package information and Table 29: Ordering information scheme. Added Figure 19. Updated Table 28 16-Nov-2017 35 Updated Table 29: Ordering information scheme 14-Mar-2018 36 Added Table 3:WLCSP 5-bumpsignals vs.bump position, Table 4: WLCSP 8-bump signals vs bump position Updated Figure 6: WLCSP 8-bump thin connections(M24C64- DFCT6TP/K) Updated: 28-Jul-2022 37 • Section Features, Section 2.2 Serial data (SDA), Section 3 Block diagram, Section 4.2 Stop condition, Section 9 Package information with all its subsection • added note in Figure 13 • Table 8, Table 9, Table 10, Table 13, Table 14, Table 15, Table 16. DC characteristics (M24C64-W), Table 17, Table 18, Table 19, Table 20, Table 28 Removed any reference to package PDIP8 DS6638 - Rev 37 page 46/51 M24C64-W M24C64-R M24C64-F M24C64-DF Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 Chip enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Write control (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5.1 5.2 6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 Write identification page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.4 Lock identification page (M24C64-D only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.5 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1.6 Minimizing write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.1 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.4 Read identification page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2.5 Read the lock status (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DS6638 - Rev 37 page 47/51 M24C64-W M24C64-R M24C64-F M24C64-DF Contents 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 9.1 WLCSP4 (CU) ultra thin package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.1.1 9.2 WLCSP5 (CS) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.2.1 9.3 SO8N recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 WLCSP8 (CT) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.7.1 10 TSSOP8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.6.1 9.7 UFDFPN8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.5.1 9.6 UFDFPN5 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.4.1 9.5 WLCSP5 (CS) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 UFDFPN5 (DFN5) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3.1 9.4 WLCSP4 (CU) package footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 WLCSP8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 DS6638 - Rev 37 page 48/51 M24C64-W M24C64-R M24C64-F M24C64-DF List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Signal names . . . . . . . . . . . . . . . . . . . . . . WLCSP 4-bump signal vs. bump position . . . WLCSP 5-bump signals vs. bump position . . WLCSP 8-bump signals vs. bump position . . Device select code . . . . . . . . . . . . . . . . . . . Most significant address byte. . . . . . . . . . . . Least significant address byte . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . Operating conditions (voltage range W) . . . . Operating conditions (voltage range R) . . . . . Operating conditions (voltage range F) . . . . . AC measurement conditions . . . . . . . . . . . . Input parameters . . . . . . . . . . . . . . . . . . . . Cycling performance . . . . . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . . DC characteristics (M24C64-W). . . . . . . . . . DC characteristics (M24C64-R) . . . . . . . . . . DC characteristics (M24C64-F, M24C64-DF) . 400 kHz AC characteristics . . . . . . . . . . . . . 1 MHz AC characteristics . . . . . . . . . . . . . . WLCSP4 (CU) - Mechanical data . . . . . . . . . WLCSP5 - Mechanical data. . . . . . . . . . . . . UFDFPN5 - Mechanical data . . . . . . . . . . . . UFDFPN8 - Mechanical data . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . WLCSP8 - Mechanical data. . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . Ordering information scheme (unsawn wafer) Document revision history . . . . . . . . . . . . . . DS6638 - Rev 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 4 . 4 10 11 11 19 20 20 20 20 21 21 21 22 23 24 25 26 30 32 33 36 37 39 42 43 44 45 page 49/51 M24C64-W M24C64-R M24C64-F M24C64-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Logic diagram. . . . . . . . . . . . . . . . . . . . . . . . 8-pin package connections, top view . . . . . . . . UFDFPN5 (DFN5) package connections . . . . . WLCSP 4-bump ultra thin package connections WLCSP 5-bump connections . . . . . . . . . . . . . WLCSP 8-bump connections . . . . . . . . . . . . . Chip enable inputs connection . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequences with WC = 0 (data write enabled) . Write mode sequences with WC = 1 (data write inhibited). Write cycle polling flowchart using ACK . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 13 15 16 21 Figure 15. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP4 (CU) - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP4 (CU) - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP5 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP5 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN5 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN5 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UFDFPN8 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS6638 - Rev 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 3 3 4 5 7 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 page 50/51 M24C64-W M24C64-R M24C64-F M24C64-DF IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS6638 - Rev 37 page 51/51