M24C64-FMH6TG

M24C64-W M24C64-R M24C64-F M24C64-DF 64-Kbit serial I²C bus EEPROM Datasheet - production data Features • Compatible with all I2C bus modes: – 1 MHz – 400 kHz – 100 kHz   PDIP8 (BN) • Memory array: – 64 Kbit (8 Kbyte) of EEPROM – Page size: 32 byte – Additional Write lockable page (M24C64-D order codes) TSSOP8 (DW) 169 mil width SO8 (MN) 150 mil width • Single supply voltage: – 1.7 V to 5.5 V over –40 °C / +85 °C – 1.6 V to 5.5 V over 0 °C / +85 °C • UFDFPN8 (MC) DFN8 - 2x3 mm UFDFPN5 (MH) DFN5 -1.7x1.4 mm Write: – Byte Write within 5 ms – Page Write within 5 ms • Random and sequential Read modes • Write protect of the whole memory array • Enhanced ESD/Latch-Up protection • More than 4 million Write cycles • More than 200-years data retention WLCSP (CS) Thin WLCSP (CT) Packages • PDIP8 ECOPACK2® • SO8 ECOPACK2® • TSSOP8 ECOPACK2® • UFDFPN ECOPACK2® WLCSP (CU) Unsawn wafer March 2018 This is information on a product in full production. • WLCSP ECOPACK2® • Unsawn wafer (each die is tested) DS6638 Rev 36 1/54 www.st.com Contents M24C64-W M24C64-R M24C64-F M24C64-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Chip Enable (E2, E1, E0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 5.2 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1.3 Write Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18 5.1.4 Lock Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . 18 5.1.5 ECC (Error Correction Code) and Write cycling . . . . . . . . . . . . . . . . . . 18 5.1.6 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 19 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.2.1 2/54 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Contents 5.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Read Identification Page (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Read the lock status (M24C64-D only) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 UFDFPN5 (DFN5) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 UFDFPN8 (DFN8) package information . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.5 PDIP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.6 WLCSP4 ultra thin package information . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.7 WLCSP5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.8 WLCSP8 thin package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DS6638 Rev 36 3/54 3 List of tables M24C64-W M24C64-R M24C64-F M24C64-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. 4/54 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 WLCSP 4-bump signals vs. bump position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP 5-bump signals vs. bump position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WLCSP 8-bump signals vs bump position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Most significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Least significant address byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (voltage range R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (voltage range F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics (M24C64-W, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M24C64-R device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M24C64-F, M24C64-DF, device grade 6) . . . . . . . . . . . . . . . . . . . . . . 29 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data. . . . . . . . . . . . 40 Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 WLCSP- 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Ordering information scheme (unsawn wafer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections, top view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 UFDFPN5 (DFN5) package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP 4 bump ultra thin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP 5-bump connections (M24C64-FCS6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WLCSP 8-bump thin connections (M24C64-DFCT6TP/K) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip enable inputs connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 16. Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline . 38 SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline . . . . . . . . . . . . . . . . . . . 40 Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm,wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 WLCSP 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale (M24C64-FCS6TP/K)- package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 WLCSP - 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DS6638 Rev 36 5/54 5 Description 1 M24C64-W M24C64-R M24C64-F M24C64-DF Description The M24C64 is a 64-Kbit I2C-compatible EEPROM (Electrically Erasable PROgrammable Memory) organized as 8 K × 8 bits. Over an ambient temperature range of -40 °C / +85 °C, the M24C64-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24C64-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M24C64-F and M24C64-DF can operate with a supply voltage from 1.7 V to 5.5 V ( the M24C64-F can also operate down to 1.6 V, under some restricting conditions). The M24C64-D offers an additional page, named the Identification Page (32 byte). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode. Figure 1. Logic diagram 9&&  (( 6'$ 0[[[ 6&/ :& 966 $,I Table 1. Signal names Signal name Function Direction E2, E1, E0 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections, top view (   9&& (   :& (   6&/ 966   6'$ $,I 1. See Section 9: Package information for package dimensions, and how to identify pin 1 6/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Description Figure 3. UFDFPN5 (DFN5) package connections 9&&  966  6'$  $%&' ;Ϯ ƚy,ϭy,Ϯ ƚ,> ƚ>, ^> ƚ>> ƚy>ϭy>Ϯ ^/Ŷ ƚ,> ƚy,ϭy,Ϯ ^ /ŶƉƵƚ ^ ƚy, ŚĂŶŐĞ ƚ>y ƚ,, ƚ,> t ƚ,t, ƚt>> ^ƚŽƉ ĐŽŶĚŝƚŝŽŶ ^ƚĂƌƚ ĐŽŶĚŝƚŝŽŶ ^> ^/Ŷ ƚt ƚ,, ƚ,> tƌŝƚĞĐLJĐůĞ ƚ,> ^> ƚ>Ys ^KƵƚ ƚ>Yy ĂƚĂǀĂůŝĚ ƚY>ϭY>Ϯ ĂƚĂǀĂůŝĚ /ϬϬϳϵϱŝ DS6638 Rev 36 33/54 53 Package information 9 M24C64-W M24C64-R M24C64-F M24C64-DF Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. For die information concerning the M24C64 delivered in unsawn wafer, please contact your nearest ST Sales Office. 9.1 UFDFPN5 (DFN5) package information Figure 18. UFDFPN5 – 1.7x1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package outline ' N / 3LQ 3LQ E ; ( ( < ' 7RSYLHZ PDUNLQJVLGH H / %RWWRPYLHZ SDGVVLGH $ $ 6LGHYLHZ $8.B0(B9 1. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from the orientation of the marking: when reading the marking, pin 1 is below the upper left package corner. Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 - 0.050 0.0000 - 0.0020 (2) 0.175 0.200 0.225 0.0069 0.0079 0.0089 D 1.600 1.700 1.800 0.0630 0.0669 0.0709 D1 1.400 1.500 1.600 0.0551 0.0591 0.0630 E 1.300 1.400 1.500 0.0512 0.0551 0.0591 E1 0.175 0.200 0.225 0.0069 0.0079 0.0089 X - 0.200 - - 0.0079 - b 34/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Package information Table 21. UFDFPN5 - 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max Y - 0.200 - - 0.0079 - e - 0.400 - - 0.0157 - L 0.500 0.550 0.600 0.0197 0.0217 0.0236 L1 - 0.100 - - 0.0039 - k - 0.400 - - 0.0157 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. Figure 19. UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead recommended footprint 3LQ         $8.B)3B9 1. Dimensions are expressed in millimeters. DS6638 Rev 36 35/54 53 Package information 9.2 M24C64-W M24C64-R M24C64-F M24C64-DF UFDFPN8 (DFN8) package information Figure 20. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package outline 3LQ,'PDUNLQJ  Ğ ď >ϭ >ϯ WŝŶϭ  Ϯ < >  Ϯ ĞĞĞ ϭ =:B0(H9 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. Table 22. UFDFPN8 – 2x3 mm, 0.55 thickness, ultra thin fine pitch dual flat package, no lead - package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - eee(2) 0.080 - - 0.0031 - - 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 36/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF 9.3 Package information TSSOP8 package information Figure 21.TSSOP8 – 3x4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package outline  ϴ ϱ Đ ϭ ϭ  ϰ ɲ > ϭ W Ϯ  >ϭ ď Ğ 76623$0B9 1. Drawing is not to scale. Table 23. TSSOP8 – 3 x 4.4 mm, 0.65 mm pitch, 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 CP - - 0.100 - - 0.0039 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DS6638 Rev 36 37/54 53 Package information 9.4 M24C64-W M24C64-R M24C64-F M24C64-DF SO8N package information Figure 22. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package outline HXƒ ! ! C CCC B E PP *$8*(3/$1( $ K  % %  ! , , 62$B9 1. Drawing is not to scale. Table 24. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package mechanical data Symbol inches(1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 38/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Package information Figure 23. SO8N – 3.9x4.9 mm, 8-lead plastic small outline, 150 mils body width, package recommended footprint   [  2B621B)3B9 1. Dimensions are expressed in millimeters. DS6638 Rev 36 39/54 53 Package information 9.5 M24C64-W M24C64-R M24C64-F M24C64-DF PDIP8 package information Figure 24. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package outline % B ! ! B ! , C E E! E" $  %  0$)0 " 1. Drawing is not to scale. 2. Not recommended for new designs. Table 25. PDIP8 – 8-pin plastic DIP, 0.25 mm lead frame, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 5.33 - - 0.2098 A1 0.38 - - 0.0150 - - A2 2.92 3.30 4.95 0.1150 0.1299 0.1949 b 0.36 0.46 0.56 0.0142 0.0181 0.0220 b2 1.14 1.52 1.78 0.0449 0.0598 0.0701 c 0.20 0.25 0.36 0.0079 0.0098 0.0142 D 9.02 9.27 10.16 0.3551 0.3650 0.4000 E 7.62 7.87 8.26 0.3000 0.3098 0.3252 E1 6.10 6.35 7.11 0.2402 0.2500 0.2799 e - 2.54 - - 0.1000 - eA - 7.62 - - 0.3000 - eB - - 10.92 - - 0.4299 L 2.92 3.30 3.81 0.1150 0.1299 0.1500 1. Values in inches are converted from mm and rounded to four decimal digits. 40/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF 9.6 Package information WLCSP4 ultra thin package information Figure 25. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm,wafer level chip scale package outline %DFNVLGHFRDWLQJ WKLFNQHVVPP ; ' EEE = 2ULHQWDWLRQ UHIHUHQFH 'HWDLO$ < H ) ( H ) DDD ; 2ULHQWDWLRQ UHIHUHQFH $ $ * $ :DIHUEDFNVLGH 6LGHYLHZ * %XPS6LGH %XPS $ HHH = = E; T FFF0 = ; < TGGG0 = 6HDWLQJSODQH 'HWDLO$ 5RWDWHGƒ $=%6&B0(B9 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.285 0.315 0.345 0.0112 0.0124 0.0136 A1 - 0.115 - - 0.0045 - A2 - 0.175 - - 0.0069 - A3 (BSC) - 0.025 - - 0.0010 - b(2) (3) - 0.160 - - 0.0063 - D - 0.795 0.815 - 0.0313 0.0321 E - 0.674 0.694 - 0.0265 0.0273 e - 0.400 - - 0.0157 - F - 0.137 - - 0.0054 - G - 0.198 - - 0.0078 - aaa - - 0.110 - - 0.0043 DS6638 Rev 36 41/54 53 Package information M24C64-W M24C64-R M24C64-F M24C64-DF Table 26. Ultra Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package mechanical data (continued) bbb - - 0.110 - - 0.0043 ccc - - 0.110 - - 0.0043 ddd - - 0.060 - - 0.0024 eee - - 0.060 - - 0.0024 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Figure 26. Thin WLCSP- 4-bump, 0.795 x 0.674 mm, wafer level chip scale package recommended footprint H H [ E $=%6&B)3B9 1. Dimensions are expressed in millimeters. 42/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF 9.7 Package information WLCSP5 package information Figure 27. WLCSP 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale (M24C64-FCS6TP/K)- package outline EEE ' = H ; <    & H 'HWDLO$ ( H % $ 2ULHQWDWLRQ UHIHUHQFH DDD [ 2ULHQWDWLRQ UHIHUHQFH $ ) * $ :DIHUEDFNVLGH 6LGHYLHZ %XPSVLGH %XPS 'HWDLO$ URWDWHGE\ƒ HHH = $ = 6HDWLQJSODQH E ; ‘FFF0 ‘GGG0 = ;< = &GB0(B9 1. Drawing is not to scale. 2. The index on the wafer back side (circle) is above the index of the bump side (triangle/arrow). DS6638 Rev 36 43/54 53 Package information M24C64-W M24C64-R M24C64-F M24C64-DF Table 27. WLCSP- 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.455 0.545 0.645 0.0179 0.0215 0.0254 A1 - 0.190 - - 0.0075 - A2 - 0.355 - - 0.0140 - (2) - 0.270 - - 0.0106 - D - 0.959 1.074 - 0.0378 0.0423 E - 1.073 1.168 - 0.0422 0.0460 e - 0.693 - - 0.0273 - e1 - 0.400 - - 0.0157 - e2 - 0.3465 - - 0.0136 - F - 0.280 - - 0.0110 - G - 0.190 - - 0.0075 - aaa - - 0.110 - - 0.0043 bbb - - 0.110 - - 0.0043 b 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 28. WLCSP - 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale recommended footprint    & H H % $ H &GB)3B9 1. Dimensions are expressed in millimeters. 44/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF 9.8 Package information WLCSP8 thin package information Figure 29. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package outline EEE = ' ; H < 'HWDLO$ ( H H DDD 5HIHUHQFH $ $ ; 6LGHYLHZ :DIHUEDFNVLGH ) 2ULHQWDWLRQ * UHIHUHQFH %XPSVVLGH %XPS $ HHH = = E Œ CCCŒ DDD- 6HDWLQJSODQH : 89 : 'HWDLO$ 5RWDWHGƒ 9GB0(B9 1. Drawing is not to scale. 2. Primary datum Z and seating plane are defined by the spherical crowns of the bump. DS6638 Rev 36 45/54 53 Package information M24C64-W M24C64-R M24C64-F M24C64-DF Table 28. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.300 0.315 0.330 0.0118 0.0124 0.0130 A1 - 0.115 - - 0.0045 - A2 - 0.200 - - 0.0079 - (2) - 0.160 - - 0.0063 - D - 1.073 1.093 - 0.0422 0.0430 E - 0.959 0.979 - 0.0378 0.0385 e - 0.693 - - 0.0273 - e1 - 0.800 - - 0.0315 - e2 - 0.400 - - 0.0157 - F - 0.133 - - 0.0052 - G - 0.137 - - 0.0054 - aaa - - 0.110 - - 0.0043 bbb - - 0.110 - - 0.0043 ccc - - 0.110 - - 0.0043 ddd - - 0.060 - - 0.0024 eee - - 0.060 - - 0.0024 b 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 30. Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package recommended footprint PP PP PP PP EXPSV[‘PP 2ULHQWDWLRQ UHIHUHQFH 9GB)3B9 1. Dimensions are expressed in millimeters. 46/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF 10 Ordering information Ordering information Table 29. Ordering information scheme Example: M24C64 -D W MC 6 T P /P F Device type M24 = I2C serial access EEPROM Device function C64 = 64 Kbit (8192 x 8 bit) Device family Blank = Without Identification page D = With Identification page Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.7 V to 5.5 V Package BN = PDIP8(1) MN = SO8 (150 mil width)(2) DW = TSSOP8 (169 mil width)(2) MC = UFDFPN8 (DFN8)(2) MH = UFDFPN5 (DFN5)(2) CS = 5-bump WLCSP(2) CT = 8-bump WLCSP(2) CU = 4-bump WLCSP Device grade 6 = Industrial: device tested with standard test flow over –40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = ECOPACK2® Process(3) or Packing option /P or /K or /T = Manufacturing technology code /12 = Packing 12 mm tape Option Blank = No Back Side Coating F = Back Side Coating (WLCSP height = 0.345mm) 1. RoHS-compliant (ECOPACK1®) 2. ECOPACK2® ((RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants)) 3. The process letter is used only when ordering WLCSP packages, the process letter is not specified when ordering any other package. These process letters appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office for further information. DS6638 Rev 36 47/54 53 Ordering information M24C64-W M24C64-R M24C64-F M24C64-DF Table 30. Ordering information scheme (unsawn wafer)(1) (2) Example: M24C64 - F T W 20 I /90 Device type M24 = I2C serial access EEPROM Device function C64 = 64 Kbit (8192 x 8 bit) Operating voltage F = VCC = 1.7 V to 5.5 V Process T = F8H+ Delivery form W = Wafer (bare die) Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C 1. For all information concerning the M24C64 delivered in unsawn wafer, please contact your nearest ST Sales Office. 2. Unsawn wafer in preview. 48/54 DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Ordering information Engineering samples Parts marked as ES or E are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences deriving from such use. In no event, will ST be liable for the customer using of these engineering samples in production. ST’s quality department must be contacted prior to any decision to use these engineering samples to run qualification activity. DS6638 Rev 36 49/54 53 Revision history 11 M24C64-W M24C64-R M24C64-F M24C64-DF Revision history Table 31. Document revision history Date Changes 14-Mar-2011 22 Updated information concerning E2, E1, E0 for the WLCSP package: – note under Figure 3: UFDFPN5 package connections – comment under Figure 7: Chip enable inputs connection – note 3 under Table 2: Device select code 07-Apr-2011 23 Updated MLP8 package data and Section 10: Part numberingAdded footnote (a) in Section 4.5: Memory addressing. 24 Updated: – Figure 3: UFDFPN5 package connections – Table 6: Absolute maximum ratings – Small text changes Added: – Figure 12: Memory cell characteristics 08-Sep-2011 25 Updated: – Table 22: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, 2 x 3 mm, data – Figure 16: Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz – Figure 6: I2C Fast mode Plus (fC = 1 MHz): maximum Rbus value versus bus parasitic capacitance (Cbus). Added tWLDL and tDHWH in: – Table 17: 400 kHz AC characteristics – Table 18: 1 MHz AC characteristics – Figure : Minor text changes. 16-Dec-2011 26 Updated A dimension in Table 25: WLCSP- 5-bump, 0.959 x 1.073 mm, 0.4 mm pitch wafer level chip scale package mechanical data. 18-May-2011 50/54 Revision DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Revision history Table 31. Document revision history (continued) Date Revision Changes Datasheet split into: – M24C64-DF, M24C64-W, M24C64-R,M24C64-F (this datasheet) for standard products (range 6), 28-Aug-2012 18-Nov-2013 27 28 – M24C64-125 datasheet for automotive products (range 3). Added 8-bump thin WLCSP. Updated single supply voltage and number of Write cycles on cover page. Updated Section 2.1: Serial Clock (SCL) and Section 2.2: Serial Data (SDA). Updated Figure 8: Block diagram. Added Section 4.5: Device addressing. Section 5.1: Write operations move to Section 5: Instructions and updated. Moved Figure 10: Write mode sequences with WC = 0 (data write enabled) to Section 5.1.1: Byte Write. Section 5.1.2: Page Write: changed address bits to A15/A5 and updated Figure 11. Case of locked Write identification Page removed from Section 5.1.4: Lock Identification Page (M24C64-D only). Updated Section 5.1.5: ECC (Error Correction Code) and Write cycling and move Figure 12: Write cycle polling flowchart using ACK to Section 5.1.6: Minimizing Write delays by polling on ACK. Added note 1 in Table 7: Operating conditions (voltage range W) and Table 8: Operating conditions (voltage range R). Added Table 12 and updated Table 13: Memory cell data retention. Removed note 2 in Table 17: 400 kHz AC characteristics for tQL1QL2, tWLDL, tDHWH, and tNS. Table 27: Ordering information scheme: removed ambient operating temperature for device grade 5 and added Note 3. to MLP8 and WLCSP packages. Added text in Chapter 5.2.2: Current Address Read Updated note (1) under Table 6: Absolute maximum ratings. Removed note (3) in Table 3: Device select code. Updated notes below Table 14: DC characteristics (M24C64-W, device grade 6) and Table 15: DC characteristics (M24C64-R device grade 6) Renamed Figure 19 and Table 25. Updated captions above Figure 26 and Figure 24. DS6638 Rev 36 51/54 53 Revision history M24C64-W M24C64-R M24C64-F M24C64-DF Table 31. Document revision history (continued) Date Changes 29 Updated Figure 3, Figure 6, Table 15, Table 9, Table 17, Table 18 and Table 27. Updated ECOPACK info on front page. Updated notes: – (1) on Table 7, Table 8, Table 14, Table 18 – (2) merged with (3) on Table 15 – (8) on Table 15 – (2) on Table 16 – (3) on Table 27 Added: – note (1) on Table 9 Added: – supply voltage level specification on Cover page. – package UFDFPN5 on Cover page – Table 18 and Figure 18 related to UFDFPN5 package. – Note (1) on Section 5.1.5 12-Nov-2014 30 Added: – note 2 on Table 14 – note 2 on DW, MC and CS package on Table 27 – note 1on BN package on Table 27 – Figure 3 Updated: – Section 1: Description – Chapter 5.1.5 – note 3 on Table 6 – note 1 on Table 9 – note 1 on Table 12 – note 1 on Table 13 – ICC0 max value and note 5 on Table 14 – ICC0 max value on Table 15 – ICC0 max value on Table 16 – note 2 on Table 27 30-Jul-2015 31 Added WLCSP package. Updated Table 27. 18-Feb-2016 32 Updated Figure 4, Figure 18,Table 19 and added Table 2 22-June-2016 33 Added Reference to unsawn wafer inside cover page and added Table 28: Ordering information scheme (unsawn wafer) 21-Jul-2014 52/54 Revision DS6638 Rev 36 M24C64-W M24C64-R M24C64-F M24C64-DF Revision history Table 31. Document revision history (continued) Date Revision Changes 13-Sep-2017 34 Added reference to DFN8 and DFN5 in: cover page figure, Figure 3: UFDFPN5 (DFN5) package connections, Section 9.1: UFDFPN5 (DFN5) package information, Section 9.2: UFDFPN8 (DFN8) package information and Table 29: Ordering information scheme. Added Figure 19: UFDFPN5 - 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package, no lead recommended footprint. Updated Section Table 28.: Thin WLCSP- 8-bump, 1.073 x 0.959 mm, wafer level chip scale package mechanical data 16-Nov-2017 35 Updated Table 29: Ordering information scheme 36 Added Table 3: WLCSP 5-bump signals vs. bump position, Table 4: WLCSP 8-bump signals vs bump position Updated Figure 6: WLCSP 8-bump thin connections (M24C64DFCT6TP/K) 14-Mar-2018 DS6638 Rev 36 53/54 53 M24C64-W M24C64-R M24C64-F M24C64-DF IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved 54/54 DS6638 Rev 36