M24LR16E-RMC6T/2

M24LR16E-R Dynamic NFC/RFID tag IC with 16-Kbit EEPROM, energy harvesting, I²C bus and ISO 15693 RF interface Datasheet - production data SO8 (MN) 150 mils width • From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands TSSOP8 (DW) • Internal tuning capacitance: 27.5pF • 64-bit unique identifier (UID) • Read Block & Write (32-bit blocks) Digital output pin UFDFPN8 (MC) • User configurable pin: RF write in progress or RF busy mode Sawn wafer on UV tape 2 x 3 mm Energy harvesting • Analog pin for energy harvesting • 4 sink current configurable ranges Features • Belonging to ST25 family, which includes all NFC/RF ID tag and reader products from ST I2C interface Temperature range: • from -40°C up to 85°C Memory 2 • 16-Kbit EEPROM organized into: – 2048 bytes in I2C mode – 512 blocks of 32 bits in RF mode • Two-wire I C serial interface supports 400 kHz protocol • Single supply voltage:1.8 V to 5.5 V • Write time – I2C: 5 ms (max.) – RF: 5.75 ms including the internal Verify time • Byte and Page Write (up to 4 bytes) • Random and Sequential read modes • Self-timed programming cycle • Automatic address incrementing • I²C timeout • Write cycling enduramce: – 1 million write cycles at 25°C – 150k write cycles at 85°C Contactless interface • More than 40-year data retention • ISO 15693 and ISO 18000-3 mode 1 compatible • Multiple password protection in RF mode • Enhanced ESD/latch-up protection • Single password protection in I2C mode • 13.56 MHz ±7k Hz carrier frequency • To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding August 2017 This is information on a product in full production. Package: • ECOPACK2® (RoHS compliant and Halogenfree) DocID018932 Rev 14 1/148 www.st.com Contents M24LR16E-R Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 RF Write in progress / RF Busy (RF WIP/BUSY) . . . . . . . . . . . . . . . . . . . 15 2.4 Energy harvesting analog output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 Device reset in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.1 2.7.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.3 Device reset in I²C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 M24LR16E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 4.2 M24LR16E-R block security in I²C mode (I2C_Write_Lock bit area) . . . . 27 4.3 Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4 5 2/148 Example of the M24LR16E-R security protection in RF mode . . . . . . . 26 4.3.1 RF WIP/BUSY pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.2 Energy harvesting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.3 FIELD_ON indicator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.4 Configuration byte access in I²C and RF modes . . . . . . . . . . . . . . . . . . 30 4.3.5 Control register access in I²C or RF mode . . . . . . . . . . . . . . . . . . . . . . 30 ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 I2C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID018932 Rev 14 M24LR16E-R Contents 5.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 I²C timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5.1 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.8 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.10 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 37 5.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.16 M24LR16E-R I2C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.16.1 I2C present password command description . . . . . . . . . . . . . . . . . . . . . 40 5.16.2 I2C write password command description . . . . . . . . . . . . . . . . . . . . . . . 41 6 M24LR16E-R memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.1 RF communication and energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . 43 7.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3 Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3.1 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3.2 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.3.3 Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 Communication signal from VCD to M24LR16E-R . . . . . . . . . . . . . . . . 46 9 Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.2 Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3 VCD to M24LR16E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 DocID018932 Rev 14 3/148 Contents M24LR16E-R 9.4 10 11 Communication signal from M24LR16E-R to VCD . . . . . . . . . . . . . . . . 53 10.1 Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.2 Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1 11.2 12 Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.1.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.2.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 M24LR16E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1 12.2 12.3 12.4 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.2.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.3.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.4.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 12.4.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13 Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 14 Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 15 Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.1 16 4/148 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 M24LR16E-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DocID018932 Rev 14 M24LR16E-R 17 18 19 M24LR16E-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.1 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.2 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.3 Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 17.4 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.1 Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.2 Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 68 18.3 Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 19.1 20 21 Contents Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 20.1 Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 20.2 Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 21.1 Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 22 Request processing by the M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . 75 23 Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26 25.1 t1: M24LR16E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 25.3 t3: VCD new request delay when no response is received from the M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DocID018932 Rev 14 5/148 Contents M24LR16E-R 26.3 Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 26.4 Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 26.5 Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 26.6 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 26.7 Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 26.8 Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 26.9 Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 26.14 Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 26.15 Lock-sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 26.16 Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 26.17 Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 26.18 Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 26.19 Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 26.20 Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 26.23 ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 26.24 WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 26.25 WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 26.26 SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 26.27 CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 27 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 28 I2C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 29 Write cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 30 RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 31 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6/148 DocID018932 Rev 14 M24LR16E-R 32 Contents 31.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 31.2 UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 31.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 142 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Appendix B CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 145 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DocID018932 Rev 14 7/148 List of tables M24LR16E-R List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. 8/148 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read / Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M24LR16E-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 M24LR16E-R sector security protection after a valid presentation of password 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Configuration byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 EH_enable bit value after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 M24LR16E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 M24LR16E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 73 Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Stay Quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 84 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 84 Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 85 Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 86 Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 DocID018932 Rev 14 M24LR16E-R Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. List of tables Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 89 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 90 Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 91 Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 92 Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Lock AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 96 Write DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 97 Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Get System Info response format when Protocol_extension_flag = 0 and Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Get System Info response format when Protocol_extension_flag = 1 and Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . 100 Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . 101 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . 102 Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . 103 Write-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . 103 Lock-sector request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Lock-sector response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 104 Lock-sector response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 106 Present-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . 106 Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 108 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . 108 Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Fast Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 112 Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 DocID018932 Rev 14 9/148 List of tables Table 98. Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. 10/148 M24LR16E-R Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 113 Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Initiate Initiated response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ReadCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ReadCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ReadCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 WriteEHCfg request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 WriteEHCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 117 WriteEHCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 WriteDOCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 WriteDOCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 119 WriteDOCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 SetRstEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 SetRstEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . 120 SetRstEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 CheckEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 CheckEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 121 CheckEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 I2C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 I2C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 I2C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Write cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Ordering and marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DocID018932 Rev 14 M24LR16E-R List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 34 Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 36 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 I2C present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I2C write password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 0, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 1, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Logic 0, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Logic 1, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Start of frame, high data rate, one subcarrier, fast commands. . . . . . . . . . . . . . . . . . . . . . 57 Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Start of frame, low data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 58 Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 End of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 End of frame, high data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 59 End of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 59 End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 M24LR16E-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DocID018932 Rev 14 11/148 List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. 12/148 M24LR16E-R M24LR16E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 M24LR16E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 74 Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 M24LR16 RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . . 82 Stay Quiet frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . 83 Read Single Block frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . 85 Write Single Block frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . 86 M24LR16 RF-Busy management following Write command . . . . . . . . . . . . . . . . . . . . . . . 87 M24LR16 RF-Wip management following Write command . . . . . . . . . . . . . . . . . . . . . . . . 88 Read Multiple Block frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . 90 Select frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . . . 91 Reset to Ready frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . 92 Write AFI frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . 94 Lock AFI frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . 95 Write DSFID frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 97 Lock DSFID frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . . . . . . 98 Get System Info frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . 100 Get Multiple Block Security Status frame exchange between VCD and M24LR16E-R . . 102 Write-sector Password frame exchange between VCD and M24LR16E-R . . . . . . . . . . . 103 Lock-sector frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 105 Present-sector Password frame exchange between VCD and M24LR16E-R . . . . . . . . . 107 Fast Read Single Block frame exchange between VCD and M24LR16E-R. . . . . . . . . . . 109 Fast Initiate frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 111 Fast Read Multiple Block frame exchange between VCD and M24LR16E-R . . . . . . . . . 113 Initiate frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . . . 115 ReadCfg frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . . . 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 WriteEHCfg frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . . 118 WriteDOCfg frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . . . . . 119 SetRstEHEn frame exchange between VCD and M24LR16E-R . . . . . . . . . . . . . . . . . . . 121 CheckEHEn frame exchange between VCD and M24LR16E-R. . . . . . . . . . . . . . . . . . . . 122 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 ASK modulated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Vout min vs. Isink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Range 11 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Range 10 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Range 01 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Range 00 domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 135 SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DocID018932 Rev 14 M24LR16E-R 1 Description Description The M24LR16E-R device is a Dynamic NFC/RFID tag IC with dual-interface, electrically erasable programmable memory (EEPROM). It features an I2C interface and can be operated from a VCC power supply. It is also a contactless memory powered by the received carrier electromagnetic wave. The M24LR16E-R is organized as 2048 × 8 bits in the I2C mode and as 512 × 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode. The M24LR16E-R also features an energy harvesting analog output, as well as a userconfigurable digital output pin toggling during either RF write in progress or RF busy mode. Figure 1. Logic diagram 9 && 9RXW 6&/ 6'$ $& 0/5(5 $& 5):,3 %86< 9 66 069 I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR16E-R is accessed via the 13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modulation (ASK: amplitude shift keying). When connected to an antenna, the operating power is derived from the RF energy and no external power supply is required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding mode. Outgoing data are generated by the M24LR16E-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR16E-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The DocID018932 Rev 14 13/148 147 Description M24LR16E-R M24LR16E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz. The M24LR16E-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface. The M24LR16E-R provides an Energy harvesting mode on the analog output pin Vout. When the Energy harvesting mode is activated, the M24LR16E-R can output the excess energy coming from the RF field on the Vout analog pin. In case the RF field strength is insufficient or when Energy harvesting mode is disabled, the analog output pin Vout goes into high-Z state and Energy harvesting mode is automatically stopped. The M24LR16E-R features a user configurable digital out pin RF WIP/BUSY that can be used to drive a micro controller interrupt input pin (available only when the M24LR16E-R is correctly powered on the Vcc pin). When configured in the RF write in progress mode (RF WIP mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF internal write operation. When configured in the RF busy mode (RF BUSY mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF command progress. The RF WIP/BUSY pin is an open drain output and must be connected to a pull-up resistor. Table 1. Signal names Signal name Function Direction Vout Energy harvesting Output Analog output SDA Serial Data I/O SCL Serial Clock Input AC0, AC1 Antenna coils I/O VCC Supply voltage - RF WIP/BUSY Digital signal Digital output VSS Ground - Figure 2. 8-pin package connections 9RXW   9&& $&   5):,3%86< $&   6&/ 966   6'$ 069 1. See Section 31 for package dimensions, and how to identify pin-1. 14/148 DocID018932 Rev 14 M24LR16E-R Signal descriptions 2 Signal descriptions 2.1 Serial clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial data (SDA) This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). 2.3 RF Write in progress / RF Busy (RF WIP/BUSY) This configurable output signal is used either to indicate that the M24LR16E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR16E-R is powered by the Vcc pin. It is an open drain output and a pull up resistor must be connected from RF WIP/BUSY to VCC. 2.4 Energy harvesting analog output (Vout) This analog output pin is used to deliver the analog voltage Vout available when the Energy harvesting mode is enabled and the RF field strength is sufficient. When the Energy harvesting mode is disabled or the RF field strength is not sufficient, the energy harvesting analog voltage output Vout is in High-Z state. 2.5 Antenna coil (AC0, AC1) These inputs are used to connect the device to an external coil exclusively. It is advised not to connect any other DC or AC path to AC0 or AC1. When correctly tuned, the coil is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1 protocols. 2.5.1 Device reset in RF mode To ensure a proper reset of the RF circuitry, the RF field must be turned off (100% modulation) for a minimum tRF_OFF period of time. DocID018932 Rev 14 15/148 147 Signal descriptions 2.6 M24LR16E-R VSS ground VSS is the reference for the VCC supply voltage and Vout analog output voltage. 2.7 Supply voltage (VCC) This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allows the external voltage applied on VCC to supply the M24LR16E-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the VCC pin. 2.7.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 119). To maintain a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal I²C write cycle (tW). 2.7.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs. 2.7.3 Device reset in I²C mode In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any I²C instruction until VCC has reached the power-on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 119). When VCC passes over the POR threshold, the device is reset and enters the Standby power mode. However, the device must not be accessed until VCC has reached a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 2.7.4 Power-down conditions During power-down (continuous decay of VCC), the device must be in Standby power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). 16/148 DocID018932 Rev 14 M24LR16E-R Signal descriptions "USLINEPULL UPRESISTOR K Figure 3. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus)  2 BU S §  (ERE2BUS §#BUSNS 4HE2X#TIMECONSTANT BUS BUS MUSTBEBELOWTHENS TIMECONSTANTLINEREPRESENTED ONTHELEFT 6## # BU S  2BUS  N K½ S )£#BUS MASTER 3#, -XXX 3$!  P&   "USLINECAPACITORP& #BUS  AIB Figure 4. I2C bus protocol 6&/ 6'$ 6'$ ,QSXW 6WDUW FRQGLWLRQ 6'$ &KDQJH 6WRS FRQGLWLRQ 6&/       6'$ $&. 06% 6WDUW FRQGLWLRQ 6&/       6'$ 06% $&. 6WRS FRQGLWLRQ -36 DocID018932 Rev 14 17/148 147 Signal descriptions M24LR16E-R Table 2. Device select code Device type identifier(1) Chip Enable address RW Device select code b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2(2) 1 1 RW 1. The most significant bit, b7, is sent first. 2. E2 is not connected to any external pin. It is however used to address the M24LR16E-R as described in Section 3 and Section 4. Table 3. Address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 b1 b0 Table 4. Address least significant byte b7 18/148 b6 b5 b4 DocID018932 Rev 14 b3 b2 M24LR16E-R User memory organization The M24LR16E-R is divided into 16 sectors of 32 blocks of 32 bits, as shown in Table 5. Figure 6 shows the memory sector organization. Each sector can be individually readand/or write-protected using a specific password command. Read and write operations are possible if the addressed data are not in a protected sector. The M24LR16E-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user and its value is written by ST on the production line. The M24LR16E-R includes an AFI register that stores the application family identifier, and a DSFID register that stores the data storage family identifier used in the anticollision algorithm. The M24LR16E-R has four 32-bit blocks that store an I2C password plus three RF password codes. Figure 5. Circuit diagram 9RXW 5RZGHFRGHU 3 User memory organization $& ((3520 5):,3%86< /DWFK 5) /RJLF , & 6&/ 6'$ $& 5)9&& 3RZHUPDQDJHPHQW &RQWDFW9&& 9&& 966 069 DocID018932 Rev 14 19/148 147 User memory organization M24LR16E-R Figure 6. Memory sector organization 6HFWRUVHFXULW\ VWDWXV 6HFWRU $UHD     .ELW((3520VHFWRU .ELW((3520VHFWRU .ELW((3520VHFWRU .ELW((3520VHFWRU ELWV     .ELW((3520VHFWRU .ELW((3520VHFWRU .ELW((3520VHFWRU .ELW((3520VHFWRU ELWV ,ð&SDVVZRUG 5)SDVVZRUG 5)SDVVZRUG 5)SDVVZRUG ELW'6),' ELW$), ELW8,' ELWFRQILJXUDWLRQ 6\VWHP ELW,ð&:ULWH/RFNBELW ELW666 6\VWHP 6\VWHP ELWV ELWV ELWV ELWV ELWV ELWV 6\VWHP 6\VWHP 6\VWHP 6\VWHP 6\VWHP 6\VWHP 069 Sector details The M24LR16E-R user memory is divided into 16 sectors. Each sector contains 1024 bits. The protection scheme is described in Section 4: System memory area. In RF mode, a sector provides 32 blocks of 32 bits. Each read and write access is done by block. Read and write block accesses are controlled by a Sector Security Status byte that defines the access rights to the 32 blocks contained in the sector. If the sector is not protected, a Write command updates the complete 32 bits of the selected block. In I2C mode, a sector provides 128 bytes that can be individually accessed in Read and Write modes. When protected by the corresponding I2C_Write_Lock bit, the entire sector is write-protected. To access the user memory, the device select code used for any I2C command must have the E2 Chip Enable address at 0. 20/148 DocID018932 Rev 14 M24LR16E-R User memory organization Table 5. Sector details Sector number 0 RF block address I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0] 0 0 user user user user 1 4 user user user user 2 8 user user user user 3 12 user user user user 4 16 user user user user 5 20 user user user user 6 24 user user user user 7 28 user user user user 8 32 user user user user 9 36 user user user user 10 40 user user user user 11 44 user user user user 12 48 user user user user 13 52 user user user user 14 56 user user user user 15 60 user user user user 16 64 user user user user 17 68 user user user user 18 72 user user user user 19 76 user user user user 20 80 user user user user 21 84 user user user user 22 88 user user user user 23 92 user user user user 24 96 user user user user 25 100 user user user user 26 104 user user user user 27 108 user user user user 28 112 user user user user 29 116 user user user user 30 120 user user user user 31 124 user user user user DocID018932 Rev 14 21/148 147 User memory organization M24LR16E-R Table 5. Sector details (continued) Sector number 1 ... 22/148 RF block address I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0] 32 128 user user user user 33 132 user user user user 34 136 user user user user 35 140 user user user user 36 144 user user user user 37 148 user user user user 38 152 user user user user 39 156 user user user user ... ... ... ... ... ... ... ... ... ... ... ... DocID018932 Rev 14 M24LR16E-R User memory organization Table 5. Sector details (continued) Sector number 15 RF block address I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0] 480 1920 user user user user 481 1924 user user user user 482 1928 user user user user 483 1932 user user user user 484 1936 user user user user 485 1940 user user user user 486 1944 user user user user 487 1948 user user user user 488 1952 user user user user 489 1956 user user user user 490 1960 user user user user 491 1964 user user user user 492 1968 user user user user 493 1972 user user user user 494 1976 user user user user 495 1980 user user user user 496 1984 user user user user 497 1988 user user user user 498 1992 user user user user 499 1996 user user user user 500 2000 user user user user 501 2004 user user user user 502 2008 user user user user 503 2012 user user user user 504 2016 user user user user 505 2020 user user user user 506 2024 user user user user 507 2028 user user user user 508 2032 user user user user 509 2036 user user user user 510 2040 user user user user 511 2044 user user user user DocID018932 Rev 14 23/148 147 System memory area M24LR16E-R 4 System memory area 4.1 M24LR16E-R block security in RF mode The M24LR16E-R provides a special protection mechanism based on passwords. In RF mode, each memory sector of the M24LR16E-R can be individually protected by one out of three available passwords, and each sector can also have Read/Write access conditions set. Each memory sector of the M24LR16E-R is assigned with a Sector security status byte including a Sector Lock bit, two Password Control bits and two Read/Write protection bits, as shown in Table 7. Table 6 describes the organization of the Sector security status byte, which can be read using the Read Single Block and Read Multiple Block commands with the Option_flag set to 1. On delivery, the default value of the SSS bytes is set to 00h. Table 6. Sector security status byte area I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0] E2 = 1 0 SSS 3 SSS 2 SSS 1 SSS 0 E2 = 1 4 SSS 7 SSS 6 SSS 5 SSS 4 E2 = 1 8 SSS 11 SSS 10 SSS 9 SSS 8 E2 = 1 12 SSS 15 SSS 14 SSS 13 SSS 12 Table 7. Sector security status byte organization b7 b6 b5 0 0 0 b4 b3 Password control bits b2 b1 b0 Read / Write protection bits Sector Lock When the Sector Lock bit is set to 1, for instance by issuing a Lock-sector command, the two Read/Write protection bits (b1, b2) are used to set the Read/Write access of the sector as described in Table 8. Table 8. Read / Write protection bit setting 24/148 Sector access Sector access when password presented when password not presented Sector Lock b2, b1 0 xx Read Write Read Write 1 00 Read Write Read No Write 1 01 Read Write Read Write 1 10 Read Write No Read No Write 1 11 Read No Write No Read No Write DocID018932 Rev 14 M24LR16E-R System memory area The next two bits of the Sector security status byte (b3, b4) are the password control bits. The value of these two bits is used to link a password to the sector, as defined in Table 9. Table 9. Password control bits b4, b3 Password 00 The sector is not protected by a password. 01 The sector is protected by password 1. 10 The sector is protected by password 2. 11 The sector is protected by password 3. The M24LR16E-R password protection is organized around a dedicated set of commands, plus a system area of three password blocks where the password values are stored. This system area is described in Table 10. Table 10. Password system area Add Password 1 Password 1 2 Password 2 3 Password 3 The dedicated commands for protection in RF mode are: • Write-sector password: The Write-sector password command is used to write a 32-bit block into the password system area. This command must be used to update password values. After the write cycle, the new password value is automatically activated. It is possible to modify a password value after issuing a valid Present-sector password command. On delivery, the three default password values are set to 0000 0000h and are activated. • Lock-sector: The Lock-sector command is used to set the sector security status byte of the selected sector. Bits b4 to b1 of the sector security status byte are affected by the Lock-sector command. The sector lock bit, b0, is set to 1 automatically. After issuing a Lock-sector command, the protection settings of the selected sector are activated. The protection of a locked block cannot be changed in RF mode. A Lock-sector command sent to a locked sector returns an error code. DocID018932 Rev 14 25/148 147 System memory area • M24LR16E-R Present-sector password: The Present-sector password command is used to present one of the three passwords to the M24LR16E-R in order to modify the access rights of all the memory sectors linked to that password (Table 8) including the password itself. If the presented password is correct, the access rights remain activated until the tag is powered off or until a new Present-sector password command is issued. If the presented password value is not correct, all the access rights of all the memory sectors are deactivated. • Sector security status byte area access conditions in I2C mode: In I2C mode, read access to the sector security status byte area is always allowed. Write access depends on the correct presentation of the I2C password (see Section 5.16.1: I2C present password command description). To access the Sector security status byte area, the device select code used for any I2C command must have the E2 Chip Enable address at 1. An I2C write access to a sector security status byte re-initializes the RF access condition to the given memory sector. 4.1.1 Example of the M24LR16E-R security protection in RF mode Table 11 and Table 12 show the sector security protections before and after a valid Presentsector password command. Table 11 shows the sector access rights of an M24LR16E-R after power-up. After a valid Present-sector password command with password 1, the memory sector access is changed as shown in Table 12. Table 11. M24LR16E-R sector security protection after power-up Sector security status byte Sector address Sector features b7b6b5 b4 b3 b2 b1 b0 0 Protection: standard Read No Write xxx 0 0 0 0 1 1 Protection: pswd 1 Read No Write xxx 0 1 0 0 1 2 Protection: pswd 1 Read Write xxx 0 1 0 1 1 3 Protection: pswd 1 No Read No Write xxx 0 1 1 0 1 4 Protection: pswd 1 No Read No Write xxx 0 1 1 1 1 Table 12. M24LR16E-R sector security protection after a valid presentation of password 1 Sector address 26/148 Sector security status byte Sector features b7b6b5 b4 b3 b2 b1 b0 0 Protection: standard Read No Write xxx 0 0 0 0 1 1 Protection: pswd 1 Read Write xxx 0 1 0 0 1 2 Protection: pswd 1 Read Write xxx 0 1 0 1 1 3 Protection: pswd 1 Read Write xxx 0 1 1 0 1 4 Protection: pswd 1 Read No Write xxx 0 1 1 1 1 DocID018932 Rev 14 M24LR16E-R 4.2 System memory area M24LR16E-R block security in I²C mode (I2C_Write_Lock bit area) In the I2C mode only, it is possible to protect individual sectors against Write operations. This feature is controlled by the I2C_Write_Lock bits stored in the 2 bytes of the I2C_Write_Lock bit area. I2C_Write_Lock bit area starts from location 2048 (see Table 13). To access the I2C_Write_Lock bit area, the device select code used for any I2C command must have the E2 Chip Enable address at 1. Using these 16 bits, it is possible to write-protect all the 16 sectors of the M24LR16E-R memory. Each bit controls the I2C write access to a specific sector as shown in Table 13. It is always possible to unprotect a sector in the I2C mode. When an I2C_Write_Lock bit is reset to 0, the corresponding sector is unprotected. When the bit is set to 1, the corresponding sector is write-protected. In I2C mode, read access to the I2C_Write_Lock bit area is always allowed. Write access depends on the correct presentation of the I2C password. On delivery, the default value of the eight bytes of the I2C_Write_Lock bit area is reset to 00h. Table 13. I2C_Write_Lock bit I2C byte address E2 = 1 4.3 2048 Bits [15:8] Bits [7:0] sectors 15-8 sectors 7-0 Configuration byte and Control register The M24LR16E-R offers an 8-bit non-volatile Configuration byte located at I²C location 2320 of the system area used to store the RF WIP/BUSY pin and the energy harvesting configuration (see Table 14). The M24LR16E-R also offers an 8-bit volatile Control register located at I²C location 2336 of the system area used to store the energy harvesting enable bit as well as a FIELD_ON bit indicator (see Table 15). 4.3.1 RF WIP/BUSY pin configuration The M24LR16E-R features a configurable open drain output RF WIP/BUSY pin used to provide RF activity information to an external device. The RF WIP/BUSY pin functionality depends on the value of bit 3 of the Configuration byte. • RF busy mode When bit 3 of the Configuration byte is set to 0, the RF WIP/BUSY pin is configured in RF busy mode. The purpose of this mode is to indicate to the I²C bus master whether the M24LR16E-R is busy in RF mode or not. In this mode, the RF WIP/BUSY pin is tied to 0 from the RF command Start Of Frame (SOF) until the end of the command execution. DocID018932 Rev 14 27/148 147 System memory area M24LR16E-R If a bad RF command is received, the RF WIP/BUSY pin is tied to 0 from the RF command SOF until the reception of the RF command CRC. Otherwise, the RF WIP/BUSY pin is in high-Z state. When tied to 0, the RF WIP/BUSY signal returns to High-Z state if the RF field is cut-off. During execution of I²C commands, the RF WIP/BUSY pin remains in high-Z state. • RF Write in progress When bit 3 of the Configuration byte is set to 1, the RF WIP/BUSY pin is configured in RF Write in progress mode. The purpose of this mode is to indicate to the I²C bus master that some data have been changed in RF mode. In this mode, the RF WIP/BUSY pin is tied to 0 for the duration of an internal write operation (i.e. between the end of a valid RF write command and the beginning of the RF answer). During execution of I²C write operations, the RF WIP/BUSY pin remains in high-Z state. 4.3.2 Energy harvesting configuration The M24LR16E-R features an Energy harvesting mode on the Vout analog output. The general purpose of the Energy harvesting mode is to deliver a part of the nonnecessary RF power received by the M24LR16E-R on the AC0-AC1 RF input in order to supply an external device. The current consumption on the analog voltage output Vout is limited to ensure that the M24LR16E-R is correctly supplied during the powering of the external device. When the Energy harvesting mode is enabled and the power delivered on the AC0-AC1 RF input exceeds the minimum required PAC0-AC1_min, the M24LR16E-R is able to deliver a limited and unregulated voltage on the Vout pin, assuming the current consumption on the Vout does not exceed the Isink_max maximum value. If one of the condition above is not met, the analog voltage output pin Vout is set in High-Z state. For robust applications using the Energy harvesting mode, four current fan-out levels can be chosen. • Vout sink current configuration The sink current level is chosen by programming EH_cfg1 and EH_cfg0 into the Configuration byte (see Table 14). The minimum power level required on AC0-AC1 RF input PAC0-AC1_min, the delivered voltage Vout, as well as the maximum current consumption Isink_max on the Vout pin corresponding to the bit values are described in Table 127. Table 14. Configuration byte I2C byte address Bit 7 Bit 6 Bit 5 Bit 4 E2=1 2320 X(1) X(1) X(1) X(1) Bit 3 RF WIP/BUSY 1. Bit 7 to Bit 4 are don’t care bits. 28/148 DocID018932 Rev 14 Bit 2 BIT 1 BIT 0 EH_mode EH_cfg1 EH_cfg0 M24LR16E-R System memory area • Energy harvesting enable control Delivery of Energy harvesting analog output voltage on the Vout pin depends on the value of the EH_enable bit of the volatile Control register (see Table 15). Table 15. Control register 2 I C byte address E2 = 1 2336 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 T_Prog(1) 0(1) 0(1) 0(1) 0(1) 0(1) Bit 1 Bit 0 FIELD_ON(1) EH_enable 1. Bit 7 to Bit 1 are read-only bits. • – When set to 1, the EH_enable bit enables the Energy harvesting mode, meaning that the Vout analog output signal is delivered when the PAC0-AC1_min and Isink_max conditions corresponding to the chosen sink current configuration bit are met (see Table 127). – When set to 0, the EH_enable bit disable the Energy harvesting mode and the analog output Vout remains in set in High-Z state. – The T_Prog flag indicates a correct duration of the I²C write time (tw). This bit is reset to 0 after POR and at the beginning of each writing cycle; it is set to 1 only after a correct completion of the writing cycle. Energy harvesting default mode control At power-up, in I²C or RF mode, the EH_enable bit is updated according to the value of the EH_mode bit stored in the non-volatile Configuration byte (see Table 16). In other words, the EH_mode bit is used to configure whether the Energy harvesting mode is enabled or not by default. Table 16. EH_enable bit value after power-up 4.3.3 Energy harvesting EH_mode value EH_enable after power-up 0 1 enabled 1 0 disabled after power-up FIELD_ON indicator bit The FIELD_ON bit indicator located as Bit 1 of the Control register is a read-only bit used to indicate when the RF power level delivered to the M24LR16E-R is sufficient to execute RF commands. Note: • When FIELD_ON = 0, the M24LR16E-R is not able to execute any RF commands. • When FIELD_ON =1, the M24LR16E-R is able to execute any RF commands. During read access to the Control register in RF mode, the FIELD_ON bit is always read at 1. DocID018932 Rev 14 29/148 147 System memory area 4.3.4 M24LR16E-R Configuration byte access in I²C and RF modes In I²C mode, read and write accesses to the non-volatile Configuration byte are always allowed. To access the Configuration byte, the device select code used for any I²C command must have the E2 Chip enable address at 1. The dedicated commands to access the Configuration byte in RF mode are: • Read configuration byte command (ReadCfg): The ReadCfg command is used to read the eight bits of the Configuration byte. • Write energy harvesting configuration command (WriteEHCfg): The WriteEHCfg command is used to write the EH_mode, EH_cfg1 and EH_cfg0 bits into the Configuration byte. • Write RF WIP/BUSY pin configuration command (WriteDOCfg): The WriteDOCfg command is used to write the RF WIP/BUSY bit into the Configuration byte. After any write access to the Configuration byte, the new configuration is automatically applied. 4.3.5 Control register access in I²C or RF mode In I²C mode, read and write accesses to the volatile Control register are always allowed. To access the Control register, the device select code used for any I²C command must have the E2 Chip enable address at 1. The dedicated commands to access the Control register in RF mode are: • Check energy harvesting enable bit command (CheckEHEn): The CheckEHEn command is used to read the eight bits of the Control register. When it is run, the FIELD_ON bit is always read at 1. • Set/reset energy harvesting enable bit command (SetRstEHEn): The SetRstEHEn command is used to set or reset the value of the EH_enable bit into the Control register. 4.4 ISO 15693 system parameters The M24LR16E-R provides the system area required by the ISO 15693 RF protocol, as shown in Table 17. The first 32-bit block starting from I2C address 2304 stores the I2C password. This password is used to activate/deactivate the write protection of the protected sector in I2C mode. At power-on, all user memory sectors protected by the I2C_Write_Lock bits can be read but cannot be modified. To remove the write protection, it is necessary to use the I2C present password described in Figure 12. When the password is correctly presented — that is, when all the presented bits correspond to the stored ones — it is also possible to modify the I2C password using the I2C write password command described in Figure 13. The next three 32-bit blocks store the three RF passwords. These passwords are neither read- nor write- accessible in the I2C mode. 30/148 DocID018932 Rev 14 M24LR16E-R System memory area The next byte stores the Configuration byte, at I²C location 2320. This Control register is used to store the three energy harvesting configuration bits and the RF WIP/BUSY configuration bit. The next two bytes are used to store the AFI, at I2C location 2322, and the DSFID, at I2C location 2323. These two values are used during the RF inventory sequence. They are read-only in the I2C mode. The next eight bytes, starting from location 2324, store the 64-bit UID programmed by ST on the production line. Bytes at I2C locations 2332 to 2335 store the IC Ref and the Mem_Size data used by the RF Get_System_Info command. The UID, Mem_Size and IC ref values are read-only data. Table 17. System parameter sector I2C byte address Bits [31:24] Bits [23:16] Bits [15:8] password Bits [7:0] (1) E2 = 1 2304 E2 = 1 2308 RF password 1 (1) E2 = 1 2312 RF password 2 (1) E2 = 1 2316 RF password 3 (1) E2 = 1 2320 DSFID (FFh) AFI (00h) ST reserved (Exh) (2) Configuration byte (F4h) E2 = 1 2324 UID UID UID UID E2 = 1 2328 UID (E0h) UID (02h) UID UID E2 = 1 2332 E2 = 1 2336 I 2C Mem_Size (03 01FFh) IC Ref (4Eh) - Prog. completion and Energy harvesting status (3) - - 1. Delivery state: I2C password= 0000 0000h, RF password = 0000 0000h, Configuration byte = F4h. 2. The product revision is the Most significant nibble of the byte located at address 0x911 (2321 d) in the system area (Device select code E2 =1). From DS rev9, the product revision value is 0xE. The Least significant nibble is ST reserved. 3. Address system 2336 (920h, E2=1) is the control register. Bit 7 is T_Prog (refer to Table 15: Control register). When accessed in RF, this bit is not significant and set to 0. Bits 2-6 are RFU and set to 0. Bit 1 is FIELD_ON (refer to Table 15: Control register). Bit 0 is EH_enable (refer to Table 15: Control register). DocID018932 Rev 14 31/148 147 I2C device operation 5 M24LR16E-R I2C device operation The device supports the I2C protocol. This is summarized in Figure 4. Any device that sends data to the bus is defined as a transmitter, and any device that reads data is defined as a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The M24LR16E-R device is a slave in all communications. 5.1 Start condition Start is identified by a falling edge of serial data (SDA) while the serial clock (SCL) is stable in the high state. A Start condition must precede any data transfer command. The device continuously monitors (except during a write cycle) the SDA and the SCL for a Start condition, and does not respond unless one is given. 5.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while the serial clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Standby mode. A Stop condition at the end of a Write command triggers the internal write cycle. 5.3 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases the serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls the SDA low to acknowledge the receipt of the eight data bits. 5.4 Data input During data input, the device samples serial data (SDA) on the rising edge of the serial clock (SCL). For correct device operation, the SDA must be stable during the rising edge of the SCL, and the SDA signal must change only when the SCL is driven low. 5.5 I²C timeout During the execution of an I²C operation, RF communications are not possible. To prevent RF communication freezing due to inadvertent unterminated instructions sent to the I²C bus, the M24LR16E-R features a timeout mechanism that automatically resets the I²C logic block. 32/148 DocID018932 Rev 14 I2C device operation M24LR16E-R 5.5.1 I²C timeout on Start condition I²C communication with the M24LR16E-R starts with a valid Start condition, followed by a device select code. If the delay between the Start condition and the following rising edge of the Serial Clock (SCL) that samples the most significant of the Device Select exceeds the tSTART_OUT time (see Table 123), the I²C logic block is reset and further incoming data transfer is ignored until the next valid Start condition. Figure 7. I²C timeout on Start condition 6&/ 6'$ W67$57B287 6WDUW FRQGLWLRQ 069 5.5.2 I²C timeout on clock period During data transfer on the I²C bus, the serial clock high pulse width High (tCHCL) or serial clock pulse width Low (tCLCH) exceeds the maximum value specified in Table 123, the I²C logic block is reset and any further incoming data transfer is ignored until the next valid Start condition. 5.6 Memory addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (on Serial Data (SDA), most significant bit first). The device select code consists of a 4-bit device type identifier and a 3-bit Chip Enable “Address” (E2,1,1). To address the memory array, the 4-bit device type identifier is 1010b. Refer to Table 2. The eighth bit is the Read/Write bit (RW). It is set to 1 for Read and to 0 for Write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (SDA) during the ninth bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. DocID018932 Rev 14 33/148 147 I2C device operation M24LR16E-R Table 18. Operating modes Mode Current address read Random address read RW bit Bytes 1 1 0 Initial sequence Start, device select, RW = 1 Start, device select, RW = 0, address 1 1 reStart, device select, RW = 1 Sequential read 1 ≥1 Byte write 0 1 Start, device select, RW = 0 Page write 0 ≤ 4 bytes Start, device select, RW = 0 Similar to current or random address read Figure 8. Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited) $&. %\WHDGGUHVV 'DWDLQ $&. %\WHDGGUHVV $&. %\WHDGGUHVV 12$&. 'DWDLQ 'DWDLQ 12$&. 12$&. 'DWDLQ1 6WRS 'HYVHOHFW 6WDUW %\WHDGGUHVV 12$&. 5: $&. 3DJH:ULWH $&. 6WRS 'HYVHOHFW 6WDUW %\WH:ULWH $&. 5: 06Y9 34/148 DocID018932 Rev 14 I2C device operation M24LR16E-R 5.7 Write operations Following a Start condition, the bus master sends a device select code with the Read/Write bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Writing to the memory may be inhibited if the I2C_Write_Lock bit = 1. A Write instruction issued with the I2C_Write_Lock bit = 1 and with no I2C_Password presented does not modify the memory contents, and the accompanying data bytes are not acknowledged, as shown in Figure 8. Each data byte in the memory has a 16-bit (two byte wide) address. The most significant byte (Table 3) is sent first, followed by the least significant byte (Table 4). Bits b15 to b0 form the address of the byte in memory. When the bus master generates a Stop condition immediately after the Ack bit (in the tenthbit time slot), either at the end of a byte write or a page write, the internal write cycle is triggered. A Stop condition at any other time slot does not trigger the internal write cycle. After the Stop condition, the delay tW, and the successful completion of a Write operation, the device’s internal address counter is incremented automatically, to point to the next byte address after the last one that was modified. During the internal write cycle, the serial data (SDA) signal is disabled internally, and the device does not respond to any requests. 5.8 Byte write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected by the I2C_Write_Lock bit (= 1), the device replies with NoAck, and the location is not modified. If the addressed location is not write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 9. 5.9 Page write The Page write mode allows up to four bytes to be written in a single write cycle, provided that they are all located in the same “row” in the memory: that is, the most significant memory address bits (b12-b2) are the same. If more bytes are sent than fit up to the end of the row, a condition known as “roll-over” occurs. This should be avoided, as data starts to become overwritten in an implementation-dependent way. The bus master sends from one to four bytes of data, each of which is acknowledged by the device if the I2C_Write_Lock bit = 0 or the I2C_Password was correctly presented. If the I2C_Write_Lock_bit = 1 and the I2C_password are not presented, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck. After each byte is transferred, the internal byte address counter (inside the page) is incremented. The transfer is terminated by the bus master generating a Stop condition. DocID018932 Rev 14 35/148 147 I2C device operation M24LR16E-R Figure 9. Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) !#+ "YTEADDRESS $ATAIN !#+ "YTEADDRESS !#+ "YTEADDRESS !#+ !#+ $ATAIN $ATAIN !#+ $ATAIN. 3TOP $EV3ELECT 3TART "YTEADDRESS !#+ 27 !#+ 0AGE7RITE !#+ 3TOP $EV3ELECT 3TART "YTE7RITE !#+ 27 !) 36/148 DocID018932 Rev 14 I2C device operation M24LR16E-R Figure 10. Write cycle polling flowchart using ACK :ULWHF\FOH LQSURJUHVV 6WDUWFRQGLWLRQ 'HYLFHVHOHFW ZLWK5:  12 )LUVWE\WHRI LQVWUXFWLRQ ZLWK5: DOUHDG\ GHFRGHGE\WKH GHYLFH $&. UHWXUQHG ϭ W Ϯ  >ϭ ď Ğ 76623$0B9 1. Drawing is not to scale. Table 130. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 CP - - 0.100 - - 0.0039 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DocID018932 Rev 14 139/148 147 Ordering information 32 M24LR16E-R Ordering information Table 131. Ordering information scheme for packaged devices Example: M24LR 16 E R MN 6 T /2 Device type M24LR = dynamic NFC/RFID tag IC Device function 16 = memory size in Kbit E = support for energy harvesting Operating voltage R = VCC = 1.8 to 5.5 V Package MN = SO8N (150 mils width) MC = UFDFPN8 (MLP8) DW = TSSOP8 Device grade 6 = industrial: device tested with standard test flow over –40 to 85 °C Option T = Tape and reel packing Capacitance /2 = 27.5 pF Note: 140/148 Parts marked as ES or E are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID018932 Rev 14 M24LR16E-R Ordering information Table 132. Ordering and marking information First line marking Reference M24LR16E-R Package Ordering code TSSOP08 Initial revision 0xF Actual revision 0xE and below M24LR16E-RDW6T/2 416EU 4DEUB MLP M24LR16E-RMC6T/2 416E 4DEB SO8N M24LR16E-RMN6T/2 24L16ER 24LDERB Bare die M24LR16E-RUW20/2 N/A N/A DocID018932 Rev 14 141/148 147 Anticollision algorithm (informative) Appendix A M24LR16E-R Anticollision algorithm (informative) The following pseudocode describes how anticollision could be implemented on the VCD, using recursivity. A.1 Algorithm for pulsed slots function function function function push (mask, address); pushes on private stack pop (mask, address); pops from private stack pulse_next_pause; generates a power pulse store(M24LR16E-R_UID); stores M24LR16E-R_UID function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask ; send the request mode = anticollision send_Request (Request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR16E-R is inventoried then store (M24LR16E-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle 142/148 DocID018932 Rev 14 M24LR16E-R CRC (informative) Appendix B B.1 CRC (informative) CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR16ER and from M24LR16E-R to VCD. Table 133. CRC definition CRC definition CRC type ISO/IEC 13239 Length 16 bits Polynomial 16 X + X12 + X5 + 1 = 8408h Direction Preset Residue Backward FFFFh F0B8h To add extra protection against shifting errors, a further transformation on the calculated CRC is made. The one’s complement of the calculated CRC is the value attached to the message for transmission. To check received messages, the two CRC bytes are often also included in the recalculation, for ease of use. In this case, the expected value for the generated CRC is the residue F0B8h. B.2 CRC calculation example This example in C language illustrates one method of calculating the CRC on a given set of bytes comprising a message. C-example to calculate or check the CRC16 according to ISO/IEC 13239 #define #define #define POLYNOMIAL0x8408// PRESET_VALUE0xFFFF CHECK_VALUE0xF0B8 x^16 + x^12 + x^5 + 1 #define #define #define NUMBER_OF_BYTES4// Example: 4 data bytes CALC_CRC1 CHECK_CRC0 void main() { unsigned int current_crc_value; unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3, 4, 0x91, 0x39}; int number_of_databytes = NUMBER_OF_BYTES; int calculate_or_check_crc; int i, j; calculate_or_check_crc = CALC_CRC; // calculate_or_check_crc = CHECK_CRC;// This could be an other example if (calculate_or_check_crc == CALC_CRC) { DocID018932 Rev 14 143/148 147 CRC (informative) M24LR16E-R number_of_databytes = NUMBER_OF_BYTES; } else // check CRC { number_of_databytes = NUMBER_OF_BYTES + 2; } current_crc_value = PRESET_VALUE; for (i = 0; i < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for (j = 0; j < 8; j++) { if (current_crc_value & 0x0001) { current_crc_value = (current_crc_value >> 1) ^ POLYNOMIAL; } else { current_crc_value = (current_crc_value >> 1); } } } if (calculate_or_check_crc == CALC_CRC) { current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\n", current_crc_value); // stream // } else { if { current_crc_value is now ready to be appended to the data (first LSByte, then MSByte) // check CRC (current_crc_value == CHECK_VALUE) printf ("Checked CRC is ok (0x%04X)\n", current_crc_value); } else { printf ("Checked CRC is NOT ok (0x%04X)\n", current_crc_value); } } } 144/148 DocID018932 Rev 14 M24LR16E-R Application family identifier (AFI) (informative) Appendix C Application family identifier (AFI) (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR16E-Rs present only the M24LR16E-R meeting the required application criteria. It is programmed by the M24LR16E-R issuer (the purchaser of the M24LR16E-R). Once locked, it cannot be modified. The most significant nibble of the AFI is used to code one specific or all application families, as defined in Table 134. The least significant nibble of the AFI is used to code one specific or all application subfamilies. Subfamily codes different from 0 are proprietary. Table 134. AFI coding(1) AFI AFI most significant nibble least significant nibble ‘0’ ‘0’ All families and subfamilies No applicative preselection ‘X’ '0 All subfamilies of family X Wide applicative preselection 'X '‘Y’ Only the Yth subfamily of family X - ‘0’ ‘Y’ Proprietary subfamily Y only - ‘1 '‘0’, ‘Y’ Transport Mass transit, bus, airline,... '2 '‘0’, ‘Y’ Financial IEP, banking, retail,... '3 '‘0’, ‘Y’ Identification Access control,... '4 '‘0’, ‘Y’ Telecommunication Public telephony, GSM,... ‘5’ ‘0’, ‘Y’ Medical - '6 '‘0’, ‘Y’ Multimedia Internet services.... '7 '‘0’, ‘Y’ Gaming - 8 '‘0’, ‘Y’ Data Storage Portable files,... '9 '‘0’, ‘Y’ Item management - 'A '‘0’, ‘Y’ Express parcels - 'B '‘0’, ‘Y’ Postal services - 'C '‘0’, ‘Y’ Airline bags - 'D '‘0’, ‘Y’ RFU - 'E '‘0’, ‘Y’ RFU - ‘F’ ‘0’, ‘Y’ RFU - Meaning Examples / Note VICCs respond from 1. X = '1' to 'F', Y = '1' to 'F' DocID018932 Rev 14 145/148 147 Revision history M24LR16E-R Revision history Table 135. Document revision history Date Revision 24-Jun-2011 1 Initial release. 28-Jul-2011 2 Updated Description, Table 118: Absolute maximum ratings, Table 127: Energy harvesting. Added figures 52, 56, 57, 83 to 87. 29-Jul-2011 3 Updated IC Ref data. 29-Jul-2011 4 Updated IC Ref data from 4Fh to 4Eh. 5 Updated: – Table 127: Energy harvesting – Section 5.6: Memory addressing – Figure 12: I2C present password command – Figure 13: I2C write password command 6 Updated: – Table 118: Absolute maximum ratings – Table 122: I2C DC characteristics – Table 125: RF characteristics – Table 127: Energy harvesting – Figure 82: ASK modulated signal – Figure 83: Vout min vs. Isink – Figure 84: Range 11 domain – Figure 85: Range 10 domain – Figure 86: Range 01 domain – Figure 87: Range 00 domain 7 Modified Table 10: Password system area on page 25 (Removed “Add” column). Modified Table 127: Energy harvesting on page 131 (4.5 V max instead of 4.0 V max). 12-Jun-2012 8 Updated Table 5: Sector details on page 21 and Figure 49: M24LR16E-R state transition diagram. Updated clock pulse width values in Table 123: I2C AC characteristics on page 126. 21-Feb-2013 9 Updated Table 15: Control register, Table 17: System parameter sector, Table 118: Absolute maximum ratings, Table 122: I2C DC characteristics and Table 125: RF characteristics. 07-Mar-2013 10 Added Table 132: Ordering and marking information. 11 Added “Dynamic NFC/RFID tag IC” to the title, Section 1: Description, and the M24LR definition in Table 131: Ordering information scheme for packaged devices. Updated VESD and Note 5 in Table 118: Absolute maximum ratings. Removed MB package from Figure 31.2: UFDFN8 package information. 09-Aug-2011 09-Nov-2011 13-Dec-2011 13-Jun-2013 146/148 Changes DocID018932 Rev 14 M24LR16E-R Revision history Table 135. Document revision history (continued) Date Revision Changes 13-May-2016 12 Updated Features in cover page. Added Section 29: Write cycle definition. 13-Mar-2017 13 Updated Features in cover page. 01-Aug-2017 14 Added note 4 on Figure 90: UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline Updated Section 32: Ordering information DocID018932 Rev 14 147/148 147 M24LR16E-R IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 148/148 DocID018932 Rev 14