M24LR64E-RMN6T/2

M24LR64E-R Dynamic NFC/RFID tag IC with 64-Kbit EEPROM, energy harvesting, I²C bus and ISO 15693 RF interface Datasheet - production data in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands • Internal tuning capacitance: 27.5 pF SO8 (MN) UFDFPN8 (MC) TSSOP8 (DW) 2 x 3 mm • 64-bit unique identifier (UID) • Read Block & Write (32-bit blocks) Digital output pin • User configurable pin: RF write in progress or RF busy mode Wafer (RUW20) Wafer (SB12I) Energy harvesting • Analog pin for energy harvesting Features • Four sink current configurable ranges • Belonging to ST25 family, which includes all NFC/RF ID tag and reader products from ST Temperature range I2 C interface Memory • Two-wires I2C serial interface supports 400 kHz protocol • 64-Kbit EEPROM organized into: – 8192 bytes in I2C mode – 2048 blocks of 32 bits in RF mode • Single supply voltage: – 1.8 V to 5.5 V • Write time – I2C: 5 ms (max.) – RF: 5.75 ms including the internal Verify time • Byte and Page Write (up to 4 bytes) • Random and Sequential read modes • Self-timed programming cycle • Write cycling endurance: – 1 million write cycles at 25 °C – 150 k write cycles at 85 °C • Automatic address incrementing • Enhanced ESD/latch-up protection • I²C timeout • More than 40-year data retention Contactless interface • Multiple password protection in RF mode • ISO 15693 and ISO 18000-3 mode 1 compatible • 13.56 MHz ± 7 kHz carrier frequency • To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding • From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers July 2017 This is information on a product in full production. • From –40 to 85 °C • Single password protection in I2C mode Package • SO8 (ECOPACK2®) • TSSOP8 (ECOPACK2®) • UFDFPN8 (ECOPACK2®) DocID022712 Rev 12 1/144 www.st.com 1 Contents M24LR64E-R Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 RF Write in progress / RF Busy (RF WIP/BUSY) . . . . . . . . . . . . . . . . . . . 15 2.4 Energy harvesting analog output (Vout) . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Antenna coil (AC0, AC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 Device reset in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.1 2.7.2 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.3 Device reset in I²C mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 User memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 System memory area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 M24LR64E-R block security in RF mode . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 4.2 M24LR64E-R block security in I²C mode (I2C_Write_Lock bit area) . . . . 27 4.3 Configuration byte and Control register . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.4 5 2/144 Example of the M24LR64E-R security protection in RF mode . . . . . . . 26 4.3.1 RF WIP/BUSY pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.3.2 Energy harvesting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.3 FIELD_ON indicator bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.4 Configuration byte access in I²C and RF modes . . . . . . . . . . . . . . . . . . 30 4.3.5 Control register access in I²C or RF mode . . . . . . . . . . . . . . . . . . . . . . 30 ISO 15693 system parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 I2C device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DocID022712 Rev 12 M24LR64E-R Contents 5.3 Acknowledge bit (Ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5 I²C timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.5.1 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.5.2 I²C timeout on clock period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.6 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.7 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.8 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.9 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.10 Minimizing system delays by polling on Ack . . . . . . . . . . . . . . . . . . . . . . 36 5.11 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.13 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.14 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.15 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.16 M24LR64E-R I2C password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.16.1 I2C present password command description . . . . . . . . . . . . . . . . . . . . . 39 5.16.2 I2C write password command description . . . . . . . . . . . . . . . . . . . . . . . 40 6 M24LR64E-R memory initial state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7 RF device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 RF communication and energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . 42 7.2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.3 Initial dialog for vicinity cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.1 Power transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.2 Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.3.3 Operating field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8 Communication signal from VCD to M24LR64E-R . . . . . . . . . . . . . . . . 45 9 Data rate and data coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.1 Data coding mode: 1 out of 256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.2 Data coding mode: 1 out of 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3 VCD to M24LR64E-R frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DocID022712 Rev 12 3/144 Contents M24LR64E-R 9.4 10 11 Communication signal from M24LR64E-R to VCD . . . . . . . . . . . . . . . . 51 10.1 Load modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.2 Subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3 Data rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Bit representation and coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1 11.2 12 Start of frame (SOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Bit coding using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 11.1.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Bit coding using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.2.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 M24LR64E-R to VCD frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.1 12.2 12.3 12.4 SOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.1.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 12.1.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 12.2.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 EOF when using one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.3.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 EOF when using two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.4.1 High data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 12.4.2 Low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13 Unique identifier (UID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 14 Application family identifier (AFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15 Data storage format identifier (DSFID) . . . . . . . . . . . . . . . . . . . . . . . . . 61 15.1 16 4/144 CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 M24LR64E-R protocol description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 DocID022712 Rev 12 M24LR64E-R 17 18 19 M24LR64E-R states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.1 Power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.2 Ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.3 Quiet state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 17.4 Selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.1 Addressed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.2 Non-addressed mode (general request) . . . . . . . . . . . . . . . . . . . . . . . . . 66 18.3 Select mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 19.1 20 21 Contents Request flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20.1 Response flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20.2 Response error code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 21.1 Request parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 22 Request processing by the M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . 73 23 Explanation of the possible cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 24 Inventory Initiated command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 25 Timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 26 25.1 t1: M24LR64E-R response delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 25.2 t2: VCD new request delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 25.3 t3: VCD new request delay when no response is received from the M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Command codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 26.1 Inventory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 26.2 Stay Quiet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DocID022712 Rev 12 5/144 Contents M24LR64E-R 26.3 Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 26.4 Write Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 26.5 Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 26.6 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 26.7 Reset to Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 26.8 Write AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 26.9 Lock AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 26.10 Write DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 26.11 Lock DSFID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 26.12 Get System Info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 26.13 Get Multiple Block Security Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 26.14 Write-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 26.15 Lock-sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 26.16 Present-sector Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 26.17 Fast Read Single Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 26.18 Fast Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 26.19 Fast Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 26.20 Fast Read Multiple Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 26.21 Inventory Initiated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 26.22 Initiate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 26.23 ReadCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 26.24 WriteEHCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 26.25 WriteDOCfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 26.26 SetRstEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 26.27 CheckEHEn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 27 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 28 I2C DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 29 Write cycle definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 30 RF electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 31 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 6/144 DocID022712 Rev 12 M24LR64E-R 32 Contents 31.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 31.2 UFDFN8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 31.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Appendix A Anticollision algorithm (informative) . . . . . . . . . . . . . . . . . . . . . . . 138 A.1 Algorithm for pulsed slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Appendix B CRC (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 B.1 CRC error detection method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 B.2 CRC calculation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Appendix C Application family identifier (AFI) (informative) . . . . . . . . . . . . . . 141 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DocID022712 Rev 12 7/144 List of tables M24LR64E-R List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 8/144 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Address least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Sector details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Read/Write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M24LR64E-R sector security protection after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 M24LR64E-R sector security protection after a valid presentation of password 1 . . . . . . . 26 I2C_Write_Lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Configuration byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 EH_enable bit value after power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 System parameter sector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10% modulation parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Response data rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 UID format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 CRC transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 VCD request frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 M24LR64E-R Response frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 M24LR64E-R response depending on Request_flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 General request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Definition of request flags 1 to 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Request flags 5 to 8 when Bit 3 = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Request flags 5 to 8 when Bit 3 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 General response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Definitions of response flags 1 to 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Response error code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Example of the addition of 0-bits to an 11-bit mask value . . . . . . . . . . . . . . . . . . . . . . . . . 71 Timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Inventory request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Stay Quiet request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 82 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 82 Write Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Write Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . 83 Write Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . 84 Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . 87 DocID022712 Rev 12 M24LR64E-R Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. List of tables Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . 87 Select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Select Block response format when Error_flag is NOT set. . . . . . . . . . . . . . . . . . . . . . . . . 88 Select response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Reset to Ready request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Reset to Ready response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . 90 Reset to ready response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Write AFI request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Write AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Write AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Lock AFI request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Lock AFI response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Lock AFI response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Write DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Write DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 94 Write DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Lock DSFID request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Lock DSFID response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . 95 Lock DSFID response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Get System Info request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Get System Info response format when Protocol_extension_flag = 0 and Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Get System Info response format when Protocol_extension_flag = 1 and Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Get System Info response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Get Multiple Block Security Status request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Get Multiple Block Security Status response format when Error_flag is NOT set . . . . . . . 99 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Get Multiple Block Security Status response format when Error_flag is set . . . . . . . . . . . . 99 Write-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Write-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . . . 100 Write-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . 100 Lock-sector request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Lock-sector response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 102 Lock-sector response format when Error_flag is set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Present-sector Password request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Present-sector Password response format when Error_flag is NOT set . . . . . . . . . . . . . 103 Present-sector Password response format when Error_flag is set . . . . . . . . . . . . . . . . . . 103 Fast Read Single Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Fast Read Single Block response format when Error_flag is NOT set . . . . . . . . . . . . . . . 105 Sector security status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Fast Read Single Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . . 105 Fast Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Fast Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Fast Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Fast Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Fast Read Multiple Block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Fast Read Multiple Block response format when Error_flag is NOT set. . . . . . . . . . . . . . 108 Sector security status if Option_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Fast Read Multiple Block response format when Error_flag is set . . . . . . . . . . . . . . . . . . 109 DocID022712 Rev 12 9/144 List of tables Table 99. Table 100. Table 101. Table 102. Table 103. Table 104. Table 105. Table 106. Table 107. Table 108. Table 109. Table 110. Table 111. Table 112. Table 113. Table 114. Table 115. Table 116. Table 117. Table 118. Table 119. Table 120. Table 121. Table 122. Table 123. Table 124. Table 125. Table 126. Table 127. Table 128. Table 129. Table 130. Table 131. Table 132. Table 133. Table 134. Table 135. 10/144 M24LR64E-R Inventory Initiated request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Inventory Initiated response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 ReadCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ReadCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . . . 112 ReadCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 WriteEHCfg request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 WriteEHCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 113 WriteEHCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 WriteDOCfg request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 WriteDOCfg response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 115 WriteDOCfg response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 SetRstEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 SetRstEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . 116 SetRstEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 CheckEHEn request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 CheckEHEn response format when Error_flag is NOT set . . . . . . . . . . . . . . . . . . . . . . . . 117 CheckEHEn response format when Error_flag is set . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 I2C operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 AC test measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 I2C DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I2C AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Write cycle endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 RF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Energy harvesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Ordering information scheme for packaged devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Ordering and marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 CRC definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 AFI coding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DocID022712 Rev 12 M24LR64E-R List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I²C timeout on Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Write mode sequences with I2C_Write_Lock bit = 1 (data write inhibited). . . . . . . . . . . . . 34 Write mode sequences with I2C_Write_Lock bit = 0 (data write enabled) . . . . . . . . . . . . . 35 Write cycle polling flowchart using Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 I2C present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I2C write password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 100% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10% modulation waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 1 out of 256 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Detail of a time period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 1 out of 4 coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 1 out of 4 coding example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SOF to select 1 out of 256 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SOF to select 1 out of 4 data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EOF for either data coding mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Logic 0, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Logic 1, high data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Logic 0, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Logic 1, low data rate, fast commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Logic 0, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 1, high data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 0, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Logic 1, low data rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Start of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Start of frame, high data rate, one subcarrier, fast commands. . . . . . . . . . . . . . . . . . . . . . 55 Start of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Start of frame, low data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 56 Start of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Start of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 End of frame, high data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 End of frame, high data rate, one subcarrier, fast commands . . . . . . . . . . . . . . . . . . . . . . 57 End of frame, low data rate, one subcarrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 End of frame, low data rate, one subcarrier, Fast commands . . . . . . . . . . . . . . . . . . . . . . 57 End of frame, high data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 End of frame, low data rate, two subcarriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 M24LR64E-R decision tree for AFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DocID022712 Rev 12 11/144 List of figures Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. 12/144 M24LR64E-R M24LR64E-R protocol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 M24LR64E-R state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Principle of comparison between the mask, the slot number and the UID . . . . . . . . . . . . . 72 Description of a possible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 M24LR64E RF-Busy management following Inventory command . . . . . . . . . . . . . . . . . . . 80 Stay Quiet frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . 81 Read Single Block frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . 83 Write Single Block frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . 84 M24LR64E RF-Busy management following Write command . . . . . . . . . . . . . . . . . . . . . . 85 M24LR64E RF-Wip management following Write command . . . . . . . . . . . . . . . . . . . . . . . 86 Read Multiple Block frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . 88 Select frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . . . 89 Reset to Ready frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . 90 Write AFI frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . 91 Lock AFI frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . 93 Write DSFID frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 95 Lock DSFID frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . . . . . . 96 Get System Info frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . 98 Get Multiple Block Security Status frame exchange between VCD and M24LR64E-R . . . 99 Write-sector Password frame exchange between VCD and M24LR64E-R . . . . . . . . . . . 101 Lock-sector frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 102 Present-sector Password frame exchange between VCD and M24LR64E-R . . . . . . . . . 104 Fast Read Single Block frame exchange between VCD and M24LR64E-R. . . . . . . . . . . 105 Fast Initiate frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 107 Fast Read Multiple Block frame exchange between VCD and M24LR64E-R . . . . . . . . . 109 Initiate frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . . . 111 ReadCfg frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . . . 112 WriteEHCfg frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . . 114 WriteDOCfg frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . . . . . 115 SetRstEHEn frame exchange between VCD and M24LR64E-R . . . . . . . . . . . . . . . . . . . 116 CheckEHEn frame exchange between VCD and M24LR64E-R. . . . . . . . . . . . . . . . . . . . 118 AC test measurement I/O waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 I2C AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 ASK modulated signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Energy harvesting: Vout min vs. Isink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Energy harvesting: working domain range 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Energy harvesting: working domain range 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Energy harvesting: working domain range 01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Energy harvesting: working domain range 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . 131 SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 DocID022712 Rev 12 M24LR64E-R 1 Description Description The M24LR64E-R device is a Dynamic NFC/RFID tag IC with a dual-interface, electrically erasable programmable memory (EEPROM). It features an I2C interface and can be operated from a VCC power supply. It is also a contactless memory powered by the received carrier electromagnetic wave. The M24LR64E-R is organized as 8192 × 8 bits in the I2C mode and as 2048 × 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode. The M24LR64E-R also features an energy harvesting analog output, as well as a user-configurable digital output pin toggling during either RF write in progress or RF busy mode. Figure 1. Logic diagram 9&& 9RXW 6&/ 6'$ $& 0/5(5 $& 5):,3%86< 966 06Y9 The I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition. The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW) (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64E-R is accessed via the 13.56 MHz carrier electromagnetic wave on which incoming data is demodulated from the received signal amplitude modulation (ASK: Amplitude Shift Keying). When connected to an antenna, the operating power is derived from the RF energy and no external power supply is required. The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s DocID022712 Rev 12 13/144 Description M24LR64E-R using the 1 out of 256 pulse coding mode, or a data rate of 26 Kbit/s using the 1 out of 4 pulse coding mode. Outgoing data is generated by the M24LR64E-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data is transferred from the M24LR64E-R at 6.6 Kbit/s in low data rate mode and at 26 Kbit/s in high data rate mode. The M24LR64E-R supports the 53 Kbit/s fast mode in high data rate mode using one subcarrier frequency at 423 kHz. The M24LR64E-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface. The M24LR64E-R provides an Energy harvesting mode on the analog output pin Vout. When the Energy harvesting mode is activated, the M24LR64E-R can output the excess energy coming from the RF field on the Vout analog pin. In case the RF field strength is insufficient or when the Energy harvesting mode is disabled, the analog output pin Vout goes into high-Z state and the Energy harvesting mode is automatically stopped. The M24LR64E-R features a user configurable digital out pin RF WIP/BUSY that can be used to drive a microcontroller interrupt input pin (available only when the M24LR64E-R is correctly powered on the VCC pin). When configured in the RF write in progress mode (RF WIP mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF internal write operation. When configured in the RF busy mode (RF BUSY mode), the RF WIP/BUSY pin is driven low for the entire duration of the RF command progress. The RF WIP/BUSY pin is an open drain output and must be connected to a pull-up resistor. Table 1. Signal names Signal name Function Direction Vout Energy harvesting Output SDA Serial Data I/O SCL Serial Clock Input AC0, AC1 Antenna coils I/O VCC Supply voltage - RF WIP/BUSY Digital signal VSS Ground Analog output Digital output - Figure 2. 8-pin package connections 9RXW   9&& $&   5):,3%86< $&   6&/ 966   6'$ 069 1. See Section 31 for package dimensions, and how to identify pin 1. 14/144 DocID022712 Rev 12 M24LR64E-R Signal descriptions 2 Signal descriptions 2.1 Serial clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor must be connected from Serial Clock (SCL) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pullup resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. 2.2 Serial data (SDA) This bidirectional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull-up resistor must be connected from Serial Data (SDA) to VCC. (Figure 3 indicates how the value of the pull-up resistor can be calculated). 2.3 RF Write in progress / RF Busy (RF WIP/BUSY) This configurable output signal is used either to indicate that the M24LR64E-R is executing an internal write cycle from the RF channel or that an RF command is in progress. RF WIP and signals are available only when the M24LR64E-R is powered by the Vcc pin. It is an open drain output and a pull-up resistor must be connected from RF WIP/BUSY to VCC. 2.4 Energy harvesting analog output (Vout) This analog output pin is used to deliver the analog voltage Vout available when the Energy harvesting mode is enabled and the RF field strength is sufficient. When the Energy harvesting mode is disabled or the RF field strength is not sufficient, the energy harvesting analog voltage output Vout is in High-Z state. 2.5 Antenna coil (AC0, AC1) These inputs are used to connect the device to an external coil exclusively. It is advised not to connect any other DC or AC path to AC0 or AC1. When correctly tuned, the coil is used to power and access the device using the ISO 15693 and ISO 18000-3 mode 1 protocols. 2.5.1 Device reset in RF mode To ensure a proper reset of the RF circuitry, the RF field must be turned off (100% modulation) for a minimum tRF_OFF period of time. DocID022712 Rev 12 15/144 Signal descriptions 2.6 M24LR64E-R VSS ground VSS is the reference for the VCC supply voltage and Vout analog output voltage. 2.7 Supply voltage (VCC) This pin can be connected to an external DC supply voltage. Note: An internal voltage regulator allows the external voltage applied on VCC to supply the M24LR64E-R, while preventing the internal power supply (rectified RF waveforms) to output a DC voltage on the VCC pin. 2.7.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 119). To maintain a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually around 10 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal I²C write cycle (tW). 2.7.2 Power-up conditions When the power supply is turned on, VCC rises from VSS to VCC. The VCC rise time must not vary faster than 1V/µs. 2.7.3 Device reset in I²C mode In order to prevent inadvertent write operations during power-up, a power-on reset (POR) circuit is included. At power-up (continuous rise of VCC), the device does not respond to any I²C instruction until VCC has reached the power-on reset threshold voltage (this threshold is lower than the minimum VCC operating voltage defined in Table 119). When VCC passes over the POR threshold, the device is reset and enters the Standby power mode. However, the device must not be accessed until VCC has reached a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range. In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops below the power-on reset threshold voltage, the device stops responding to any instruction sent to it. 2.7.4 Power-down conditions During power-down (continuous decay of VCC), the device must be in Standby power mode (mode reached after decoding a Stop condition, assuming that there is no internal write cycle in progress). 16/144 DocID022712 Rev 12 M24LR64E-R Signal descriptions "USLINEPULL UPRESISTOR K Figure 3. I2C Fast mode (fC = 400 kHz): maximum Rbus value versus bus parasitic capacitance (Cbus)  2 BU S §  (ERE2BUS §#BUSNS K½ 4HE2X#TIMECONSTANT BUS BUS MUSTBEBELOWTHENS TIMECONSTANTLINEREPRESENTED ONTHELEFT 6## # BU S  2BUS  N S )£#BUS MASTER 3#, -XXX 3$!  P&   "USLINECAPACITORP&  #BUS AIB Figure 4. I2C bus protocol DocID022712 Rev 12 17/144 Signal descriptions M24LR64E-R Table 2. Device select code Device type identifier(1) Chip Enable address RW Device select code b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2(2) 1 1 RW 1. The most significant bit, b7, is sent first. 2. E2 is not connected to any external pin. It is however used to address the M24LR64E-R as described in Section 3 and Section 4. Table 3. Address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 b1 b0 Table 4. Address least significant byte b7 18/144 b6 b5 b4 DocID022712 Rev 12 b3 b2 M24LR64E-R User memory organization The M24LR64E-R is divided into 64 sectors of 32 blocks of 32 bits, as shown in Table 5. Figure 6 shows the memory sector organization. Each sector can be individually readand/or write-protected using a specific password command. Read and write operations are possible if the addressed data is not in a protected sector. The M24LR64E-R also has a 64-bit block that is used to store the 64-bit unique identifier (UID). The UID is compliant with the ISO 15963 description, and its value is used during the anticollision sequence (Inventory). This block is not accessible by the user in RF device operation and its value is written by ST on the production line. The M24LR64E-R includes an AFI register that stores the application family identifier, and a DSFID register that stores the data storage family identifier used in the anticollision algorithm. The M24LR64E-R has four 32-bit blocks that store an I2C password plus three RF password codes. Figure 5. Circuit diagram 9RXW 5RZGHFRGHU 3 User memory organization $& ((3520 5):,3%86< /DWFK 5) /RJLF , & 6&/ 6'$ $& 5)9&& 3RZHUPDQDJHPHQW &RQWDFW9&& 9&& 966 069 DocID022712 Rev 12 19/144 User memory organization M24LR64E-R Figure 6. Memory sector organization ^ĞĐƚŽƌ Ϭ ϭ Ϯ ϯ ͘͘͘ ϲϬ ϲϭ ϲϮ ϲϯ ƌĞĂ ^ĞĐƚŽƌƐĞĐƵƌŝƚLJ ƐƚĂƚƵƐ ϭ H_ISO > 1000 mA/m 15 - 30 H_ISO > 1000 mA/m 10 - 30 10% rise and fall time - 0.5 - 3.0 µs 10% minimum pulse width for bit - 7.1 - 9.44 µs MI=(A-B)/(A+B)(4) 95 - 100 % % MICARRIER 100% carrier modulation index tRFR, tRFF 100% rise and fall time - 0.5 - 3.5 µs tRFSBL 100% minimum pulse width for bit - 7 - 9.44 µs tMIN CD Minimum time from carrier generation to first data From H-field min - - 1 ms fSH Subcarrier frequency high fCC/32 - 423.75 - kHz fSL Subcarrier frequency low fCC/28 - 484.28 - kHz t1 Time for M24LR64E-R response 4224/fS 318.6 320.9 323.3 µs t2 Time between commands 4224/fS 309 311.5 314 µs Wt RF write time (including internal Verify) - - 5.75 - ms VAC0-VAC1 (4 V peak to peak) - 20 - µA f = 13.56 MHz 24.8 27.5 30.2 pF ICC_RF Operating current (Read)(5) (6) CTUN Internal tuning capacitor in SO8 VBACK Backscattered level as defined by ISO test ISO10373-7 10 - - mV VMAX_1(3) RF input voltage amplitude between AC0 and AC1, GND pad left floating, VAC0-VAC1 peak to peak(7) - - - 20 V VMAX_2(3) AC voltage between AC0 and GND or between AC1 and GND - -1 - 8.5 V DocID022712 Rev 12 125/144 RF electrical parameters M24LR64E-R Table 125. RF characteristics(1) (2) (continued) Symbol Parameter Condition Min Typ Max Unit Inventory and Read operations - 4 4.5 V VMIN_1(3) RF input voltage amplitude between AC0 and AC1, GND pad left floating, VAC0-VAC1 peak to peak(7) Write operations - 4.5 5 V VMIN_2(3) AC voltage between AC0 and GND or between AC1 and GND Inventory and Read operations - 1.8 2 V Write operations - 2 2.2 V Chip reset 2 - - ms tRF_OFF RF OFF time 1. TA = –40 to 85 °C. Characterized only. 2. All timing characterizations were performed on a reference antenna with the following characteristics: External size: 75 mm x 48 mm Number of turns: 5 Width of conductor: 0.5 mm Space between two conductors: 0.3 mm Value of the tuning capacitor in SO8: 27.5 pF (M24LR64E-R) Value of the coil: 5 µH Tuning frequency: 13.56 MHz. 3. 15% (or more) carrier modulation index offers a better signal/noise ratio and therefore a wider operating range with a better noise immunity. 4. Temperature range 0 °C to 90 °C. 5. Characterized on bench. 6. Characterized only, at room temperature only, measured at VAC0-VAC1 = 1 V peak to peak. 7. Characterized only, at room temperature only. Table 126. Operating conditions Symbol TA Parameter Min. Max. Unit -40 85 °C Ambient operating temperature Figure 81 shows an ASK modulated signal from the VCD to the M24LR64E-R. The test conditions for the AC/DC parameters are: 126/144 • Close coupling condition with tester antenna (1 mm) • M24LR64E-R performance measured at the tag antenna • M24LR64E-R synchronous timing, transmit and receive DocID022712 Rev 12 M24LR64E-R RF electrical parameters Figure 81. ASK modulated signal $ % W5)) W5)5 I&& W5)6%/ W0,1&' -36 Table 127 summarizes, respectively, the minimum AC0-AC1 input power level PAC0-AC1_min required for the Energy harvesting mode, the corresponding maximum current consumption Isink_max, and the variation of the analog voltage Vout for the various Energy harvesting fan-out configurations defined by bits b0 and b1 of the Configuration byte. Table 127. Energy harvesting(1) (2) Range Hmin(3) Pmin(4) Vout@I=0 Vout@Isink_max Isink_max@Pmin 00 3.5 A/m 100 mW 2.7 V min 4.5 V max 1.7 V 6 mA 01 2.4 A/m 60 mW 2.7 V min 4.5 V max 1.9 V 3 mA 10 1.6 A/m 30 mW 2.7 V min 4.5 V max 2.1 V 1 mA 11 1.0 A/m 16 mW 2.7 V min 4.5 V max 2.3 V 300 µA 1. Characterized only. 2. Valid from -40 °C to +85 °C. 3. Hmin characterized according to ISO10373-7 test method. 4. Pmin calculated from DC measurements. Note: It is recommended to choose the Energy Harvesting Range according to the maximum current requested by the application to avoid any disabling of Energy Harvesting mode (for example, choose Range 01 for a max consumption of 2 mA). DocID022712 Rev 12 127/144 RF electrical parameters M24LR64E-R Figure 82. Energy harvesting: Vout min vs. Isink 7PVU 
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N" *TJOL -36 Figure 83. Energy harvesting: working domain range 11 )DQRXW $ P$ :RUNLQJGRPDLQZKHQ 5DQJHLVVHOHFWHG P$ P$ P$ $P $P $P $P $P )LHOG +UPV 069 128/144 DocID022712 Rev 12 M24LR64E-R RF electrical parameters Figure 84. Energy harvesting: working domain range 10 )DQRXW $ P$ :RUNLQJGRPDLQZKHQ 5DQJHLVVHOHFWHG P$ P$ P$ $P $P $P $P $P )LHOG +UPV 069 Figure 85. Energy harvesting: working domain range 01 )DQRXW $ P$ :RUNLQJGRPDLQZKHQ 5DQJHLVVHOHFWHG P$ P$ P$ $P $P $P $P $P )LHOG +UPV 069 DocID022712 Rev 12 129/144 RF electrical parameters M24LR64E-R Figure 86. Energy harvesting: working domain range 00 )DQRXW $ :RUNLQJGRPDLQZKHQ 5DQJHLVVHOHFWHG P$ P$ P$ P$ $P $P $P $P $P )LHOG +UPV 069 130/144 DocID022712 Rev 12 M24LR64E-R 31 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 31.1 SO8N package information Figure 87. SO8N – 8-lead plastic small outline, 150 mils body width, package outline HXƒ ! ! C CCC B E PP *$8*(3/$1( $ K  % %  ! , , 62$B9 1. Drawing is not to scale. Table 128. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.170 - 0.230 0.0067 - 0.0091 D 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 DocID022712 Rev 12 131/144 Package information M24LR64E-R Table 128. SO8N – 8-lead plastic small outline, 150 mils body width, package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. Figure 88. SO8N – 8-lead plastic small outline, 150 mils body width, package recommended footprint   [  2B621B)3B9 1. Dimensions are expressed in millimeters. 132/144 DocID022712 Rev 12 M24LR64E-R 31.2 Package information UFDFN8 package information Figure 89. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline ' 1 $ % $ $ FFF  3LQ ,'PDUNLQJ ( & HHH & 6HDWLQJSODQH $ 6LGHYLHZ [ DDD &  DDD & [  7RSYLHZ ' H  'DWXP$ E  / / / / 3LQ ,'PDUNLQJ ( H / H . 7HUPLQDOWLS 'HWDLO³$´ (YHQWHUPLQDO / 1'[ H 6HH'HWDLO³$´ %RWWRPYLHZ =:EB0(B9 1. Max. package warpage is 0.05 mm. 2. Exposed copper is not systematic and can appear partially or totally according to the cross section. 3. Drawing is not to scale. 4. The central pad (E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 129. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 (2) DocID022712 Rev 12 133/144 Package information M24LR64E-R Table 129. UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 - - 0.050 - - 0.0020 - - 0.080 - - 0.0031 E2 ddd eee (3) 0.0197 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 31.3 TSSOP8 package information Figure 90.TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline  ϴ ϱ Đ ϭ ϭ  ϰ ɲ ϭ W >ϭ ď Ğ 1. Drawing is not to scale. 134/144 > Ϯ  DocID022712 Rev 12 76623$0B9 M24LR64E-R Package information Table 130. TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 CP - - 0.100 - - 0.0039 D 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1 4.300 4.400 4.500 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - α 0° - 8° 0° - 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DocID022712 Rev 12 135/144 Part numbering 32 M24LR64E-R Part numbering Table 131. Ordering information scheme for packaged devices Example: M24LR64E-R MN 6 T /2 Device type M24LR = dynamic NFC/RFID tag IC 64 = memory size in Kbit E = support for energy harvesting Operating voltage(1) R = VCC = 1.8 to 5.5 V Package MN = SO8N (150 mils width) MC = UFDFPN8 (MLP8) DW = TSSOP8 SB12I = 120 µm ± 15 µm bumped and sawn inkless wafer on 8-inch frame(2) RUW20 = 725 µm ± 25 µm unsawn inkless 8-inch wafer(2) Device grade(1) 6 = industrial: device tested with standard test flow over –40 to 85 °C Option(1) T = Tape and reel packing Capacitance(1) /2 = 27.5 pF 1. For packaged devices only. 2. Delivery type: wafer tested. Bad chip identification by STIF wafer maps available on STMicroelectronics inkless central transfer server. Note: 136/144 Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID022712 Rev 12 M24LR64E-R Part numbering Table 132. Ordering and marking information First line marking Reference M24LR64E-R Package Ordering code TSSOP08 Initial revision (0xF) Actual revision (0xE and below) M24LR64E-RDW6T/2 464EU 4FEUB MLP M24LR64E-RMC6T/2 464E 4FEB SO8N M24LR64E-RMN6T/2 24L64ER 24LFERB SB12I M24LR64E-SB12I/2 - - RUW20 M24LR64E-RUW20/2 - - DocID022712 Rev 12 137/144 Anticollision algorithm (informative) Appendix A M24LR64E-R Anticollision algorithm (informative) The following pseudocode describes how anticollision could be implemented on the VCD, using recursivity. A.1 Algorithm for pulsed slots function push (mask, address); pushes on private stack function pop (mask, address); pops from private stack function pulse_next_pause; generates a power pulse function store(M24LR64E-R_UID); stores M24LR64E-R_UID function poll_loop (sub_address_size as integer) pop (mask, address) mask = address & mask; generates new mask ; send the request mode = anticollision send_Request (Request_cmd, mode, mask length, mask value) for sub_address = 0 to (2^sub_address_size - 1) pulse_next_pause if no_collision_is_detected ; M24LR64E-R is inventoried then store (M24LR64E-R_UID) else ; remember a collision was detected push(mask,address) endif next sub_address if stack_not_empty ; if some collisions have been detected and then ; not yet processed, the function calls itself poll_loop (sub_address_size); recursively to process the last stored collision endif end poll_loop main_cycle: mask = null address = null push (mask, address) poll_loop(sub_address_size) end_main_cycle 138/144 DocID022712 Rev 12 M24LR64E-R CRC (informative) Appendix B B.1 CRC (informative) CRC error detection method The cyclic redundancy check (CRC) is calculated on all data contained in a message, from the start of the flags through to the end of Data. The CRC is used from VCD to M24LR64ER and from M24LR64E-R to VCD. Table 133. CRC definition CRC type Length Polynomial Direction Preset Residue ISO/IEC 13239 16 bits X16 + X12 + X5 + 1 = 8408h Backward FFFFh F0B8h To add extra protection against shifting errors, a further transformation on the calculated CRC is made. The one’s complement of the calculated CRC is the value attached to the message for transmission. To check received messages, the two CRC bytes are often also included in the recalculation, for ease of use. In this case, the expected value for the generated CRC is the residue F0B8h. B.2 CRC calculation example This example in C language illustrates one method of calculating the CRC on a given set of bytes comprising a message. C-example to calculate or check the CRC16 according to ISO/IEC 13239 #define #define #define POLYNOMIAL0x8408// PRESET_VALUE0xFFFF CHECK_VALUE0xF0B8 x^16 + x^12 + x^5 + 1 #define #define #define NUMBER_OF_BYTES4// Example: 4 data bytes CALC_CRC1 CHECK_CRC0 void main() { unsigned int current_crc_value; unsigned char array_of_databytes[NUMBER_OF_BYTES + 2] = {1, 2, 3, 4, 0x91, 0x39}; int number_of_databytes = NUMBER_OF_BYTES; int calculate_or_check_crc; int i, j; calculate_or_check_crc = CALC_CRC; // calculate_or_check_crc = CHECK_CRC;// This could be an other example if (calculate_or_check_crc == CALC_CRC) { number_of_databytes = NUMBER_OF_BYTES; DocID022712 Rev 12 139/144 CRC (informative) } else { M24LR64E-R // check CRC number_of_databytes = NUMBER_OF_BYTES + 2; } current_crc_value = PRESET_VALUE; for (i = 0; i < number_of_databytes; i++) { current_crc_value = current_crc_value ^ ((unsigned int)array_of_databytes[i]); for (j = 0; j < 8; j++) { if (current_crc_value & 0x0001) { current_crc_value = (current_crc_value >> 1) ^ POLYNOMIAL; } else { current_crc_value = (current_crc_value >> 1); } } } if (calculate_or_check_crc == CALC_CRC) { current_crc_value = ~current_crc_value; printf ("Generated CRC is 0x%04X\n", current_crc_value); // current_crc_value is now ready to be appended to the data stream // (first LSByte, then MSByte) } else { // check CRC if (current_crc_value == CHECK_VALUE) { printf ("Checked CRC is ok (0x%04X)\n", current_crc_value); } else { printf ("Checked CRC is NOT ok (0x%04X)\n", current_crc_value); } } } 140/144 DocID022712 Rev 12 M24LR64E-R Application family identifier (AFI) (informative) Appendix C Application family identifier (AFI) (informative) The AFI (application family identifier) represents the type of application targeted by the VCD and is used to extract from all the M24LR64E-Rs present only the one meeting the required application criteria. It is programmed by the M24LR64E-R issuer (the purchaser of the M24LR64E-R). Once locked, it cannot be modified. The most significant nibble of the AFI is used to code one specific or all application families, as defined in Table 134. The least significant nibble of the AFI is used to code one specific or all application subfamilies. Subfamily codes different from 0 are proprietary. Table 134. AFI coding(1) AFI most significant nibble AFI least significant nibble ‘0’ ‘0’ All families and subfamilies No applicative preselection ‘X’ '0 All subfamilies of family X Wide applicative preselection Meaning VICCs respond from th Examples / Note 'X '‘Y’ Only the Y subfamily of family X - ‘0’ ‘Y’ Proprietary subfamily Y only - ‘1 '‘0’, ‘Y’ Transport Mass transit, bus, airline,... '2 '‘0’, ‘Y’ Financial IEP, banking, retail,... '3 '‘0’, ‘Y’ Identification Access control,... '4 '‘0’, ‘Y’ Telecommunication Public telephony, GSM,... ‘5’ ‘0’, ‘Y’ Medical - '6 '‘0’, ‘Y’ Multimedia Internet services.... '7 '‘0’, ‘Y’ Gaming - 8 '‘0’, ‘Y’ Data Storage Portable files,... '9 '‘0’, ‘Y’ Item management - 'A '‘0’, ‘Y’ Express parcels - 'B '‘0’, ‘Y’ Postal services - 'C '‘0’, ‘Y’ Airline bags - 'D '‘0’, ‘Y’ RFU - 'E '‘0’, ‘Y’ RFU - ‘F’ ‘0’, ‘Y’ RFU - 1. X = '1' to 'F', Y = '1' to 'F' DocID022712 Rev 12 141/144 Revision history M24LR64E-R Revision history Table 135. Document revision history Date Revision Changes 12-Apr-2012 1 Initial release. 08-Jun-2012 2 Updated Section 7.1: RF communication and energy harvesting on page 42 and Figure 49: M24LR64E-R state transition diagram on page 65. Updated clock pulse width values in Table 123: I2C AC characteristics on page 122. 19-Jun-2012 3 Updated notes for Figure 49: M24LR64E-R state transition diagram. – – – – 21-Feb-2013 4 Number of sectors updated in Section 3. Updated Section 4.2. Updated Figure 6: Memory sector organization. M24LR64E changed into M24LR64x in Figure 52: M24LR64E RF-Busy management following Inventory command, Figure 56: M24LR64E RFBusy management following Write command and Figure 57: M24LR64E RF-Wip management following Write command. – Updated Table 15: Control register, Table 17: System parameter sector, Table 118: Absolute maximum ratings, Table 122: I2C DC characteristics and Table 125: RF characteristics. 07-Mar-2013 5 Added Table 132: Ordering and marking information. 6 Added “Dynamic NFC/RFID tag IC” to the title, Section 1: Description, and the M24LR definition in Table 131: Ordering information scheme for packaged devices. Updated VESD and Note 5 in Table 118: Absolute maximum ratings. Removed MB package from Figure 88: UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, package outline. 7 Updated Figure 1: Logic diagram, Figure 14: 100% modulation waveform and Figure 15: 10% modulation waveform. Updated footnote 4 in Table 123: I2C AC characteristics. Added note on Engineering samples marking in Section 32: Part numbering. 06-Nov-2015 8 Updated figure on Cover page with new wafer code SB12I. Updated Figure 10: Write cycle polling flowchart using Ack, Figure 14: 100% modulation waveform and Figure 15: 10% modulation waveform. Updated Table 118: Absolute maximum ratings and its footnote 4. Updated Section 31: Package information and its subsections. Updated Table 131: Ordering information scheme for packaged devices and added footnotes 1 and 2. 27-Apr-2016 9 Updated Table 132: Ordering and marking information. 10 Updated Features. Updated Figure 51: Description of a possible anticollision sequence and Figure 53: Stay Quiet frame exchange between VCD and M24LR64E-R. Updated Table 118: Absolute maximum ratings. Added Section 29: Write cycle definition. 12-Jun-2013 21-Nov-2014 09-May-2016 142/144 DocID022712 Rev 12 M24LR64E-R Revision history Table 135. Document revision history (continued) Date 13-Mar-2017 20-Jul-2017 Revision Changes 11 Updated image on cover page with introduction of RUW20 wafer option. Updated Features. Added footnote 4 to Figure 89: UFDFN8 - 8-lead, 2 × 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package outline. Updated Table 131: Ordering information scheme for packaged devices and Table 132: Ordering and marking information. 12 Updated caption of Figure 90: TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package outline and of Table 130: TSSOP8 – 8-lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package mechanical data. DocID022712 Rev 12 143/144 M24LR64E-R IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 144/144 DocID022712 Rev 12