M24M01-DWDW3TP/K

M24M01-A125 Automotive 1-Mbit serial I²C bus EEPROM with 1 MHz clock Datasheet - production data Features • Compatible with all I2C bus modes – 1 MHz – 400 kHz – 100 kHz TSSOP8 (DW) 169 mil width • Memory array – 1 Mbit (128 Kbytes) of EEPROM – Page size: 256 bytes – Additional Write lockable page (Identification page) • Extended temperature and voltage ranges – -40 °C to 125 °C; 2.5 V to 5.5 V • Schmitt trigger inputs for noise filtering. SO8 (MN) 150 mil width • Short Write cycle time – Byte Write within 4 ms – Page Write within 4 ms • Write cycle endurance – 4 million Write cycles at 25 °C – 1.2 million Write cycles at 85 °C – 600 k Write cycles at 125 °C • Data retention – 50 years at 125 °C – 100 years at 25 °C • ESD Protection (Human Body Model) – 4000 V • Packages – RoHS compliant and halogen-free (ECOPACK®2) February 2014 This is information on a product in full production. DocID023765 Rev 4 1/37 www.st.com Contents M24M01-A125 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Chip Enable (E2, E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.4 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 Identification page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 2/37 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.1 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.2 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 Write Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.4 Lock Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.5 Minimizing Write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 18 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.2 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.3 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 Read Identification Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 Read the lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.6 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DocID023765 Rev 4 M24M01-A125 5 Contents Application design recommendations . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Operating supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.3 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . . . 24 6 Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID023765 Rev 4 3/37 3 List of tables M24M01-A125 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. 4/37 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Address significant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device identification code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Cycling performance by groups of four bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (voltage range W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 400 kHz AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1 MHz AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TSSOP8 – 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 33 SO8N – 8 lead plastic small outline, 150 mils body width, package data . . . . . . . . . . . . . . 34 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DocID023765 Rev 4 M24M01-A125 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write mode sequences with WC = 1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Maximum Rbus value versus bus parasitic capacitance Cbus) for an I2C bus at maximum frequency fC = 1MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TSSOP8 – 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 33 SO8N – 8 lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34 DocID023765 Rev 4 5/37 5 Description 1 M24M01-A125 Description The M24M01-A125 is a 1-Mbit serial EEPROM Automotive grade device operating up to 125 °C. The M24M01-A125 is compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 1. The device is accessed by a simple serial I2C compatible interface running up to 1 MHz. The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M24M01-A125 is a byte-alterable memory (128 K × 8 bits) organized as 512 pages of 256 bytes in which the data integrity is significantly improved with an embedded Error Correction Code logic. The M24M01-A125 offers an additional Identification Page (256 bytes) in which the ST device identification can be read. This page can also be used to store sensitive application parameters which can be later permanently locked in read-only mode. Figure 1. Logic diagram 7# % % (IGHVOLTAGE GENERATOR #ONTROLLOGIC 3#, 3$! )/SHIFTREGISTER $ATA REGISTER 9DECODER !DDRESSREGISTER ANDCOUNTER PAGE )DENTIFICATIONPAGE 8DECODER -36 6/37 DocID023765 Rev 4 M24M01-A125 Description Table 1. Signal names Signal name Function Direction E2, E1 Chip Enable Input SDA Serial Data I/O SCL Serial Clock Input WC Write Control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections -- $5 % % 633         6## 7# 3#, 3$! -36 1. DU: Don't Use (if connected, must be connected to VSS) 2. See Section 9: Package mechanical data for package dimensions, and how to identify pin 1. DocID023765 Rev 4 7/37 36 Signal description M24M01-A125 2 Signal description 2.1 Serial Clock (SCL) The signal applied on this input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial Data (SDA) SDA is an input/output used to transfer data in or out of the device. SDA(out) is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected between SDA and VCC (Figure 10 indicates how to calculate the value of the pull-up resistor). 2.3 Chip Enable (E2, E1) (E2,E1) input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2) of the 7-bit device select code (see Table 2). These inputs must be tied to VCC or VSS, as shown in Figure 3. When not connected (left floating), these inputs are read as low (0). Figure 3. Device select code 6## 6## -XXX -XXX %I %I 633 633 !I 2.4 Write Control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when Write Control (WC) is driven high. Write operations are enabled when Write Control (WC) is either driven low or left floating. When Write Control (WC) is driven high, device select and address bytes are acknowledged, Data bytes are not acknowledged. 8/37 DocID023765 Rev 4 M24M01-A125 2.5 Signal description VSS (ground) VSS is the reference for the VCC supply voltage. 2.6 Supply voltage (VCC) VCC is the supply voltage pin. DocID023765 Rev 4 9/37 36 Device operation 3 M24M01-A125 Device operation The device supports the I2C protocol (see Figure 4). The I2C bus is controlled by the bus master and the device is always a slave in all communications. The device (bus master or a slave) that sends data on to the bus is defined as a transmitter; the device (bus master or a slave) is defined as a receiver when reading the data. Figure 4. I2C bus protocol 3#, 3$! 3$! )NPUT 34!24 #ONDITION 3#,  3$! -3"  3$! #HANGE 34/0 #ONDITION     !#+ 34!24 #ONDITION 3#,  3$! -3"      !#+ 34/0 #ONDITION !)" 10/37 DocID023765 Rev 4 M24M01-A125 3.1 Device operation Start condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the high state. A Start condition must precede any data transfer instruction. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition. 3.2 Stop condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven high. A Stop condition terminates communication between the device and the bus master. A Stop condition at the end of a Write instruction triggers the internal Write cycle. 3.3 Data input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven low. 3.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to acknowledge the receipt of the eight data bits. DocID023765 Rev 4 11/37 36 Device operation 3.5 M24M01-A125 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, as shown in Table 2. The device select code consists of a 4-bit device type identifier and a 2-bit Chip Enable address (E2, E1). A device select code handling any value other than 1010b (to select the memory) or 1011b (to select the Identification page) is not acknowledged by the memory device. Up to four memory devices can be connected on a single I2C bus. Each one is given a unique 2-bit code on the Chip Enable (E2, E1) inputs. When the device select code is received, the memory device only responds if the Chip Enable Address is the same as the value decoded on the E2, E1 inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. Table 2. Device select code Chip Enable address(2) Device type identifier(1) When accessing the memory When accessing the Identification page Address bit RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 1 0 E2 E1 A16 RW 1 0 1 1 E2 E1 X(3) RW 1. The most significant bit, b7, is sent first. 2. E2 and E1 bits are compared with the value read on input pins E2,E1. 3. X = don’t care. If a match occurs on the device select code, the corresponding memory device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the memory device does not match the device select code, it deselects itself from the bus, and goes into Standby mode. Once the memory device has acknowledged the device select code (Table 2), the memory device waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The memory device responds to each address byte with an acknowledge bit. Note: A: significant address bit. X: bit is Don’t Care. 12/37 DocID023765 Rev 4 M24M01-A125 Device operation Table 3. Address significant bits Memory(1) (2) Identification page (Device type identifier = 1010b) Lower address byte Upper address byte Device Select bit 1 (Device type identifier = 1011b) Random Address Read Write Read Identification page Write Identification page Lock Identification page Read lock status b16 A16 A16 X X X X b15 A15 A15 X X X X b14 A14 A14 X X X X b13 A13 A13 X X X X b12 A12 A12 X X X X b11 A11 A11 X X X X b10 A10 A10 X 0 1 0 b9 A9 A9 X X X X b8 A8 A8 X X X X b7 A7 A7 A7 A7 X X b6 A6 A6 A6 A6 X X b5 A5 A5 A5 A5 X X b4 A4 A4 A4 A4 X X b3 A3 A3 A3 A3 X X b2 A2 A2 A2 A2 X X b1 A1 A1 A1 A1 X X b0 A0 A0 A0 A0 X X 1. A: significant address bit. 2. X: bit is Don’t Care. DocID023765 Rev 4 13/37 36 Device operation 3.6 M24M01-A125 Identification page The M24M01-A125 offers an Identification Page (256 bytes) in addition to the 1 Mb memory. The Identification page contains two fields: Note: • Device identification code: the first three bytes are programmed by STMicroelectronics with the Device identification code, as shown in Table 4. • Application parameters: the bytes after the Device identification code are available for application specific data. If the end application does not need to read the Device identification code, this field can be overwritten and used to store application-specific data. Once the application-specific data are written in the Identification page, the whole Identification page should be permanently locked in Read-only mode. The instructions Read, Write and Lock Identification Page are detailed in Section 4: Instructions. Table 4. Device identification code Address in Identification page 00h 14/37 Content ST manufacturer code 2C family code 01h I 02h Memory density code DocID023765 Rev 4 Value 20h E0h 11h (1024 Kbit) M24M01-A125 4 Instructions 4.1 Write operations Instructions For a Write operation, the bus master sends a Start condition followed by a device select code with the R/W bit reset to 0. The device acknowledges this, as shown in Figure 5, and waits for the master to send two address bytes (most significant address byte sent first, followed by the least significant address byte (Table 3). The device responds to each address byte with an acknowledge bit, and then waits for the data byte. The 128 Kbytes (1 Mb) are addressed with 17 address bits, the 16 lower address bits being defined by the two address bytes and the most significant address bit (A16) being included in the Device Select code (see Table 2). When the bus master generates a Stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal Write cycle tW is then triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does not respond to any requests. After the successful completion of an internal Write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. If the Write Control input (WC) is driven High, the Write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 6. DocID023765 Rev 4 15/37 36 Instructions 4.1.1 M24M01-A125 Byte Write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified (see Figure 6). If, instead, the addressed location is not Write-protected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 5. Figure 5. Write mode sequences with WC = 0 (data write enabled) 7# !#+ !#+ "YTEADDR "YTEADDR !#+ $ATAIN 3TOP $EVSEL 3TART "YTE7RITE !#+ 27 7# !#+ "YTEADDR $EVSEL 3TART 0AGE7RITE !#+ !#+ "YTEADDR !#+ $ATAIN $ATAIN 27 7#CONTgD !#+ $ATAIN. 3TOP 0AGE7RITECONTgD !#+ 16/37 DocID023765 Rev 4 !)D M24M01-A125 Page Write The Page Write mode allows up to N(a) bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A16/A8, are the same. If more bytes are sent than will fit up to the end of the page, a condition known as “roll-over” occurs. In case of roll-over, the first bytes of the page are overwritten. The bus master sends from 1 to N(a) bytes of data, each of which is acknowledged by the device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the addressed memory location are not modified, and each data byte received by the device is not acknowledged, as shown in Figure 6. After each byte is transferred, the internal byte address counter is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 6. Write mode sequences with WC = 1 (data write inhibited) 7# !#+ !#+ "YTEADDR !#+ "YTEADDR ./!#+ $ATAIN 3TOP $EVSEL 3TART "YTE7RITE 27 7# !#+ 0AGE7RITE $EVSEL 3TART !#+ "YTEADDR !#+ "YTEADDR ./!#+ $ATAIN $ATAIN 27 7#CONTgD ./!#+ 0AGE7RITECONTgD ./!#+ $ATAIN. 3TOP 4.1.2 Instructions !)D a. N is the number of bytes in a page. DocID023765 Rev 4 17/37 36 Instructions 4.1.3 M24M01-A125 Write Identification Page The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences: • Device type identifier = 1011b • Most significant address bits A16/A8 are don't care, except for address bit A10 which must be “0”. Least significant address bits A7/A0 define the byte location inside the Identification page. If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck). 4.1.4 Lock Identification Page The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions: 4.1.5 • Device type identifier = 1011b • Address bit A10 must be ‘1’; all other address bits are don't care • The data byte must be equal to the binary value xxxx xx1x, where x is don't care Minimizing Write delays by polling on ACK The maximum Write time (tw) is shown in AC characteristics tables in Section 8: DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 7, is: 18/37 • Initial condition: a Write cycle is in progress. • Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). • Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). DocID023765 Rev 4 M24M01-A125 Instructions Figure 7. Write cycle polling flowchart using ACK :ULWHF\FOH LQSURJUHVV 6WDUWFRQGLWLRQ 'HYLFHVHOHFW ZLWK5:  12 )LUVWE\WHRILQVWUXFWLRQ ZLWK5: DOUHDG\ GHFRGHGE\WKHGHYLFH $&. UHWXUQHG Ϯ ƚy,ϭy,Ϯ ƚ,> ^ƚĂƌƚ ĐŽŶĚŝƚŝŽŶ ƚ>, ^> ƚ>> ƚy>ϭy>Ϯ ^/Ŷ ƚ,> ƚy,ϭy,Ϯ ^ /ŶƉƵƚ ƚy, ^ ŚĂŶŐĞ ƚ>y ƚ,, ƚ,> t ƚ,t, ƚt>> ^ƚŽƉ ĐŽŶĚŝƚŝŽŶ ^ƚĂƌƚ ĐŽŶĚŝƚŝŽŶ ^> ^/Ŷ ƚt ƚ,, ƚ,> tƌŝƚĞĐLJĐůĞ ƚ,> ^> ƚ>Ys ^KƵƚ 32/37 ƚ>Yy ĂƚĂǀĂůŝĚ ĂƚĂǀĂůŝĚ DocID023765 Rev 4 ƚY>ϭY>Ϯ /ϬϬϳϵϱŝ M24M01-A125 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 13. TSSOP8 – 8-lead thin shrink small outline, package outline 1. Drawing is not to scale. Table 13. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ. Min. Max. Typ. Min. Max. A - - 1.200 - - 0.0472 A1 - 0.050 0.150 - 0.0020 0.0059 A2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.0118 c - 0.090 0.200 - 0.0035 0.0079 CP - 0.100 - - 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 - - 0.0394 - - α - 0° 8° - 0° 8° 1. Values in inches are converted from mm and rounded to four decimal digits. DocID023765 Rev 4 33/37 36 Package mechanical data M24M01-A125 Figure 14. SO8N – 8 lead plastic small outline, 150 mils body width, package outline K[ƒ $ $ F FFF E H PP *$8*(3/$1( ' N  ( (  / $ / 62$ 1. Drawing is not to scale. Table 14. SO8N – 8 lead plastic small outline, 150 mils body width, package data inches (1) millimeters Symbol Typ Min Max Typ Min Max A - - 1.750 - - 0.0689 A1 - 0.100 0.250 - 0.0039 0.0098 A2 - 1.250 - - 0.0492 - b - 0.280 0.480 - 0.0110 0.0189 c - 0.170 0.230 - 0.0067 0.0091 ccc - - 0.100 - - 0.0039 D 4.900 4.800 5.000 0.1929 0.1890 0.1969 E 6.000 5.800 6.200 0.2362 0.2283 0.2441 E1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 - - 0.0500 - - h - 0.250 0.500 - 0.0098 0.0197 k - 0° 8° - 0° 8° L - 0.400 1.270 - 0.0157 0.0500 L1 1.040 - - 0.0409 - - 1. Values in inches are converted from mm and rounded to four decimal digits. 34/37 DocID023765 Rev 4 M24M01-A125 10 Part numbering Part numbering Table 15. Ordering information scheme Example: M24M01-D W MN 3 T P /K Device type M24 = I2C serial access EEPROM Device function M01-D = 1 Mbit (128 K x 8 bits) plus identification page Operating voltage W = VCC = 2.5 V to 5.5 V Package MN = SO8 (150 mil width)(1) DW = TSSOP8 (169 mil width)(1) Device grade 3 = -40 to 125 °C. Device tested with high reliability certified flow(2) Option blank = standard packing T = Tape and reel packing Plating technology P = ECOPACK® (RoHS compliant) Process /K = Manufacturing technology code 1. RoHS-compliant and halogen-free (ECOPACK2®) 2. The high reliability certified flow (HRCF) is described in quality note QNEE9801. Please ask your nearest ST sales office for a copy. For a list of available options (speed, package, etc.) or for further information on any aspect of the devices, please contact your nearest ST sales office. DocID023765 Rev 4 35/37 36 Revision history 11 M24M01-A125 Revision history Table 16. Document revision history 36/37 Date Revision Changes 24-Jan-2013 1 Initial release. 27-May-2013 2 Document reformatted. Document status changed from “Target specification” to “Preliminary data”. Updated: – Section 3.6: Identification page – Note (1) under Table 5: Absolute maximum ratings – ICC ,VIL and VOL values in Table 10: DC characteristics – Package information in Table 15: Ordering information scheme Removed information related to UFDFPN8 (MLP8) package. 19-Aug-2013 3 Document status changed from “Preliminary data” to “Production data”. Updated “VOL” row in Table 10: DC characteristics. 04-Feb-2014 4 Changed Data retention from "40 years at 55 °C" to "50 years at 125 °C" in Features. DocID023765 Rev 4 M24M01-A125 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2014 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com DocID023765 Rev 4 37/37 37