M24M02-DRCS6TP/K

M24M02-DR M24M02-R Datasheet 2-Mbit serial I²C bus EEPROM Features • SO8N (MN) 150 mil width • • WLSCP Unsawn wafer Product status link • • • • • • • Compatible with following I2C bus modes: – 1 MHz – 400 kHz – 100 kHz Memory array: – 2 Mbit (256 Kbyte) of EEPROM – Page size: 256 byte – Additional write lockable page (M24M02-DR order codes) Single supply voltage: – 1.8 V to 5.5 V over –40 °C / +85 °C Write time: – Byte write within 10 ms – Page write within 10 ms Random and sequential read modes Write protect of the whole memory array Enhanced ESD/latch-Up protection More than 4 million write cycles More than 200-years data retention Packages: – SO8N ECOPACK2 – WLCSP ECOPACK2 – Unsawn wafer (each die is tested) – RoHS compliant and halogen-free (ECOPACK2) M24M02-DR M24M02-R DS7025 - Rev 11 - October 2022 For further information contact your local STMicroelectronics sales office. www.st.com M24M02-DR M24M02-R Description 1 Description The M24M02 is a 2-Mbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 256 K × 8 bits. The M24M02-DR and M24M02-R can operate with a supply voltage from 1.8 V to 5.5 V, over an ambient temperature range of –40 °C / +85 °C. The M24M02-DR offers an additional page, named the identification page (256 byte). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. Figure 1. Logic diagram VCC E2 M24M02-xR SCL SDA WC VSS MS49601V1 Table 1. Signal names Signal name Function Direction E2 Chip enable Input SDA Serial data I/O SCL Serial clock Input WC Write control Input VCC Supply voltage - VSS Ground - Figure 2. 8-pin package connections, top view DU 1 8 DU 2 7 WC E2 3 6 SCL VSS 4 5 SDA VCC AI17727v2 DS7025 - Rev 11 1. DU: Don’t use (no signal should be applied on this pin; if connected, must be connected to VSS). 2. See Section 9 Package information for package dimensions, and how to identify pin 1. page 2/40 M24M02-DR M24M02-R Description Figure 3. WLCSP connections 1 2 4 3 3 4 2 1 A A B B C C D D Bump side (bottom view) Marking side (top view) MS38243V3 1. DU: Don’t use (no signal should be applied on this pin; if connected, must be connected to VSS). 2. See Section 9 Package information for package dimensions, and how to identify pin 1. Table 2. Signal vs. bump position DS7025 - Rev 11 Position A B C D 1 - - SCL - 2 VCC WC - SDA 3 DU - - VSS 4 - DU E2 - page 3/40 M24M02-DR M24M02-R Signal description 2 Signal description 2.1 Serial clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wired-AND with other open drain or open collector signals on the bus. A pull-up resistor must be connected (Figure 12 and Figure 13 indicate how to calculate the value of the pull-up resistor). 2.3 Chip enable (E2) This input signal is used to set the value that is to be looked for on the least significant bit b3 of the 7-bit device select code. This input must be tied to VCC or VSS, to establish the device select code as shown in Figure 4. When not connected (left floating), this input is read as low (0). Figure 4. Chip enable inputs connection VCC VCC M24xxx M24xxx Ei Ei VSS 2.4 VSS Write control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for the VCC supply voltage. DS7025 - Rev 11 page 4/40 M24M02-DR M24M02-R Supply voltage (VCC) 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8 DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). DS7025 - Rev 11 page 5/40 M24M02-DR M24M02-R Block diagram 3 Block diagram The block diagram is organized as shown below. Figure 5. Block diagram SENSE AMPLIFIERS PAGE LATCHES ARRAY SCL I/O X DECODER Y DECODER DATA REGISTER + ECC SDA WC START & STOP DETECT E2 CONTROL LOGIC IDENTIFICATION PAGE HV GENERATOR + SEQUENCER ADDRESS REGISTER DS7025 - Rev 11 page 6/40 M24M02-DR M24M02-R Device operation 4 Device operation The device supports the I2C protocol. This is summarized in Figure 6. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The device is always a slave in all communications. Figure 6. I2C bus protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition DS7025 - Rev 11 page 7/40 M24M02-DR M24M02-R Start condition 4.1 Start condition Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition. 4.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A stop condition terminates communication between the device and the bus master. A read instruction that is followed by NoAck can be followed by a stop condition to force the device into the standby mode. A stop condition at the end of a write instruction triggers the internal write cycle. 4.3 Data input During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. DS7025 - Rev 11 page 8/40 M24M02-DR M24M02-R Device addressing 4.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 3 (most significant bit first). Table 3. Device select code Device type identifier(1) Chip Enable address MSB address bits RW b7 b6 b5 b4 b3 b2 b1 b0 Device select code when addressing the memory array 1 0 1 0 E2(2) A17 A16 RW Device select code when addressing the Identification page 1 0 1 1 E2(2) X(3) X(3) RW 1. The most significant bit, b7, is sent first. 2. E2 bit value is compared to the logic level applied on the input pin E2. 3. X : Don't care bit When the device select code is received, the device only responds if the chip enable address is the same as the value on the chip enable (E2) input. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgment on serial data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into standby mode after a stop condition. DS7025 - Rev 11 page 9/40 M24M02-DR M24M02-R Instructions 5 Instructions 5.1 Write operations Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7, and waits for two address bytes. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 4. Most significant address byte A15 A14 A13 A12 A11 A10 A9 A8 Table 5. Least significant address byte A7 A6 A5 A4 A3 A2 A1 A0 The 256 Kbytes (2 Mb) are addressed with 18 address bits, the 16 lower address bits being defined by the two address bytes and the most significant address bits (A17, A16) being included in the Device Select code (see Table 4). When the bus master generates a stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. After the stop condition and the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 8. DS7025 - Rev 11 page 10/40 M24M02-DR M24M02-R Write operations 5.1.1 Byte write After the device select code and the address bytes, the bus master sends one data byte. If the addressed location is write-protected, by write control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not write-protected, the device replies with Ack. The bus master terminates the transfer by generating a stop condition, as shown in Figure 7. Figure 7. Write mode sequences with WC = 0 (data write enabled) WC ACK Byte addr ACK ACK Data in Byte addr Stop Dev sel Start Byte Write ACK RW WC ACK Dev sel Start Page Write ACK Byte addr ACK Byte addr ACK Data in 1 Data in 2 RW WC (cont’d) ACK Data in N Stop Page Write (cont’d) ACK DS7025 - Rev 11 page 11/40 M24M02-DR M24M02-R Write operations 5.1.2 Page write The page write mode allows up to 256 byte to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A17/A8, are the same. If more bytes are sent than fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 256 byte of data, each of which is acknowledged by the device if write control (WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 8. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 8. Write mode sequences with WC = 1 (data write inhibited) WC Byte write WC Page write WC (cont’d) Page write (cont’d) DS7025 - Rev 11 page 12/40 M24M02-DR M24M02-R Write operations 5.1.3 Write identification page (M24M02-DR only) The identification page (256 byte) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences: • • Device type identifier = 1011b MSB address bits A17/A8 are don't care except for address bit A10 which must be ‘0’. LSB address bits A7/A0 define the byte address inside the identification page. If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoAck). 5.1.4 Lock identification page (M24M02-DR only) The lock identification page instruction (Lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions: • • • 5.1.5 Device type identifier = 1011b Address bit A10 must be ‘1’; all other address bits are don't care The data byte must be equal to the binary value xxxx xx1x, where x is don't care ECC (error correction code) and write cycling The error correction code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 10. DS7025 - Rev 11 page 13/40 M24M02-DR M24M02-R Write operations 5.1.6 Minimizing write delays by polling on ACK During the internal write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum write time (tw) is shown in AC characteristics tables in Section 8 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 9, is: • • • Initial condition: a write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 9. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop 1. DS7025 - Rev 11 NO StartCondition YES Data for the write operation Device select with RW = 1 Continue the write operation Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the figure) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the figure). page 14/40 M24M02-DR M24M02-R Read operations 5.2 Read operations Read operations are performed independently of the state of the write control (WC) signal. After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its standby mode after a stop condition. Figure 10. Read mode sequences ACK Data out Stop Start Dev sel NO ACK RW ACK Random Address Read Byte addr Dev sel * ACK ACK Data out 1 ACK NO ACK Data out N ACK Byte addr ACK Byte addr RW ACK Dev sel * Start Dev sel * Start Data out RW RW ACK NO ACK Stop Start Dev sel Sequential Random Read ACK Byte addr RW ACK Sequential Current Read ACK Start Start Dev sel * ACK Stop Current Address Read ACK Data out1 RW NO ACK Stop Data out N Note: DS7025 - Rev 11 The seven most significant bits of the first device select code of a random read must be identical to the seven most significant bits of the device select code of the write. page 15/40 M24M02-DR M24M02-R Read operations 5.2.1 Random address read A dummy write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1 Random address read) instead of the current address Read instruction. 5.2.3 Sequential read This operation can be used after a current address read or a random address read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. 5.2.4 Read identification page (M24M02-DR only) The identification page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The identification page can be read by issuing an read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. The MSB address bits A17/A8 are don't care, the LSB address bits A7/A0 define the byte address inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the identification page from location 100d, the number of bytes should be less than or equal to 156, as the ID page boundary is 256 bytes). DS7025 - Rev 11 page 16/40 M24M02-DR M24M02-R Read operations 5.2.5 Read the lock status (M24M02-DR only) The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit if the identification page is unlocked, otherwise a NoAck bit if the identification page is locked. Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that: • • DS7025 - Rev 11 Start: the truncated command is not executed because the start condition resets the device internal logic, Stop: the device is then set back into standby mode by the stop condition. page 17/40 M24M02-DR M24M02-R Initial delivery state 6 Initial delivery state The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh). DS7025 - Rev 11 page 18/40 M24M02-DR M24M02-R Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 6 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Absolute maximum ratings Symbol Parameter Min. Max. Unit - Ambient operating temperature -40 130 °C TSTG Storage temperature -65 150 °C TLEAD Lead temperature during soldering IOL DC output current (SDA = 0) – 5 mA VIO Input or output range -0.50 6.5 V VCC Supply voltage -0.50 6.5 V VESD Electrostatic pulse (Human Body model)(2) – 3000 V see note (1) °C 1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to ANSI/ESDA/JEDEC JS-001, C1=100 pF, R1=1500 Ω). DS7025 - Rev 11 page 19/40 M24M02-DR M24M02-R DC and AC parameters 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 7. Operating conditions Symbol Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Load capacitance 0 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V VCC TA Parameter Table 8. AC measurement conditions Symbol Cbus Parameter Figure 11. AC measurement I/O waveform Input voltage levels Input and output Timing reference levels 0.8VCC 0.7VCC 0.3V CC 0.2VCC Table 9. Input parameters Symbol Parameter(1) Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 30 - kΩ VIN > 0.7 VCC 500 - kΩ ZL ZH Input impedance (E2, WC)(2) 1. Evaluated by characterization – Not tested in production. 2. Input impedance when the memory is selected (after a start condition). DS7025 - Rev 11 page 20/40 M24M02-DR M24M02-R DC and AC parameters Table 10. Cycling performance Symbol Ncycle Parameter Write cycle endurance(1) Test condition Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle(2) 1. The write cycle endurance is defined for group of four bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. The write cycle endurance is defined by characterization and qualification. 2. A write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page instruction is decoded. When using the byte write, the page write or the write identification page, refer also to Section 5.1.5 ECC (error correction code) and write cycling Table 11. Memory cell data retention Parameter Data retention(1) Test condition TA = 55 °C Min. Unit 200 Year 1. The data retention behavior is checked in production, while the 200-year limit is defined from characterization and qualification results. DS7025 - Rev 11 page 21/40 M24M02-DR M24M02-R DC and AC parameters Table 12. DC characteristics Symbol ILI ILO ICC ICC0 Parameter Input leakage current (E2, SCL, SDA) Test conditions (in addition to those in Table 7 and Table 8) Min. Max. Unit - ±2 µA - ±2 µA VCC = 1.8 V, fc = 400 kHz - 1 mA VCC = 2.5 V, fc = 400 kHz - 1 mA VCC = 5.5 V, fc = 400 kHz - 2 mA 1.8 V < VCC < 5.5 V, fc = 1 MHz - 2.5 mA - 2(1) mA - 3 µA - 5 µA - 5 µA VIN = VSS or VCC, device in Standby mode Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC Supply current (Read) Supply current (Write) Averaged value during tW 1.8 V ≤ VCC ≤ 5.5 V Device not selected,(2) VIN = VSS or VCC, VCC = 1.8 V ICC1 Standby supply current Device not selected(2), VIN = VSS or VCC, VCC = 2.5 V Device not selected(2), VIN = VSS or VCC, VCC = 5.5 V VIL VIH VOL Input low voltage 1.8 V ≤ VCC < 2.5 V -0.45 0.25 VCC V (SCL, SDA, WC) 2.5 V ≤ VCC < 5.5 V -0.45 0.30 VCC V Input high voltage 1.8 V ≤ VCC < 2.5 V 0.75 VCC VCC + 1 V (SCL, SDA, WC) 2.5 V ≤ VCC < 5.5 V 0.70 VCC VCC + 1 V IOL = 1.0 mA, VCC = 1.8 V - 0.2 V IOL = 2.1 mA, VCC = 2.5 V - 0.4 V IOL = 3.0 mA, VCC = 5.5 V - 0.4 V Output low voltage 1. Evaluated by characterization - Not tested in production. 2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). DS7025 - Rev 11 page 22/40 M24M02-DR M24M02-R DC and AC parameters Table 13. 400 kHz AC characteristics Parameter(1) Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tF SDA (out) fall time 20(3) 120 ns tXH1XH2 tR Input signal rise time (4) (4) ns tXL1XL2 tF Input signal fall time (4) (4) ns tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(5) tDH Data out hold time 100 - ns (6) tAA Clock low to next data valid (access time) 100 900 ns tQL1QL2 tCLQV (2) tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tWLDL(2)(7) tSU:WC WC set up time (before the Start condition) 0 - µs (2)(8) tHD:WC WC hold time (after the Stop condition) 1 - µs Write time - 10 ms Pulse width ignored (input filter on SCL and SDA) - single glitch - 80 ns tDHWH tW tNS (2) tWR - 1. Test conditions (in addition to those specified under Table 7 and Table 8). 2. Evaluated by characterization - Not tested in production. 3. With CL = 10 pF. 4. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 5. The min value for tCLQX (Data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the falling edge SCL. 6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 12. 7. WC=0 set up time condition to enable the execution of a WRITE command. 8. WC=0 hold time condition to enable the execution of a WRITE command. DS7025 - Rev 11 page 23/40 M24M02-DR M24M02-R DC and AC parameters Table 14. 1 MHz AC characteristics Symbol Alt. Min. Max. Unit fC fSCL Clock frequency 0 1 MHz tCHCL tHIGH Clock pulse width high 260 - ns tCLCH tLOW Clock pulse width low 400 - ns tXH1XH2 tR Input signal rise time (1) (1) ns tXL1XL2 tF Input signal fall time (1) (1) ns tQL1QL2(2) tF SDA (out) fall time 20(3) 120 ns tDXCH tSU:DAT Data in setup time 50 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(4) tDH Data out hold time 100 - ns tCLQV(5) tAA Clock low to next data valid (access time) - 450 ns tCHDL tSU:STA Start condition setup time 250 - ns tDLCL tHD:STA Start condition hold time 250 - ns tCHDH tSU:STO Stop condition setup time 250 - ns tDHDL tBUF Time between Stop condition and next Start condition 500 - ns tWLDL(2)(6) tSU:WC WC set up time (before the Start condition) 0 - µs (2)(7) tHD:WC WC hold time (after the Stop condition) 1 - µs Write time - 10 ms Pulse width ignored (input filter on SCL and SDA) - 80 ns tDHWH tW tWR tNS(2) - Parameter 1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be less than 120 ns when fC < 1 MHz. 2. Evaluated by characterization - Not tested in production. 3. With CL = 10 pF. 4. To avoid spurious start and stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 13. 6. WC=0 set up time condition to enable the execution of a WRITE command. 7. WC=0 hold time condition to enable the execution of a WRITE command. DS7025 - Rev 11 page 24/40 M24M02-DR M24M02-R DC and AC parameters Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line Pull up resistor (kΩ) 100 VCC The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left Rb us 10 xC bu s 00 Here Rbus x Cbus= 120 ns 4 =4 Rbus I²C bus master SCL M24xxx SDA ns Cbus 1 10 30 100 1000 Bus line capacitor (pF) Figure 13. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz Bus line pull-up resistor (kΩ ) 100 10 Rbu s xC bus The Rbus x Cbus time constant must be below the 150 ns time constant line represented on the left = 15 0 ns 4 VCC Rbus I²C bus master SCL M24xxx SDA Here Rbus x Cbus = 120 ns Cbus 1 10 30 100 Bus line capacitor (pF) DS7025 - Rev 11 page 25/40 M24M02-DR M24M02-R DC and AC parameters Figure 14. AC waveforms Start condition Start Stop condition condition tXL1XL2 tXH1XH2 tCHCL tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX SDA tDXCH Change tCHDH tDHDL WC tDHWH tWLDL Stop condition Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS7025 - Rev 11 tCLQX Data valid tQL1QL2 Data valid page 26/40 M24M02-DR M24M02-R Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. For die information concerning the M24M02 delivered in unsawn wafer, contact your nearest ST Sales Office. DS7025 - Rev 11 page 27/40 M24M02-DR M24M02-R SO8N package information 9.1 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 15. SO8N – Outline Package SO8N (package code O7) A2 h x 45˚ A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 E 1 L A1 L1 1. Drawing is not to scale. Table 15. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0039 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS7025 - Rev 11 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 28/40 M24M02-DR M24M02-R SO8N package information Figure 16. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS7025 - Rev 11 Dimensions are expressed in millimeters. page 29/40 M24M02-DR M24M02-R WLCSP8 package information 9.2 WLCSP8 package information This WLCSP is a 8-ball, 3.556 x 2.011 mm, wafer level chip scale package. Figure 17. WLCSP8 - Outline Package WLCSP8 (package code E1 option a) D aaa Z X H DETAIL A E e2 G Y e e1 J aaa Orientation reference (4X) TOP VIEW A A2 H F G Orientation reference BOTTOM VIEW BUMP A1 eee Z Z b(8x) ccc ddd Z Z Y SEATING PLANE DETAIL A ROTATED 900 E1_a_WLCSP8_ME_V5 1. 2. 3. 4. DS7025 - Rev 11 Drawing is not to scale. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Primary datum Z and seating plane are defined by the spherical crowns of the bump. Bump position designation per JESD 95-1, SPP-010. page 30/40 M24M02-DR M24M02-R WLCSP8 package information Table 16. WLCSP8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.500 0.540 0.580 0.0197 0.0213 0.0228 A1 - 0.190 - - 0.0075 - A2 - 0.350 - - 0.0138 - b(2) - 0.270 - - 0.0106 - D - 3.556 3.576 - 0.1400 0.1408 E - 2.011 2.031 - 0.0792 0.0800 e - 1.000 - - 0.0394 - e1 - 1.200 - - 0.0472 - e2 - 2.100 - - 0.0827 - F - 0.505 - - 0.0199 - G - 0.500 - - 0.0197 - H - 0.728 - - 0.0287 - J - 0.200 - - 0.0079 - aaa - 0.110 - - 0.0043 - bbb - 0.110 - - 0.0043 - ccc - 0.110 - - 0.0043 - ddd - 0.060 - - 0.0024 - eee - 0.060 - - 0.0024 - 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 18. WLCSP8 - Recommended footprint 2.100 0.500 1.200 1.000 ø 0.270 1. DS7025 - Rev 11 0.500 0.200 Dimensions are expressed in millimeters. page 31/40 M24M02-DR M24M02-R Ordering information 10 Ordering information Table 17. Ordering information scheme Example: M24 M02 -D R MN 6 T P /K Device type M24 = I2C serial access EEPROM Device function M02 = 2 Mbit (256 K x 8 bit) Device family Blank = Without identification page D = With identification page Operating voltage R = VCC = 1.8 V to 5.5 V Package(1) MN = SO8N (150 mil width) CS = WLCSP8 Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = ECOPACK2 Process(2) /K = Manufacturing technology code 1. All package are ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants). 2. These process letters appear on the device package (marking) and on the shipment box. Contact your nearest ST sales office for further information DS7025 - Rev 11 page 32/40 M24M02-DR M24M02-R Ordering information Table 18. Ordering information scheme (unsawn wafer) Example: M24 M02 - D R K W 20 I /90 Device type M24 = I2C serial access EEPROM Device function M02 = 2 Mbit (256 K x 8 bit) Device family D = With identification page Blank = Without Identification page Operating voltage R = VCC = 1.8 V to 5.5 V Process K = F8H Delivery form W =Unsawn wafer Wafer thickness 20 = Non-backlapped wafer Wafer testing I = Inkless test Device grade 90 = -40°C to 85°C Note: For all information concerning the M24M02 delivered in unsawn wafer, please contact your nearest ST Sales Office. Note: Parts marked as ES or E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DS7025 - Rev 11 page 33/40 M24M02-DR M24M02-R Revision history Table 19. Document revision history Date Revision 22-Dec-2010 1 Changes Initial release. Updated: 09-Feb-2011 2 • • • • • • • • Section 3.18:Read Identification Page Section 3.19: Read thelock status Figure 2: SO8 connections Table 6: Absolute maximum ratings Table 10: Input parameters Table 11: DCcharacteristics Table 12: AC characteristics at 400 kHz Table 13: 1 MHz AC characteristics Deleted: • 09-Aug-2011 3 Table 15: Available M24M02-xproducts(package, voltage range, frequency, temperature grade) Updated Figure 5: MaximumRbus value versusbusparasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1 MHz and Table 11: DCcharacteristics. Updated: 07-Feb-2012 4 25-Oct-2012 5 • • • • • Table 2: Device select code Table 3: Most significant address byte Table 4: Leastsignificant address byte. Section 3.6: Write operations Section 3.8: Page Write Updated document template and text (minor changes). Cycling updated to 4 million cycles and data retention updated to 200 years. Added WLCSP packages. Document reformatted. Removed information related to thin WLCSP package. Updated: 04-Jun-2013 6 • • • • WLCSP package silhouette on cover page Section 1: Description Figure 25: WLCSP connections Note (1) under Table 14: Absolute maximum ratings. Added Figure 57: WLCSP- 8-bump, 3.556 x 2.011 mm, wafer level chip scale package recommended footprint 23-May-2014 7 removed note on page 7, Updated Table 5: Device select code, updated section numbering for Section 5.2.4 and Section 5.2.6, updated note 1 on Table 30: Memory cell data retention, updated Figure 57: WLCSP- 8-bump, 3.556 x2.011 mm, wafer level chip scale package recommended footprint. Updated: 27-Jul-2015 8 • • • Figure 3 with note 1. Table 2 Section 9.1: SO8N package information and Section 9.2: WLCSP package information Updated: • 02-Mar-2017 9 Added: • • DS7025 - Rev 11 Figure 18: WLCSP-8-bump, 3.556 x 2.011 mm, wafer levelchip scale package recommended footprint Unsawn wafer on cover page Table 18: Ordering information scheme (unsawn wafer) page 34/40 M24M02-DR M24M02-R Date Revision Changes Added M24M02-R RPN. Updated 14-Jan-2018 10 • • • Features Figure 1: Logic diagram, Table 17: Ordering information scheme, Table18:Ordering information scheme (unsawn wafer) Updated: 18-Oct-2022 11 • • • • • DS7025 - Rev 11 WLCSP8 silouette. title of Figure 2 Section 2.2 Serial data (SDA), Section 3 Block diagram, Section 4.2 Stop condition, Section 5.2 Read operations Table 3. Device select code, Section 9.1 SO8N package information Note 1 and 2 in Table 6, note 1 in Table 9, note 1 in Table 11, note 1 in Table 12, note 2 in Table 13 and Table 14, note 2 in Table 17 page 35/40 M24M02-DR M24M02-R Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Chip enable (E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Write control (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.1 5.2 6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 Write identification page (M24M02-DR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 Lock identification page (M24M02-DR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.5 ECC (error correction code) and write cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.6 Minimizing write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.1 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.4 Read identification page (M24M02-DR only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2.5 Read the lock status (M24M02-DR only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 DS7025 - Rev 11 page 36/40 M24M02-DR M24M02-R Contents 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 10 9.1 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2 WLCSP8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 DS7025 - Rev 11 page 37/40 M24M02-DR M24M02-R List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . Signal vs. bump position . . . . . . . . . . . . . . . Device select code . . . . . . . . . . . . . . . . . . . Most significant address byte. . . . . . . . . . . . Least significant address byte . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . Operating conditions . . . . . . . . . . . . . . . . . AC measurement conditions . . . . . . . . . . . . Input parameters . . . . . . . . . . . . . . . . . . . . Cycling performance . . . . . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . . . . . DC characteristics . . . . . . . . . . . . . . . . . . . 400 kHz AC characteristics . . . . . . . . . . . . . 1 MHz AC characteristics . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . WLCSP8 - Mechanical data. . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . Ordering information scheme (unsawn wafer) Document revision history . . . . . . . . . . . . . . DS7025 - Rev 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 9 10 10 19 20 20 20 21 21 22 23 24 28 31 32 33 34 page 38/40 M24M02-DR M24M02-R List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Logic diagram. . . . . . . . . . . . . . . . . 8-pin package connections, top view . WLCSP connections . . . . . . . . . . . . Chip enable inputs connection . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequences with WC = 0 (data write enabled) . Write mode sequences with WC = 1 (data write inhibited). Write cycle polling flowchart using ACK . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 12 14 15 20 Figure 12. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 1MHz AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLCSP8 - Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DS7025 - Rev 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 4 6 25 26 28 29 30 31 page 39/40 M24M02-DR M24M02-R IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS7025 - Rev 11 page 40/40