M27C2001-55B1TR

M27C2001 2 Mbit (256Kb x 8) UV EPROM and OTP EPROM s 5V ± 10% SUPPLY VOLTAGE in READ OPERATION ACCESS TIME: 55ns LOW POWER CONSUMPTION: – Active Current 30mA at 5MHz – Standby Current 100µA 1 1 32 32 s s s s s PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100µs/word ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 61h FDIP32W (F) PDIP32 (B) DESCRIPTION The M27C2001 is a high speed 2 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large programs and is organised as 262,144 by 8 bits. The FDIP32W (window ceramic frit-seal package) and LCCC32W (leadless chip carrier package) have a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27C2001 is offered in PDIP32, PLCC32 and TSOP32 (8 x 20 mm) packages. LCCC32W (L) PLCC32 (C) TSOP32 (N) 8 x 20 mm Figure 1. Logic Diagram VCC VPP 18 A0-A17 8 Q0-Q7 P E G M27C2001 VSS AI00716B November 2000 1/17 M 27C2001 Figure 2A. DIP Connections Figure 2B. LCC Connections VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 M27C2001 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 AI00717 VCC P A17 A14 A13 A8 A9 A11 G A10 E Q7 Q6 Q5 Q4 Q3 A7 A6 A5 A4 A3 A2 A1 A0 Q0 A12 A15 A16 VPP VCC P A17 1 32 A14 A13 A8 A9 A11 G A10 E Q7 9 M27C2001 25 17 VSS Q3 Q4 Q5 Q6 AI00718 Figure 2C. TSOP Connections Table 1. Signal Names A0-A17 Q0-Q7 Address Inputs Data Outputs Chip Enable Output Enable Program Program Supply Supply Voltage Ground A11 A9 A8 A13 A14 A17 P VCC VPP A16 A15 A12 A7 A6 A5 A4 1 32 8 9 M27C2001 (Normal) 25 24 16 17 AI01153B G A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 A3 E G P VPP VCC VSS 2/17 Q1 Q2 M27C2001 Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value –40 to 125 –50 to 125 –65 to 150 –2 to 7 –2 to 7 –2 to 13.5 –2 to 14 Unit °C °C °C V V V V Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Output Disable Program Verify Program Inhibit Standby Electronic Signature Note: X = VIH or VIL, VID = 12V ± 0.5V. E VIL VIL VIL VIL VIH VIH VIL G VIL V IH V IH VIL X X VIL P X X VIL Pulse VIH X X VIH A9 X X X X X X VID VPP VCC or VSS VCC or VSS VPP VPP VPP VCC or VSS VCC Q7-Q0 Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes Table 4. Electronic Signature Identifier Manufacturer’s Code Device Code A0 VIL VIH Q7 0 0 Q6 0 1 Q5 1 1 Q4 0 0 Q3 0 0 Q2 0 0 Q1 0 0 Q0 0 1 Hex Data 20h 61h 3/17 M 27C2001 Table 5. AC Measurement Conditions High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 10ns 0 to 3V 1.5V Standard ≤ 20ns 0.4V to 2.4V 0.8V and 2V Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01822 1N914 3.3kΩ Standard 2.4V OUT CL 0.4V CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. DEVICE OPERATION The operating modes of the M27C2001 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for VPP and 12V on A9 for Electronic Signature. Read Mode The M27C2001 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27C2001 has a standby mode which reduces the supply current from 30mA to 100µA. The M27C2001 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. 4/17 M27C2001 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS Test Condition 0V ≤ VIN ≤ VCC 0V ≤ VOUT ≤ VCC E = VIL , G = VIL, IOUT = 0mA, f = 5MHz E = VIH E > VCC – 0.2V V PP = VCC Min Max ± 10 ± 10 30 1 100 10 Unit µA µA mA mA µA µA V V V V V –0.3 2 IOL = 2.1mA IOH = –400µA IOH = –100µA 2.4 VCC – 0.7V 0.8 VCC + 1 0.4 VOL VOH Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C2001 Symbol Alt Parameter Test Condition -55 (3) Min tAVQV tELQV tGLQV tEHQZ (2) t GHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL , G = V IL G = VIL E = VIL G = VIL E = VIL E = VIL , G = V IL 0 0 0 -70 -80 -90 Min Max 90 90 40 0 0 0 30 30 ns ns ns ns ns ns Unit Max Min 55 55 30 30 30 0 0 0 Max Min Max 70 70 35 30 30 0 0 0 80 80 40 30 30 Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 3. In case of 45ns speed see High Speed AC measurement conditions. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 5/17 M 27C2001 Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC) M27C2001 Symbol Alt Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ (2) tGHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -10 Max 100 100 50 30 30 0 0 0 Min -12 Max 120 120 50 40 40 0 0 0 -15/-20/-25 Min Max 150 150 60 50 50 ns ns ns ns ns ns Unit Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A17 VALID tAVQV tAXQX VALID E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ AI00719B System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line 6/17 output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supply connection point. The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. M27C2001 Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = –400µA 2.4 11.5 12.5 E = VIL –0.3 2 Test Condition 0 ≤ V IN ≤ VIH Min Max ± 10 50 50 0.8 VCC + 0.5 0.4 Unit µA mA mA V V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol tAVPL tQVPL tVPHPL t VCHPL tELPL tPLPH tPHQX tQXGL tGLQV tGHQZ (2) tGHAX Alt tAS tDS tVPS tVCS tCES tPW tDH tOES tOE tDFP tAH Parameter Address Valid to Program Low Input Valid to Program Low VPP High to Program Low VCC High to Program Low Chip Enable Low to Program Low Program Pulse Width Program High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 2 95 2 2 100 130 105 Max Unit µs µs µs µs µs µs µs µs ns ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27C2001 are in the ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in the data word. The only way to change a ’0’ to a ’1’ is by die exposure to ultraviolet light (UV EPROM). The M27C2001 is in the programming mode when V PP input is at 12.75V, E is at V IL and P is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. 7/17 M 27C2001 Figure 6. Programming and Verify Modes AC Waveforms A0-A17 tAVPL Q0-Q7 tQVPL VPP tVPHPL VCC tVCHPL E tELPL P tPLPH G tQXGL tGHAX tGLQV tGHQZ DATA IN tPHQX DATA OUT VALID PROGRAM VERIFY AI00720 Figure 7. Programming Flowchart VCC = 6.25V, VPP = 12.75V n=0 P = 100µs Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr FAIL YES CHECK ALL BYTES 1st: VCC = 6V 2nd: VCC = 4.2V AI00715C PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows the whole array to be programmed with a guaranteed margin, in a typical time of 26.5 seconds. Programming with PRESTO II consists of applying a sequence of 100µs program pulses to each byte until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27C2001s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27C2001 may be common. A TTL low level pulse applied to a M27C2001’s P input, with E low and VPP at 12.75V, will program that M27C2001. A high level E input inhibits the other M27C2001s from being programmed. Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E and G at VIL, P at VIH, VPP at 12.75V and VCC at 6.25V. 8/17 M27C2001 Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25° C ± 5°C ambient temperature range that is required when programming the M27C2001. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27C2001 with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at V IL during Electronic Signature mode. Byte 0 (A0 = VIL) represents the manufacturer code and byte 1 (A0 = VIH) the device identifier code. For the STMicroelectronics M27C2001, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27C2001 are such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Data shows that constant exposure to room level fluorescent lighting could erase a typical M27C2001 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27C2001 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27C2001 window to prevent unintentional erasure. The recommended erasure procedure for the M27C2001 is exposure to short wave ultraviolet light which has wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M27C2001 should be placed within 2.5 cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. 9/17 M 27C2001 Table 11. Ordering Information Scheme Example: Device Type M27 Supply Voltage C = 5V Device Function 2001 = 2 Mbit (256Kb x 8) Speed -55 -70 -80 -90 -10 = 55 ns = 70 ns = 80 ns = 90 ns = 100 ns (1) M27C2001 -55 X C 1 X Not For New Design (2) -12 = 120 ns -15 = 150 ns -20 = 200 ns -25 = 250 ns V CC Tolerance X = ± 5% blank = ± 10% Package F = FDIP32W B = PDIP32 L = LCCC32W C = PLCC32 N = TSOP32: 8 x 20 mm Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Optio ns X = Additional Burn-in TR = Tape & Reel Packing Note: 1. High Speed, see AC Characteristics section for further information. 2. These speeds are replaced by the 100ns. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 10/17 M27C2001 Table 12. Revision History Date June 1998 09/20/00 11/29/00 First Issue AN620 Reference removed PLCC codification changed (Table 11) Revision Details 11/17 M 27C2001 Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data Symbol A A1 A2 A3 B B1 C D D2 E E1 e eA eB L S ∅ α N 7.11 2.54 14.99 38.10 15.24 1.45 0.51 3.91 3.89 0.41 – 0.23 41.73 – – 13.06 – – 16.18 3.18 1.52 – 4° 32 2.49 – 11° 0.280 mm Typ Min Max 5.72 1.40 4.57 4.50 0.56 – 0.30 42.04 – – 13.36 – – 18.03 0.100 0.590 1.500 0.600 0.057 0.020 0.154 0.153 0.016 – 0.009 1.643 – – 0.514 – – 0.637 0.125 0.060 – 4° 32 0.098 – 11° Typ inches Min Max 0.225 0.055 0.180 0.177 0.022 – 0.012 1.655 – – 0.526 – – 0.710 Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline A2 A3 A1 B1 B D2 D S N ∅ 1 A L α eA eB C e E1 E FDIPW-a Drawing is not to scale. 12/17 M27C2001 Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data Symbol Typ A A1 A2 B B1 C D D2 E E1 e1 eA eB L S α N 2.54 15.24 38.10 15.24 1.52 mm Min – 0.38 3.56 0.38 – 0.20 41.78 – – 13.59 – – 15.24 3.18 1.78 0° 32 Max 5.08 – 4.06 0.51 – 0.30 42.04 – – 13.84 – – 17.78 3.43 2.03 10° 0.100 0.600 1.500 0.600 0.060 Typ inches Min – 0.015 0.140 0.015 – 0.008 1.645 – – 0.535 – – 0.600 0.125 0.070 0° 32 Max 0.200 – 0.160 0.020 – 0.012 1.655 – – 0.545 – – 0.700 0.135 0.080 10° Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline A2 A1 B1 B D2 D S N A L α eA eB C e1 E1 1 E PDIP Drawing is not to scale. 13/17 M 27C2001 Table 15. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Mechanical Data mm Symbol Typ A B D E e e1 e2 e3 h j L L1 K K1 N 7.62 10.16 1.02 0.51 1.27 0.51 11.23 13.72 – 0.39 – – – – 1.14 1.96 10.50 8.03 32 Min Max 2.28 0.71 11.63 14.22 – – – – – – 1.40 2.36 10.80 8.23 0.300 0.400 0.040 0.020 0.050 0.020 0.442 0.540 – 0.015 – – – – 0.045 0.077 0.413 0.316 32 Typ Min Max 0.090 0.028 0.458 0.560 – – – – – – 0.055 0.093 0.425 0.324 inches Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Outline e2 D e N j x 45o 1 L1 K E e3 e1 B K1 A h x 45o L LCCCW-a Drawing is not to scale. 14/17 M27C2001 Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol A A1 A2 B B1 D D1 D2 e E E1 E2 F R N Nd Ne CP 0.89 32 7 9 0.10 1.27 14.86 13.89 12.45 0.00 15.11 14.10 13.46 0.25 0.035 32 7 9 0.004 millimeters Typ Min 2.54 1.52 0.38 0.33 0.66 12.32 11.35 9.91 0.53 0.81 12.57 11.56 10.92 0.050 0.585 0.547 0.490 0.000 0.595 0.555 0.530 0.010 Max 3.56 2.41 Typ inches Min 0.100 0.060 0.015 0.013 0.026 0.485 0.447 0.390 0.021 0.032 0.495 0.455 0.430 Max 0.140 0.095 Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline D D1 1N A1 A2 B1 Ne E1 E F 0.51 (.020) D2/E2 B e 1.14 (.045) Nd A R CP PLCC Drawing is not to scale. 15/17 M 27C2001 Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data mm Symb Typ A A1 A2 B C D D1 E e L α N CP 0.50 0.05 0.95 0.15 0.10 19.80 18.30 7.90 0.50 0° 32 0.10 Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 8.10 0.70 5° 0.020 0.002 0.037 0.006 0.004 0.780 0.720 0.311 0.020 0° 32 0.004 Typ Min Max 0.047 0.007 0.041 0.011 0.008 0.795 0.728 0.319 0.028 5° inches Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a A1 α L Drawing is not to scale. 16/17 M27C2001 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics ® 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A . http://w ww.st.com 17/17