M27V400-100F6TR

M27V400 4 Mbit (512Kb x8 or 256Kb x16) UV EPROM and OTP EPROM NOT FOR NEW DESIGN s s M27V400 is replaced by the M27W400 3V to 3.6V LOW VOLTAGE in READ OPERATION ACCESS TIME: 100ns BYTE-WIDE or WORD-WIDE CONFIGURABLE 4 Mbit MASK ROM REPLACEMENT LOW POWER CONSUMPTION – Active Current 30mA at 8MHz – Stand-by Current 20µA 40 40 s s s s 1 1 FDIP40W (F) PDIP40 (B) s s s PROGRAMMING VOLTAGE: 12.5V ± 0.25V PROGRAMMING TIME: 50µs/word ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: B8h Figure 1. Logic Diagram DESCRIPTION The M27V400 is an 4 Mbit EPROM offered in the two ranges UV (ultra violet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems requiring large data or program storage. It is organised as either 512 Kwords of 8 bit or 256 Kwords of 16 bit. The pin-out is compatible with the most common 4 Mbit Mask ROM. The FDIP40W (window ceramic frit-seal package) has a transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written rapidly to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V400 is offered in PDIP40 package. VCC 18 A0-A17 15 Q15A–1 Q0-Q14 E G BYTEVPP M27C400 VSS AI01634 July 2000 This is information on a product still in production but not recommended for new designs. 1/14 M27V400 Figure 2. DIP Connections A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 1 40 2 39 3 38 4 37 5 36 6 35 7 34 33 8 32 9 31 10 M27C400 30 11 29 12 28 13 27 14 26 15 25 16 17 24 18 23 19 22 20 21 AI01635 Table 1. Signal Names A0-A17 Address Inputs Data Outputs Data Outputs Data Output / Address Input Chip Enable Output Enable Byte Mode / Program Supply Supply Voltage Ground A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTEVPP VSS Q15A–1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q0-Q7 Q8-Q14 Q15A–1 E G BYTEVPP VCC VSS DEVICE OPERATION The operating modes of the M27V400 are listed in the Operating Modes Table. A single power supply is required in the read mode. All inputs are TTL compatible except for V PP and 12V on A9 for the Electronic Signature. Read Mode The M27V400 has two organisations, Word-wide and Byte-wide. The organisation is selected by the signal level on the BYTEVPP pin. When BYTEVPP is at VIH the Word-wide organisation is selected and the Q15A–1 pin is used for Q15 Data Output. When the BYTEVPP pin is at V IL the Byte-wide organisation is selected and the Q15A–1 pin is used for the Address Input A–1. When the memory is logically regarded as 16 bit wide, but read in the Byte-wide organisation, then with A–1 at VIL the lower 8 bits of the 16 bit data are selected and with A–1 at VIH the upper 8 bits of the 16 bit data are selected. The M27V400 has two control functions, both of which must be logically active in order to obtain data at the outputs. In addition the Word-wide or Byte- wide organisation must be selected. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27V400 has a standby mode which reduces the supply current from 30mA to 20µA. The M27V400 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the G input. 2/14 M27V400 Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value –40 to 125 –50 to 125 –65 to 150 –2 to 7 –2 to 7 –2 to 13.5 –2 to 14 Unit °C °C °C V V V V Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is V CC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Word-wide Read Byte-wide Upper Read Byte-wide Lower Output Disable Program Verify Program Inhibit Standby Electronic Signature E VIL VIL VIL VIL VIL Pulse VIH VIH VIH VIL G VIL VIL VIL VIH VIH VIL VIH X VIL BYTEVPP VIH VIL VIL X VPP VPP VPP X VIH A9 X X X X X X X X VID Q7-Q0 Data Out Data Out Data Out Hi-Z Data In Data Out Hi-Z Hi-Z Codes Q14-Q8 Data Out Hi-Z Hi-Z Hi-Z Data In Data Out Hi-Z Hi-Z Codes Q15A–1 Data Out VIH VIL Hi-Z Data In Data Out Hi-Z Hi-Z Code Note: X = VIH or VIL, V ID = 12V ± 0.5V. Table 4. Electronic Signature Identifier Manufacturer’s Code Device Code A0 VIL VIH Q7 0 1 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 0 Q2 0 0 Q1 0 1 Q0 0 0 Hex Data 20h B8h Note: Outputs Q15-Q8 are set to '0'. 3/14 M27V400 Table 5. AC Measurement Conditions High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 10ns 0 to 3V 1.5V Standard ≤ 20ns 0.4V to 2.4V 0.8V and 2V Figure 3. Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01822 1N914 3.3kΩ Standard 2.4V OUT CL 0.4V CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance (except BYTEVPP) Input Capacitance (BYTEVPP) Output Capacitance Test Condition VIN = 0V VIN = 0V VOUT = 0V Min Max 10 120 12 Unit pF pF pF Note: 1. Sampled only, not 100% tested. Two Line Output Control Because EPROMs are usually used in larger memory arrays, this product features a 2-line control function which accommodates the use of multiple memory connection. The two-line control function allows: a. the lowest possible memory power dissipation b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 4/14 M27V400 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 5% or 3.3V ± 10%; VPP = VCC) Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current Test Condition 0V ≤ VIN ≤ VCC 0V ≤ VOUT ≤ VCC E = VIL, G = VIL, IOUT = 0mA, f = 8MHz Supply Current E = VIL, G = VIL, IOUT = 0mA, f = 5MHz Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL IOL = 2.1mA IOH = –400µA 2.4 E = VIH E > VCC – 0.2V VPP = VCC –0.3 2 20 1 20 10 0.8 VCC + 1 0.4 mA mA µA µA V V V V Min Max ±1 ±10 30 Unit µA µA mA ICC ICC1 ICC2 IPP VIL VIH (2) VOL VOH Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the supplies to the devices. The supply current I CC has three segments of importance to the system designer: the standby current, the active current and the transient peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device outputs. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor is used on every device between V CC and VSS. This should be a high frequency type of low inherent inductance and should be placed as close as possible to the device. In addition, a 4.7µF electrolytic capacitor should be used between V CC and VSS for every eight devices. This capacitor should be mounted near the power supply connection point. The purpose of this capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. Programming When delivered (and after each erasure for UV EPROM), all bits of the M27V400 are in the '1' state. Data is introduced by selectively programming '0's into the desired bit locations. Although only '0's will be programmed, both '1's and '0's can be present in the data word. The only way to change a '0' to a '1' is by die exposition to ultraviolet light (UV EPROM). The M27V400 is in the programming mode when V PP input is at 12.5V, G is at VIH and E is pulsed to V IL. The data to be programmed is applied to 16 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. V CC is specified to be 6.25V ± 0.25V. 5/14 M27V400 Table 8. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 5% or 3.3V ± 10%; VPP = VCC) M27V400 Symbol Alt Parameter Test Condition Min tAVQV tBHQV tELQV tGLQV tBLQZ (2) tEHQZ (2) tGHQZ (2) tAXQX tBLQX tACC tST tCE tOE tSTD tDF tDF tOH tOH Address Valid to Output Valid BYTE High to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid BYTE Low to Output Hi-Z Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition BYTE Low to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL E = VIL E = VIL, G = VIL G = VIL E = VIL E = VIL, G = VIL E = VIL, G = VIL 0 0 5 5 -100 Max 100 100 100 50 45 45 45 ns ns ns ns ns ns ns ns ns Unit Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP 2. Sampled only, not 100% tested. 6/14 M27V400 Figure 5. Word-Wide Read Mode AC Waveforms A0-A17 VALID tAVQV tAXQX VALID E tGLQV G tELQV Q0-Q15 tGHQZ Hi-Z tEHQZ AI01636 Note: BYTEVPP = VIH. Figure 6. Byte-Wide Read Mode AC Waveforms A–1,A0-A17 VALID tAVQV tAXQX VALID E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ AI01637 Note: BYTEVPP = VIL. 7/14 M27V400 Figure 7. BYTE Transition AC Waveforms A0-A17 VALID A–1 tAVQV BYTEVPP VALID tAXQX tBHQV Q0-Q7 tBLQX Hi-Z Q8-Q15 tBLQZ AI01638B DATA OUT DATA OUT Note: Chip Enable (E) and Output Enable (G) = VIL. Table 9. Programming Mode DC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V) Symbol ILI ICC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = –2.5mA 3.5 11.5 12.5 E = VIL –0.3 2.4 Test Condition 0 ≤ VIN ≤ VCC Min Max ±1 50 50 0.8 VCC + 0.5 0.4 Unit µA mA mA V V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 8/14 M27V400 Table 10. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.5V ± 0.25V) Symbol tAVEL tQVEL tVPHAV tVCHAV tELEH tEHQX tQXGL tGLQV tGHQZ (2) tGHAX Alt tAS tDS tVPS tVCS tPW tDH tOES tOE tDFP tAH Parameter Address Valid to Chip Enable Low Input Valid to Chip Enable Low VPP High to Address Valid VCC High to Address Valid Chip Enable Program Pulse Width Chip Enable High to Input Transition Input Transition to Output Enable Low Output Enable Low to Output Valid Output Enable High to Output Hi-Z Output Enable High to Address Transition 0 0 Test Condition Min 2 2 2 2 45 2 2 120 130 55 Max Unit µs µs µs µs µs µs µs ns ns ns Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Figure 8. Programming and Verify Modes AC Waveforms A0-A17 tAVEL Q0-Q15 DATA IN tQVEL BYTEVPP tVPHAV VCC tVCHAV E tELEH G VALID DATA OUT tEHQX tGLQV tGHQZ tGHAX tQXGL PROGRAM VERIFY AI01639 9/14 M27V400 Figure 9. Programming Flowchart Program Verify A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E at V IH and G at VIL, V PP at 12.5V and VCC at 6.25V. Electronic Signature The Electronic Signature (ES) mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The ES mode is functional in the 25°C ± 5°C ambient temperature range that is required when programming the M27V400. To activate the ES mode, the programming equipment must force 11.5V to 12.5V on address line A9 of the M27V400, with VPP = VCC = 5V. Two identifier bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All other address lines must be held at V IL during Electronic Signature mode. Byte 0 (A0 = V IL) represents the manufacturer code and byte 1 (A0 = V IH) the device identifier code. For the STMicroelectronics M27V400, these two identifier bytes are given in Table 4 and can be read-out on outputs Q7 to Q0. ERASURE OPERATION (applies to UV EPROM) The erasure characteristics of the M27V400 is such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 Å. It should be noted that sunlight and some type of fluorescent lamps have wavelengths in the 3000-4000 Å range. Research shows that constant exposure to room level fluorescent lighting could erase a typical M27V400 in about 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the M27V400 is to be exposed to these types of lighting conditions for extended periods of time, it is suggested that opaque labels be put over the M27V400 window to prevent unintentional erasure. The recommended erasure procedure for M27V400 is exposure to short wave ultraviolet light which has a wavelength of 2537 Å. The integrated dose (i.e. UV intensity x exposure time) for erasure should be a minimum of 30 W-sec/cm 2. The erasure time with this dosage is approximately 30 to 40 minutes using an ultraviolet lamp with 12000 µW/cm2 power rating. The M27V400 should be placed within 2.5cm (1 inch) of the lamp tubes during the erasure. Some lamps have a filter on their tubes which should be removed before erasure. VCC = 6.25V, VPP = 12.5V n=0 E = 50µs Pulse NO ++n = 25 YES NO VERIFY YES Last Addr NO ++ Addr FAIL YES CHECK ALL WORDS BYTEVPP =VIH 1st: VCC = 6V 2nd: VCC = 3V AI03075 PRESTO III Programming Algorithm The PRESTO III Programming Algorithm allows the whole array to be programed with a guaranteed margin in a typical time of 13 seconds. Programming with PRESTO III consists of applying a sequence of 50µs program pulses to each word until a correct verify occurs (see Figure 9). During programing and verify operation a MARGIN MODE circuit is automatically activated to guarantee that each cell is programed with enough margin. No overpromise pulse is applied since the verify in MARGIN MODE provides the necessary margin to each programmed cell. Program Inhibit Programming of multiple M27V400s in parallel with different data is also easily accomplished. Except for E, all like inputs including G of the parallel M27V400 may be common. A TTL low level pulse applied to a M27V400's E input and V PP at 12.5V, will program that M27V400. A high level E input inhibits the other M27V400s from being programmed. 10/14 M27V400 Table 11. Ordering Information Scheme Example: Device Type M27 Supply Voltage V = 3V to 3.6V Device Function 400 = 4 Mbit (512Kb x8 or 256Kb x16) Speed -100 = 100 ns VCC Tolerance blank = ± 10% X = ± 5% Package F = FDIP40W B = PDIP40 Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Options TR = Tape & Reel Packing M27V400 -100 X F 1 TR M27V400 is replaced by the M27W400 For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 11/14 M27V400 Table 12. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Mechanical Data Symb A A1 A2 A3 B B1 C D D2 E E1 e ea. be L S ∅ α N 8.13 2.54 14.99 48.26 15.24 1.45 0.51 3.91 3.89 0.41 – 0.23 51.79 – – 13.06 – – 16.18 3.18 1.52 – 4° 40 mm Typ Min Max 5.72 1.40 4.57 4.50 0.56 – 0.30 52.60 – – 13.36 – – 18.03 – 2.49 – 11° 0.320 0.100 0.590 1.900 0.600 0.057 0.020 0.154 0.153 0.016 – 0.009 2.039 – – 0.514 – – 0.637 0.125 0.060 – 4° 40 Typ inches Min Max 0.225 0.055 0.180 0.177 0.022 – 0.012 2.071 – – 0.526 – – 0.710 – 0.098 – 11° Figure 10. FDIP40W - 40 lead Ceramic Frit-seal DIP with window, Package Outline A2 A3 A1 B1 B D2 D S N ∅ 1 A L α eA eB C e E1 E FDIPW-a Drawing is not to scale. 12/14 M27V400 Table 13. PDIP40 - 40 pin Plastic DIP, 600 mils width, Package Mechanical Data mm Symb Typ A A1 A2 B B1 C D D2 E E1 e1 ea. be L S α N 2.54 15.24 48.26 4.45 0.64 Min – 0.38 3.56 0.38 1.14 0.20 51.78 – 14.80 13.46 – – 15.24 3.05 1.52 0° 40 Max – – 3.91 0.53 1.78 0.31 52.58 – 16.26 13.99 – – 17.78 3.81 2.29 15° 0.100 0.600 1.900 Typ 0.175 0.025 Min – 0.015 0.140 0.015 0.045 0.008 2.039 – 0.583 0.530 – – 0.600 0.120 0.060 0° 40 0.700 0.150 0.090 15° Max – – 0.154 0.021 0.070 0.012 2.070 – 0.640 0.551 – inches Figure 11. PDIP40 - 40 lead Plastic DIP, 600 mils width, Package Outline A2 A1 B1 B D2 D S N A L α eA eB C e1 E1 1 E PDIP Drawing is not to scale. 13/14 M27V400 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics ® 2000 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 14/14