M27V512-100K1TR

M27V512 512 Kbit (64Kb x8) Low Voltage UV EPROM and OTP EPROM s LOW VOLTAGE READ OPERATION: 3V to 3.6V FAST ACCESS TIME: 100ns LOW POWER CONSUMPTION: – Active Current 10mA at 5MHz – Standby Current 10µA 28 28 s s s s s PROGRAMMING VOLTAGE: 12.75V ± 0.25V PROGRAMMING TIME: 100µs/byte (typical) ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: 3Dh 1 1 FDIP28W (F) PDIP28 (B) DESCRIPTION The M27V512 is a low voltage 512 Kbit EPROM offered in the two ranges UV (ultra viloet erase) and OTP (one time programmable). It is ideally suited for microprocessor systems and is organized as 65,536 by 8 bits. The M27V512 operates in the read mode with a supply voltage as low as 3V. The decrease in operating power allows either a reduction of the size of the battery or an increase in the time between battery recharges. The FDIP28W (window ceramic frit-seal package) has transparent lid which allows the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the device by following the programming procedure. For applications where the content is programmed only one time and erasure is not required, the M27V512 is offered in PDIP28, PLCC32 and TSOP28 (8 x 13.4 mm) packages. Table 1. Signal Names A0-A15 Q0-Q7 E GV PP VCC VSS Address Inputs Data Outputs Chip Enable Output Enable Supply Voltage Ground PLCC32 (K) TSOP28 (N) 8 x 13.4mm Figure 1. Logic Diagram VCC 16 A0-A15 8 Q0-Q7 E GVPP M27V512 VSS AI00732B May 1998 1/16 M 27V512 Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections AI01907 VSS DU Q3 Q4 Q5 AI00733B A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M27V512 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC A14 A13 A8 A9 A11 GVPP A10 E Q7 Q6 Q5 Q4 Q3 A6 A5 A4 A3 A2 A1 A0 NC Q0 A7 A12 A15 DU VCC A14 A13 1 32 A8 A9 A11 NC GVPP A10 E Q7 Q6 9 M27V512 25 17 Q1 Q2 Warning: NC = Not Connected, DU = Don’t Use Figure 2C. TSOP Pin Connections GVPP A11 A9 A8 A13 A14 VCC A15 A12 A7 A6 A5 A4 A3 22 21 28 1 M27V512 15 14 7 8 AI00734B A10 E Q7 Q6 Q5 Q4 Q3 VSS Q2 Q1 Q0 A0 A1 A2 DEVICE OPERATION The operating modes of the M27V512 are listed in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL levels except for GVPP and 12V on A9 for Electronic Signature. Read Mode The M27V512 has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data to the output pins, independent of device selection. Assuming that the addresses are stable, the address access time (tAVQV) is equal to the delay from E to output (tELQV). Data is available at the output after a delay of t GLQV from the falling edge of G, assuming that E has been low and the addresses have been stable for at least tAVQV-tGLQV. Standby Mode The M27V512 has a standby mode which reduces the supply current from 10mA to 10µA with low voltage operation VCC ≤ 3.6V, see Read Mode DC Characteristics table for details.The M27V512 is placed in the standby mode by applying a CMOS high signal to the E input. When in the standby mode, the outputs are in a high impedance state, independent of the GVPP input. 2/16 M27V512 Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) VCC VA9 (2) VPP Parameter Ambient Operating Temperature (3) Temperature Under Bias Storage Temperature Input or Output Voltage (except A9) Supply Voltage A9 Voltage Program Supply Voltage Value –40 to 125 –50 to 125 –65 to 150 –2 to 7 –2 to 7 –2 to 13.5 –2 to 14 Unit °C °C °C V V V V Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode Read Output Disable Program Program Inhibit Standby Electronic Signature Note: X = VIH or VIL, VID = 12V ± 0.5V. E VIL VIL VIL Pulse V IH V IH VIL GV PP V IL VIH VPP VPP X V IL A9 X X X X X VID Q0-Q7 Data Out Hi-Z Data In Hi-Z Hi-Z Codes Table 4. Electronic Signature Identifier Manufacturer’s Code Device Code A0 VIL VIH Q7 0 0 Q6 0 0 Q5 1 1 Q4 0 1 Q3 0 1 Q2 0 1 Q1 0 0 Q0 0 1 Hex Data 20h 3Dh Two Line Output Control Because EPROMs are usually used in larger memory arrays, the product features a 2 line control function which accommodates the use of multiple memory connection. The two line control function allows: a. the lowest possible memory power dissipation, b. complete assurance that output bus contention will not occur. For the most efficient use of these two control lines, E should be decoded and used as the primary device selecting function, while G should be made a common connection to all devices in the array and connected to the READ line from the system control bus. This ensures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is required from a particular memory device. 3/16 M 27V512 Table 5. AC Measurement Conditions High Speed Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 10ns 0 to 3V 1.5V Standard ≤ 20ns 0.4V to 2.4V 0.8V and 2V Figure 3. Testing Input Output Waveform Figure 4. AC Testing Load Circuit 1.3V High Speed 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V AI01822 1N914 3.3kΩ Standard 2.4V OUT CL 0.4V CL = 30pF for High Speed CL = 100pF for Standard CL includes JIG capacitance AI01823B Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol C IN COUT Parameter Input Capacitance Output Capacitance Test Condit ion VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. System Considerations The power switching characteristics of Advanced CMOS EPROMs require careful decoupling of the devices. The supply current, ICC, has three segments that are of interest to the system designer: the standby current level, the active current level, and transient current peaks that are produced by the falling and rising edges of E. The magnitude of the transient current peaks is dependent on the capacitive and inductive loading of the device at the output. The associated transient voltage peaks can be suppressed by complying with the two line output control and by properly selected decoupling capacitors. It is recommended that a 0.1µF ceramic capacitor be used on every device between VCC and VSS. This should be a high frequency capacitor of low inherent inductance and should be placed as close to the device as possible. In addition, a 4.7µF bulk electrolytic capacitor should be used between VCC and VSS for every eight devices. The bulk capacitor should be located near the power supplyconnection point.The purpose of the bulk capacitor is to overcome the voltage drop caused by the inductive effects of PCB traces. 4/16 M27V512 Table 7. Read Mode DC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC) Symbol ILI ILO ICC ICC1 ICC2 IPP VIL VIH (2) VOL VOH VOH Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL Output High Voltage CMOS IOL = 2.1mA IOH = –400µA IOH = –100µA 2.4 VCC – 0.7V Test Condition 0V ≤ VIN ≤ VCC 0V ≤ VOUT ≤ VCC E = VIL, G = VIL, IOUT = 0mA, f = 5MHz, VCC ≤ 3.6V E = VIH E > VCC – 0.2V, VCC ≤ 3.6V VPP = VCC –0.3 2 Min Max ± 10 ± 10 10 1 10 10 0.8 VCC + 1 0.4 Unit µA µA mA mA µA µA V V V V V Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Maximum DC voltage on Output is VCC +0.5V. Table 8A. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC) M27V512 Symbol Alt Parameter Test Condition -100 (3) Min tAVQV tELQV tGLQV tEHQZ (2) t GHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 Max 100 100 45 30 30 0 0 0 -120 Min Max 120 120 45 35 35 ns ns ns ns ns ns Unit Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. 5/16 M 27V512 Table 8B. Read Mode AC Characteristics (1) (TA = 0 to 70 °C or –40 to 85 °C; VCC = 3.3V ± 10%; VPP = VCC)) M27V512 Symbol Alt Parameter Test Condition Min tAVQV tELQV tGLQV tEHQZ (2) t GHQZ (2) tAXQX tACC tCE tOE tDF tDF tOH Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 -150 Max 150 150 50 40 40 0 0 0 -200 Min Max 200 200 60 50 50 ns ns ns ns ns ns Unit Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP. 2. Sampled only, not 100% tested. Figure 5. Read Mode AC Waveforms A0-A15 VALID tAVQV tAXQX VALID E tGLQV G tELQV Q0-Q7 tGHQZ Hi-Z tEHQZ AI00735B Programming The M27V512 has been designed to be fully compatible with the M27C512 and has the same electronic signature. As a result the M27V512 can be programmed as the M27C512 on the same programming equipments applying 12.75V on VPP and 6.25V on VCC by the use of the same PRESTO IIB algorithm. When delivered (and after each erasure for UV EPROM), all bits of the M27V512 are in the ’1’ state. Data is introduced by selectively programming ’0’s into the desired bit locations. Although only ’0’s will be programmed, both ’1’s and ’0’s can be present in the data word. The only way to change a ’0’ to a ’1’ is by die exposure to ul- traviolet light (UV EPROM). The M27V512 is in the programming mode when VPP input is at 12.75V and E is pulsed to VIL. The data to be programmed is applied to 8 bits in parallel to the data output pins.The levels required for the address and data inputs are TTL. VCC is specified to be 6.25V ± 0.25V. The M27V512 can use PRESTO IIB Programming Algorithm that drastically reduces the programming time (typically less than 6 seconds). Nevertheless to achieve compatibility with all programming equipments, PRESTO Programming Algorithm can be used as well. 6/16 M27V512 Table 9. Programming Mode AC Characteristics (1) (TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V) Symbol ILI I CC IPP VIL VIH VOL VOH VID Parameter Input Leakage Current Supply Current Program Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage TTL A9 Voltage IOL = 2.1mA IOH = –1mA 3.6 11.5 12.5 E = VIL –0.3 2 Test Condition V IL