M29DW128F70ZA6E

M29DW128F 128 Mbit (16Mb x8 or 8Mb x16, Multiple Bank, Page, Boot Block) 3V supply Flash memory Feature summary ■ Supply voltage – VCC = 2.7V to 3.6V for Program, Erase and Read – VPP =12V for Fast Program (optional) Asynchronous Random/Page Read – Page width: 8 Words – Page access: 25, 30ns – Random access: 60, 70ns Programming time – 10µs per Byte/Word typical – 4 Words / 8 Bytes Program – 32-Word Write Buffer Erase Verify Memory blocks – Quadruple Bank Memory Array: 16Mbit+48Mbit+48Mbit+16Mbit – Parameter Blocks (at Top and Bottom) Dual Operation – While Program or Erase in one bank, Read in any of the other banks Program/Erase Suspend and Resume modes – Read from any Block during Program Suspend – Read and Program another Block during Erase Suspend Unlock Bypass Program – Faster Production/Batch Programming Common Flash Interface – 64 bit Security Code 100,000 Program/Erase cycles per block ■ ■ TSOP56 (NF) 14 x 20mm BGA ■ TBGA64 (ZA) 10 x 13mm Low power consumption – Standby and Automatic Standby Hardware Block Protection – VPP/WP Pin for fast program and write protect of the four outermost parameter blocks Security features – Standard Protection – Password Protection Extended Memory Block – Extra block used as security block or to store additional information Electronic Signature – Manufacturer Code: 0020h – Device Code: 227Eh + 2220h + 2200h ECOPACK® packages available ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ October 2006 Rev 7 1/94 www.st.com 1 Contents M29DW128F Contents 1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 14 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VCC supply voltage (2.7V to 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 3.2 3.3 3.4 3.5 3.6 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Special Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 Read Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Verify Extended Block Protection Indicator . . . . . . . . . . . . . . . . . . . . . . 19 Verify Block Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Hardware Block Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Temporary Unprotect of high voltage Protected Blocks . . . . . . . . . . . . . 20 4 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/94 M29DW128F Contents 4.2 Temporary Block Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Software Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 Standard Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 5.1.2 Block Lock/Unlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Non-Volatile Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Password Protection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2.1 5.2.2 Block Lock/Unlock Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Non-Volatile Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 Standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 6.1.9 6.1.10 6.1.11 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Blank Verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Program Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Program Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.2.6 6.2.7 6.2.8 6.2.9 6.2.10 6.2.11 Write to Buffer and Program command . . . . . . . . . . . . . . . . . . . . . . . . . 36 Write to Buffer and Program Confirm command . . . . . . . . . . . . . . . . . . 37 Write to Buffer and Program Abort and Reset command . . . . . . . . . . . 37 Double Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Quadruple Word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Double byte Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Quadruple byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Octuple byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.3 Block Protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.3.1 Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3/94 Contents 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12 6.3.13 6.3.14 6.3.15 6.3.16 6.3.17 6.3.18 6.3.19 M29DW128F Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Set Extended Block Protection bit command . . . . . . . . . . . . . . . . . . . . . 42 Verify Extended Block Protection bit command . . . . . . . . . . . . . . . . . . . 42 Password Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Password Verify command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Password Protection Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . 43 Set Password Protection mode command . . . . . . . . . . . . . . . . . . . . . . . 43 Verify Password Protection mode command . . . . . . . . . . . . . . . . . . . . . 43 Set Standard Protection mode command . . . . . . . . . . . . . . . . . . . . . . . 44 Verify Standard Protection mode command . . . . . . . . . . . . . . . . . . . . . 44 Set Non-Volatile Modify Protection bit command . . . . . . . . . . . . . . . . . . 44 Verify Non-Volatile Modify Protection bit command . . . . . . . . . . . . . . . . 44 Clear Non-Volatile Modify Protection bits command . . . . . . . . . . . . . . . 45 Set Lock bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clear Lock bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Verify Lock bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Set Lock-Down bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Verify Lock-Down bit command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.1 7.2 7.3 7.4 7.5 7.6 Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Write to Buffer and Program Abort bit (DQ1) . . . . . . . . . . . . . . . . . . . . . . 50 8 9 10 11 12 Dual Operations and Multiple Bank architecture . . . . . . . . . . . . . . . . . 53 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/94 M29DW128F Contents Appendix A Block addresses and Read/Modify Protection Groups . . . . . . . . . 69 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Appendix C Extended Memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 C.1 C.2 Factory Locked Section of the Extended Block . . . . . . . . . . . . . . . . . . . . . 83 Customer Lockable Section of the Extended Block. . . . . . . . . . . . . . . . . . 84 Appendix D High Voltage Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 D.1 D.2 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Appendix E Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 5/94 List of tables M29DW128F List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus operations, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read Electronic Signature, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Block Protection, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus operations, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read Electronic Signature, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Block Protection, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Hardware Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Block Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Standard Commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Standard Commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Fast Program Commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Fast Program Commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Block Protection Commands, 8-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Block Protection Commands, 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Protection Command Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Program, Erase Times and Program, Erase Endurance Cycles. . . . . . . . . . . . . . . . . . . . . 48 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Dual Operations allowed in other Banks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Dual Operations allowed in same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Write AC characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Write AC characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Toggle and Alternative Toggle bits AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data . . . 66 TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data. . . . . . . 67 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Block Addresses and Protection Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 CFI Query System Interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Primary Algorithm-Specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Extended Block Address and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Programmer technique Bus operations, 8-bit or 16-bit mode . . . . . . . . . . . . . . . . . . . . . . . 86 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6/94 M29DW128F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 TBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Protection State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Software Protection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Random Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Page Read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Write AC waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Write AC waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Toggle and Alternative Toggle bits mechanism, Chip Enable Controlled . . . . . . . . . . . . . . 63 Toggle and Alternative Toggle bits mechanism, Output Enable Controlled . . . . . . . . . . . . 63 Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing) . . . . . . . 64 Reset/Block Temporary Unprotect During Program/Erase Operation AC waveforms . . . . 64 Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline . . . . . . . . . . . 66 TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline . . . . . . . . . . . . . . 67 Programmer equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Programmer equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 In-System equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 In-System equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Write to Buffer and Program flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . 91 7/94 Summary description M29DW128F 1 Summary description The M29DW128F is a 128 Mbit (16Mb x8 or 8Mb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6V) supply. At Power-up the memory defaults to its Read mode. The M29DW128F features an asymmetrical block architecture, with 16 parameter and 254 main blocks, divided into four Banks, A, B, C and D, providing multiple Bank operations. While programming or erasing in one bank, read operations are possible in any other bank. The bank architecture is summarized in Table 2. Eight of the Parameter Blocks are at the top of the memory address space, and eight are at the bottom. Program and Erase commands are written to the Command Interface of the memory. An onchip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The Chip Enable, Output Enable and Write Enable signals control the bus operations of the memory. They allow simple connection to most microprocessors, often without additional logic. The device supports Asynchronous Random Read and Page Read from all blocks of the memory array. The M29DW128F has one extra 256 byte block (Extended Block) that can be accessed using a dedicated command. The Extended Block can be protected and so is useful for storing security information. However the protection is irreversible, once protected the protection cannot be undone. Each block can be erased independently, so it is possible to preserve valid data while old data is erased. The device features four different levels of hardware and software block protection to avoid unwanted program or erase (modify). The software block protection features are available in 16 bit memory organization only: ● Hardware Protection: – – The VPP/WP provides a hardware protection of the four outermost parameter blocks (two at the top and two at the bottom of the address space). The RP pin temporarily unprotects all the blocks previously protected using a High Voltage Block Protection technique (see Appendix D: High Voltage Block Protection). Standard Protection Password Protection ● Software Protection – – The memory is offered in TSOP56 (14 x 20mm) and TBGA64 (10 x 13mm, 1mm pitch) packages. The 8-bit Bus mode is only available when the M29DW128F is delivered in TSOP56 package. In order to meet environmental requirements, ST offers the M29DW128F in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. The memory is supplied with all the bits erased (set to ’1’). 8/94 M29DW128F Table 1. A0-A22 DQ0-DQ7 DQ8-DQ14 DQ15A–1 E G W RP RB BYTE VCC VPP/WP VSS NC Summary description Signal names Address Inputs Data Inputs/Outputs Data Inputs/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset/Block Temporary Unprotect Ready/Busy Output Byte/Word Organization Select(1) Supply voltage VPP/Write Protect Ground Not Connected Internally 1. The x8 organization is only available in TSOP56 Package while the x16 organization is available for both packages. Figure 1. Logic diagram VCC VPP/WP 23 A0-A22 W E G RP BYTE M29DW128F 15 DQ0-DQ14 DQ15A–1 RB VSS AI09208b 9/94 Summary description Table 2. Bank M29DW128F Bank architecture Parameter Blocks Bank size No. of Blocks 8 — — 8 Block size 8 Kbytes/ 4 KWords — — 8 Kbytes/ 4 KWords No. of Blocks 31 96 96 31 Main Blocks Block size 64 Kbytes/ 32 KWords 64 Kbytes/ 32 KWords 64 Kbytes/ 32 KWords 64 Kbytes/ 32 KWords A B C D 16 Mbit 48 Mbit 48 Mbit 16 Mbit Figure 2. TSOP connections NC A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 W RP A21 VPP/WP RB A18 A17 A7 A6 A5 A4 A3 A2 A1 NC NC 1 56 14 43 M29DW128F 15 42 NC NC A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 NC VCC AI09209c 28 29 10/94 M29DW128F Figure 3. TBGA connections (top view through package) 1 2 3 4 5 6 7 Summary description 8 A NC A3 A7 RB W A9 A13 NC B NC A4 A17 VPP/WP RP A8 A12 A22 C NC A2 A6 A18 A21 A10 A14 NC D NC A1 A5 A20 A19 A11 A15 VCC E NC A0 DQ0 DQ2 DQ5 DQ7 A16 VSS F VCC E DQ8 DQ10 DQ12 DQ14 NC NC G NC G DQ9 DQ11 VCC DQ13 DQ15 NC H NC VSS DQ1 DQ3 DQ4 DQ6 VSS NC AI09210c 11/94 Summary description Figure 4. Block Addresses (x8) (x8) Address lines A22-A0, DQ15A-1 M29DW128F 000000h 8 KBytes 001FFFh Total of 8 Parameter Blocks 00E000h 8 KBytes Bank A 00FFFFh 010000h 64 KBytes 01FFFFh Total of 31 Main Blocks 800000h 64 KBytes 80FFFFh Bank C Total of 96 Main Blocks DF0000h 64 KBytes DFFFFFh E00000h 64 KBytes E0FFFFh Total of 31 Main Blocks 1F0000h 64 KBytes 1FFFFFh 200000h 64 KBytes 20FFFFh Bank B Total of 96 Main Blocks Bank D FE0000h 64 KBytes FEFFFFh FF0000h 8 KBytes FF1FFFh Total of 8 Parameter Blocks FFE000h 64 KBytes 8 KBytes FFFFFFh 7F0000h 7FFFFFh AI08966 1. Also see Appendix A and Table 34 for a full listing of the Block Addresses. 12/94 M29DW128F Figure 5. Block Addresses (x16) (x16) Address lines A22-A0 Summary description 000000h 4 KWords 000FFFh Total of 8 Parameter Blocks 007000h 4 KWords Bank A 007FFFh 008000h 32 KWords 00FFFFh Total of 31 Main Blocks Bank C 400000h 32 KWords 407FFFh Total of 96 Main Blocks 6F8000h 32 KWords 6FFFFFh 700000h 32 KWords 707FFFh Total of 31 Main Blocks 0F8000h 32 KWords 0FFFFFh 100000h 32 KWord 107FFFh Bank B Total of 96 Main Blocks Bank D 7F0000h 32 KWords 7F7FFFh 7F8000h 4 KWords 7F8FFFh Total of 8 Parameter Blocks 7FF000h 32 KWords 4 KWords 7FFFFFh 3F8000h 3FFFFFh AI08967 1. Also see Appendix A, Table 34 for a full listing of the Block Addresses. 13/94 Signal descriptions M29DW128F 2 Signal descriptions See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address Inputs (A0-A22) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. 2.2 Data Inputs/Outputs (DQ0-DQ7) The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. 2.3 Data Inputs/Outputs (DQ8-DQ14) The Data I/O outputs the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. 2.4 Data Input/Output or Address Input (DQ15A–1) When the device is in x16 Bus mode, this pin behaves as a Data Input/Output pin (as DQ8DQ14). When the device is in x8 Bus mode, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the addressed Word, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when the device operates in x16 bus mode and references to the Address Inputs to include this pin when the device operates in x8 bus mode except when stated explicitly otherwise. 2.5 Chip Enable (E) The Chip Enable pin, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.6 Output Enable (G) The Output Enable pin, G, controls the Bus Read operation of the memory. 14/94 M29DW128F Signal descriptions 2.7 Write Enable (W) The Write Enable pin, W, controls the Bus Write operation of the memory’s Command Interface. 2.8 VPP/Write Protect (VPP/WP) The VPP/Write Protect pin provides two functions. The VPP function allows the memory to use an external high voltage power supply to reduce the time required for Program operations. This is achieved by bypassing the unlock cycles and/or using the multiple Word (2 or 4 at-a-time) or multiple byte Program (2, 4 or 8 at-a-time) commands. The Write Protect function provides a hardware method of protecting the four outermost boot blocks (two at the top, and two at the bottom of the address space). When VPP/Write Protect is Low, VIL, the memory protects the four outermost boot blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect is Low, even when RP is at VID. When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status of the four outermost boot blocks. Program and Erase operations can now modify the data in these blocks unless the blocks are protected using Block Protection. Applying VPPH to the VPP/WP pin will temporarily unprotect any block previously protected (including the four outermost parameter blocks) using a High Voltage Block Protection technique (In-System or Programmer technique). See Table 9: Hardware Protection for details. When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes. During Unlock Bypass Program operations the memory draws IPP from the pin to supply the programming circuits. See the description of the Unlock Bypass command in the Command Interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than tVHVPP, see Figure 20. Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the memory may be left in an indeterminate state. The VPP/Write Protect pin must not be left floating or unconnected or the device may become unreliable. A 0.1µF capacitor should be connected between the VPP/Write Protect pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Unlock Bypass Program, IPP. 15/94 Signal descriptions M29DW128F 2.9 Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique (In-System or Programmer technique). Note that if VPP/WP is at VIL, then the four outermost parameter blocks will remain protected even if RP is at VID. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 30: Reset/Block Temporary Unprotect AC characteristics and Figure 18 and Figure 19 for more details. Holding RP at VID will temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique. Program and erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. 2.10 Ready/Busy Output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or erase operation. During Program or erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 30: Reset/Block Temporary Unprotect AC characteristics and Figure 18 and Figure 19. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.11 Byte/Word Organization Select (BYTE) It is used to switch between the x8 and x16 Bus modes of the memory when the M29DW128F is delivered in TSOP56 package. When Byte/Word Organization Select is Low, VIL, the memory is in x8 mode, when it is High, VIH, the memory is in x16 mode. 16/94 M29DW128F Signal descriptions 2.12 VCC supply voltage (2.7V to 3.6V) VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during Program and erase operations, ICC2. 2.13 VSS Ground VSS is the reference for all voltage measurements. The device features two VSS pins both of which must be connected to the system ground. 17/94 Bus operations M29DW128F 3 Bus operations There are five standard bus operations that control the device. These are Bus Read (Random and Page modes), Bus Write, Output Disable, Standby and Automatic Standby. Dual operations are possible in the M29DW128F, thanks to its multiple bank architecture. While programming or erasing in one banks, read operations are possible in any of the other banks. Write operations are only allowed in one bank at a time. See Table 3 and Table 6, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable, Write Enable, and Reset/Block Temporary Unprotect pins are ignored by the memory and do not affect bus operations. 3.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface. To speed up the read operation the memory array can be read in Page mode where data is internally read and stored in a page buffer. The Page has a size of 8 Words and is addressed by the address inputs A0-A2. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 12: Random Read AC waveforms, Figure 13: Page Read AC waveforms, and Table 26: Read AC characteristics, for details of when the output becomes valid. 3.2 Bus Write Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 14 and Figure 15, Write AC Waveforms, and Table 27 and Table 28, Write AC Characteristics, for details of the timing requirements. 3.3 Output Disable The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. 3.4 Standby When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 25: DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. 18/94 M29DW128F Bus operations 3.5 Automatic Standby If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. 3.6 Special Bus operations Additional bus operations can be performed to read the Electronic Signature, verify the Protection Status of the Extended Memory Block (second section), and apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. 3.6.1 Read Electronic Signature The memory has two codes, the Manufacturer code and the Device code used to identify the memory. These codes can accessed by performing read operations with control signals and addresses set as shown in Table 4 and Table 6. These codes can also be accessed by issuing an Auto Select command (see Section 6.1.2: Auto Select command). 3.6.2 Verify Extended Block Protection Indicator The Extended Block is divided in two sections of which one is Factory Locked and the second one is either Customer Lockable or Customer Locked. The Protection Status of the second section of the Extended Block (Customer Lockable or Customer Locked) can be accessed by reading the Extended Block Protection Indicator. This is performed by applying the signals as shown in Table 5 and Table 8. The Protection Status of the Extended Block is then output on bits DQ7 and DQ6 of the Data Input/Outputs. (see Table 3 and Table 6, Bus Operations). The Protection Status of the Extended Block can also be accessed by issuing an Auto Select command (see Section 6.1.2: Auto Select command). 3.6.3 Verify Block Protection Status The Protection Status of a Block can be directly accessed by performing a read operation with control signals and addresses set as shown in Table 5 and Table 8. If the Block is protected, then 01h (in x8 mode) is output on Data Input/Outputs DQ0-DQ7, otherwise 00h is output. 3.6.4 Hardware Block Protect The VPP/WP pin can be used to protect the four outermost parameter blocks. When VPP/WP is at VIL the four outermost parameter blocks are protected and remain protected regardless of the Block Protection Status or the Reset/Block Temporary Unprotect pin state. 19/94 Bus operations M29DW128F 3.6.5 Temporary Unprotect of high voltage Protected Blocks The RP pin can be used to temporarily unprotect all the blocks previously protected using the In-System or the Programmer protection technique (High Voltage techniques). Refer to Section 2.9: Reset/Block Temporary Unprotect (RP). Table 3. Bus operations, 8-bit mode(1) Address Inputs Operation E G W RP VPP/WP A22-A0, DQ15A-1 Bus Read Bus Write Output Disable Standby 1. X = VIL or VIH. VIL VIL X VIH VIL VIH VIH X VIH VIL VIH X VIH VIH VIH VIH VIH VIH VIH VIH Cell Address Command Address X X DQ14-DQ8 Hi-Z Hi-Z Hi-Z Hi-Z DQ7-DQ0 Data Output Data Input Hi-Z Hi-Z Data Inputs/Outputs Table 4. Read Electronic Signature, 8-bit mode(1) Address Inputs Data Inputs/Outputs A2 VIL VIL VIH VIH A1 VIL VIL VIH VIH A0 VIL VIH VIL VIH DQ15A-1 X X X X DQ14DQ8 Hi-Z Hi-Z Hi-Z Hi-Z DQ7DQ0 20h 7Eh 20h 00h Read Cycle E G W A22-A10 A9 A8 A7-A6 A5-A4 X A3 VIL VIL VIL VIH VIH Manufacturer Code Device Code (Cycle 1) Device Code (Cycle 2) Device Code (Cycle 3) 1. X = VIL or VIH. VIL VIL VIH X VID X VIL Table 5. Block Protection, 8-bit mode(1) Address Inputs Data Inputs/Outputs DQ15 DQ14 A-1 -DQ8 VPP/ A5 A22 A3WP A11A1 A9 A8 A7 A6 A2 A10 A4 A12 Operation E G W RP A0 DQ7-DQ0 Verify Extended Block Protection Indicator (bits VIL VIL VIH VIH DQ6, DQ7) Verify Block Protection Status Temporary Block Unprotect (3) X X X VID BA VIH BKA X VID X X VIL VIL X VIL VIH VIH X 80h (Customer Lockable) C0h (Customer Locked)(2) Hi-Z 01h (protected) 00h (unprotected) Data Input VIL VIL X X Valid 1. X = VIL or VIH. BKA Bank Address, BA any Address in the Block. 2. This indicates the protection status of the second section of the Extended Block; the first section of the Extended Block being always Factory Locked. 3. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique. 20/94 M29DW128F Table 6. Bus operations, 16-bit mode(1) E G W RP VPP/ WP VIH VIH VIH VIH Address Inputs A22-A0 Cell Address Command Address X X Bus operations Data Inputs/Outputs DQ15A-1, DQ14-DQ0 Data Output Data Input Hi-Z Hi-Z Operation Bus Read Bus Write Output Disable Standby 1. X = VIL or VIH. VIL VIL X VIH VIL VIH VIH X VIH VIL VIH X VIH VIH VIH VIH Table 7. Read Electronic Signature, 16-bit mode(1) Address Inputs Data Inputs/Outputs A2 VIL VIL VIH VIH A1 VIL VIL VIH VIH A0 VIL VIH VIL VIH DQ15A-1, DQ14-DQ0 0020h 227Eh 2220h 2200h E G W Read Cycle A22A10 A9 A8 A7A6 A5A4 X A3 VIL VIL Manufacturer Code Device Code (Cycle 1) Device Code (Cycle 2) Device Code (Cycle 3) 1. X = VIL or VIH. VIL VIL VIH X VID X VIL VIL VIH VIH Table 8. Operation Block Protection, 16-bit mode(1) Address Inputs E G Data Inputs/Outputs A0 DQ15A-1, DQ14-DQ0 0080h (Customer Lockable) 00C0h (Customer Locked)(2) 0001h (protected) 0000h (unprotected) Data Input W VPP/ RP WP A22- A11A9 A12 A10 A8 A7 A6 A5- A3A1 A4 A2 Verify Extended Block Indicator (bits DQ6, DQ7) Verify Block Protection Status Temporary Block Unprotect (3) BA VIL VIL VIH VIH VIH BKA X X X VID X X VID X X VIL VIL Valid X VIL VIL VIH VIH VIL 1. X = VIL or VIH. BKA Bank Address, BA Any Address in the Block. 2. This indicates the protection status of the second section of the Extended Block; the first section of the Extended Block being always Factory Locked. 3. The RP pin unprotects all the blocks that have been previously protected using a High Voltage protection Technique. 21/94 Hardware Protection M29DW128F 4 Hardware Protection The M29DW128F features hardware protection/unprotection. Refer to Table 9 for details on hardware block protection/unprotection using VPP/WP and RP pins. 4.1 Write Protect The VPP/WP pin protects the four outermost parameter blocks (refer to Section 2: Signal descriptions for a detailed description of the signals). 4.2 Temporary Block Unprotect When held at VID, the Reset/Block Temporary Unprotect pin, RP, will temporarily unprotect all the blocks previously protected using a High Voltage Block Protection technique. Table 9. Hardware Protection VPP/WP RP VIH VIL VID VIH or VID VPPH VID VIH or VID Function 4 outermost parameter blocks protected from Program/Erase operations All blocks temporarily unprotected except the 4 outermost blocks(1) All blocks temporarily unprotected(1) All blocks temporarily unprotected(1) 1. The temporary unprotection is valid only for the blocks that have been protected using the High Voltage Protection Technique (see Appendix D: High Voltage Block Protection). The blocks protected using a software protection method (Standard, Password) do not follow this rules. 22/94 M29DW128F Software Protection 5 Software Protection The M29DW128F has two different Software Protection modes: the Standard Protection mode and the Password Protection mode. On first use all parts default to the Standard Protection mode and the customer is free to activate the Standard or the Password Protection mode. The desired protection mode is activated by setting one of two one-time programmable bits, the Standard Protection Mode Lock bit or the Password Protection Mode Lock bit. Programming the Standard and the Password Protection Mode Lock bit to ‘1’ will permanently activate the Standard Protection mode and the Password Protection mode, respectively. These two bits are one-time programmable and non-volatile, once the Protection mode has been programmed, it cannot be changed and the device will permanently operate in the selected Protection mode. It is recommended to activate the desired Software Protection mode when first programming the device. The device is shipped with all blocks unprotected. The Block Protection Status can be read by issuing the Auto Select command (see Table 10: Block Protection status). The Standard and Password Protection modes offer two levels of protection, a Block Lock/Unlock protection and a Non-Volatile protection. For the four outermost parameter blocks, an even higher level of block protection can be achieved by locking the blocks using the Non-Volatile Protection and then by holding the VPP/WP pin Low. 5.1 5.1.1 Standard Protection mode Block Lock/Unlock Protection It is a flexible mechanism to protect/unprotect a block or a group of blocks from program or erase operations. A volatile Lock bit is assigned to each block or group of blocks. When the lock bit is set to ‘1’ the associated block or group of blocks is protected from program/erase operations, when the Lock bit is set to ‘0’ the associated block or group of blocks is unprotected and can be programmed or erased. The Lock bits can be set (‘1’) and cleared (‘0’) individually as often as required by issuing a Set Lock Bit command and Clear Lock bit command, respectively. After a Power-up or Hardware Reset, all the Lock bits are cleared to ‘0’ (block unlocked). 23/94 Software Protection M29DW128F 5.1.2 Non-Volatile Protection A Non-Volatile Modify Protection bit is assigned to each block or group of blocks. When a Non-Volatile Modify Protection bit is set to ‘1’ the associated block or group of blocks is protected, preventing any program or erase operations in this block or group of blocks. The Non-Volatile Modify Protection bits are set individually by issuing a Set Non-Volatile Modify Protection bit command. They are non-volatile and will remain set through a hardware reset or a power-down/power-up sequence. The Non-Volatile Modify Protection bits cannot be cleared individually, they can only be cleared all at the same time by issuing a Clear Non-Volatile Modify Protection bits command. However if any one of the Non-Volatile Modify Protection bits has to be cleared, care should be taken to preprogram to ‘1’ all the Non-Volatile Modify Protection bits prior to issuing the Clear Non-Volatile Modify Protection bits in order to prevent the over-erasure of previously cleared Non Volatile Modify Protection bits. It is crucial to prevent over-erasure because the process may lead to permanent damage to the Non-Volatile Modify Protection bits and the device does not have any built-in means of preventing over-erasure. The device features a volatile Lock-Down bit which can be used to prevent changing the state of the Non-Volatile Modify Protection bits. When set to ‘1’, the Non-Volatile Modify Protection bits can no longer be modified; when set to ‘0’, the Non-Volatile Modify Protection bits can be set and reset using the Set Non-Volatile Modify Protection bit command and the Clear Non-Volatile Modify Protection bits command, respectively. The Lock-Down bit is set by issuing the Set Lock-Down bit Command. It is not cleared using a command, but through a hardware reset or a power-down/power-up sequence. The parts are shipped with the Non-Volatile Modify Protection bits set to ‘0’. Locked blocks and Non-Volatile Locked blocks can co-exist in the same memory array. Refer to Table 10: Block Protection status and Figure 7: Software Protection scheme for details on the block protection mechanism. 5.2 Password Protection mode The Password Protection mode provides a more advanced level of software protection than the Standard Protection mode. Prior to entering the Password Protection mode, it is necessary to set a password and to verify it (see Section 6.3.5: Password Program command and Section 6.3.6: Password Verify command). The Password Protection mode is then activated by programming the Password Protection Mode Lock bit to ‘1’. The Reset/Block Temporary Unprotect pin, RP, can be at VID or at VIH. This operation is not reversible and once the bit is programmed the device will permanently remain in the Password Protection mode. The Password Protection mode uses the same protection mechanisms as the Standard Protection mode (Block Lock/Unlock, Non-Volatile Protection). 24/94 M29DW128F Software Protection 5.2.1 Block Lock/Unlock Protection The Block Lock/Unlock Protection operates exactly in the same way as in the Standard Protection mode. 5.2.2 Non-Volatile Protection The Non-Volatile Protection is more advanced in the Password Protection mode. In this mode, the Lock-Down bit cannot be cleared through a hardware reset or a power-down/power-up sequence. The Lock-Down bit is cleared by issuing the Password Protection Unlock command along with the correct password. Once the correct Password has been provided, the Lock-Down bit is cleared and the Non-Volatile Modify Protection bits can be set or reset using the appropriate commands (the Set Non-Volatile Modify Protection bit command or the Clear Non-Volatile Modify Protection bits command, respectively). If the Password provided is not correct, the Lock-Down bit remains locked and the state of the NonVolatile Modify Protection bits cannot be modified. The Password is a 64-bit code located in the memory space. It must be programmed by the user prior to selecting the Password Protection mode. The Password is programmed by issuing a Password Program command and checked by issuing a Password Verify command. The Password should be unique for each part. Once the device is in Password Protection mode, the Password can no longer be read or retrieved. Moreover, all commands to the address where the password is stored, are disabled. Refer to Table 10: Block Protection status and Figure 7: Software Protection scheme for details on the block protection scheme. Table 10. Block Protection status Block Protection status Non-Volatile Modify Protection bit can be modified(1) Non-Volatile Modify Protection bit cannot be modified(1) Non-Volatile Modify Protection bit can be modified(1) Volatile Non-Volatile Block Lock-Down Lock Modify Protection bit Protection bit bit status 0 0 0 1 1 0 1 1 0 0 1 0 1 1 0 1 0 00h 1 0 0 0 01h 1 1 1 Block Program/ Erase Protected Block Unprotected Non-Volatile Modify Protection bit cannot be modified(1) 1. The Lock bit can always be modified by issuing a Clear Lock bit command or by taking the device through a Power-up or Hardware Reset. 25/94 Software Protection Figure 6. Block Protection State diagram Default: Standard Protection M29DW128F Set Standard Protection Mode Set Password Protection Mode Standard Protection Password Protection ai11503 Figure 7. Software Protection scheme Parameter Block or Up to 4 Main Blocks Lock Bit Non-Volatile Modify Protection Bit Lock-Down bit Standard Protection mode Block Lock/Unlock Protection Non-Volatile Protection Password Protection mode AI11504 26/94 M29DW128F Command interface 6 Command interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. 6.1 Standard commands See either Table 12, or Table 11, depending on the configuration that is being used, for a summary of the Standard commands. 6.1.1 Read/Reset command The Read/Reset command returns the memory to Read mode. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to Read mode. If the Read/Reset command is issued during the time-out of a Block erase operation, the memory will take up to 10µs to abort. During the abort period no valid data can be read from the memory. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. 6.1.2 Auto Select command The Auto Select command is used to read the Manufacturer Code, the Device Code, the Protection Status of each block (Block Protection Status) and the Extended Block Protection Indicator. It can be addressed to either Bank. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued Bus Read operations to specific addresses output the Manufacturer Code, the Device Code, the Extended Block Protection Indicator and a Block Protection Status (see Table 11 and Table 12 in conjunction with Table 4, Table 5, Table 7 and Table 8). The memory remains in Auto Select mode until a Read/Reset or CFI Query command is issued. 27/94 Command interface M29DW128F 6.1.3 Read CFI Query command The Read CFI Query Command is used to put the addressed bank in Read CFI Query mode. Once in Read CFI Query mode Bus Read operations to the same bank will output data from the Common Flash Interface (CFI) Memory Area. If the read operations are to a different bank from the one specified in the command then the read operations will output the contents of the memory array and not the CFI data. One Bus Write cycle is required to issue the Read CFI Query Command. Care must be taken to issue the command to one of the banks (A22-A19) along with the address shown in Table 3 and Table 6. Once the command is issued subsequent Bus Read operations in the same bank (A22-A19) to the addresses shown in Appendix B: Common Flash Interface (CFI) (A7-A0), will read from the Common Flash Interface Memory Area. This command is valid only when the device is in the Read Array or Auto Select mode. To enter Read CFI query mode from Auto Select mode, the Read CFI Query command must be issued to the same bank address as the Auto Select command, otherwise the device will not enter Read CFI Query mode. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Auto Select mode). A second Read/Reset command is required to put the device in Read Array mode from Auto Select mode. See Appendix B, Table 35, Table 36, Table 37, Table 38, Table 39 and Table 40 for details on the information contained in the Common Flash Interface (CFI) memory area. 6.1.4 Blank Verify command The Blank Verify command is used to check if a block is blank or in other words, if it has been successfully erased and all its bits set to '1'. Three cycles are required to issue a Verify command: 1. 2. 3. The command starts with two unlock cycles. The third bus write cycle sets up the Verify command code along with the address of the block to be checked. Bus Read operations during the Blank Verify operation output the Status Register on Data Inputs/Outputs (see 7: Status Register). After the Blank Verify command has completed, the memory returns to Read mode, unless an error has occurred. When an error occurs, the memory continues to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.F 6.1.5 Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected, then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 18. All Bus Read operations during the Chip Erase 28/94 M29DW128F Command interface operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 29/94 Command interface M29DW128F 6.1.6 Block Erase command The Block Erase command can be used to erase a list of one or more blocks in one or more Banks. It sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller after a time-out period of 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. After the sixth Bus Write operation a Bus Read operation within the same Bank will output the Status Register. See the Status Register section for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command and the Read/Reset command which is only accepted during the 50µs time-out period. Typical block erase times are given in Table 18. After the Erase operation has started all Bus Read operations to the Banks being erased will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs, Bus Read operations to the Banks where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. 6.1.7 Erase Suspend command The Erase Suspend command may be used to temporarily suspend a Block or multiple Block Erase operation. One Bus Write operation specifying the Bank Address of one of the Blocks being erased is required to issue the command. Issuing the Erase Suspend command returns the whole device to Read mode. The Program/Erase Controller will suspend within the Erase Suspend Latency time (see Table 18 for value) of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. 30/94 M29DW128F Command interface It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. During Erase Suspend a Bus Read operation to the Extended Block will output the Extended Block data. Once in the Extended Block mode, the Exit Extended Block command must be issued before the erase operation can be resumed. 6.1.8 Erase Resume command The Erase Resume command is used to restart the Program/Erase Controller after an Erase Suspend. The command must include the Bank Address of the Erase-Suspended Bank, otherwise the Program/Erase Controller is not restarted. The device must be in Read Array mode before the Resume command will be accepted. An Erase can be suspended and resumed more than once. 6.1.9 Program Suspend command The Program Suspend command allows the system to interrupt a program operation so that data can be read from any block. When the Program Suspend command is issued during a program operation, the device suspends the program operation within the Program Suspend Latency time (see Table 18 for value) and updates the Status Register bits. The Bank Addresses of the Block being programmed must be specified in the Program Suspend command. After the program operation has been suspended, the system can read array data from any address. However, data read from Program-Suspended addresses is not valid. The Program Suspend command may also be issued during a program operation while an erase is suspended. In this case, data may be read from any addresses not in Erase Suspend or Program Suspend. If a read is needed from the Extended Block area (One-time Program area), the user must use the proper command sequences to enter and exit this region. The system may also issue the Auto Select command sequence when the device is in the Program Suspend mode. The system can read as many Auto Select codes as required. When the device exits the Auto Select mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Auto Select command sequence for more information. 6.1.10 Program Resume command After the Program Resume command is issued, the device reverts to programming. The controller can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information. The system must write the Program Resume command, specifying the Bank addresses of the Program-Suspended Block, to exit the Program Suspend mode and to continue the programming operation. Further issuing of the Resume command is ignored. Another Program Suspend command can be written after the device has resumed programming. 31/94 Command interface M29DW128F 6.1.11 Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final Write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. Programming can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.9: Program Suspend command and Section 6.1.10: Program Resume command paragraphs). If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. See the section on the Status Register for more details. Typical program times are given in Table 18. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 32/94 M29DW128F Table 11. Standard Commands, 8-bit mode(1)(2) Bus operations Command Length 1st Add 1 Read/Reset 3 Manufacturer Code Device Code Auto Select Extended Block Protection Indicator Block Protection Status Program Blank Verify Command Verify Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 3 3 6 6 + 1 1 1 AAA AAA AAA AAA AAA BKA BKA (BKA) AAA AA AA AA AA AA B0 30 98 555 555 555 555 555 55 55 55 55 55 AAA BA BA AAA AAA A0 BC BC 80 80 AAA AAA AA AA PA PD 3 AAA AA 555 55 (BKA) AAA 90 (3) (3) Command interface 2nd Data Add Data F0 AA 555 55 X 3rd Add Data 4th 5th 6th Add Data Add Data Add Data X AAA F0 555 555 55 55 AAA BA 10 30 1. Grey cells represent Read cycles. The other cells are Write cycles. 2. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in hexadecimal. 3. The Auto Select addresses and data are given in Table 4: Read Electronic Signature, 8-bit mode, and Table 5: Block Protection, 8-bit mode, except for A9 that is ‘Don’t Care’. 33/94 Command interface Table 12. Standard Commands, 16-bit mode(1)(2) Bus operations Command Length 1st Add 1 Read/Reset 3 Manufacturer Code Device Code Auto Select Extended Block Protection Indicator Block Protection Status Program Blank Verify Command Verify Chip Erase Block Erase Erase/Program Suspend Erase/Program Resume Read CFI Query 4 3 3 6 6+ 1 1 1 555 555 555 555 555 BKA BKA (BKA) 555 AA AA AA AA AA B0 30 98 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 555 BA BA 555 555 A0 BC BC 80 80 555 555 AA AA 2AA 2AA PA PD 3 555 AA 2AA 55 (BKA) 555 90 (3) (3) M29DW128F 2nd Data Add Data F0 AA 2AA 55 X 3rd Add Data 4th Add 5th 6th Add Data Data Add Data X 555 F0 55 55 555 BA 10 30 1. Grey cells represent Read cycles. The other cells are Write cycles. 2. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address. All values in the table are in hexadecimal. 3. The Auto Select addresses and data are given in Table 7: Read Electronic Signature, 16-bit mode, and Table 8: Block Protection, 16-bit mode, except for A9 that is ‘Don’t Care’. 34/94 M29DW128F Command interface 6.2 Fast Program commands The M29DW128F offers a set of Fast Program commands to improve the programming throughput: ● ● ● ● Write to Buffer and Program Double and Quadruple Word, Program Double, Quadruple and Octuple Byte Program Unlock Bypass. See either Table 14, or Table 13, depending on the configuration that is being used, for a summary of the Fast Program commands. When VPPH is applied to the VPP/Write Protect pin the memory automatically enters the Fast Program mode. The user can then choose to issue any of the Fast Program commands. Care must be taken because applying a VPPH to the VPP/WP pin will temporarily unprotect any protected block. Only one bank can be programmed at any one time. The other bank must be in Read mode or Erase Suspend. After programming has started, Bus Read operations in the Bank being programmed output the Status Register content, while Bus Read operations to the other Bank output the contents of the memory array. Fast program commands can be suspended and then resumed by issuing a Program Suspend command and a Program Resume command, respectively (see Section 6.1.9: Program Suspend command and Section 6.1.10: Program Resume command paragraphs.) After the fast program operation has completed, the memory will return to the Read mode, unless an error has occurred. When an error occurs Bus Read operations to the Bank where the command was issued will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Typical Program times are given in Table 18: Program, Erase Times and Program, Erase Endurance Cycles. 35/94 Command interface M29DW128F 6.2.1 Write to Buffer and Program command The Write to Buffer and Program Command makes use of the device’s 64-byte Write Buffer to speed up programming. 32 Words/64 bytes can be loaded into the Write Buffer. Each Write Buffer has the same A5-A22 addresses.The Write to Buffer and Program command dramatically reduces system programming time compared to the standard non-buffered Program command. When issuing a Write to Buffer and Program command, the VPP/WP pin can be either held High, VIH or raised to VPPH. See Table 18 for details on typical Write to Buffer and Program times in both cases. Five successive steps are required to issue the Write to Buffer and Program command: 1. 2. 3. The Write to Buffer and Program command starts with two unlock cycles. The third Bus Write cycle sets up the Write to Buffer and Program command. The setup code can be addressed to any location within the targeted block. The fourth Bus Write cycle sets up the number of Words/bytes to be programmed. Value N is written to the same block address, where N+1 is the number of Words/bytes to be programmed. N+1 must not exceed the size of the Write Buffer or the operation will abort. The fifth cycle loads the first address and data to be programmed. Use N Bus Write cycles to load the address and data for each Word/bytes into the Write Buffer. Addresses must lie within the range from the start address+1 to the start address + N-1. Optimum performance is obtained when the start address corresponds to a 64 byte boundary. If the start address is not aligned to a 64 byte boundary, the total programming time is doubled. 4. 5. All the addresses used in the Write to Buffer and Program operation must lie within the same page. To program the content of the Write Buffer, this command must be followed by a Write to Buffer and Program Confirm command. If an address is written several times during a Write to Buffer and Program operation, the address/data counter will be decremented at each data load operation and the data will be programmed to the last word loaded into the Buffer. Invalid address combinations or failing to follow the correct sequence of Bus Write cycles will abort the Write to Buffer and Program. The Status Register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device status during a Write to Buffer and Program operation. If is not possible to detect Program operation fails when changing programmed data from ‘0’ to ‘1’, that is when reprogramming data in a portion of memory already programmed. The resulting data will be the logical OR between the previous value and the current value. A Write to Buffer and Program Abort and Reset command must be issued to abort the Write to Buffer and Program operation and reset the device in Read mode. During Write to Buffer and Program operations, the bank being programmed will accept Program/Erase Suspend commands. See Appendix E, Figure 27: Write to Buffer and Program flowchart and Pseudo Code, for a suggested flowchart on using the Write to Buffer and Program command. 36/94 M29DW128F Command interface 6.2.2 Write to Buffer and Program Confirm command The Write to Buffer and Program Confirm command is used to confirm a Write to Buffer and Program command and to program the N+1 Words/bytes loaded in the Write Buffer by this command. 6.2.3 Write to Buffer and Program Abort and Reset command The Write to Buffer and Program Abort and Reset command is used to abort Write to Buffer and Program command. 6.2.4 Double Word Program command This is used to write two adjacent Words in x16 mode, simultaneously. The addresses of the two Words must differ only in A0. Three bus write cycles are necessary to issue the command: 1. 2. 3. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written and starts the Program/Erase Controller. 6.2.5 Quadruple Word Program command This is used to write a page of four adjacent Words, in x16 mode, simultaneously. The addresses of the four Words must differ only in A1 and A0. Five bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first Word to be written. The third bus cycle latches the Address and the Data of the second Word to be written. The fourth bus cycle latches the Address and the Data of the third Word to be written. The fifth bus cycle latches the Address and the Data of the fourth Word to be written and starts the Program/Erase Controller. 6.2.6 Double byte Program Command This is used to write two adjacent bytes in x8 mode, simultaneously. The addresses of the two bytes must differ only in DQ15A-1. Three bus write cycles are necessary to issue the command: 1. 2. 3. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written and starts the Program/Erase Controller. 37/94 Command interface M29DW128F 6.2.7 Quadruple byte Program command This is used to write four adjacent bytes in x8 mode, simultaneously. The addresses of the four bytes must differ only in A0, DQ15A-1. Five bus write cycles are necessary to issue the command. 1. 2. 3. 4. 5. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written. The fourth bus cycle latches the Address and the Data of the third byte to be written. The fifth bus cycle latches the Address and the Data of the fourth byte to be written and starts the Program/Erase Controller. 6.2.8 Octuple byte Program command This is used to write eight adjacent bytes, in x8 mode, simultaneously. The addresses of the eight bytes must differ only in A1, A0 and DQ15A-1. Nine bus write cycles are necessary to issue the command: 1. 2. 3. 4. 5. 6. 7. 8. 9. The first bus cycle sets up the command. The second bus cycle latches the Address and the Data of the first byte to be written. The third bus cycle latches the Address and the Data of the second byte to be written. The fourth bus cycle latches the Address and the Data of the third byte to be written. The fifth bus cycle latches the Address and the Data of the fourth byte to be written. The sixth bus cycle latches the Address and the Data of the fifth byte to be written. The seventh bus cycle latches the Address and the Data of the sixth byte to be written. The eighth bus cycle latches the Address and the Data of the seventh byte to be written. The ninth bus cycle latches the Address and the Data of the eighth byte to be written and starts the Program/Erase Controller. 6.2.9 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory faster than with the standard program commands. When the cycle time to the device is long, considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the bank enters Unlock Bypass mode. When in Unlock Bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. The Unlock Bypass Program command can then be issued to program addresses within the bank, or the Unlock Bypass Reset command can be issued to return the bank to Read mode. In Unlock Bypass mode the memory can be read as if in Read mode. 38/94 M29DW128F Command interface 6.2.10 Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. The operation cannot be aborted, a Bus Read operation to the Bank where the command was issued outputs the Status Register. See the Program command for details on the behavior. 6.2.11 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass mode. Table 13. Fast Program Commands, 8-bit mode(1) Bus Write operations Command Length 1st Add Write to Buffer and Program Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Double byte Program Quadruple byte Program Octuple byte Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset 1. 2. 3. 4. 5. N + 5 Data 2nd Add Data 3rd Add Data 4th Add Data N(2) 5th Add PA (3) 6th Add WBL (4) 7th Add Data 8th Add Data 9th Add Data Data Data AAA AA 555 55 BA 25 BA PD PD 3 AAA AA 555 55 AAA F0 1 BA (5) 29 3 5 9 3 2 2 AAA AAA AAA AAA X X 50 56 8B AA A0 90 PA0 PA0 PA0 555 PA X PD0 PD0 PD0 55 PD 00 PA1 PA1 PA1 AAA PD1 PD1 PD1 20 PA2 PA2 PD2 PD2 PA3 PA3 PD3 PD3 PA4 PD4 PA5 PD5 PA6 PD6 PA7 PD7 X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address, WBL Write Buffer Location. All values in the table are in hexadecimal. The maximum number of cycles in the command sequence is 68. N+1 is the number of bytes to be programmed during the Write to Buffer and Program operation. Each buffer has the same A5-A22 addresses. A0-A4 and A-1 are used to select a byte within the N+1 byte page. The 6th cycle has to be issued N time. WBL scans the byte inside the page. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles. 39/94 Command interface Table 14. Fast Program Commands, 16-bit mode(1) Bus Write operations Length Command 1st Add Write to Buffer and Program Write to Buffer and Program Abort and Reset Write to Buffer and Program Confirm Double Word Program Quadruple Word Program Unlock Bypass Unlock Bypass Program Unlock Bypass Reset N+ 5 3 1 3 5 3 2 2 555 555 BA(5) 555 555 555 X X Data AA AA 29 50 56 AA A0 90 PA0 PA0 2AA PA X PD0 PD0 55 PD 00 PA1 PA1 555 PD1 PD1 20 PA2 PD2 PA3 2nd Add 2AA 2AA Data 55 55 Add BA 555 3rd Data 25 F0 Add BA 4th Data N(2) Add PA(3) 5th M29DW128F 6th Add WBL (4) Data PD Data PD PD3 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block, BKA Bank Address, WBL Write Buffer Location. All values in the table are in hexadecimal. 2. The maximum number of cycles in the command sequence is 36. N+1 is the number of Words to be programmed during the Write to Buffer and Program operation. 3. Each buffer has the same A5-A22 addresses. A0-A4 are used to select a Word within the N+1 Word page. 4. The 6th cycle has to be issued N time. WBL scans the Word inside the page. 5. BA must be identical to the address loaded during the Write to buffer and Program 3rd and 4th cycles. 40/94 M29DW128F Command interface 6.3 Block Protection commands Blocks or groups of blocks can be protected against accidental program, erase or read operations. The Protection Groups are shown in Appendix A, Table 34: Block Addresses and Protection Groups. The device block protection scheme is shown in Figure 7: Software Protection scheme and Figure 6: Block Protection State diagram. See either Table 15, or Table 16, depending on the configuration that is being used, for a summary of the Block Protection commands. Only the commands related to the Extended Block Protection are available in both 8 bit and 16 bit memory configuration. The other block protection commands are available in 16-bit configuration only. 6.3.1 Enter Extended Block command The M29DW128F has one extra 256-byte block (Extended Block) that can only be accessed using the Enter Extended Block command. Three Bus Write cycles are required to issue the Extended Block command. Once the command has been issued the device enters the Extended Block mode where all Bus Read or Program operations are conducted on the Extended Block. Once the device is in the Extended Block mode, the Extended Block is addressed by using the addresses occupied by the boot blocks in the other operating modes (see Table 34: Block Addresses and Protection Groups). The device remains in Extended Block mode until the Exit Extended Block command is issued or power is removed from the device. After power-up or a hardware reset, the device reverts to the Read mode where commands issued to the Boot Block Address space will address the Boot Blocks. Note that when the device is in the Extended Block mode, the VPP/WP pin cannot be used for fast programming and the Unlock Bypass mode is not available. The Extended Block cannot be erased, and can be treated as one-time programmable (OTP) memory. In Extended Block mode only array cell locations (Bank A) with the same addresses as the Extended Block are not accessible. In Extended Block mode dual operations are allowed and the Extended Block physically belongs to Bank A. In Extended Block mode, Erase, Chip Erase, Erase Suspend and Erase resume commands are not allowed. To exit from the Extended Block mode the Exit Extended Block command must be issued. The Extended Block can be protected by setting the Extended Block Protection bit to ‘1’; however once protected the protection cannot be undone. 6.3.2 Exit Extended Block command The Exit Extended Block command is used to exit from the Extended Block mode and return the device to Read mode. Four Bus Write operations are required to issue the command. 41/94 Command interface M29DW128F 6.3.3 Set Extended Block Protection bit command The Set Extended Block Protection bit command programs the Extended Block Protection bit to ‘1’ thus preventing the second section of the Extended Block from being programmed. A Read/Reset command must be issued to abort a Set Extended Block Protection bit command. Six successive steps are required to issue the Set Extended Block Protection bit command. 1. 2. 3. 4. The command starts with two unlock cycles. The third Bus Write cycle sets up the Set Extended Block Protection bit command. The fourth Bus Write Cycle programs the Extended Block Protection bit to ‘1’. The last two cycles verify the value programmed at the Extended Block Protection bit address: if bit DQ0 of Data Inputs/Outputs is set to ’1’, it indicates that the Extended Block Protection bit has been successfully programmed. If DQ0 is ‘0’, the Set Extended Block Protection bit command must be issued and verified again. 6.3.4 Verify Extended Block Protection bit command The Verify Extended Block Protection bit command reads the status of the Extended Block Protection bit on bit DQ0 of the Data Inputs/Outputs. If DQ0 is ‘1’, the second section of the Extended Block is protected from program operations. 6.3.5 Password Program command The Password Program Command is used to program the 64-bit Password used in Password Protection mode. Four cycles are required to program the Password: 1. 2. 3. The first two cycles are unlock cycles. The third cycle issues the Password Program command. The fourth cycle inputs the 16-bit data required to program the Password. To program the 64-bit Password, the complete command sequence must be entered four times at four consecutive addresses selected by A1 to A0. Read operations can be used to read the Status Register during a Password Program operation. All other operations are forbidden. The Password can be checked by issuing a Password Verify command. Once Password Program operation has completed, a Read/ Reset command must be issued to return the device to Read mode. The Password Protection mode can then be selected. By default, all Password bits are set to ‘1’. 42/94 M29DW128F Command interface 6.3.6 Password Verify command The Password Verify Command is used to verify the Password used in Password Protection mode. To verify the 64-bit Password, the complete command sequence must be entered four times at four consecutive addresses selected by A1 to A0. If the Password Mode Locking bit is programmed and the user attempts to verify the Password, the device will output all F’s onto the I/O data bus. The Password is output regardless of the bank address. The user must issue a Read/reset command to return the device to Read mode. Dual operations are not allowed during a Password Verify operation. 6.3.7 Password Protection Unlock command The Password Protection Unlock command is used to clear the Lock-Down bit in order to unprotect all Non-Volatile Modify Protection bits when the device is in Password Protection mode. The Password Protection Unlock command must be issued along with the correct Password. The complete command sequence must be entered for each 16 bits of the Password. There must be a 2µs delay between successive Password Protection Unlock commands in order to prevent hackers from cracking the Password by trying all possible 64-bit combinations. If this delay is not respected, the latest command will be ignored. 6.3.8 Set Password Protection mode command The Set Password Protection Mode command puts the device in Password Protection mode by programming the Password Protection Mode Lock bit to ‘1’. This command can be issued either with the Reset/Block Temporary Unprotect pin, RP, at VID or at VIH. Six cycles are required to issue a Set Password Protection Mode command: 1. 2. 3. 4. The first two cycles are unlock cycles. The third cycle issues the command. The fourth and fifth cycles select the address (see Table 34). The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the device has successfully entered the Password Protection mode. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 100µs delay between the fourth and fifth cycles. Once the Password Protection mode is activated the device will permanently remain in this mode. 6.3.9 Verify Password Protection mode command The Verify Password Protection Mode command reads the status of the Password Protection Mode Lock bit. If it is ‘1’, the device is in Password Protection mode. 43/94 Command interface M29DW128F 6.3.10 Set Standard Protection mode command The Set Standard Protection Mode command puts the device in Standard Protection mode by programming the Standard Protection Mode Lock bit to ‘1’. Six cycles are required to issue the Standard Protection Mode command: 1. 2. 3. 4. The first two cycles are unlock cycles. The third cycle issues the program command. The fourth and fifth cycles select the address (see Table 34). The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the Standard Protection Mode has been successfully activated. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 100µs delay between the fourth and fifth cycles. Once the Standard Protection mode is activated the device will permanently remain in this mode. 6.3.11 Verify Standard Protection mode command The Verify Standard Protection Mode command reads the status of the Standard Protection Mode Lock bit. If it is ‘1’, the device is in Standard Protection mode. 6.3.12 Set Non-Volatile Modify Protection bit command A block or group of blocks can be protected from program or erase by issuing a Set NonVolatile Modify Protection bit command along with the block address. This command sets the Non-Volatile Modify Protection bit to ‘1’ for a given block or group of blocks. Six cycles are required to issue the command: 1. 2. 3. 4. The first two cycles are unlock cycles. The third cycle issues the program command. The fourth and fifth cycles select the address (see Table 34). The last cycle verifies if the operation has been successful. If DQ0 is set to ’1’, the NonVolatile Modify Protection bit has been successfully programmed. If DQ0 is ‘0’, the operation has failed and the command must be re-issued. There must be a 100µs delay between the fourth and fifth cycles. The Non-Volatile Modify Protection bits are erased simultaneously by issuing a Clear NonVolatile Modify Protection bits command except if the Lock-Down bit is set to ‘1’. The Non-Volatile Modify Protection bits can be set a maximum of 100 times. 6.3.13 Verify Non-Volatile Modify Protection bit command The status of a Non-Volatile Modify Protection bit for a given block or group of blocks can be read by issuing a Verify Non-Volatile Modify Protection Bit command along with the block address. 44/94 M29DW128F Command interface 6.3.14 Clear Non-Volatile Modify Protection bits command This command is used to clear all Non-Volatile Modify Protection bits. No specific block address is required. If the Lock-Down bit is set to ‘1’, the command will fail. Six cycles are required to issue a Clear Non-Volatile Modify Protection bits command: 1. 2. 3. The first two cycles are unlock cycles. The third cycle issues the command. The last three cycles verify if the operation has been successful. If DQ0 is set to ’0’, all Non-Volatile Modify Protection bits have been successfully cleared. If DQ0 is ‘1’, the operation has failed and the command must be re-issued. There must be a 12ms delay between the fourth and fifth cycles. 6.3.15 Set Lock bit command The Set Lock bit command individually sets the Lock bit to ‘1’ for a given block or group of blocks. If the Non-Volatile Lock bit for the same block or group of blocks is set, the block is locked regardless of the value of the Lock bit. (see Table 10: Block Protection status). 6.3.16 Clear Lock bit command The Clear Lock bit command individually clears (sets to ‘0’) the Lock bit for a given block or group of blocks. If the Non-Volatile Lock bit for the same block or group of blocks is set, the block or group of blocks remains locked (see Table 10: Block Protection status). 6.3.17 Verify Lock bit command The status of a Lock bit for a given block can be read by issuing a Verify Lock bit command along with the block address. 6.3.18 Set Lock-Down bit command This command is used to set the Lock-Down bit to ‘1’ thus protecting the Non-Volatile Modify Protection bits from program and erase. There is no Unprotect Lock-Down bit command. 6.3.19 Verify Lock-Down bit command This command is used to read the status of the Lock-Down bit. The status is output on bit DQ1. If DQ1 is ‘1’, all the Non-Volatile Modify Protection bits are protected from program or erase operations. 45/94 Command interface Table 15. Block Protection Commands, 8-bit mode(1)(2) Bus operations Command Length 1st Add Set Extended Block Protection bit Verify Extended Block Protection bit Enter Extended Block Exit Extended Block 6 4 3 4 AAA AAA AAA AAA Data AA AA AA AA Add 555 555 555 555 2nd Data 55 55 55 55 3rd Add AAA AAA AAA AAA Data 60 60 88 90 X 00 4th Add OW OW Data 68 DQ0 Add OW (3) M29DW128F 5th Data 48 6th Add OW Data DQ0 1. OW Extended Block Protection bit Address (A7-A0=’00011010’), X Don’t Care. All values in the table are in hexadecimal. 2. Grey cells represent Read cycles. The other cells are Write cycles. 3. A 100µs timeout is required between cycles 4 and 5. Table 16. Block Protection Commands, 16-bit mode (1)(2)(3)(4) Bus operations Length Command 1st Add 2nd 3rd Add 4th Data Add 5th Data Add 6th Data 7th Add Data Data Add Data Add Data Set Extended Block Protection bit(5)(6) Verify Extended Block Protection bit Enter Extended Block Exit Extended Block Password Program (5)(7)(8) Password Verify(8)(9) Password Protection Unlock(7)(10)(11) Set Password Protection mode(5)(6) Verify Password Protection mode Set NonVolatile Modify Protection bit(5) (6) 6 555 AA 2AA 55 555 60 OW 68 OW 48 OW DQ0 4 555 AA 2AA 55 555 60 OW DQ0 3 4 4 4 555 555 555 555 AA AA AA AA 2AA 2AA 2AA 2AA 55 55 55 55 555 555 555 555 88 90 38 C8 X X[0-3] PWA [0-3] 00 PW [0-3] RPW [0-3] PWA [1] RPW [1] PWA [2] RPW [2] PWA RPW [3] [3] 7 555 AA 2AA 55 555 28 PWA[0] RPW[0] 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL DQ0 4 555 AA 2AA 55 555 60 PL DQ0 6 555 AA 2AA 55 555 60 (BA)/ NVMP 68 (BA)/ NVMP 48 (BA)/ NVMP DQ0 46/94 M29DW128F Table 16. Block Protection Commands, 16-bit mode (continued)(1)(2)(3)(4) Bus operations Command Length 1st Add Verify NonVolatile Modify Protection bit Clear NonVolatile Modify Protection bits(12)(13)(14) Set Lock-Down bit Verify LockDown bit(15) Set Lock bit(7) 2nd 3rd Add (BA)/ NVMP 4th Data Add (BA)/ NVMP 5th Data Command interface 6th Add Data 7th Add Data Data Add Data Add Data 4 555 AA 2AA 55 555 60 48 DQ0 6 555 AA 2AA 55 555 60 NVMP 60 (BA)/ NVMP 40 (BA)/ NVMP DQ0 3 4 4 555 555 555 555 555 555 AA AA AA AA AA AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 555 555 555 555 555 555 78 58 48 48 58 60 BA BA BA BA SL DQ1 X1h X0h DQ0 68 SL 48 SL DQ0 Clear Lock bit(7) 4 Verify Lock bit Set Standard Protection mode(5)(6) Verify Standard Protection mode(5) 4 6 4 555 AA 2AA 55 555 60 SL DQ0 1. Grey cells represent Read cycles. The other cells are Write cycles. 2. SA Protection Group Address, BA Any address in the Block, BKA Bank Address, SL Standard Protection Mode Lock bit Address, PL Password Protection Mode Lock bit Address, PW Password Data, PWA Password Address, RPW Password Data Being Verified, NVMP Non-Volatile Modify Protection bit Address, OW Extended Block Protection bit Address, X Don’t Care. All values in the table are in hexadecimal. 3. Addresses are described in Table 34. 4. During Unlock and Command cycles, if the lower address bits are 555h or 2AAh then the address bits higher than A11 (except where BA is required) and data bits higher than DQ7 are Don't Care. 5. A Reset Command must be issued to return to the Read mode. 6. The 4th Bus Write cycle programs a protection bit (Extended Block Protection bit, Password Protection Mode Lock bit, Standard Protection Mode Lock bit, and a block NVMP bit). The 5th and 6th cycles verify that the bit has been successively programmed when DQ0=1. If DQ0=0 in the 6th cycle, the program command must be issued again and verified again. A 100µs delay is required between the 4th and the 5th cycle. 7. Data is latched on the rising edge of W. 8. The entire command sequence must be entered for each portion of the password. 9. The command sequence returns FFh if the Password Protection Mode locking bit is set. 10. The password is written over four consecutive cycles, at addresses [0-3] 11. A 2µs timeout is required between any two portions of the password. 12. A 10ms delay is required between the 4th and the 5th cycle. 13. A 12ms timeout is required between cycles 4 and 5. 14. Cycle 4 erases all Non-Volatile Modify Protection bits. Cycles 5 and 6 verify that the bits have been successfully cleared when DQ0=0. If DQ0=1 in the 6th cycle, the erase command must be issued again and verified again. Before issuing the erase command, all Non-Volatile Modify Protection bits should be programmed to prevent over erasure. 15. DQ1=1 if the Non-Volatile Modify Protection bit is locked, DQ1 = 0 if it is unlocked. 47/94 Command interface Table 17. Protection Command Addresses Bit Password Protection Mode Lock bit Address (PL) Standard Protection Mode Lock bit Address (SL) Non-Volatile Modify Protection bit Address (NVMP) Extended Block Protection bit Address (OW) Condition RP at VIH RP at VID Address Inputs A7-A0 00001010 10001010 00010010 00000010 00011010 M29DW128F Other Address Inputs X X X Block Protection Group Address X Table 18. Program, Erase Times and Program, Erase Endurance Cycles Parameter Min Typ(1)(2) 80 0.8 Max(2) 400(3) 6 (4) Unit s s µs µs µs µs µs µs µs s s s s µs cycles years Chip Erase Block Erase (64 kbytes) Erase Suspend Latency Time Single or Multiple byte Program (1, 2, 4 or 8 bytes at-a-time) Byte Program Write to Buffer and Program (64 bytes at-a-time) VPP/WP =VPPH VPP/WP=VIH 50(4) 10 90 280 10 90 280 80 40 20 10 5 100,000 20 200(3) 700(3) 1400(3) 200(3) 700(3) 1400(3) 400(3) 200 100 (3) (3) Single or Multiple Word Program (1, 2 or 4 Words at-a-time) Word Program Write to Buffer and Program (32 Words at-a-time) Chip Program (byte by byte) Chip Program (Word by Word) Chip Program (Quadruple byte or Double Word) Chip Program (Octuple byte or Quadruple Word) Program Suspend Latency Time Program/Erase Cycles (per Block) Data Retention 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. VPP/WP=VPPH VPP/WP=VIH 50(3) 15 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC. 48/94 M29DW128F Status Register 7 Status Register The M29DW128F has one Status Register. The Status Register provides information on the current or previous Program or Erase operations executed in each bank. The various bits convey information and errors on the operation. Bus Read operations from any address within the Bank, always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 19: Status Register bits. 7.1 Data Polling bit (DQ7) The Data Polling bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read mode. In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 8: Data Polling flowchart, gives an example of how to use the Data Polling bit. A Valid Address is the address being programmed or an address within the block being erased. 7.2 Toggle bit (DQ6) The Toggle bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle bit is output on DQ6 when the Status Register is read. During a Program/Erase operation the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle bit will output when addressing a cell within a block being erased. The Toggle bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. Figure 9: Toggle flowchart, gives an example of how to use the Data Toggle bit. Figure 16 and Figure 17 describe Toggle bit timing waveform. 49/94 Status Register M29DW128F 7.3 Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase Controller. The Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 7.4 Erase Timer bit (DQ3) The Erase Timer bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer bit is output on DQ3 when the Status Register is read. 7.5 Alternative Toggle bit (DQ2) The Alternative Toggle bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory array data as if in Read mode. After an Erase operation that causes the Error bit to be set, the Alternative Toggle bit can be used to identify which block or blocks have caused the error. The Alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle bit does not change if the addressed block has erased correctly. Figure 16 and Figure 17 describe Alternative Toggle bit timing waveform. 7.6 Write to Buffer and Program Abort bit (DQ1) The Write to Buffer and Program Abort bit, DQ1, is set to ‘1’ when a Write to Buffer and Program operation aborts. The Write to Buffer and Program Abort and Reset command must be issued to return the device to Read mode (see Write to Buffer and Program in COMMANDS section). 50/94 M29DW128F Table 19. Status Register bits(1)(2) Address Bank Address Bank Address Bank Address Bank Address Any Address Erasing Block Non-Erasing Block Erasing Block Block Erase Non-Erasing Block Erasing Block Erase Suspend Non-Erasing Block Good Block Address Erase Error Faulty Block Address 1. Unspecified data bits should be ignored. 2. Figure 16 and Figure 17 describe Toggle and Alternative Toggle bits timing waveforms. Status Register Operation Program Program During Erase Suspend Write to Buffer and Program Abort Program Error Chip Erase Block Erase before timeout DQ7 DQ7 DQ7 DQ7 DQ7 0 0 0 0 0 1 DQ6 Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle Toggle No Toggle DQ5 0 0 0 1 0 0 0 0 0 0 DQ3 – – – – 1 0 0 1 1 – DQ2 – – – – Toggle Toggle No Toggle Toggle No Toggle Toggle DQ1 0 – 1 – – – – – – – – RB 0 0 0 Hi-Z 0 0 0 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Data read as normal 0 0 Toggle Toggle 1 1 1 1 No Toggle Toggle – – Figure 8. Data Polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA NO NO DQ5 = 1 YES YES READ DQ7 at VALID ADDRESS DQ7 = DATA NO FAIL YES PASS AI07760 51/94 Status Register Figure 9. Toggle flowchart START READ DQ6 ADDRESS = BA READ DQ5 & DQ6 ADDRESS = BA M29DW128F DQ6 = TOGGLE YES NO DQ5 =1 YES NO READ DQ6 TWICE ADDRESS = BA DQ6 = TOGGLE YES FAIL NO PASS AI08929b 1. BA = Address of Bank being Programmed or Erased. 52/94 M29DW128F Dual Operations and Multiple Bank architecture 8 Dual Operations and Multiple Bank architecture The Multiple Bank Architecture of the M29DW128F gives greater flexibility for software developers to split the code and data spaces within the memory array. The Dual Operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The Dual Operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency. Only one bank at a time is allowed to be in program or erase mode. However, certain commands can cross bank boundaries, which means that during an operation only the banks that are not concerned with the cross bank operation are available for dual operations. For example, if a Block Erase command is issued to erase blocks in both Bank A and Bank B, then only Banks C or D are available for read operations while the erase is being executed. If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. Also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in Erase Suspend mode, one programming and other banks in read mode. By using a combination of these features, read operations are possible at any moment. Table 20 and Table 21 show the dual operations possible in other banks and in the same bank. Note that only the commonly used commands are represented in these tables. Table 20. Dual Operations allowed in other Banks(1) Commands allowed in another bank Status of Bank Read/ Reset Yes Yes Yes Yes Yes Read Read CFI Status Query (2) Register Yes(3) No No No No Yes No No Yes Yes Auto Select Yes No No Yes Yes Program/ Erase Suspend Yes(3) No No Program/ Erase Resume Yes(4) No No Yes(5) Yes(6) Program Yes – – No Yes Erase Yes – – No No Idle Programming Erasing Program Suspended Erase Suspended 1. If several banks are involved in a program or erase operation, then only the banks that are not concerned with the operation are available for dual operations. 2. Read Status Register is not a command. The Status Register can be read during a block program or erase operation. 3. Only after a program or erase operation in that bank. 4. Only after a Program or Erase Suspend command in that bank. 5. Only a Program Resume is allowed if the bank was previously in Program Suspend mode. 6. Only an Erase Resume is allowed if the bank was previously in Erase Suspend mode. 53/94 Dual Operations and Multiple Bank architecture Table 21. Dual Operations allowed in same Bank Commands allowed in same Bank Status of Bank Read Status Register (1) M29DW128F Read/ Reset Yes No No Yes(6) Yes(6) Read CFI Query Yes No No Yes Yes Auto Select Yes No No Yes Yes Program Erase Program/ Erase Suspend Yes(2) Yes(4) Yes – – (5) Program/ Erase Resume Yes(3) – – Yes Yes Idle Programming Erasing Program Suspended Erase Suspended Yes Yes Yes No Yes(7) Yes – – No Yes(6) Yes – No – No 1. Read Status Register is not a command. The Status Register can be read by addressing the block being programmed or erased. 2. Only after a program or erase operation in that bank. 3. Only after a Program or Erase Suspend command in that bank. 4. Only a Program Suspend. 5. Only an Erase suspend. 6. Not allowed in the Block or Word that is being erased or programmed. 7. The Status Register can be read by addressing the block being erase suspended. 54/94 M29DW128F Maximum rating 9 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 22. Symbol TBIAS TSTG VIO VCC VID VPP(3) Absolute maximum ratings Parameter Temperature Under Bias Storage Temperature Input or Output Supply voltage Identification voltage Program voltage voltage(1)(2) Min –50 –65 –0.6 –0.6 –0.6 –0.6 Max 125 150 VCC +0.6 4 13.5 13.5 Unit °C °C V V V V 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. 3. VPP must not remain at 12V for more than a total of 80hrs. 55/94 DC and AC parameters M29DW128F 10 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 23: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 23. Operating and AC measurement conditions M29DW128F Parameter Min VCC supply voltage Ambient Operating Temperature Load capacitance (CL) Input Rise and Fall Times Input pulse voltages Input and Output Timing Ref. voltages 0 to VCC VCC/2 2.7 –40 30 10 0 to VCC VCC/2 60 Max 3.6 85 Min 2.7 –40 30 10 70 Max 3.6 85 V °C pF ns V V Unit Figure 10. AC measurement I/O waveform VCC VCC/2 0V AI05557 Figure 11. AC measurement Load Circuit VPP VCC VCC 25kΩ DEVICE UNDER TEST 25kΩ CL 0.1µF 0.1µF CL includes JIG capacitance AI05558 56/94 M29DW128F Table 24. Symbol CIN COUT DC and AC parameters Device capacitance Parameter Input capacitance Output capacitance Test condition VIN = 0V VOUT = 0V Min Max(1) 6 12 Unit pF pF 1. Sampled only, not 100% tested. Table 25. Symbol ILI ILO ICC1(1) ICC2 DC Characteristics Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) Test condition 0V ≤VIN ≤VCC 0V ≤VOUT ≤VCC E = VIL, G = VIH, f = 6MHz E = VCC ±0.2V, RP = VCC ±0.2V Program/Erase Controller active VPP/WP = VIL or VIH VPP/WP = VPPH –0.5 0.7VCC VCC = 2.7V ±10% VCC =2.7V ±10% IOL = 1.8mA IOH = –100µA VCC –0.4 11.5 1.8 12.5 2.3 11.5 Min Max ±1 ±1 10 100 20 20 0.8 VCC +0.3 12.5 15 0.45 Unit µA µA mA µA mA mA V V V mA V V V V ICC3(1)(2) Supply Current (Program/Erase) VIL VIH VPPH IPP VOL VOH VID VLKO Input Low voltage Input High voltage Voltage for VPP/WP Program Acceleration Current for VPP/WP Program Acceleration Output Low voltage Output High voltage Identification voltage Program/Erase Lockout supply voltage 1. In Dual operations the Supply Current will be the sum of ICC1(read) and ICC3 (program/erase). 2. Sampled only, not 100% tested. 57/94 DC and AC parameters Figure 12. Random Read AC waveforms M29DW128F tAVAV A0-A22/ A–1 tAVQV E tELQV tELQX G tGLQX tGLQV DQ0-DQ7/ DQ8-DQ15 tBHQV BYTE tELBL/tELBH tBLQZ AI08970 VALID tAXQX tEHQX tEHQZ tGHQX tGHQZ VALID 58/94 M29DW128F A3-A22 A-1 VALID Figure 13. Page Read AC waveforms A0-A2 VALID VALID VALID VALID VALID VALID VALID VALID tAVQV E tEHQX tEHQZ tELQV G tGLQV tAVQV1 VALID VALID VALID VALID VALID VALID VALID tGHQX tGHQZ VALID DQ0-DQ15 AI08971c DC and AC parameters 59/94 DC and AC parameters Table 26. Symbol M29DW128F Read AC characteristics M29DW128F Alt Parameter Test condition 60 70 70 70 30 0 70 0 25 25 25 0 ns ns ns ns ns ns ns ns ns ns E = VIL, G = VIL E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL Unit tAVAV tAVQV tAVQV1 tELQX(1) tELQV tGLQX(1) tGLQV tEHQZ(1) tGHQZ(1) tEHQX tGHQX tAXQX tELBL tELBH tBLQZ tBHQV tRC tACC tPAGE tLZ tCE tOLZ tOE tHZ tDF tOH tELFL tELFH tFLQZ tFHQV Address Valid to Next Address Valid Address Valid to Output Valid Address Valid to Output Valid (Page) Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Chip Enable, Output Enable or Address Transition to Output Transition Chip Enable to BYTE Low or High(2) BYTE Low to Output Hi-Z(2) BYTE High to Output Valid(2) Min Max Max Min Max Min Max Max Max Min 60 60 25 0 60 0 20 25 25 0 Max Max Max 5 25 30 5 25 30 ns ns ns 1. Sampled only, not 100% tested. 2. TSOP56 package only. 60/94 M29DW128F Figure 14. Write AC waveforms, Write Enable Controlled tAVAV A0-A22/ A–1 VALID tWLAX tAVWL E tELWL G tGHWL W tWLWH tWHEH DC and AC parameters tWHGL tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX VCC tVCHEL RB tWHRL AI08972 Table 27. Symbol tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tWHGL tWHRL (1) Write AC characteristics, Write Enable Controlled M29DW128F Alt tWC tCS tWP tDS tDH tCH tWPH tAS tAH Parameter 60 Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High Write Enable High to Write Enable Low Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tOEH tBUSY tVCS Write Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Chip Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 60 0 45 45 0 0 30 0 45 0 0 30 50 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns µs Unit tVCHEL 1. Sampled only, not 100% tested. 61/94 DC and AC parameters Figure 15. Write AC waveforms, Chip Enable Controlled tAVAV A0-A22/ A–1 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH M29DW128F VCC tVCHWL RB tEHRL AI08973 Table 28. Symbol tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tEHGL tEHRL(1) tVCHWL Write AC characteristics, Chip Enable Controlled M29DW128F Alt tWC tWS tCP tDS tDH tWH tCPH tAS tAH Parameter 60 Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low tOEH tBUSY tVCS Chip Enable High to Output Enable Low Program/Erase Valid to RB Low VCC High to Write Enable Low Min Min Min Min Min Min Min Min Min Min Min Max Min 60 0 45 45 0 0 30 0 45 0 0 30 50 70 70 0 45 45 0 0 30 0 45 0 0 30 50 ns ns ns ns ns ns ns ns ns ns ns ns µs Unit 1. Sampled only, not 100% tested. 62/94 M29DW128F DC and AC parameters Figure 16. Toggle and Alternative Toggle bits mechanism, Chip Enable Controlled Address Outside the Bank being Programmed or Erased Address in the Bank being Programmed or Erased tAXEL E Address Outside the Bank being Programmed or Erased A0-A22 G tELQV DQ2(1)/DQ6(2) Data Toggle/ Alt.Toggle Bit Read Operation in the Bank Being Programmed or Erased tELQV Toggle/ Alt.Toggle Bit Data Read Operation outside the Bank Being Programmed or Erased Read Operation Outside the Bank Being Programmed or Erased AI08914e 1. The Toggle bit is output on DQ6. 2. The Alternative Toggle bit is output on DQ2. 3. Refer to Table 26: Read AC characteristics for the value of tELQV. Figure 17. Toggle and Alternative Toggle bits mechanism, Output Enable Controlled A0-A22 Address Outside the Bank being Programmed/Erased Address in the Bank being Programmed/Erased tAXGL G Address Outside the Bank being Programmed/Erased E tGLQV DQ2(1)/DQ6(2) Data Toggle/ Alt.Toggle Bit tGLQV Toggle/ Alt.Toggle Bit Data Read Operation outside Bank Being Programmed or Erased Read Operation in Bank Being Programmed or Erased Read Operation outside Bank Being Programmed or Erased AI08915e 1. The Toggle bit is output on DQ6. 2. The Alternative Toggle bit is output on DQ2. 3. Refer to Table 26: Read AC characteristics for the value of tGLQV. Table 29. Symbol tAXEL tAXGL Toggle and Alternative Toggle bits AC characteristics M29DW128F Alt Parameter 60 Address Transition to Chip Enable Low Address Transition to Output Enable Low Min Min 10 10 70 10 10 ns ns Unit 63/94 DC and AC parameters M29DW128F Figure 18. Reset/Block Temporary Unprotect AC waveforms (No Program/Erase ongoing) RB E, G tPHEL, tPHGL RP tPLPX AI11300b Figure 19. Reset/Block Temporary Unprotect During Program/Erase Operation AC waveforms tPLYH RB tRHEL, tRHGL E, G RP tPLPX AI11301b Figure 20. Accelerated Program Timing waveforms VPP VPP/WP VIL or VIH tVHVPP tVHVPP AI05563 64/94 M29DW128F Table 30. Symbol DC and AC parameters Reset/Block Temporary Unprotect AC characteristics M29DW128F Alt Parameter 60 70 20 500 50 20 0 µs ns ns ns ns RP Low to Read mode, during Program or Erase RP Pulse Width RP High to Write Enable Low, Chip Enable Low, Output Enable Low RP Low to Standby Mode. RB High to Write Enable Low, Chip Enable Low, Output Enable Low Unit tPLYH(1) tPLPX tPHEL, tPHGL(1) tREADY tRP tRH tRPD Max Min Min Min Min tRHEL tRHGL(1) tRB 1. Sampled only, not 100% tested. 65/94 Package mechanical M29DW128F 11 Package mechanical Figure 21. TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package outline A2 1 N e E B N/2 D1 D A CP DIE C TSOP-b A1 α L 1. Drawing is not to scale. Table 31. Symbol TSOP56 – 56 lead Plastic Thin Small Outline, 14 x 20mm, package mechanical data millimeters Typ Min Max 1.200 0.100 1.000 0.220 0.050 0.950 0.170 0.100 0.150 1.050 0.270 0.210 0.100 20.000 18.400 0.500 14.000 0.600 3° 56 19.800 18.300 – 13.900 0.500 0 20.200 18.500 – 14.100 0.700 5° 0.7874 0.7244 0.0197 0.5512 0.0236 3° 56 0.7795 0.7205 – 0.5472 0.0197 0 0.0039 0.0394 0.0087 0.0020 0.0374 0.0067 0.0039 Typ inches Min Max 0.0472 0.0059 0.0413 0.0106 0.0083 0.0039 0.7953 0.7283 – 0.5551 0.0276 5° A A1 A2 B C CP D D1 e E L α N 66/94 M29DW128F Package mechanical Figure 22. TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package outline D FD FE D1 SD E E1 SE ddd BALL "A1" A e b A1 A2 BGA-Z23 1. Drawing is not to scale. Table 32. Symbol TBGA64 10x13mm - 8x8 active ball array, 1mm pitch, package mechanical data millimeters Typ Min Max 1.200 0.300 0.800 0.350 10.000 7.000 9.900 – 0.500 10.100 – 0.100 1.000 13.000 7.000 1.500 3.000 0.500 0.500 – 12.900 – – – – – – 13.100 – – – – – 0.0394 0.5118 0.2756 0.0591 0.1181 0.0197 0.0197 – 0.5079 – – – – – 0.3937 0.2756 0.200 0.350 0.0118 0.0315 0.0138 0.3898 – 0.0197 0.3976 – 0.0039 – 0.5157 – – – – – 0.0079 Typ inches Min Max 0.0472 0.0138 A A1 A2 b D D1 ddd e E E1 FD FE SD SE 67/94 Part numbering M29DW128F 12 Table 33. Example: Device type M29 Architecture Part numbering Ordering information scheme M29DW128F 70 NF 1 T D = Dual Operation Operating voltage W = VCC = 2.7 to 3.6V Device function 128F = 128 Mbit (x8/x16), Multiple Bank, Page, Boot Block, 16+48+48+16 partitioning, Flash Memory Speed 60 = 60ns 70 = 70ns Package NF = TSOP56: 14 x 20 mm ZA = TBGA64: 10 x13mm, 1mm pitch Temperature range 1 = 0 to 70 °C 6 = –40 to 85 °C Option Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel 24mm Packing Note: This product is also available with the Extended Block factory locked. For further details and ordering information contact your nearest ST sales office. Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 68/94 M29DW128F Block addresses and Read/Modify Protection Groups Appendix A Block addresses and Read/Modify Protection Groups Table 34. Bank Block Addresses and Protection Groups Block 0 1 2 3 4 5 6 7 8 9 10 11 Size (kbytes/KWords) 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 64/32 64/32 64/32 64/32 64/32 Protection Group 13 14 15 16 17 18 19 20 21 22 23 24 25 26 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 120000h-12FFFFh 130000h-13FFFFh 090000h–097FFFh 098000h–09FFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 070000h–077FFFh 078000h–07FFFFh 080000h–087FFFh 088000h–08FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 050000h–057FFFh 058000h–05FFFFh 060000h–067FFFh 068000h–06FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 030000h–037FFFh 038000h–03FFFFh 040000h–047FFFh 048000h–04FFFFh Protection Group Protection Block Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group (x8) 000000h-001FFFh(1) 002000h-003FFFh(1) 004000h-005FFFh(1) 006000h-007FFFh(1) 008000h-009FFFh(1) 00A000h-00BFFFh(1) 00C000h-00DFFFh(1) 00E000h-00FFFFh(1) 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh (x16) 000000h–000FFFh(1) 001000h–001FFFh(1) 002000h–002FFFh(1) 003000h–003FFFh(1) 004000h–004FFFh(1) 005000h–005FFFh(1) 006000h–006FFFh(1) 007000h–007FFFh(1) 008000h–00FFFFh 010000h–017FFFh 018000h–01FFFFh 020000h–027FFFh 028000h–02FFFFh Bank A 12 69/94 Block addresses and Read/Modify Protection Groups Table 34. Bank M29DW128F Block Addresses and Protection Groups (continued) Block 27 28 29 30 31 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 49 50 51 52 53 54 55 56 57 58 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 320000h-32FFFFh 330000h-33FFFFh 190000h–197FFFh 198000h–19FFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 170000h–177FFFh 178000h–17FFFFh 180000h–187FFFh 188000h–18FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 150000h–157FFFh 158000h–15FFFFh 160000h–167FFFh 168000h–16FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 130000h–137FFFh 138000h–13FFFFh 140000h–147FFFh 148000h–14FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 110000h–117FFFh 118000h–11FFFFh 120000h–127FFFh 128000h–12FFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 0F0000h–0F7FFFh 0F8000h–0FFFFFh 100000h–107FFFh 108000h–10FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 0D0000h–0D7FFFh 0D8000h–0DFFFFh 0E0000h–0E7FFFh 0E8000h–0EFFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 0B0000h–0B7FFFh 0B8000h–0BFFFFh 0C0000h–0C7FFFh 0C8000h–0CFFFFh Protection Block Group (x8) 140000h-14FFFFh 150000h-15FFFFh (x16) 0A0000h–0A7FFFh 0A8000h–0AFFFFh Bank A 32 Bank B 48 70/94 M29DW128F Table 34. Bank Block addresses and Read/Modify Protection Groups Block Addresses and Protection Groups (continued) Block 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 77 78 79 80 81 82 83 84 85 86 87 88 89 90 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 520000h–52FFFFh 530000h–53FFFFh 290000h–297FFFh 298000h–29FFFFh 4E0000h–4EFFFFh 4F0000h–4FFFFFh 500000h–50FFFFh 510000h–51FFFFh 270000h–277FFFh 278000h–27FFFFh 280000h–287FFFh 288000h–28FFFFh 4A0000h–4AFFFFh 4B0000h–4BFFFFh 4C0000h–4CFFFFh 4D0000h–4DFFFFh 250000h–257FFFh 258000h–25FFFFh 260000h–267FFFh 268000h–26FFFFh 460000h–46FFFFh 470000h–47FFFFh 480000h–48FFFFh 490000h–49FFFFh 230000h–237FFFh 238000h–23FFFFh 240000h–247FFFh 248000h–24FFFFh 420000h–42FFFFh 430000h–43FFFFh 440000h–44FFFFh 450000h–45FFFFh 210000h–217FFFh 218000h–21FFFFh 220000h–227FFFh 228000h–22FFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h–40FFFFh 410000h–41FFFFh 1F0000h–1F7FFFh 1F8000h–1FFFFFh 200000h–207FFFh 208000h–20FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 1D0000h–1D7FFFh 1D8000h–1DFFFFh 1E0000h–1E7FFFh 1E8000h–1EFFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 1B0000h–1B7FFFh 1B8000h–1BFFFFh 1C0000h–1C7FFFh 1C8000h–1CFFFFh Protection Block Group (x8) 340000h-34FFFFh 350000h-35FFFFh (x16) 1A0000h–1A7FFFh 1A8000h–1AFFFFh Bank B 74 75 76 71/94 Block addresses and Read/Modify Protection Groups Table 34. Bank M29DW128F Block Addresses and Protection Groups (continued) Block 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 109 110 111 112 113 114 115 116 117 118 119 120 121 122 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 720000h–72FFFFh 730000h–73FFFFh 390000h–397FFFh 398000h–39FFFFh 6E0000h–6EFFFFh 6F0000h–6FFFFFh 700000h–70FFFFh 710000h–71FFFFh 370000h–377FFFh 378000h–37FFFFh 380000h–387FFFh 388000h–38FFFFh 6A0000h–6AFFFFh 6B0000h–6BFFFFh 6C0000h–6CFFFFh 6D0000h–6DFFFFh 350000h–357FFFh 358000h–35FFFFh 360000h–367FFFh 368000h–36FFFFh 660000h–66FFFFh 670000h–67FFFFh 680000h–68FFFFh 690000h–69FFFFh 330000h–337FFFh 338000h–33FFFFh 340000h–347FFFh 348000h–34FFFFh 620000h–62FFFFh 630000h–63FFFFh 640000h–64FFFFh 650000h–65FFFFh 310000h–317FFFh 318000h–31FFFFh 320000h–327FFFh 328000h–32FFFFh 5E0000h–5EFFFFh 5F0000h–5FFFFFh 600000h–60FFFFh 610000h–61FFFFh 2F0000h–2F7FFFh 2F8000h–2FFFFFh 300000h–307FFFh 308000h–30FFFFh 5A0000h–5AFFFFh 5B0000h–5BFFFFh 5C0000h–5CFFFFh 5D0000h–5DFFFFh 2D0000h–2D7FFFh 2D8000h–2DFFFFh 2E0000h–2E7FFFh 2E8000h–2EFFFFh 560000h–56FFFFh 570000h–57FFFFh 580000h–58FFFFh 590000h–59FFFFh 2B0000h–2B7FFFh 2B8000h–2BFFFFh 2C0000h–2C7FFFh 2C8000h–2CFFFFh Protection Block Group (x8) 540000h–54FFFFh 550000h–55FFFFh (x16) 2A0000h–2A7FFFh 2A8000h–2AFFFFh Bank B 106 107 108 72/94 M29DW128F Table 34. Bank Block addresses and Read/Modify Protection Groups Block Addresses and Protection Groups (continued) Block 123 124 125 126 127 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 145 146 147 148 149 150 151 152 153 154 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 920000h–92FFFFh 930000h–93FFFFh 490000h–497FFFh 498000h–49FFFFh 8E0000h–8EFFFFh 8F0000h-8FFFFFh 900000h-90FFFFh 910000h–91FFFFh 470000h–477FFFh 478000h–47FFFFh 480000h–487FFFh 488000h–48FFFFh 8A0000h–8AFFFFh 8B0000h–8BFFFFh 8C0000h–8CFFFFh 8D0000h–8DFFFFh 450000h–457FFFh 458000h–45FFFFh 460000h–467FFFh 468000h–46FFFFh 860000h–86FFFFh 870000h–87FFFFh 880000h–88FFFFh 890000h–89FFFFh 430000h–437FFFh 438000h–43FFFFh 440000h–447FFFh 448000h–44FFFFh 820000h–82FFFFh 830000h–83FFFFh 840000h–84FFFFh 850000h–85FFFFh 410000h–417FFFh 418000h–41FFFFh 420000h–427FFFh 428000h–42FFFFh 7E0000h–7EFFFFh 7F0000h-7FFFFFh 800000h–80FFFFh 810000h–81FFFFh 3F0000h–3F7FFFh 3F8000h-3FFFFFh 400000h–407FFFh 408000h–40FFFFh 7A0000h–7AFFFFh 7B0000h–7BFFFFh 7C0000h–7CFFFFh 7D0000h–7DFFFFh 3D0000h–3D7FFFh 3D8000h–3DFFFFh 3E0000h–3E7FFFh 3E8000h–3EFFFFh 760000h–76FFFFh 770000h–77FFFFh 780000h–78FFFFh 790000h–79FFFFh 3B0000h–3B7FFFh 3B8000h–3BFFFFh 3C0000h–3C7FFFh 3C8000h–3CFFFFh Protection Block Group (x8) 740000h–74FFFFh 750000h–75FFFFh (x16) 3A0000h–3A7FFFh 3A8000h–3AFFFFh Bank B 128 Bank C 144 73/94 Block addresses and Read/Modify Protection Groups Table 34. Bank M29DW128F Block Addresses and Protection Groups (continued) Block 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 173 174 175 176 177 178 179 180 181 182 183 184 185 186 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 B20000h–B2FFFFh B30000h-B3FFFFh 590000h–597FFFh 598000h–59FFFFh AE0000h–AEFFFFh AF0000h-AFFFFFh B00000h–B0FFFFh B10000h–B1FFFFh 570000h–577FFFh 578000h–57FFFFh 580000h–587FFFh 588000h–58FFFFh AA0000h–AAFFFFh AB0000h–ABFFFFh AC0000h–ACFFFFh AD0000h–ADFFFFh 550000h–557FFFh 558000h–55FFFFh 560000h–567FFFh 568000h–56FFFFh A60000h–A6FFFFh A70000h–A7FFFFh A80000h–A8FFFFh A90000h–A9FFFFh 530000h–537FFFh 538000h–53FFFFh 540000h–547FFFh 548000h–54FFFFh A20000h–A2FFFFh A30000h–A3FFFFh A40000h–A4FFFFh A50000h–A5FFFFh 510000h–517FFFh 518000h–51FFFFh 520000h–527FFFh 528000h–52FFFFh 9E0000h–9EFFFFh 9F0000h–9FFFFFh A00000h–A0FFFFh A10000h–A1FFFFh 4F0000h–4F7FFFh 4F8000h-4FFFFFh 500000h–507FFFh 508000h–50FFFFh 9A0000h–9AFFFFh 9B0000h–9BFFFFh 9C0000h–9CFFFFh 9D0000h–9DFFFFh 4D0000h–4D7FFFh 4D8000h–4DFFFFh 4E0000h–4E7FFFh 4E8000h–4EFFFFh 960000h–96FFFFh 970000h–97FFFFh 980000h–98FFFFh 990000h–99FFFFh 4B0000h–4B7FFFh 4B8000h–4BFFFFh 4C0000h–4C7FFFh 4C8000h–4CFFFFh Protection Block Group (x8) 940000h–94FFFFh 950000h–95FFFFh (x16) 4A0000h–4A7FFFh 4A8000h–4AFFFFh Bank C 170 171 172 74/94 M29DW128F Table 34. Bank Block addresses and Read/Modify Protection Groups Block Addresses and Protection Groups (continued) Block 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 205 206 207 208 209 210 211 212 213 214 215 216 217 218 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 D20000h–D2FFFFh D30000h–D3FFFFh 690000h–697FFFh 698000h–69FFFFh CE0000h–CEFFFFh CF0000h-CFFFFFh D00000h–D0FFFFh D10000h–D1FFFFh 670000h–677FFFh 678000h–67FFFFh 680000h–687FFFh 688000h–68FFFFh CA0000h–CAFFFFh CB0000h–CBFFFFh CC0000h–CCFFFFh CD0000h–CDFFFFh 650000h–657FFFh 658000h–65FFFFh 660000h–667FFFh 668000h–66FFFFh C60000h–C6FFFFh C70000h-C7FFFFh C80000h–C8FFFFh C90000h–C9FFFFh 630000h–637FFFh 638000h–63FFFFh 640000h–647FFFh 648000h–64FFFFh C20000h–C2FFFFh C30000h–C3FFFFh C40000h–C4FFFFh C50000h–C5FFFFh 610000h–617FFFh 618000h–61FFFFh 620000h–627FFFh 628000h–62FFFFh BE0000h–BEFFFFh BF0000h–BFFFFFh C00000h–C0FFFFh C10000h–C1FFFFh 5F0000h–5F7FFFh 5F8000h-5FFFFFh 600000h–607FFFh 608000h–60FFFFh BA0000h–BAFFFFh BB0000h–BBFFFFh BC0000h–BCFFFFh BD0000h–BDFFFFh 5D0000h–5D7FFFh 5D8000h–5DFFFFh 5E0000h–5E7FFFh 5E8000h–5EFFFFh B60000h–B6FFFFh B70000h-B7FFFFh B80000h–B8FFFFh B90000h–B9FFFFh 5B0000h–5B7FFFh 5B8000h–5BFFFFh 5C0000h–5C7FFFh 5C8000h–5CFFFFh Protection Block Group (x8) B40000h–B4FFFFh B50000h–B5FFFFh (x16) 5A0000h–5A7FFFh 5A8000h–5AFFFFh Bank C 202 203 204 75/94 Block addresses and Read/Modify Protection Groups Table 34. Bank M29DW128F Block Addresses and Protection Groups (continued) Block 219 220 221 222 223 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 241 242 243 244 245 246 247 248 249 250 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 F20000h-F2FFFFh F30000h-F3FFFFh 790000h–797FFFh 798000h–79FFFFh EE0000h-EEFFFFh EF0000h-EFFFFFh F00000h-F0FFFFh F10000h-F1FFFFh 770000h–777FFFh 778000h–77FFFFh 780000h–787FFFh 788000h–78FFFFh EA0000h-EAFFFFh EB0000h-EBFFFFh EC0000h-ECFFFFh ED0000h-EDFFFFh 750000h–757FFFh 758000h–75FFFFh 760000h–767FFFh 768000h–76FFFFh E60000h-E6FFFFh E70000h-E7FFFFh E80000h-E8FFFFh E90000h-E9FFFFh 730000h–737FFFh 738000h–73FFFFh 740000h–747FFFh 748000h–74FFFFh E20000h-E2FFFFh E30000h-E3FFFFh E40000h-E4FFFFh E50000h-E5FFFFh 710000h–717FFFh 718000h–71FFFFh 720000h–727FFFh 728000h–72FFFFh DE0000h-DEFFFFh DF0000h-DFFFFFh E00000h-E0FFFFh E10000h-E1FFFFh 6F0000h–6F7FFFh 6F8000h-6FFFFFh 700000h–707FFFh 708000h–70FFFFh DA0000h-DAFFFFh DB0000h-DBFFFFh DC0000h-DCFFFFh DD0000h-DDFFFFh 6D0000h–6D7FFFh 6D8000h–6DFFFFh 6E0000h–6E7FFFh 6E8000h–6EFFFFh D60000h–D6FFFFh D70000h-D7FFFFh D80000h-D8FFFFh D90000h-D9FFFFh 6B0000h–6B7FFFh 6B8000h–6BFFFFh 6C0000h–6C7FFFh 6C8000h–6CFFFFh Protection Block Group (x8) D40000h–D4FFFFh D50000h–D5FFFFh (x16) 6A0000h–6A7FFFh 6A8000h–6AFFFFh Bank C 224 Bank D 240 76/94 M29DW128F Table 34. Bank Block addresses and Read/Modify Protection Groups Block Addresses and Protection Groups (continued) Block 251 252 253 254 255 256 257 258 Size (kbytes/KWords) 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 Protection Group 64/32 64/32 64/32 64/32 64/32 8/4 8/4 8/4 8/4 8/4 8/4 8/4 8/4 Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group Protection Group FA0000h-FAFFFFh FB0000h-FBFFFFh FC0000h-FCFFFFh FD0000h-FDFFFFh FE0000h-FEFFFFh FF0000h-FF1FFFh (1) Protection Block Group (x8) F40000h-F4FFFFh F50000h-F5FFFFh F60000h-F6FFFFh F70000h-F7FFFFh F80000h-F8FFFFh F90000h-F9FFFFh (x16) 7A0000h–7A7FFFh 7A8000h–7AFFFFh 7B0000h–7B7FFFh 7B8000h–7BFFFFh 7C0000h–7C7FFFh 7C8000h–7CFFFFh 7D0000h–7D7FFFh 7D8000h–7DFFFFh 7E0000h–7E7FFFh 7E8000h–7EFFFFh 7F0000h-7F7FFFh 7F8000h-7F8FFFh(1) 7F9000h-7F9FFFh(1) 7FA000h-7FAFFFh(1) 7FB000h-7FBFFFh(1) 7FC000h-7FCFFFh(1) 7FD000h-7FDFFFh(1) 7FE000h-7FEFFFh(1) 7FF000h-7FFFFFh(1) Bank D 259 260 261 262 263 264 265 266 267 268 269 FF2000h-FF3FFFh(1) FF4000h-FF5FFFh(1) FF6000h-FF7FFFh(1) FF8000h-FF9FFFh(1) FFA000h-FFBFFFh(1) FFC000h-FFDFFFh(1) FFE000h-FFFFFFh(1) 1. Parameter Blocks. 77/94 Common Flash Interface (CFI) M29DW128F Appendix B Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query command is issued the addressed bank enters Read CFI Query mode and read operations in the same bank (A22-A19) output the CFI data. Table 35, Table 36, Table 37, Table 38, Table 39 and Table 40 show the addresses (A-1, A0-A10) used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 40: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Table 35. Query Structure Overview(1) Sub-section Name x16 10h 1Bh 27h 40h 61h x8 20h 36h 4Eh 80h C2h CFI Query Identification String System Interface Information Device Geometry Definition Primary Algorithm-specific Extended Query table Security Code Area Command set ID and algorithm data offset Device timing & voltage information Flash device layout Additional information specific to the Primary Algorithm (optional) 64 bit unique device number Description Address 1. Query data are always presented on the lowest order data outputs. Table 36. CFI Query Identification String(1) Data Description Value “Q” Query Unique ASCII String "QRY" "R" "Y" AMD Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Compatible Address for Primary Algorithm extended Query table (see Table 39) P = 40h Address x16 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah x8 20h 22h 24h 26h 28h 2Ah 2Ch 2Eh 30h 32h 34h 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h Address for Alternate Algorithm extended Query table 0000h 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA NA 78/94 M29DW128F Table 37. CFI Query System Interface information(1) Data x16 x8 Description Common Flash Interface (CFI) Address Value 1Bh 36h 0027h VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100mV VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100mV VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100mV VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4HEX value in volts bit 3 to 0BCD value in 10mV Typical timeout per single byte/Word program = 2n µs Typical timeout for minimum size write buffer program = Typical timeout per individual block erase = 2 ms Typical timeout for full Chip Erase = 2 ms Maximum timeout for byte/Word program = 2n times typical Maximum timeout for write buffer program = 2 times typical Maximum timeout per individual block erase = 2 times typical Maximum timeout for Chip Erase = 2n times typical n n n n 2.7V 1Ch 38h 0036h 3.6V 1Dh 3Ah 00B5h 11.5V 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 00C5h 0004h 0000h 0009h 0000h 0005h 0000h 0004h 0000h 12.5V 16µs 2n µs NA 512ms NA 512µs NA 8s NA 1. The values given in the above table are valid for both packages. 79/94 Common Flash Interface (CFI) Table 38. Device Geometry Definition(1) Data x16 27h x8 4Eh 0018h 0001h 28h 50h 0002h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 52h 54h 56h 58h 5Ah 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 78h 0000h 0006h 0000h 0003h 0007h 0000h 0020h 0000h 00FDh 0000h 0000h 0001h 0007h 0000h 0020h 0000h 0000h 0000h 0000h 0000h Number of Erase Block Regions(1). It specifies the number of regions containing contiguous Erase Blocks of the same size. Erase Block Region 1 Information Number of Erase Blocks of identical size = 0007h+1 Erase Block Region 1 Information Block size in Region 1 = 0020h * 256 byte Erase Block Region 2 Information Number of Erase Blocks of identical size = 00FDh+1 Erase Block Region 2 Information Block size in Region 2 = 0100h * 256 byte Erase Block Region 3 information Number of Erase Blocks of identical size = 0007h + 1 Erase Block Region 3 information Block size in region 3 = 0020h * 256 bytes TSOP56 Flash Device Interface Code description (x8/x16) Both Packages Maximum number of bytes in Multiple-byte program or Page= 2n Device Size = 2n in number of bytes TBGA64 (x16 only) Description M29DW128F Address Value 16 Mbytes x8, x16 Async. 64 3 8 8 Kbytes 254 64 Kbytes 8 8 Kbytes Erase Block Region 4 information 0 1. Erase Block Region 1 corresponds to addresses 000000h to 007FFFh; Erase block Region 2 corresponds to addresses 008000h to 3F7FFFh and Erase Block Region 3 corresponds to addresses 3F8000h to 3FFFFFh. 80/94 M29DW128F Table 39. Primary Algorithm-Specific Extended Query table (1) Data x16 40h 41h 42h 43h 44h 45h x8 80h 82h 84h 86h 88h 8Ah 0050h 0052h 0049h 0031h 0033h 000Ch Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Description Common Flash Interface (CFI) Address Value "P" Primary Algorithm Extended Query table unique ASCII string “PRI” "R" "I" "1" "3" Yes 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 0002h 0001h 0001h 0006h 00E7 0000h 0002h 00B5h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write Block Protection 00 = not supported, x = number of sectors in per group Temporary Block Unprotect 00 = not supported, 01 = supported Block Protect /Unprotect 06 = M29DW128F Simultaneous Operations, x = number of blocks (excluding Bank A) Burst Mode, 00 = not supported, 01 = supported Page Mode, 00 = not supported, 02 = 8-Word page VPP Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100mV VPP Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100mV Top/Bottom Boot Block Flag 00h = Uniform device 01h = 8 x8 Kbyte Blocks or 4KWords, Top and Bottom Boot with Write Protect 02h = Bottom boot device 03h = Top Boot Device 04h = Both Top and Bottom Program Suspend, 00 = not supported, 01 = supported Bank Organization, 00 = data at 4Ah is zero X = number of banks Bank A information X = number of blocks in Bank A 2 1 Yes 6 231 No Yes 11.5V 4Eh 9Ch 00C5h 12.5V 4Fh 9Eh 0001h T/B 50h 57h 58h A0h AEh B0h 0001h 0004h 0027h Yes 4 39 81/94 Common Flash Interface (CFI) Table 39. Primary Algorithm-Specific Extended Query table (continued)(1) Data x16 59h 5Ah 5Bh x8 B2h B4h B6h 0060h 0060h 0027h Bank B information X = number of blocks in Bank B Bank C information X = number of blocks in Bank C Bank D information X = number of blocks in Bank D Description M29DW128F Address Value 96 96 39 1. The values given in the above table are valid for both packages. Table 40. Security Code Area Data Description Address x16 61h 62h 63h 64h x8 C3h, C2h C5h, C4h C7h, C6h C9h, C8h XXXX XXXX 64 bit: unique device number XXXX XXXX 82/94 M29DW128F Extended Memory Block Appendix C Extended Memory Block The M29DW128F has an extra block, the Extended Block, that can be accessed using a dedicated command. This Extended Block is 128 Words in x16 mode and 256 bytes in x8 mode. It is used as a security block (to provide a permanent security identification number) or to store additional information. The Extended Block is divided into two memory areas of 64 Words each: ● ● The first one is Factory Locked. The second one is Customer Lockable. It is up to the customer to protect it from program operations. Its status is indicated by bit DQ6 and DQ7. When DQ7 is set to ‘1’ and DQ6 to ‘0’, it indicates that this second memory area is Customer Lockable. When DQ7 and DQ6 are both set to ‘1’, it indicates that the second part of the Extended Block is Customer Locked and protected from program operations. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. Bits DQ6 and DQ7 are the most significant bits in the Extended Block Protection Indicator and a specific procedure must be followed to read it. See “Section 3.6.2: Verify Extended Block Protection Indicator” and Table 5 and Table 8, Block Protection, for details of how to read bit DQ7. The Extended Block can only be accessed when the device is in Extended Block mode. For details of how the Extended Block mode is entered and exited, refer to the Section 6.1.11: Program command and Section 6.3.2: Exit Extended Block command paragraphs, and to Table 15 and Table 16, Block Protection Commands. C.1 Factory Locked Section of the Extended Block The first section of The Extended Block is permanently protected from program operations and cannot be unprotected. The Random Number, Electronic Serial Number (ESN) and Security Identification Number (see Table 41: Extended Block Address and Data) are written in this section in the factory. 83/94 Extended Memory Block M29DW128F C.2 Customer Lockable Section of the Extended Block The device is delivered with the second section of the Extended Block "Customer Lockable": bits DQ7 and DQ6 are set to '1' and '0' respectively. It is up to the customer to program and protect this section of the Extended Block but care must be taken because the protection is not reversible. There are three ways of protecting this section: ● Issue the Enter Extended Block command to place the device in Extended Block mode, then use the In-System Technique with RP either at VIH or at VID. Refer to Section D.2: In-System technique in Appendix D: High Voltage Block Protection, and to the corresponding flowcharts Figure 25 and Figure 26 for a detailed explanation of the technique). Issue the Enter Extended Block command to place the device in Extended Block mode, then use the Programmer Technique. Refer to Section D.1: Programmer technique in Appendix D: High Voltage Block Protection, and to the corresponding flowcharts Figure 23 and Figure 24 for a detailed explanation of the technique). Issue a Set Extended Block Protection bit command to program the Extended Block Protection bit to ‘1’ thus preventing the second section of the Extended Block from being programmed. ● ● Bit DQ6 of the Extended Block Protection Indicator is automatically set to '1' to indicate that the second section of the Extended Block is Customer Locked. Once the Extended Block is programmed and protected, the Exit Extended Block command must be issued to exit the Extended Block mode and return the device to Read mode. Table 41. Device x8 000000h00007Fh M29DW128F 000080h0000FFh 000040h00007Fh x16 000000h00003Fh Factory Locked Random Number, ESN(2), Security Identification Number Unavailable Customer Lockable Unavailable Determined by Customer Extended Block Address and Data Address(1) Data 1. See Table 34: Block Addresses and Protection Groups. 2. ESN = Electronic Serial Number. 84/94 M29DW128F High Voltage Block Protection Appendix D High Voltage Block Protection The High Voltage Block Protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A, Table 34 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. To protect the Extended Block issue the Enter Extended Block command and then use either the Programmer or In-System technique. Once protected issue the Exit Extended Block command to return to read mode. The Extended Block protection is irreversible, once protected the protection cannot be undone. D.1 Programmer technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 23: Programmer equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 24: Programmer equipment Chip Unprotect flowchart. Table 42: Programmer technique Bus operations, 8-bit or 16-bit mode, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 85/94 High Voltage Block Protection M29DW128F D.2 (1) In-System technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP . This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 25: In-System equipment Group Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 26: In-System equipment Chip Unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Note: RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. Programmer technique Bus operations, 8-bit or 16-bit mode E G W Address Inputs A0-A22 A9 = VID, A12-A22 Block Address Others = X A6 = VIH, A9 = VID, A12 = VIH, A15 = VIH Others = X A0 = VIL, A1 = VIH, A2-A7 = VIL, A9 = VID, A12-A22 Block Address Others = X A0 = VIL, A1 = VIH, A2 -A5 = VIL, A6 = VIH, A7 = VIL, A9 = VID, A12-A22 Block Address Others = X Data Inputs/Outputs DQ15A–1, DQ14-DQ0 X X Pass = xx01h Retry = xx00h. Table 42. Operation Block (Group) Protect(1) Chip Unprotect Block (Group) Protect Verify VIL VID VID VID VIL Pulse VIL Pulse VIL VIL VIH Block (Group) Unprotect Verify VIL VIL VIH Pass = xx00h Retry = xx01h. 1. Block Protection Groups are shown inAppendix A, Table 34. 86/94 M29DW128F Flowcharts Appendix E Flowcharts Figure 23. Programmer equipment Group Protect flowchart START ADDRESS = GROUP ADDRESS Set-up W = VIH n=0 G, A9 = VID, E = VIL Wait 4µs W = VIL Protect Wait 100µs W = VIH E, G = VIH, A1 = VIH A0, A2 to A7 = VIL E = VIL Wait 4µs Verify G = VIL Wait 60ns Read DATA DATA = 01h YES A9 = VIH E, G = VIH End PASS NO ++n = 25 YES A9 = VIH E, G = VIH FAIL NO AI07756b 1. Block Protection Groups are shown in Appendix A, Table 34. 87/94 Flowcharts Figure 24. Programmer equipment Chip Unprotect flowchart START PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 M29DW128F Set-up A6, A12, A15 = VIH(1) E, G, A9 = VID Wait 4µs Unprotect W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0, A2, A3, A4, A5, A7 = VIL A1, A6 = VIH E = VIL Wait 4µs INCREMENT CURRENT GROUP G = VIL Verify Wait 60ns Read DATA NO DATA = 00h YES NO ++n = 1000 YES LAST GROUP YES A9 = VIH E, G = VIH PASS NO End A9 = VIH E, G = VIH FAIL AI07757b 1. Block Protection Groups are shown in Appendix A, Table 34. 88/94 M29DW128F Figure 25. In-System equipment Group Protect flowchart Flowcharts START Set-up n=0 RP = VID WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH WRITE 60h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Wait 100µs WRITE 40h ADDRESS = GROUP ADDRESS A0, A2, A3, A6 = VIL, A1 = VIH Verify Wait 4µs READ DATA ADDRESS = GROUP ADDRESS A1 = VIH, A0, A2 to A7 = VIL NO Protect DATA = 01h YES RP = VIH End ++n = 25 YES RP = VIH NO ISSUE READ/RESET COMMAND PASS ISSUE READ/RESET COMMAND FAIL AI07758b 1. Block Protection Groups are shown in Appendix A, Table 34. 2. RP can be either at VIH or at VID when using the In-System Technique to protect the Extended Block. 89/94 Flowcharts Figure 26. In-System equipment Chip Unprotect flowchart START PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 M29DW128F Set-up RP = VID WRITE 60h ANY ADDRESS WITH A1 = VIH, A0, A2 to A7 = VIL Unprotect WRITE 60h ANY ADDRESS WITH A0, A2, A3, A4, A5, A7 = VIL A1, A6 = VIH Wait 10ms WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A1 = VIH, A0, A2 to A7 = VIL Verify Wait 4µs READ DATA ADDRESS = CURRENT GROUP ADDRESS A1 = VIH, A0, A2 to A7 = VIL NO YES INCREMENT CURRENT GROUP DATA = 00h NO End ++n = 1000 YES RP = VIH LAST GROUP YES RP = VIH NO ISSUE READ/RESET COMMAND FAIL ISSUE READ/RESET COMMAND PASS AI07759d 1. Block Protection Groups are shown in Appendix A, Table 34. 90/94 M29DW128F Figure 27. Write to Buffer and Program flowchart and Pseudo Code Start Write to Buffer F0h Command, Block Address Write n(1), Block Address Flowcharts First Part of the Write to Buffer and Program Command Write Buffer Data, Start Address X=n X=0 NO Abort Write to Buffer NO YES YES Write to a Different Block Address Write Next Data,(3) Program Address Pair Write to Buffer and Program Aborted(2) X = X-1 Program Buffer to Flash Block Address Read Status Register (DQ1, DQ5, DQ7) at Last Loaded Address YES DQ7 = Data NO DQ1 = 1 YES NO NO DQ5 = 1 YES Check Status Register (DQ5, DQ7) at Last Loaded Address DQ7 = Data (4) YES NO FAIL OR ABORT(5) END AI08968b 1. n+1 is the number of addresses to be programmed. 2. A Write to Buffer and Program Abort and Reset must be issued to return the device in Read mode. 91/94 Flowcharts M29DW128F 3. When the block address is specified, any address in the selected block address space is acceptable. However when loading Write Buffer address with data, all addresses must fall within the selected Write Buffer page. 4. DQ7 must be checked since DQ5 and DQ7 may change simultaneously. 5. If this flowchart location is reached because DQ5=’1’, then the Write to Buffer and Program command failed. If this flowchart location is reached because DQ1=’1’, then the Write to Buffer and Program command aborted. In both cases, the appropriate reset command must be issued to return the device in Read mode: a Reset command if the operation failed, a Write to Buffer and Program Abort and Reset command if the operation aborted. 6. See Table 11 and Table 12, for details on Write to Buffer and Program command sequence. 92/94 M29DW128F Revision history Revision history Table 43. Date 02-Aug-2005 13-Oct-2005 Document revision history Revision 1.0 2.0 Changes First Issue derived from the M29DW128F/FS datasheet revision 0.5. Table 18: Program, Erase Times and Program, Erase Endurance Cycles updated. Datasheet status updated to “FULL DATASHEET“. Program Suspend Latency time updated in Table 18: Program, Erase Times and Program, Erase Endurance Cycles. Table 19: Status Register bits: DQ7 changed into DQ7 for Program, Program Error and Program during Erase Suspend operations. Section 6.2.1: Write to Buffer and Program command, and Section 6.2.2: Write to Buffer and Program Confirm command updated to cover 8-bit mode. Note 2, Note 3, and Note 4 updated in Table 13: Fast Program Commands, 8-bit mode. Blank Verify command added in Section 6: Command interface. Input/output supply voltage, VCCQ, removed. Address Inputs A7-A0 modified for NVMPbits in Table 17: Protection Command Addresses. Updated Table 19: Status Register bits; updated blank verify command description and removed verify command in Section 6: Command interface. 02-Dec-2005 3.0 13-Mar-2006 4.0 13-Jun-2006 20-Jun-2006 5 6 26-Oct-2006 7 93/94 M29DW128F Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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