M29F080D90N1

M29F080D 8 Mbit (1Mb x8, Uniform Block) 5V Supply Flash Memory FEATURES SUMMARY ■ SUPPLY VOLTAGE Figure 1. Packages – VCC = 5V ±10% for PROGRAM, ERASE and READ OPERATIONS ■ ACCESS TIME: 55, 70, 90ns ■ PROGRAMMING TIME – 10µs per Byte typical ■ 16 UNIFORM 64Kbyte MEMORY BLOCKS ■ PROGRAM/ERASE CONTROLLER – Embedded Byte Program algorithms ■ ERASE SUSPEND and RESUME MODES TSOP40 (N) 10 x 20mm – Read and Program another Block during Erase Suspend ■ UNLOCK BYPASS PROGRAM COMMAND – Faster Production/Batch Programming ■ TEMPORARY BLOCK UNPROTECTION MODE ■ COMMON FLASH INTERFACE SO44 (M) – 64 bit Security Code ■ LOW POWER CONSUMPTION – Standby and Automatic Standby ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code: F1h ■ ECOPACK® PACKAGES AVAILABLE September 2005 1/37 M29F080D TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VCC Supply Voltage (5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/37 M29F080D Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 13 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 23 TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 23 SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline. . . . . . . . . . . . . . . . 24 SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . . . . . . . 24 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 15. Block Addresses, M29F080D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/37 M29F080D Table 16. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 17. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 18. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 19. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 20. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 21. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 22. Programmer Technique Bus Operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . 31 Figure 14. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 16. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 23. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4/37 M29F080D SUMMARY DESCRIPTION The M29F080D is a 8 Mbit (1Mb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into 16 uniform blocks of 64Kbytes (see Figure 5, Block Addresses) that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected in groups of 4 to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in TSOP40 (10 x 20mm) and SO44 packages. Access times of 55, 70 and 90ns are available. In order to meet environmental requirements, ST offers the M29F080D in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. The memory is supplied with all the bits erased (set to ’1’). Figure 2. Logic Diagram Table 1. Signal Names VCC 20 8 A0-A19 DQ0-DQ7 W E M29F080D G RB RP A0-A19 Address Inputs DQ0-DQ7 Data Inputs/Outputs E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output VCC Supply Voltage VSS Ground NC Not Connected Internally VSS AI06141 5/37 M29F080D Figure 3. TSOP Connections A19 A18 A17 A16 A15 A14 A13 A12 E VCC NC RP A11 A10 A9 A8 A7 A6 A5 A4 1 10 11 20 Figure 4. SO Connections 40 M29F080D 31 30 21 NC RP A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VSS VSS NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC VSS VSS DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 AI06142 6/37 1 44 43 2 3 42 4 41 40 5 39 6 38 7 37 8 36 9 35 10 34 11 M29F080D 33 12 13 32 14 31 30 15 29 16 17 28 18 27 19 26 20 25 21 24 22 23 VCC E A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC W G RB DQ7 DQ6 DQ5 DQ4 VCC AI06143 M29F080D Figure 5. Block Addresses M29F080D Block Addresses 0FFFFFh 64 KByte 0F0000h 0EFFFFh 64 KByte 0E0000h 0DFFFFh 64 KByte 0D0000h 0CFFFFh Total of 16 64 KByte Blocks 02FFFFh 64 KByte 020000h 01FFFFh 64 KByte 010000h 00FFFFh 64 KByte 000000h AI06144 Note: Also see Appendix A, Table 15 for a full listing of the Block Addresses. 7/37 M29F080D SIGNAL DESCRIPTIONS See Figure 2, Logic Diagram, and Table 1, Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Reset/Block Temporary Unprotect (RP). The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/ Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See the Ready/Busy Output section, Table 13 and Figure 13, Reset/ Temporary Unprotect AC Characteristics for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and 8/37 Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 13 and Figure 13, Reset/Temporary Unprotect AC Characteristics. The use of an open-drain output allows the Ready/ Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. VCC Supply Voltage (5V). VCC provides the power supply for all operations (Read, Program and Erase). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply, see Figure 10, AC Measurement Load Circuit. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. VSS Ground. VSS is the reference for all voltage measurements. M29F080D BUS OPERATIONS There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Tables 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10, Read Mode AC Waveforms, and Table 10, Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figures 11 and 12, Write AC Waveforms, and Tables 11 and 12, Write AC Characteristics, for details of the timing requirements. Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. Standby. When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 9, DC Characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. Automatic Standby. If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. Special Bus Operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Tables 2, Bus Operations. Block Protection and Blocks Unprotection. Blocks can be protected in groups of 4 against accidental Program or Erase. See Appendix A, Table 15, Block Addresses, for details of which blocks must be protected together as a group. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. Block Protect and Chip Unprotect operations are described in Appendix C. Table 2. Bus Operations Operation Address Inputs A0-A19 Data Inputs/Outputs DQ7-DQ0 E G W Bus Read VIL VIL VIH Cell Address Bus Write VIL VIH VIL Command Address X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 20h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH F1h Output Disable Data Output Data Input Note: X = VIL or VIH. 9/37 M29F080D COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. Refer to Table 3, Commands, in conjunction with the following text descriptions. Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/ Reset commands are accepted in Auto Select mode, all other commands are ignored. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 20h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Device Code for the M29F080D F1h. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A19 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0DQ7, otherwise 00h is output. Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. 10/37 If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the cycle time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. Unlock Bypass Reset Command. The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset M29F080D command does not exit from Unlock Bypass Mode. Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 4. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register section for details on how to identify if the Program/ Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 4. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. Erase Suspend Command. The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume. 11/37 M29F080D During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. Erase Resume Command. The Erase Resume command must be used to restart the Program/ Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once. Read CFI Query Command. The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This 12/37 command is valid when the device is in the Read Array mode, or when the device is in Autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/ Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode. See Appendix B, Tables 16, 17, 18, 19, 20 and 21 for details on the information contained in the Common Flash Interface (CFI) memory area. Block Protect and Chip Unprotect Commands. Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A, Table 15. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix C. M29F080D Length Table 3. Commands Command Bus Write Operations 1st 2nd Addr Data 1 X F0 3 555 Auto Select 3 Program 3rd 4th Addr Data Addr Data AA 2AA 55 X F0 555 AA 2AA 55 555 90 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 Block Erase 6+ 555 AA 2AA 55 555 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 55 98 5th Addr Data PA PD 80 555 80 555 6th Addr Data Addr Data AA 2AA 55 555 10 AA 2AA 55 BA 30 Read/Reset Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. Table 4. Program, Erase Times and Program, Erase Endurance Cycles Typ (1) Typical after 100k W/E Cycles (1) Max Unit Chip Erase 12 12 60 s Block Erase (64 Kbytes) 0.8 6 s Program (Byte) 10 200 µs Chip Program (Byte by Byte) 12 60 s Parameter Program/Erase Cycles (per Block) Min 100,000 cycles Note: 1. TA = 25°C, VCC = 5V. 13/37 M29F080D STATUS REGISTER Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 5, Status Register Bits. Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 6, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no er- 14/37 ror is signalled and DQ6 toggles for approximately 1µs. Figure 7, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit. Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. Alternative Toggle Bit (DQ2). The Alternative Toggle Bit can be used to monitor the Program/ Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. M29F080D Table 5. Status Register Bits Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Any Address DQ7 Toggle 0 – – 0 Program During Erase Suspend Any Address DQ7 Toggle 0 – – 0 Program Error Any Address DQ7 Toggle 1 – – 0 Chip Erase Any Address 0 Toggle 0 1 Toggle 0 Block Erase before timeout Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 – Toggle 1 Block Erase Erase Suspend Non-Erasing Block Data read as normal 1 Good Block Address 0 Toggle 1 1 No Toggle 0 Faulty Block Address 0 Toggle 1 1 Toggle 0 Erase Error Note: Unspecified data bits should be ignored. Figure 6. Data Polling Flowchart Figure 7. Data Toggle Flowchart START START READ DQ5 & DQ6 READ DQ5 & DQ7 at VALID ADDRESS READ DQ6 DQ7 = DATA YES DQ6 = TOGGLE NO NO YES NO DQ5 =1 NO YES DQ5 =1 YES READ DQ7 at VALID ADDRESS READ DQ6 TWICE DQ7 = DATA YES DQ6 = TOGGLE NO FAIL PASS NO YES FAIL PASS AI05278 AI05279 15/37 M29F080D MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute Maximum Ratings Symbol Parameter Min Max Unit TBIAS Temperature Under Bias –50 125 °C TSTG Storage Temperature –65 150 °C VIO Input or Output Voltage (1) –0.6 VCC + 0.6 V VCC Supply Voltage –0.6 6 V VID Identification Voltage –0.6 13.5 V Note: 1. Minimum Voltage may undershoot to –2V or overshoot to VCC +2V during transition for a maximum of 20ns. 16/37 M29F080D DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 7, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 7. Operating and AC Measurement Conditions M29F080D Parameter 55 70/ 90 Unit Min Max Min Max VCC Supply Voltage 4.5 5.5 4.5 5.5 V Ambient Operating Temperature – 40 85 – 40 85 °C Load Capacitance (CL) 30 Input Rise and Fall Times 100 pF 10 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 8. AC Measurement I/O Waveform 10 ns 0 to 3 0.45 to 2.4 V 1.5 0.8 and 2.0 V Figure 9. AC Measurement Load Circuit 1.3V High Speed (55ns) VCC 3V 1N914 1.5V 0V 3.3kΩ DEVICE UNDER TEST Standard (70, 90ns) 2.4V OUT CL 2.0V 0.8V 0.45V 0.1µF AI05276 CL includes JIG capacitance AI05277 Table 8. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: Sampled only, not 100% tested. 17/37 M29F080D Table 9. DC Characteristics Symbol Parameter Test Condition Min Max Unit 0V ≤VIN ≤VCC ±1 µA 0V ≤VOUT ≤VCC ±1 µA E = VIL, G = VIH, f = 6MHz 20 mA E = VIH 2 mA ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) ICC2 Supply Current (Standby) TTL ICC3 Supply Current (Standby) CMOS E = VCC ± 0.2V, RP = VCC ±0.2V 150 µA ICC4 (1) Supply Current (Program/Erase) Program/Erase Controller active 20 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2 VCC + 0.5 V VOL Output Low Voltage 0.45 V Output High Voltage TTL IOH = –2.5mA 2.4 V Output High Voltage CMOS IOH = –100µA VCC – 0.4 V VOH VID Identification Voltage IID Identification Current VLKO (1) Program/Erase Lockout Supply Voltage Note: 1. Sampled only, not 100% tested. 18/37 IOL = 5.8mA 11.5 A9 = VID 3.2 12.5 V 100 µA 4.2 V M29F080D Figure 10. Read AC Waveforms tAVAV VALID A0-A19 tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGHQZ tGLQV VALID DQ0-DQ7 AI06145 Table 10. Read AC Characteristics M29F080D Symbol Alt Parameter Test Condition Unit 55 70/ 90 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 55 70 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 55 70 ns tELQX (1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns tGLQX (1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns tGHQZ (1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 ns Note: 1. Sampled only, not 100% tested. 19/37 M29F080D Figure 11. Write AC Waveforms, Write Enable Controlled tAVAV A0-A19 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7 tWHDX VALID VCC tVCHEL RB tWHRL AI06146 Table 11. Write AC Characteristics, Write Enable Controlled M29F080D Symbol Alt Parameter Unit 55 70/ 90 tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns tDVWH tDS Input Valid to Write Enable High Min 45 45 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns Output Enable High to Write Enable Low Min 0 0 ns tGHWL tWHGL tOEH Write Enable High to Output Enable Low Min 0 0 ns tWHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns tVCHEL tVCS VCC High to Chip Enable Low Min 50 50 µs Note: 1. Sampled only, not 100% tested. 20/37 M29F080D Figure 12. Write AC Waveforms, Chip Enable Controlled tAVAV A0-A19 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7 tEHDX VALID VCC tVCHWL RB tEHRL AI06147 Table 12. Write AC Characteristics, Chip Enable Controlled M29F080D Symbol Alt Parameter Unit 55 70/ 90 tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns tDVEH tDS Input Valid to Chip Enable High Min 45 45 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns Output Enable High Chip Enable Low Min 0 0 ns tGHEL tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns tEHRL (1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs Note: 1. Sampled only, not 100% tested. 21/37 M29F080D Figure 13. Reset/Block Temporary Unprotect AC Waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL tPLPX RP tPHPHH tPLYH AI02931B Table 13. Reset/Block Temporary Unprotect AC Characteristics M29F080D Symbol tPHWL (1) tPHEL Alt Min 50 50 ns tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 ns tRP RP Pulse Width Min 500 500 ns Max 10 10 µs Min 500 500 ns (1) tPLPX tPLYH (1) tPHPHH (1) tREADY RP Low to Read Mode tVIDR RP Rise Time to VID Note: 1. Sampled only, not 100% tested. 22/37 70/ 90 RP High to Write Enable Low, Chip Enable Low, Output Enable Low tRHWL (1) tRHGL Unit 55 tRH tPHGL (1) tRHEL (1) Parameter M29F080D PACKAGE MECHANICAL TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline A2 1 N e E B N/2 D1 A CP D DIE C A1 TSOP-a α L Note: Drawing is not to scale. TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.050 0.150 0.0020 0.0059 A2 0.950 1.050 0.0374 0.0413 B 0.170 0.270 0.0067 0.0106 C 0.100 0.210 0.0039 0.0083 D 19.800 20.200 0.7795 0.7953 D1 18.300 18.500 0.7205 0.7283 E 9.900 10.100 0.3898 0.3976 – – – – L 0.500 0.700 0.0197 0.0276 α 0° 5° 0° 5° N 40 e CP 0.500 0.0197 40 0.100 0.0039 23/37 M29F080D SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline A A2 C b e CP D N E EH 1 A1 α L SO-d Note: Drawing is not to scale. SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 2.80 A1 Max 0.1102 0.10 0.0039 A2 2.30 2.20 2.40 0.0906 0.0866 0.0945 b 0.40 0.35 0.50 0.0157 0.0138 0.0197 C 0.15 0.10 0.20 0.0059 0.0039 0.0079 CP 0.08 0.0030 E 13.30 13.20 13.50 0.5236 0.5197 0.5315 D 28.20 28.00 28.40 1.1102 1.1024 1.1181 e 1.27 – – 0.0500 – – HE 16.00 15.75 16.25 0.6299 0.6201 0.6398 L 0.80 N α 24/37 Max 0.0315 44 44 8 8 M29F080D PART NUMBERING Table 14. Ordering Information Scheme Example: M29F080D 55 N 1 T Device Type M29 Operating Voltage F = VCC = 5V ± 10% Device Function 080D = 8 Mbit (1Mb x8), Uniform Block Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns Package N = TSOP40: 10 x 20 mm M = SO44 Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Option Blank = Standard Packing T = Tape & Reel Packing E = ECOPACK Package, Standard Packing F = ECOPACK Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 25/37 M29F080D APPENDIX A. BLOCK ADDRESS TABLE Table 15. Block Addresses, M29F080D # Size, KByte Address Range 15 64 0F0000h-0FFFFFh 14 64 0E0000h-0EFFFFh 13 64 0D0000h-0DFFFFh 12 64 0C0000h-0CFFFFh 11 64 0B0000h-0BFFFFh 10 64 0A0000h-0AFFFFh 9 64 090000h-09FFFFh 8 64 080000h-08FFFFh 7 64 070000h-07FFFFh 6 64 060000h-06FFFFh 5 64 050000h-05FFFFh 4 64 040000h-04FFFFh 3 64 030000h-03FFFFh 2 64 020000h-02FFFFh 1 64 010000h-01FFFFh 0 64 000000h-00FFFFh 26/37 Protection Group 3 2 1 0 M29F080D APPENDIX B. COMMON FLASH INTERFACE (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 16, 17, 18, 19, 20 and 21 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 21, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode. Table 16. Query Structure Overview Address Sub-section Name Description 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout 40h Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) 61h Security Code Area 64 bit unique device number Note: Query data are always presented on the lowest order data outputs. Table 17. CFI Query Identification String Address Data Description 10h 51h 11h 52h 12h 59h 13h 02h 14h 00h 15h 40h 16h 00h 17h 00h 18h 00h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported 19h 00h Address for Alternate Algorithm extended Query table 1Ah 00h Value "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 19) AMD Compatible P = 40h NA NA 27/37 M29F080D Table 18. CFI Query System Interface Information Address Data Description 1Bh 45h VCC Logic Supply Minimum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 4.5V 1Ch 55h VCC Logic Supply Maximum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 5.5V 1Dh 00h VPP [Programming] Supply Minimum Program/Erase voltage 00h not supported NA 1Eh 00h VPP [Programming] Supply Maximum Program/Erase voltage 00h not supported NA 1Fh 04h Typical timeout per single byte program = 2n µs 20h 00h Typical timeout for minimum size write buffer program = 2n µs NA 21h 0Ah Typical timeout per individual block erase = 2n ms 1s 22h 00h Typical timeout for full chip erase = 2n ms 23h 04h Maximum timeout for byte program = 2n times typical 24h 00h Maximum timeout for write buffer program = 2n times typical NA 25h 03h Maximum timeout per individual block erase = 2n times typical 8s 26h 00h Maximum timeout for chip erase = 2n times typical Note: 1. Not supported in the CFI 28/37 Value 16µs see note (1) 256µs see note (1) M29F080D Table 19. Device Geometry Definition Address Data Description Value 27h 14h Device Size = 2n in number of bytes 1 MByte 28h 29h 00h 00h Flash Device Interface Code description x8 only Async. 2Ah 2Bh 00h 00h Maximum number of bytes in multi-byte program or page = 2n 2Ch 01h Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. 1 2Dh 2Eh 0Fh 00h Region 1 Information Number of identical size erase block = 000Fh+1 16 2Fh 30h 00h 01h Region 1 Information Block size in Region 1 = 0100h * 256 byte NA 64 Kbyte 29/37 M29F080D Table 20. Primary Algorithm-Specific Extended Query Table Address Data Description 40h 50h 41h 52h 42h 49h 43h 31h Major version number, ASCII "1" 44h 30h Minor version number, ASCII "0" 45h 00h Address Sensitive Unlock (bits 1 to 0) 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Yes 46h 02h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write 2 47h 04h Block Protection 00 = not supported, x = number of blocks per group 4 48h 01h Temporary Block Unprotect 00 = not supported, 01 = supported 49h 04h Block Protect /Unprotect 04 = M29W400B mode 4Ah 00h Simultaneous Operations, 00 = not supported No 4Bh 00h Burst Mode, 00 = not supported, 01 = supported No 4Ch 00h Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No "P" Primary Algorithm extended Query table unique ASCII string “PRI” "R" "I" yes 4 Table 21. Security Code Area Address Data 61h XX 62h XX 63h XX 64h XX 65h XX 66h XX 67h XX 68h XX 30/37 Value Description 64 bit: unique device number M29F080D APPENDIX C. BLOCK PROTECTION Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to Appendix A, Table 15 for details of the Protection Groups. Once protected, Program and Erase operations within the protected group fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. To protect the Extended Block issue the Enter Extended Block command and then use either the Programmer or In-System technique. Once protected issue the Exit Extended Block command to return to read mode. The Extended Block protection is irreversible, once protected the protection cannot be undone. Programmer Technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a group of blocks follow the flowchart in Figure 14, Programmer Equipment Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 15, Programmer Equipment Chip Unprotect Flowchart. Table 22, Programmer Technique Bus Operations, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. In-System Technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. To protect a group of blocks follow the flowchart in Figure 16, In-System Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 17, In-System Chip Unprotect Flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. Table 22. Programmer Technique Bus Operations, BYTE = VIH or VIL E G W Address Inputs A0-A19 Data Inputs/Outputs DQ15A–1, DQ14-DQ0 Block (Group) Protect(1) VIL VID VIL Pulse A9 = VID, A12-A19 Block Address Others = X X Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH Others = X X Block (Group) Protection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A19 Block Address Others = X Pass = XX01h Retry = XX00h Block (Group) Unprotection Verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A19 Block Address Others = X Retry = XX01h Pass = XX00h Operation Note: 1. Block Protection Groups are shown in Appendix A, Table 15. 31/37 M29F080D Figure 14. Programmer Equipment Group Protect Flowchart START Set-up ADDRESS = GROUP ADDRESS W = VIH n=0 G, A9 = VID, E = VIL Protect Wait 4µs W = VIL Wait 100µs W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Verify Wait 4µs G = VIL Wait 60ns Read DATA DATA NO = 01h YES A9 = VIH E, G = VIH ++n = 25 NO End YES PASS A9 = VIH E, G = VIH FAIL Note: Block Protection Groups are shown in Appendix A, Table 15. 32/37 AI05574 M29F080D Figure 15. Programmer Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Unprotect Wait 4µs W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1, A6 = VIH E = VIL Wait 4µs G = VIL INCREMENT CURRENT GROUP Verify Wait 60ns Read DATA NO End NO DATA = 00h ++n = 1000 YES LAST GROUP YES YES A9 = VIH E, G = VIH A9 = VIH E, G = VIH FAIL PASS NO AI05575 Note: Block Protection Groups are shown in Appendix A, Table 15. 33/37 M29F080D Figure 16. In-System Equipment Group Protect Flowchart Set-up START n=0 RP = VID Protect WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL WRITE 60h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 100µs Verify WRITE 40h ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 4µs READ DATA ADDRESS = GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIL DATA NO = 01h YES End RP = VIH ISSUE READ/RESET COMMAND PASS ++n = 25 NO YES RP = VIH ISSUE READ/RESET COMMAND FAIL AI05576 Note: Block Protection Groups are shown in Appendix A, Table 15. 34/37 M29F080D Figure 17. In-System Equipment Chip Unprotect Flowchart START Set-up PROTECT ALL GROUPS n=0 CURRENT GROUP = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Wait 10ms Verify WRITE 40h ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Wait 4µs READ DATA ADDRESS = CURRENT GROUP ADDRESS A0 = VIL, A1 = VIH, A6 = VIH NO End NO ++n = 1000 YES DATA = 00h INCREMENT CURRENT GROUP YES LAST GROUP NO YES RP = VIH RP = VIH ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI05577 Note: Block Protection Groups are shown in Appendix A, Table 15. 35/37 M29F080D REVISION HISTORY Table 23. Document Revision History Date Version 03-Dec-2001 -01 First Issue 05-Apr-2002 -02 Description of Ready/Busy signal clarified (and Figure 13 modified) Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section 19-Sep-2005 3.0 Table 14. Ordering Information Scheme: standard package added and ECOPACK version added for both standard package and Tape & Reel packing. Datasheet status changed to FULL DATASHEET. 36/37 Revision Details M29F080D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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