M29W800T90M6R

M29W800T M29W800B 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) Low Voltage Single Supply Flash Memory NOT FOR NEW DESIGN M29W800T and M29W800B are replaced respectively by the M29W800AT and M29W800AB 2.7V to 3.6V SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPERATIONS FAST ACCESS TIME: 90ns FAST PROGRAMMING TIME – 10µs by Byte / 20µs by Word typical PROGRAM/ERASE CONTROLLER (P/E.C.) – Program Byte-by-Byte or Word-by-Word – Status Register bits and Ready/Busy Output MEMORY BLOCKS – Boot Block (Top or Bottom location) – Parameter and Main blocks BLOCK, MULTI-BLOCK and CHIP ERASE MULTI BLOCK PROTECTION/TEMPORARY UNPROTECTION MODES ERASE SUSPEND and RESUME MODES – Read and Program another Block during Erase Suspend LOW POWER CONSUMPTION – Stand-by and Automatic Stand-by 100,000 PROGRAM/ERASE CYCLES per BLOCK 20 YEARS DATA RETENTION – Defectivity below 1ppm/year ELECTRONIC SIGNATURE – Manufacturer Code: 0020h – Device Code, M29W800T: 00D7h – Device Code, M29W800B: 005Bh DESCRIPTION The M29W800 is a non-volatile memory that may be erased electrically at the block or chip level and programmed in-system on a Byte-by-Byteor Wordby-Word basis using only a single 2.7V to 3.6V VCC supply. For Program and Erase operations the necessary high voltages are generated internally. The device can also be programmed in standard programmers. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. Blocks can be protected against programing and erase on programming equipment, June 1999 44 1 TSOP48 (N) 12 x 20 mm SO44 (M) Figure 1. Logic Diagram VCC 19 A0-A18 W E G RP M29W800T M29W800B 15 DQ0-DQ14 DQ15A–1 BYTE RB VSS AI02178 1/33 This is information on a product still in production but not recommended for new designs. M29W800T, M29W800B Figure 2A. TSOP Pin Connections A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 48 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 Figure 2B. TSOP Reverse Pin Connections A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 1 48 A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 12 13 M29W800T M29W800B (Normal) 37 36 12 13 M29W800T M29W800B (Reverse) 37 36 24 25 AI02179 24 25 AI02180 Warning: NC = Not Connected. Warning: NC = Not Connected. Figure 2C. SO Pin Connections Table 1. Signal Names A0-A18 Address Inputs Data Input/Outputs, Command Inputs Data Input/Outputs Data Input/Output or Address Input Chip Enable Output Enable Write Enable Reset / Block Temporary Unprotect Ready/Busy Output Byte/Word Organisation Supply Voltage Ground RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 M29W800T 12 M29W800B 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ0-DQ7 DQ8-DQ14 DQ15A–1 E G W RP RB BYTE VCC VSS AI02181 2/33 M29W800T, M29W800B Table 2. Absolute Maximum Ratings (1) Symbol TA TBIAS TSTG VIO (2) Parameter Ambient Operating Temperature Temperature Under Bias Storage Temperature Input or Output Voltages Supply Voltage (2) (3) Value –40 to 85 –50 to 125 –65 to 150 –0.6 to 5 –0.6 to 5 –0.6 to 13.5 Unit °C °C °C V V V VCC V(A9, E, G, RP) A9, E, G, RP Voltage Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns. 3. Depends on range. DESCRIPTION (Cont’d) and temporarily unprotected to make changes in the application. Each block can be programmed and erased over 100,000 cycles. Instructions for Read/Reset, Auto Select for reading the Electronic Signature or Block Protection status, Programming, Block and Chip Erase, Erase Suspend and Resume are written to the device in cycles of commandsto a Command Interfaceusing standard microprocessor write timings. The device is offered in TSOP48 (12 x 20mm) and SO44 packages. Both normal and reverse pinouts are available for the TSOP48 package. Organisation The M29W800 is organised as 1 M x8 or 512K x16 bits selectable by the BYTE signal. When BYTE is Low the Byte-wide x8 organisation is selected and the address lines are DQ15A–1 and A0-A18. The Data Input/Output signal DQ15A–1 acts as address line A–1 which selects the lower or upper Byte of the memory word for output on DQ0-DQ7, DQ8-DQ14 remain at High impedan ce. When BYTE is High the memory uses the address inputs A0-A18 and the Data Input/Outputs DQ0-DQ15. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. AReset/Block TemporaryUnprotection RP tri-level input provides a hardware reset when pulled Low, and when held High (at VID) temporarily unprotects blocks previously protected allowing them to be programed and erased. Erase and Program operations are controlled by an internal Program/Erase Controller (P/E.C.). Status Register data output on DQ7 provides a Data Polling signal, and DQ6 and DQ2 provide Toggle signals to indicate the state of the P/E.C operations. A Ready/Busy RB output indicates the completion of the internal algorithms. Memory Blocks The devices feature asymmetrically blocked architecture providing system memory integration. Both M29W800Tand M29W800Bdevices have an array of 19 blocks, one Boot Block of 16 KBytes or 8 KWords, two Parameter Blocks of 8 KBytes or 4 KWords, one Main Block of 32 KBytes or 16 KWords and fifteenMain Blocks of 64 KBytes or 32 KWords. The M29W800T has the Boot Block at the top of the memory address space and the M29W800B locates the Boot Block starting at the bottom. The memory maps are showed in Figure 3. Each block can be erased separately, any combination of blocks can be specified for multi-block erase or the entire chip may be erased. The Erase operations are managed automatically by the P/E.C. The block erase operation can be suspended in order to read from or program to any block not being ersased, and then resumed. Block protection provides additional data security. Each block can be separately protected or unprotected against Program or Erase on programming equipment. All previously protected blocks can be temporarily unprotected in the application. Bus Operations The following operations can be performed using the appropriatebus cycles: Read (Array, Electronic Signature, Block Protection Status), Write command, Output Disable, Standby, Reset, Block Prot ec t io n , Unp ro t e ct io n, P ro t e cti on Verif y, Unprotection Verify and Block Temporary Unprotection. See Tables 4 and 5. 3/33 M29W800T, M29W800B Figure 3A. Top Boot Block Memory Map and Block Address Table TOP BOOT BLOCK Word-Wide 7FFFFh 78000h 77FFFh 70000h 6FFFFh 68000h 67FFFh 60000h 5FFFFh 58000h 57FFFh 50000h 4FFFFh 48000h 47FFFh 40000h 3FFFFh 38000h 37FFFh 30000h 2FFFFh 28000h 27FFFh 20000h 1FFFFh 18000h 17FFFh 10000h 0FFFFh 08000h 07FFFh 00000h Byte-Wide FFFFFh 16K BOOT BLOCK F0000h EFFFFh 64K MAIN BLOCK E0000h DFFFFh 64K MAIN BLOCK D0000h CFFFFh 64K MAIN BLOCK C0000h BFFFFh 64K MAIN BLOCK B0000h AFFFFh 64K MAIN BLOCK A0000h 9FFFFh 64K MAIN BLOCK 90000h 8FFFFh 64K MAIN BLOCK 80000h 7FFFFh 64K MAIN BLOCK 70000h 6FFFFh 64K MAIN BLOCK 60000h 5FFFFh 64K MAIN BLOCK 50000h 4FFFFh 64K MAIN BLOCK 40000h 3FFFFh 64K MAIN BLOCK 30000h 2FFFFh 64K MAIN BLOCK 20000h 1FFFFh 64K MAIN BLOCK 10000h 0FFFFh 64K MAIN BLOCK 00000h AI01725B Byte-Wide FFFFFh FC000h FBFFFh 8K PARAMETER BLOCK FA000h F9FFFh 8K PARAMETER BLOCK F8000h F7FFFh 32K MAIN BLOCK F0000h Word-Wide 7FFFFh 7E000h 7DFFFh 7D000h 7CFFFh 7C000h 7BFFFh 78000h 4/33 M29W800T, M29W800B Figure 3B. Bottom Boot Block Memory Map and Block Address Table BOTTOM BOOT BLOCK Word-Wide 7FFFFh 78000h 77FFFh 70000h 6FFFFh 68000h 67FFFh 60000h 5FFFFh 58000h 57FFFh 50000h 4FFFFh 48000h 47FFFh 40000h 3FFFFh 38000h 37FFFh 30000h 2FFFFh 28000h 27FFFh 20000h 1FFFFh 18000h 17FFFh 10000h 0FFFFh 08000h 07FFFh 00000h Byte-Wide FFFFFh 64K MAIN BLOCK F0000h EFFFFh 64K MAIN BLOCK E0000h DFFFFh 64K MAIN BLOCK D0000h CFFFFh 64K MAIN BLOCK C0000h BFFFFh 64K MAIN BLOCK B0000h AFFFFh 64K MAIN BLOCK A0000h 9FFFFh 64K MAIN BLOCK 90000h 8FFFFh 64K MAIN BLOCK 80000h 7FFFFh 64K MAIN BLOCK 70000h 6FFFFh 64K MAIN BLOCK 60000h 5FFFFh 64K MAIN BLOCK 50000h 4FFFFh 64K MAIN BLOCK 40000h 3FFFFh 64K MAIN BLOCK 30000h 2FFFFh 64K MAIN BLOCK 20000h 1FFFFh 64K MAIN BLOCK 10000h 0FFFFh 16K BOOT BLOCK 00000h AI01731B Byte-Wide 0FFFFh 32K MAIN BLOCK 08000h 07FFFh 8K PARAMETER BLOCK 06000h 05FFFh 8K PARAMETER BLOCK 04000h 03FFFh 00000h Word-Wide 07FFFh 04000h 03FFFh 03000h 02FFFh 02000h 01FFFh 00000h 5/33 M29W800T, M29W800B Table 3A. M29W800T Block Address Table Address Range (x8) 00000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-F7FFFh F8000h-F9FFFh FA000h-FBFFFh FC000h-FFFFFh Address Range (x16) 00000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7BFFFh 7C000h-7CFFFh 7D000h-7DFFFh 7E000h-7FFFFh A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X 0 1 X Command Interface Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller through a Command Interface (C.I.). For added data protection, program or erase execution starts after 4 or 6 cycles. The first, second,fourth and fifth cycles are used to input Coded cycles to the C.I. This Coded sequence is the same for all Program/Erase Controller instructions. The ’Command’ itself and its confirmation, when applicable, are given on the third, fourth or sixth cycles. Any incorrect command or any improper command sequence will reset the device to Read Array mode. 6/33 M29W800T, M29W800B Table 3B. M29W800B Block Address Table Address Range (x8) 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-0FFFFh 10000h-1FFFFh 20000h-2FFFFh 30000h-3FFFFh 40000h-4FFFFh 50000h-5FFFFh 60000h-6FFFFh 70000h-7FFFFh 80000h-8FFFFh 90000h-9FFFFh A0000h-AFFFFh B0000h-BFFFFh C0000h-CFFFFh D0000h-DFFFFh E0000h-EFFFFh F0000h-FfFFFh Address Range (x16) 00000h-01FFFh 02000h-02FFFh 03000h-03FFFh 04000h-07FFFh 08000h-0FFFFh 10000h-17FFFh 18000h-1FFFFh 20000h-27FFFh 28000h-2FFFFh 30000h-37FFFh 38000h-3FFFFh 40000h-47FFFh 48000h-4FFFFh 50000h-57FFFh 58000h-5FFFFh 60000h-67FFFh 68000h-6FFFFh 70000h-77FFFh 78000h-7FFFFh A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A14 0 0 0 1 X X X X X X X X X X X X X X X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X Instructions Seven instructions are defined to perform Read Array, Auto Select (to read the ElectronicSignature or Block ProtectionStatus), Program, Block Erase, Chip Erase, Erase Suspend and Erase Resume. The internal P/E.C. automatically handles all timing and verification of the Program and Erase operations. The Status Register Data Polling, Toggle, Error bits and the RB output may be read at any time, during programming or erase, to monitor the progress of the operation. Instructions are composed of up to six cycles. The first two cycles input a Coded sequence to the Command Interfacewhich iscommon to all instructions (see Table 8). The third cycle inputs the instruction set-up command. Subsequent cycles output the addressed data, Electronic Signature or Block Protection Status for Read operations. In order to give additional data protection, the instructions for Program and Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be programmed. For an Erase instruction (Block or Chip), the fourth and fifth cycles input a further Coded sequence before the Erase confirm command on the sixthcycle. Erasure of a memory block may be suspended, in order to read data from another block or to program data in another block, and then resumed. When power is first applied or if VCC falls below VLKO, the command interface is reset to Read Array. 7/33 M29W800T, M29W800B SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A18). The address inputs for the memory array are latched during a write operation on the falling edge at Chip Enable E or Write Enable W. In Word-wide organisation the address lines are A0-A18, in Byte-wide organisation DQ15A–1 acts as an additional LSB address line. When A9 is raised to VID, either a Read Electronic Signature Manufacturer or Device Code, Block Protection Status or a Write Block Protection or Block Unprotection is enabled depending on the combination of levels on A0, A1, A12 and A15. Data Input/Outputs (DQ0-DQ7). T h e s e I nputs/Outputsare used in the Byte-wide and Wordwide organisations. The input is data to be programmed in the memory array or a command to be written to the C.I. Both are latched on the rising edge of Chip Enable E or Write Enable W. The output is data from the Memory Array, the Electronic Signature Manufacturer or Device codes, the Block Protection Status or the Status register Data Polling bit DQ7, the Toggle Bits DQ6 and DQ2, the Error bit DQ5 or the Erase Timer bit DQ3. Outputs are valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected or the outputsare disabledand when RP is at a Low level. Data Input/Outputs (DQ8-DQ14 and DQ15A–1). These Inputs/Outputs are additionally used in the Word-wide organisation.When BYTEis High DQ8DQ14 and DQ15A–1 act as the MSB of the Data Input or Output, functioning as described for DQ0DQ7 above, and DQ8 - DQ15 are ’don’t care’ for command inputs or status outputs. When BYTE is Low, DQ0-DQ14 are high impedance, DQ15A–1 is the Address A–1 input. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E High deselects thememory and reducesthe power consumptionto the standby level. E can also be used to control writing to the command register and to the memory array, while W remains at a low level. The Chip Enable must be forced to VID during the Block Unprotection operation. Output Enable (G). The Output Enable gates the outputs through the data buffers during a read operation. When G is High the outputs are High impedance. G must be forced to VID level during Block Protection and Unprotection operations. Write Enable (W). This input controls writing to the Command Registerand Addressand Datalatches. Byte/Word Organization Select (BYTE). The BYTE input selects the output configuration for the device: Byte-wide (x8) mode or Word-wide (x16) mode. When BYTE is Low, the Byte-wide mode is selected and the data is read and programmed on DQ0-DQ7. In this mode, DQ8-DQ14 are at high impedance and DQ15A–1 is the LSB address. When BYTE is High, the Word-wide mode is selected and the data is read and programmed on DQ0-DQ15. Ready/Busy Output (RB). Ready/Busy is an open-drainoutput and gives the internalstate of the P/E.C. of the device. When RB is Low, the device is Busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase Suspend instruction. When RB is High, the device is ready for any Read, Program or Erase operation. The RB will also be High when the memory is put in Erase Suspend or Standby modes. Reset/Block Temporary Unprotect Input (RP). The RP Input provides hardware reset and protected block(s) temporary unprotection functions. Reset of the memory is acheived by pulling RP to VIL for at least t PLPX. When the reset pulse is given, if the memory is in Read or Standby modes, it will be available for new operations in tPHEL after the rising edge of RP. If the memory is in Erase, Erase Suspend or Program modes the reset will take tPLYH during which the RB signal will be held at VIL. The end of the memory reset will be indicated by the rising edge of RB. A hardware reset during an Erase or Program operation will corrupt the data being programmed or the sector(s) being erased. See Table 14 and Figure 9. Temporary block unprotection is made by holding RP at VID. In this condition previously protected blocks can be programmed or erased. The transition of RP from VIH to VID must slower than t PHPHH. See Table 15 and Figure 9. When RP is returned from VID to VIH all blocks temporarily unprotected will be again protected. VCC Supply Voltage. The power supply for all operations (Read, Program and Erase). VSS Ground. VSS is the reference for all voltage measurements. 8/33 M29W800T, M29W800B DEVICE OPERATIONS See Tables 4, 5 and 6. Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register or the Block Protection Status. Both Chip Enable E and Output Enable G must be low in order to read the output of the memory. Write. Write operationsare used to give Instruction Commands to the memory or to latch input data to be programmed. A write operationis initiated when Chip Enable E is Low and Write Enable W is Low with Output Enable G High. Addresses are latched on the falling edge of W or E whicheveroccurs last. Commands and Input Data are latchedon the rising edge of W or E whichever occurs first. Output Disable. The data outputs are high impedance when the Output Enable G is High with Write Enable W High. Standby. The memory is in standby when Chip Enable E is High and the P/E.C. is idle. The power consumption is reduced to the standby level and the outputs are high impedance, independent of the Output Enable G or Write Enable W inputs. Automatic Standby. After 150ns of bus inactivity and when CMOS levels are driving the addresses, the chip automatically enters a pseudo-standby mode where consumptionis reduced to the CMOS standby value, while outputs still drive the bus. Electronic Signature. Two codes identifying the manufacturer and the device can be read from the memory. The manufacturer’s code for STMicroelectronics is 20h, the device code is D7h for the M29W800T (Top Boot) and 5Bh for the M29W800B (Bottom Boot). These codes allow programming equipment or applications to automatically match their interface to the characteristics of the M29W800. The Electronic Signature is output by a Read operation when the voltage applied to A9 is at VID and address inputs A1 is Low. The manufacturer code is output when the Address input A0 is Low and the device code when this input is High. Other Address inputs are ignored. The codes are output on DQ0-DQ7. The Electronic Signature can also be read, without raising A9 to VID, by giving the memory the Instruction AS. If the Byte-wide configuration is selected the codes are output on DQ0-DQ7with DQ8-DQ14 at High impedance; if the Word-wide configuration is selected the codes are output on DQ0-DQ7 with DQ8-DQ15 at 00h. Block Protection. Each block can be separately protected against Program or Erase on programming equipment. Block protection provides additional data security, as it disables all program or erase operations.This mode is activatedwhen both A9 and G are raised to VID and an address in the block is applied on A12-A18. Block protection is initiated on the edge of W falling to VIL. Then after a delay of 100µs, the edge of W rising to VIH ends the protection operations. Block protection verify is achieved by bringing G, E, A0and A6 to VIL and A1 to VIH, while W is at VIH and A9 at VID. Under these conditions, reading the data output will yield 01h if the block defined by the inputs on A12-A18 is protected. Any attempt to program or erase a protected block will be ignored by the device. Block Temporary Unprotection. Any previously protected block can be temporarily unprotected in order to change stored data. The temporary unprotection mode is activated by bringing RP to VID. During the temporary unprotection mode the previously protected blocks are unprotected. A block can be selected and data can be modified by executingthe Erase or Programinstruction with the RP signal held at VID. When RP is returned to VIH, all the previously protected blocks are again protected. Block Unprotection. All protected blocks can be unprotected on programming equipment to allow updating of bit contents. All blocks must first be protected before the unprotection operation. Block unprotection is activated when A9, G and E are at VID and A12, A15 at VIH. Unprotection is initiated by the edge of W fallingto VIL. Aftera delay of 10ms, the unprotection operation will end. Unprotection verify is achieved by bringing G and E to VIL while A0 is at VIL, A6 and A1 are at VIH and A9 remains at VID. In these conditions, reading the output data will yield 00h if the block defined by the inputs A12-A18 has been succesfully unprotected. Each block must be separately verified by giving its address in order to ensure that it has been unprotected. 9/33 M29W800T, M29W800B Table 4. User Bus Operations (1) Operation Read Word Read Byte Write Word Write Byte Output Disable Standby Reset Block Protection(2,4) Blocks Unprotection(4) Block Protection (2,4) Verify Block Unprotection Verify(2,4) Block Temporary Unprotection Notes: 1. 2. 3. 4. E VIL VIL VIL VIL VIL VIH X VIL VID VIL G VIL VIL VIH VIH VIH X X VID VID VIL W VIH VIH VIL VIL VIH X X VIL Pulse VIL Pulse VIH RP VIH VIH VIH VIH VIH VIH VIL VIH VIH VIH BYTE VIH VIL VIH VIL X X X X X X A0 A0 A0 A0 A0 X X X X X VIL A1 A1 A1 A1 A1 X X X X X VIH A6 A6 A6 A6 A6 X X X X X VIL A9 A9 A9 A9 A9 X X X VID VID VID A12 A12 A12 A12 A12 X X X X VIH A12 A15 A15 A15 A15 A15 X X X X VIH A15 DQ15 A–1 Data Output Address Input DQ8DQ14 Data Output Hi-Z DQ0-DQ7 Data Output Data Output Data Input Data Input Hi-Z Hi-Z Hi-Z X X Block Protect (3) Status Block Protect Status (3) X Data Input Data Input Address Input Hi-Z Hi-Z Hi-Z X X X Hi-Z Hi-Z Hi-Z Hi-Z X X X VIL VIL VIH VIH X VIL VIH VIH VID A12 A15 X X X X X VID X X X X X X X X X X = VIL or VIH Block Address must be given on A12-A18 bits. See Table 6. Operation performed on programming equipment. Table 5. Read Electronic Signature (following AS instruction or with A9 = VID) Org. Code Manufact. Code Device Code Manufact. Code Bytewide Device Code M29W800T M29W800B M29W800T M29W800B Device E VIL VIL VIL VIL VIL VIL G VIL VIL VIL VIL VIL VIL W VIH VIH VIH VIH VIH VIH BYTE VIH VIH VIH VIL VIL VIL A0 VIL VIH VIH VIL VIH VIH A1 VIL VIL VIL VIL VIL VIL Other Addresses Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care DQ15 A–1 0 0 0 Don’t Care Don’t Care Don’t Care DQ8DQ14 00h 00h 00h Hi-Z Hi-Z Hi-Z DQ0DQ7 20h D7h 5Bh 20h D7h 5Bh Wordwide Table 6. Read Block Protection with AS Instruction Code Protected Block Unprotected Block E VIL VIL G VIL VIL W VIH VIH A0 VIL VIL A1 VIH VIH A12-A18 Block Address Block Address Other Addresses Don’t Care Don’t Care DQ0-DQ7 01h 00h 10/33 M29W800T, M29W800B INSTRUCTIONS AND COMMANDS The Command Interface latches commands written to the memory. Instructions are made up from one or more commands to perform Read Memory Array, Read Electronic Signature, Read Block Protection, Program, Block Erase, Chip Erase, Erase Suspen d and Erase Resume. Commands are made of address and data sequences. The instructions require from 1 to 6 cycles, the first or first three of which are always write operations used to initiate the instruction. They are followed by either further write cycles to confirm the first command or execute the command immediately. Command sequencing must be followed exactly. Any invalid combination of commands will reset the device to Read Array. The increased number of cycles has been chosen to assure maximum data security. Instructions are initialised by two initial Coded cycles which unlock the Command Interface.In addition, for Erase, instruction confirmation is again preceded by the two Coded cycles. Status Register Bits P/E.C. status is indicated during execution by Data Polling on DQ7, detection of Toggle on DQ6 and DQ2, or Error on DQ5 and Erase Timer DQ3 bits. Any read attempt during Program or Erase command execution will automatically output these five Status Register bits. The P/E.C. automatically sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other bits (DQ0, DQ1 and DQ4) are reserved for future use and should be masked. See Tables 9 and 10. Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7. During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last programmed or a ’1’ after erasing. Data Polling is valid and only effective during P/E.C. operation, that is after the fourth W pulse for programming or after the sixth W pulse for erase. It must be performed at the address being programmed or at an address within the block being erased. If all the blocks selected for erasure are protected,DQ7 will be set to ’0’ for about 100µs, and then return to the previous addressed memory data value. See Figure 11 for the Data Polling flowchart and Figure 10 for the Data Polling waveforms. DQ7 will also flag the Erase Suspend mode by switching from ’0’ to ’1’ at the start of the Erase Suspend. In order to monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend mode, DQ7 will output ’1’ if the read is attempted on a blockbeing erased and the data value on other blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as in the normal program execution outside of the suspend mode. Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary data.DQ6 will toggle following toggling of either G, or E when G is low. The operation is completed when two successive reads yield the same output data. The next read will output the bit last programmedor a ’1’ after erasing. The toggle bit DQ6 is valid only during P/E.C. operations, that is after the fourth W pulse for programming or after the sixth W pulse for Erase. If the blocks selected for erasure are protected, DQ6 will toggle for about 100µs and then return back to Read. DQ6 will be set to ’1’ if a Read operationis attemptedon an Erase Suspendblock. When erase is suspended DQ6 will toggle during programming operations in a block different to the block in Erase Suspend. Either E or G toggling will cause DQ6 to toggle. See Figure 12 for Toggle Bit flowchart and Figure 13 for Toggle Bit waveforms. Table 7. Commands Hex Code 00h 10h 20h 30h 80h 90h A0h B0h F0h Command Invalid/Reserved Chip Erase Confirm Reserved Block Erase Resume/Confirm Set-up Erase Read Electronic Signature/ Block Protection Status Program Erase Suspend Read Array/Reset 11/33 M29W800T, M29W800B Table 8. Instructions (1) Mne. Instr. Cyc. 1+ RD (2,4) 1st Cyc. Addr. Data Addr. (3,7) Byte Word Data Addr. (3,7) Byte Word Data Addr. (3,7) Byte Word Data Addr. (3,7) Byte Word Data Addr. (3,7) Byte Word Data (3,7) 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc. 7th Cyc. X F0h AAAAh 5555h AAh AAAAh 5555h AAh AAAAh 5555h AAh AAAAh 5555h AAh AAAAh 5555h AAh Read Memory Array until a new write cycle is initiated. Read/Reset Memory Array 3+ 5555h 2AAAh 55h 5555h 2AAAh 55h 5555h 2AAAh 55h 5555h 2AAAh 55h 5555h 2AAAh 55h AAAAh 5555h F0h AAAAh 5555h 90h AAAAh 5555h A0h AAAAh 5555h 80h AAAAh 5555h 80h Program Address Program Data AAAAh 5555h AAh AAAAh 5555h AAh 5555h 2AAAh 55h 5555h 2AAAh 55h Block Additional (8) Address Block 30h AAAAh 5555h 10h Note 9 30h Read Electronic Signature or Block Protection Status until a new write cycle is initiated. See Note 5 and 6. Read Memory Array until a new write cycle is initiated. AS (4) Auto Select 3+ PG Program 4 Read Data Polling or Toggle Bit until Program completes. BE Block Erase 6 CE Chip Erase 6 ES (10) Erase Suspend Erase Resume 1 Addr. Data (3,7) X B0h Read until Toggle stops, then read all the data needed from any Block(s) not being erased then Resume Erase. Read Data Polling or Toggle Bits until Erase completes or Erase is suspended another time ER 1 Addr. Data (3,7) X 30h Notes: 1. Commands not interpreted in this table will default to read array mode. 2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase or Program mode before starting any new operation (see Table 14 and Figure 9). 3. X = Don’t Care. 4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles. 5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device code. 6. Block Protection Address: A0, at V IL, A1 at VIH and A15-A18 within the Block will output the Block Protection status. 7. For Coded cycles address inputs A15-A18 are don’t care. 8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, read Data Polling or Toggle bit until Erase is completed or suspended. 9. Read Data Polling, Toggle bits or RB until Erase completes. 10.During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased. 12/33 M29W800T, M29W800B Table 9. Status Register Bits DQ Name Logic Level ’1’ 7 Data Polling ’0’ DQ DQ ’-1-0-1-0-1-0-1-’ 6 Toggle Bit DQ ’-1-1-1-1-1-1-1-’ ’1’ ’0’ 4 Reserved ’1’ Erase Timeout Period Expired Erase Timeout Period On-going Chip Erase, Erase or Erase Suspend on the currently addressed block. Erase Error due to the currently addressed block (when DQ5 = ’1’). Program on-going, Erase on-going on another block or Erase Complete Erase Suspend read on non Erase Suspend block P/E.C. Erase operation has started. Only possible command entry is Erase Suspend (ES). An additional block to be erased in parallel can be entered to the P/E.C. Definition Erase Complete or erase block in Erase Suspend Erase On-going Program Complete or data of non erase block during Erase Suspend Program On-going Erase or Program On-going Program Complete Erase Complete or Erase Suspend on currently addressed block Program or Erase Error Program or Erase On-going Successive reads output complementary data on DQ6 while Programming or Erase operations are on-going. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. This bit is set to ’1’ in the case of Programming or Erase failure. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase Success. Note 5 Error Bit 3 Erase Time Bit ’0’ ’-1-0-1-0-1-0-1-’ 2 Toggle Bit 1 Indicates the erase status and allows to identify the erased block DQ 1 0 Reserved Reserved Notes: Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations. 13/33 M29W800T, M29W800B Table 10. Polling and Toggle Bits Mode Program Erase Erase Suspend Read (in Erase Suspend block) Erase Suspend Read (outside Erase Suspend block) Erase Suspend Program DQ7 DQ7 0 1 DQ6 Toggle Toggle 1 DQ2 1 Note 1 Toggle DQ7 DQ7 DQ6 Toggle DQ2 N/A Note: 1. Toggle if the address is within a block being erased. ’1’ if the address is within a block not being erased. Toggle Bit (DQ2). This toggle bit, together with DQ6, can be used to determine the device status during the Erase operations. It can also be used to identify the block being erased. During Erase or Erase Suspend a read from a block being erased will cause DQ2 to toggle. A read from a block not being erased will set DQ2 to ’1’ during erase and to DQ2 during Erase Suspend. During Chip Erase a read operation will cause DQ2 to toggle as all blocks are being erased. DQ2 will be set to ’1’ during program operation and when erase is complete. After erase completion and if the error bit DQ5 is set to ’1’, DQ2 will toggle if the faulty block is addressed. Error Bit (DQ5). This bit is set to ’1’ by the P/E.C. when there is a failure of programming, block erase, or chip erase that results in invalid data in the memory block. In caseof an error in block erase or program, the block in which the error occured or to which the programmed data belongs, must be discarded. The DQ5 failure condition will also appear if a user tries to program a ’1’ to a locationthat is previously programmed to ’0’. Other Blocks may stillbe used.The error bit resets after a Read/Reset (RD) instruction. In case of success of Program or Erase, the error bit will be set to ’0’ . Erase Timer Bit (DQ3). This bit is set to ’0’ by the P/E.C. when the last block Erase command has been entered to the Command Interface and it is awaiting the Erase start. When the erase timeout period is finished, after 50µs to 90µs, DQ3 returns to ’1’. Coded Cycles The two Coded cycles unlock the Command Interface. They are followed by an input command or a confirmation command. The Coded cycles consist of writing the data AAh at address AAAAh in the Byte-wide configuration and at address 5555h in the Word-wide configuration during the first cycle. During the second cycle the Coded cycles consist of writing the data 55h at address 5555h in the Byte-wide configuration and at address 2AAAh in the Word-wide configuration. In the Byte-wide configuration the address lines A–1 to A14 are valid, in Word-wide A0 to A15 are valid, other address lines are ’don’t care’. The Coded cycles happen on first and second cycles of the command write or on the fourth and fifth cycles. Instructions See Table 8. Read/Reset (RD) Instruction. The Read/Reset instruction consists of one write cycle giving the command F0h. It canbe optionallyprecededby the two Coded cycles. Subsequentread operationswill read the memory array addressed and output the data read. A wait state of 10µs is necessary after Read/Reset prior to any valid read if the memory was in an Erase mode when the RD instruction is given. Auto Select (AS) Instruction. This instruction uses the two Coded cycles followed by one write cycle giving the command 90h to address AAAAh in the Byte-wide configuration or address 5555h in the Word-wide configuration for command set-up. A subsequent read will output the manufacturer code and the device code or the block protection status depending on the levels of A0 and A1. The manufacturer code, 20h, is output when the addresses lines A0 and A1 are Low, the device code, EEh for Top Boot, EFh for Bottom Boot is output when A0 is High with A1 Low. The AS instruction also allows access to the block protectionstatus.After givingthe AS instruction, A0 is set to VIL with A1 at VIH, while A12-A18 define the address of the block to be verified. A read in these conditions will output a 01h if the block is protected and a 00h if the block is not protected. Program (PG) Instruction. This instruction uses four write cycles. Both for Byte-wide configuration and for Word-wide configuration. The Program command A0h is written to address AAAAh in the Byte-wide configuration or to address 5555h in the Word-wide configurationon the third cycle after two Coded cycles. A fourth write operation latches the Address on the falling edge of W or E and the Data to be written on the rising edge and starts the P/E.C. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing ’0’ in place of ’1’. Status bits DQ6 and DQ7 determine if programming is on-goingand DQ5 allows verification of any possible error. Programming at an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will toggle at the address being programmed. 14/33 M29W800T, M29W800B Table 11. AC Measurement Conditions Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages ≤ 10ns 0 to 3V 1.5V 1N914 Figure 5. AC Testing Load Circuit 0.8V Figure 4. AC Testing Input Output Waveform DEVICE UNDER TEST 1.5V 0V AI01417 3.3kΩ OUT CL = 30pF or 100pF 3V CL includes JIG capacitance AI01968 Table 12. Capacitance (1) (TA = 25 °C, f = 1 MHz ) Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. Table 13. DC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C; VCC = 2.7V to 3.6V) Symbol ILI ILO ICC1 ICC1 ICC3 ICC4 (1) VIL VIH VOL VOH VID IID VLKO Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Byte Supply Current (Read) Word Supply Current (Standby) Supply Current (Program or Erase) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage CMOS A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage (Erase and Program lock-out) A9 = VID 2.0 IOL = 1.8mA IOH = –100µA VCC –0.4V 11.5 12.5 100 2.3 Test Condition 0V ≤ VIN ≤ VCC 0V ≤ VOUT ≤ VCC E = VIL, G = VIH, f = 6MHz E = VIL, G = VIH, f = 6MHz E = VCC ± 0.2V Byte program, Block or Chip Erase in progress –0.5 0.7 VCC Min Max ±1 ±1 10 10 100 20 0.8 VCC + 0.3 0.45 Unit µA µA mA mA µA mA V V V V V µA V Note: 1. Sampled only, not 100% tested. 15/33 M29W800T, M29W800B Table 14A. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Alt Parameter Test Condition -90 VCC = 3.0V to 3.6V C L = 30pF Min tAVAV tAVQV tELQX (1) tELQV (2) -100 VCC = 2.7V to 3.6V CL = 30pF Min 100 90 100 0 90 100 0 35 40 0 30 30 0 30 30 0 10 10 50 500 5 50 50 5 50 50 Max Unit Max tRC tACC tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL G = VIL E = VIL E = VIL E = VIL, G = VIL 90 ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns 0 tGLQX (1) tGLQV (2) tEHQX tEHQZ (1) tGHQX tGHQZ (1) tAXQX tPLYH (1,3) tPHEL tPLPX tELBL tELBH tBLQZ tBHQV 0 0 0 0 tRRB RP Low to Read Mode tREADY tRH tRP RP High to Chip Enable Low RP Pulse Width 50 500 tELFL Chip Enable to BYTE tELFH Switching Low or High tFLQZ tFHQV BYTE Switching Low to Output High Z BYTE Switching High to Output Valid Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode. 16/33 M29W800T, M29W800B Table 14B. Read AC Characteristics (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Alt Parameter Test Condition -120 VCC = 2.7V to 3.6V C L = 100pF Min tAVAV tAVQV tELQX (1) tELQV (2) tGLQX (1) tGLQV (2) tEHQX tEHQZ (1) tGHQX tGHQZ (1) tAXQX tPLYH (1,3) tPHEL tPLPX tELBL tELBH tBLQZ tBHQV tRC tACC tLZ tCE tOLZ tOE tOH tHZ tOH tDF tOH Address Valid to Next Address Valid Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Transition Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL G = VIL E = VIL E = VIL E = VIL, G = VIL 0 10 50 500 5 60 60 50 500 5 60 60 0 30 0 10 0 30 0 40 0 50 0 40 0 120 0 55 120 120 0 150 Max -150 VCC = 2.7V to 3.6V CL = 100pF Min 150 150 Max ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns Unit tRRB RP Low to Read Mode tREADY tRH tRP tELFL tELFH tFLQZ tFHQV RP High to Chip Enable Low RP Pulse Width Chip Enable to BYTE Switching Low or High BYTE Switching Low to Output High Z BYTE Switching High to Output Valid Notes: 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 3. To be considered only if the Reset pulse is given while the memory is in Erase or Program mode. 17/33 18/33 tAVAV VALID tAVQV tELQV tAXQX tEHQZ tELQX tEHQX tGLQV tGLQX VALID tBHQV tGHQX tGHQZ tELBL/tELBH tBLQZ ADDRESS VALID AND CHIP ENABLE OUTPUT ENABLE DATA VALID AI02182 M29W800T, M29W800B A0-A18/ A–1 Figure 6. Read Mode AC Waveforms E G DQ0-DQ7/ DQ8-DQ15 BYTE Note: Write Enable (W) = High. M29W800T, M29W800B Table 15A. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Alt Parameter -90 VCC = 3.0V to 3.6V C L = 30pF Min tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tVCHEL tWHGL tPHPHH (1,2) tPLPX tWHRL tPHWL (1) (1) -100 VCC = 2.7V to 3.6V CL = 30pF Min 100 0 50 50 0 0 30 0 50 0 50 0 500 500 90 90 4 Max Unit Max tWC tCS tWP tDS tDH tCH Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High 90 0 45 45 0 0 30 0 45 0 50 0 500 500 ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns µs tWPH Write Enable High to Write Enable Low tAS tAH Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tVCS tOEH VCC High to Chip Enable Low Write Enable High to Output Enable Low tVIDR RP Rise Time to VID tRP RP Pulse Width tBUSY Program Erase Valid to RB Delay tRSP RP High to Write Enable Low 4 Notes: 1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. 19/33 M29W800T, M29W800B Table 15B. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Alt Parameter -120 VCC = 2.7V to 3.6V CL = 100pF Min tAVAV tELWL tWLWH tDVWH tWHDX tWHEH tWHWL tAVWL tWLAX tGHWL tVCHEL tWHGL tPHPHH (1,2) tPLPX tWHRL tPHWL (1) (1) -150 VCC = 2.7V to 3.6V CL = 100pF Min 150 0 65 65 0 0 35 0 65 0 50 0 500 500 90 90 4 Max Unit Max tWC tCS tWP tDS tDH tCH Address Valid to Next Address Valid Chip Enable Low to Write Enable Low Write Enable Low to Write Enable High Input Valid to Write Enable High Write Enable High to Input Transition Write Enable High to Chip Enable High 120 0 50 50 0 0 30 0 50 0 50 0 500 500 ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns µs tWPH Write Enable High to Write Enable Low tAS tAH Address Valid to Write Enable Low Write Enable Low to Address Transition Output Enable High to Write Enable Low tVCS tOEH VCC High to Chip Enable Low Write Enable High to Output Enable Low tVIDR RP Rise Time to VID tRP RP Pulse Width tBUSY Program Erase Valid to RB Delay tRSP RP High to Write Enable Low 4 Notes: 1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Block Erase (BE) Instruction. This instruction uses a minimum of six write cycles. The Erase Set-up command 80h is written to address AAAAh in the Byte-wide configuration or address 5555h in the Word-wide configuration on third cycle after the two Coded cycles. The Block Erase Confirm command 30h is similarly written on the sixth cycle after another two Coded cycles. During the input of the second command an addresswithin the block to be erased is given and latched into the memory. Additional block Erase Confirm commands and block addresses can be written subsequently to erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description). Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input of a new Erase Confirm command will restart the timeout period. The status of the internal timer can be monitored through the level of DQ3, if DQ3 is ’0’ the Block Erase Command has been given and the timeout is running, if DQ3 is ’1’, the timeout has expired and the P/E.C. is erasing the Block(s). If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array. It is not necessary to program the block with 00h as the P/E.C. will do this automatically before to erasing to FFh. Read operations after the sixth rising edge of W or E output the status register status bits. 20/33 M29W800T, M29W800B Figure 7. Write AC Waveforms, W Controlled tAVAV A0-A18/ A–1 VALID tWLAX tAVWL E tELWL G tGHWL W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 VALID tWHDX tWLWH tWHGL tWHEH VCC tVCHEL RB tWHRL AI02183 Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W. During the executionof the erase by the P/E.C., the memory accepts only the Erase Suspend ES and Read/Reset RD instructions. Data Polling bit DQ7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. The Toggle bit DQ2 and DQ6 toggle during the erase operation. They stop when erase is completed. After completion the Status Register bit DQ5 returns’1’ if there has been an erase failure. In such a situation, the Toggle bit DQ2 can be used to determine which block is not correctly erased. In the case of erase failure, a Read/Reset RD instruction is necessary in order to reset the P/E.C. ChipErase (CE) Instruction. This instructionuses six write cycles. The Erase Set-up command 80h is written to address AAAAh in the Byte-wide configuration or the address 5555h in the Word-wide configurationon the third cycle after the two Coded cycles. The Chip Erase Confirm command 10h is similarly written on the sixth cycle after anothertwo Coded cycles. If the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts and the device is reset to Read Array. It is not necessaryto programthe array with 00h firstas theP/E.C. will automaticallydo this before erasing it to FFh. Read operations after the sixth rising edge of W or E output the Status Register bits. During the execution of the erase by the P/E.C., Data Polling bit DQ7 returns ’0’, then ’1’ on completion. The Toggle bits DQ2 and DQ6 toggle during erase operation and stop when erase is completed. After completion the Status Register bit DQ5 returns ’1’ if there has been an Erase Failure. 21/33 M29W800T, M29W800B Table 16A. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Alt Parameter -90 VCC = 3.0V to 3.6V C L = 30pF Min tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tVCHWL tEHGL tPHPHH (1,2) -100 VCC = 2.7V to 3.6V C L = 30pF Min 100 0 50 50 0 0 30 0 50 0 50 0 500 500 90 90 4 Max Unit Max tWC tWS tCP tDS tDH tWH tCPH tAS tAH Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low 90 0 45 45 0 0 30 0 45 0 50 0 500 500 ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns µs tVCS tOEH tVIDR tRP tBUSY tRSP VCC High to Write Enable Low Chip Enable High to Output Enable Low RP Rise TIme to VID RP Pulse Width Program Erase Valid to RB Delay RP High to Write Enable Low tPLPX tEHRL tPHWL (1) (1) 4 Notes: 1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Erase Suspend (ES) Instruction. The Block Erase operation may be suspendedby this instruction which consists of writing the command B0h without any specific address. No Coded cycles are required. It permits reading of data from another block and programming in another block while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during Erase timeout will, in addition to suspending the erase, terminate the timeout. The Toggle bit DQ6 stops toggling when the P/E.C. is suspended.The Toggle bits will stop toggling between 0.1µs and 15µs after the Erase Suspend (ES) command has been writ- ten. The device will then automatically be set to Read Memory Array mode. When erase is suspended, a Read from blocks being erased will output DQ2 toggling and DQ6 at ’1’. A Read from a block not being erased returns valid data. During suspension the memory will respond only to the Erase Resume ER and the Program PG instructions. A Program operation can be initiated during erase suspend in one of the blocks not being erased. It will result in both DQ2 and DQ6 toggling when the data is being programmed.A Read/Reset command will definitively abort erasure and result in invalid data in the blocks being erased. 22/33 M29W800T, M29W800B Table 16B. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Alt Parameter -120 VCC = 2.7V to 3.6V CL = 100pF Min tAVAV tWLEL tELEH tDVEH tEHDX tEHWH tEHEL tAVEL tELAX tGHEL tVCHWL tEHGL tPHPHH (1,2) -150 VCC = 2.7V to 3.6V CL = 100pF Min 150 0 65 65 0 0 35 0 65 0 50 0 500 500 90 90 4 Max Unit Max tWC tWS tCP tDS tDH tWH tCPH tAS tAH Address Valid to Next Address Valid Write Enable Low to Chip Enable Low Chip Enable Low to Chip Enable High Input Valid to Chip Enable High Chip Enable High to Input Transition Chip Enable High to Write Enable High Chip Enable High to Chip Enable Low Address Valid to Chip Enable Low Chip Enable Low to Address Transition Output Enable High Chip Enable Low 120 0 50 50 0 0 30 0 50 0 50 0 500 500 ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns µs tVCS tOEH tVIDR tRP tBUSY tRSP VCC High to Write Enable Low Chip Enable High to Output Enable Low RP Rise TIme to VID RP Pulse Width Program Erase Valid to RB Delay RP High to Write Enable Low tPLPX tEHRL tPHWL (1) (1) 4 Notes: 1. Sample only, not 100% tested. 2. This timing is for Temporary Block Unprotection operation. Erase Resume (ER) Instruction. If an Erase Suspend instruction was previously executed, the erase operation may be resumed by giving the command 30h, at any address, and without any Coded cycles. POWER SUPPLY Power Up The memory Command Interfaceis reset on power up to Read Array. Either E or W must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of E and W. Any write cycle initiation is blocked when Vcc is below VLKO. Supply Rails Normal precautions must be taken for supply voltage decoupling; each device in a system should have the VCC rail decoupledwith a 0.1µF capacitor close to the VCC and VSS pins. The PCB trace widths should be sufficient to carry the VCC program and erase currents required. 23/33 M29W800T, M29W800B Figure 8. Write AC Waveforms, E Controlled tAVAV A0-A18/ A–1 VALID tELAX tAVEL W tWLEL G tGHEL E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 VALID tEHDX tELEH tEHGL tEHWH VCC tVCHWL RB tEHRL AI02184 Note: Address are latched on the falling edge of E, Data is latched on the rising edge of E. Figure 9. Read and Write AC Characteristics, RP Related E tPHEL W tPHWL RB RP tPLPX tPHPHH tPLYH AI02091 24/33 M29W800T, M29W800B Table 17A. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Parameter -90 VCC = 3.0V to 3.6V CL = 30pF Min Write Enable High to DQ7 Valid (Program, W Controlled) Write Enable High to DQ7 Valid (Chip Erase, W Controlled) Chip Enable High to DQ7 Valid (Program, E Controlled) Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) tQ7VQV tWHQV Q7 Valid to Output Valid (Data Polling) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Chip Erase) tEHQV Chip Enable High to Output Valid (Program) Chip Enable High to Output Valid (Chip Erase) Note: 1. All other timings are defined in Read AC Characteristics table. -100 VCC = 2.7V to 3.6V CL = 30pF Min 10 1.0 10 1.0 Max 2400 60 2400 60 40 10 1.0 10 1.0 2400 60 2400 60 Unit Max 2400 60 2400 60 35 10 1.0 10 1.0 ms sec µs sec ns µs sec µs sec tWHQ7V tEHQ7V 10 1.0 10 1.0 2400 60 2400 60 Table 17B. Data Polling and Toggle Bit AC Characteristics (1) (TA = 0 to 70°C, –20 to 85°C or –40 to 85°C) M29W800T / M29W800B Symbol Parameter -120 VCC = 2.7V to 3.6V CL = 100pF Min Write Enable High to DQ7 Valid (Program, W Controlled) Write Enable High to DQ7 Valid (Chip Erase, W Controlled) Chip Enable High to DQ7 Valid (Program, E Controlled) Chip Enable High to DQ7 Valid (Chip Erase, E Controlled) tQ7VQV tWHQV Q7 Valid to Output Valid (Data Polling) Write Enable High to Output Valid (Program) Write Enable High to Output Valid (Chip Erase) tEHQV Chip Enable High to Output Valid (Program) Chip Enable High to Output Valid (Chip Erase) Note: 1. All other timings are defined in Read AC Characteristics table. -150 VCC = 2.7V to 3.6V CL = 100pF Min 10 1.0 10 1.0 Max 2400 60 2400 60 55 10 1.0 10 1.0 2400 60 2400 60 Unit Max 2400 60 2400 60 50 10 1.0 10 1.0 ms sec µs sec ns µs sec µs sec tWHQ7V tEHQ7V 10 1.0 10 1.0 2400 60 2400 60 25/33 26/33 DATA OUTPUT VALID ADDRESS (WITHIN BLOCKS) tAVQV tELQV tEHQ7V tGLQV tWHQ7V DQ7 VALID IGNORE tQ7VQV VALID DATA POLLING READ CYCLES DATA POLLING (LAST) CYCLE MEMORY ARRAY READ CYCLE AI02185 M29W800T, M29W800B A0-A18/ A–1 E Figure 10. Data Polling DQ7 AC Waveforms G W DQ7 DQ0-DQ6/ DQ8-DQ15 LAST WRITE CYCLE OF PROGRAM OR ERASE INSTRUCTION M29W800T, M29W800B Figure 11. Data Polling Flowchart Figure 12. Data Toggle Flowchart START START READ DQ5 & DQ7 at VALID ADDRESS READ DQ2, DQ5 & DQ6 DQ7 = DATA NO NO YES DQ2, DQ6 = TOGGLE YES NO NO DQ5 =1 YES READ DQ7 DQ5 =1 YES READ DQ2, DQ6 DQ7 = DATA NO FAIL YES DQ2, DQ6 = TOGGLE YES PASS FAIL NO PASS AI01369 AI01873 Table 18. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70°C; VCC = 2.7V to 3.6V) M29W800T / M29W800B Parameter Min Chip Erase (Preprogrammed) Chip Erase Boot Block Erase Parameter Block Erase Main Block (32Kb) Erase Main Block (64Kb) Erase Chip Program (Byte) Byte Program Word Program Program/Erase Cycles (per Block) 100,000 Typ 5 12 2.4 2.3 2.7 3.3 8 10 20 8 10 20 15 Typical after 100k W/E Cycles 5 12 Unit Max sec sec sec sec sec sec sec µs µs cycles 27/33 28/33 VALID tEHQV tAVQV tELQV tGLQV tWHQV STOP TOGGLE VALID IGNORE VALID DATA TOGGLE READ CYCLE DATA TOGGLE READ CYCLE MEMORY ARRAY READ CYCLE AI02186 M29W800T, M29W800B A0-A18/ A–1 E G Figure 13. Data Toggle DQ6, DQ2 AC Waveforms W DQ6,DQ2 DQ0-DQ1,DQ3-DQ5,DQ7/ DQ8-DQ15 LAST WRITE CYCLE OF PROGRAM OF ERASE INSTRUCTION Note: All other timings are as a normal Read cycle. M29W800T, M29W800B ORDERING INFORMATION SCHEME Example: M29W800T -90 N 1 TR Operating Voltage W 2.7V to 3.6V R TR Option Reverse Pinout Tape & Reel Packing Array Matrix T B Top Boot Bottom Boot Speed -90 90ns -100 100ns -120 120ns -150 150ns M N Package TSOP48 12 x 20mm SO44 1 5 6 Temp. Range 0 to 70 °C –20 to 85 °C –40 to 85 °C M29W800T and M29W800B are replaced respectively by the new version M29W800AT and M29W800AB Devices are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further informationon any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 29/33 M29W800T, M29W800B TSOP48 Normal Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm Symb Typ A A1 A2 B C D D1 E e L α N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 0.50 0° 48 0.10 mm Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 0.70 5° 0.020 0.002 0.037 0.007 0.004 0.780 0.720 0.469 0.020 0° 48 0.004 Typ inches Min Max 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.476 0.028 5° A2 1 N e E B N/2 D1 D A CP DIE C TSOP-a Drawing is not to scale. A1 α L 30/33 M29W800T, M29W800B TSOP48 Reverse Pinout - 48 lead Plastic Thin Small Outline, 12 x 20mm Symb Typ A A1 A2 B C D D1 E e L α N CP 0.50 0.05 0.95 0.17 0.10 19.80 18.30 11.90 – 0.50 0° 48 0.10 mm Min Max 1.20 0.15 1.05 0.27 0.21 20.20 18.50 12.10 – 0.70 5° 0.020 0.002 0.037 0.007 0.004 0.780 0.720 0.469 – 0.020 0° 48 0.004 Typ inches Min Max 0.047 0.006 0.041 0.011 0.008 0.795 0.728 0.476 – 0.028 5° A2 1 N e E B N/2 D1 D A CP DIE C TSOP-b A1 α L Drawing is not to scale. 31/33 M29W800T, M29W800B SO44 - 44 lead Plastic Small Outline, 525 mils body width Symb Typ A A1 A2 B C D E e H L α N CP 0.80 3° 44 0.10 1.27 15.90 16.10 0.031 3° 44 0.004 0.10 28.10 13.20 mm Min 2.42 0.22 2.25 Max 2.62 0.23 2.35 0.50 0.25 28.30 13.40 0.050 0.626 0.634 0.004 1.106 0.520 Typ inches Min 0.095 0.009 0.089 Max 0.103 0.010 0.093 0.020 0.010 1.114 0.528 A2 B e D A C CP N E 1 H A1 α L SO-b Drawing is not to scale. 32/33 M29W800T, M29W800B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Spec ifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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