M34C02-RDW6TP

M34C02 2 Kbit Serial I²C Bus EEPROM For DIMM Serial Presence Detect FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Software Data Protection for lower 128 Bytes Two Wire I2C Serial Interface 100kHz and 400kHz Transfer Rates Single Supply Voltage: – 2.5 to 5.5V up to 400kHz for M34C02-W – 2.2 to 5.5V up to 400kHz for M34C02-L – 1.8 to 5.5V up to 400kHz for M34C02-R – 1.7 to 3.6V up to 100kHz for M34C02-F BYTE and PAGE WRITE (up to 16 bytes) RANDOM and SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Protection More than 1 Million Erase/Write Cycles More than 40 Year Data Retention Packages – ECOPACK® (RoHS compliant) Figure 1. Packages 8 1 PDIP8 (BN) TSSOP8 (DW) 169 mil width Table 1. Product List Reference Part Number M34C02-W M34C02-L M34C02 M34C02-R TSSOP8 (DS) 3x3mm² body size (MSOP) M34C02-F UFDFPN8 (MB) 2x3mm² (MLP) October 2005 1/28 M34C02 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. DIP, TSSOP and MLP Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Chip Enable input connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 5. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I²C Bus . . . . . . . . . . . 6 Figure 6. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 7. Setting the Write Protection Register (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Setting the Software Write-Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. Result of Setting the Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Write Mode Sequences in a Non Write-Protected Area . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10.Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 11.Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 USE WITHIN A DRAM DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2/28 M34C02 Programming the M34C02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. DRAM DIMM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 12.Serial Presence Detect Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Operating Conditions (M34C02-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Operating Conditions (M34C02-L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 9. Operating Conditions (M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Operating Conditions (M34C02-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 13. DC Characteristics (M34C02-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 14. DC Characteristics (M34C02-L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 15. DC Characteristics (M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 16. DC Characteristics (M34C02-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 17. AC Characteristics (M34C02-W, M34C02-L, M34C02-R) . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 18. AC Characteristics (M34C02-F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 14.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 22 Table 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 22 Figure 16.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 17.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 24 Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 24 Figure 18.TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Outline . . . . 25 Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Data . . . . . . 25 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 23. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 24. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/28 M34C02 SUMMARY DESCRIPTION The M34C02 is a 2Kbit serial EEPROM memory able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual interline memory modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. This bottom half of the memory area can be writeprotected using a specially designed software write protection mechanism. By sending the device a specific sequence, the first 128 Bytes of the memory become permanently write protected. Care must be taken when using this sequence as its effect cannot be reversed. In addition, the device allows the entire memory area to be write protected, using the WC input (for example by tieing this input to VCC). These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits. In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. access the memory area and a second Device Type Identifier Code (0110) to access the Protection Register. These codes are used together with three chip enable inputs (E2, E1, E0) so that up to eight 2Kbit devices may be attached to the I²C bus and selected individually. The device behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 3.), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ. Figure 3. DIP, TSSOP and MLP Connections (Top View) M34C02 E0 E1 E2 Figure 2. Logic Diagram VSS VCC 1 2 3 4 8 7 6 5 VCC WC SCL SDA AI01932C 3 E0-E2 SCL SDA M34C02 Table 2. Signal Names WC VSS AI01931 I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to 4/28 Note: See PACKAGE MECHANICAL section for package dimensions, and how to identify pin-1. E0, E1, E2 Chip Enable SDA Serial Data SCL Serial Clock WC Write Control VCC Supply Voltage VSS Ground M34C02 Device Internal Reset In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (continuous rise up of VCC), the device will not respond to any instruction until the VCC has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VCC operating voltage (as defined in Table 7. to Table 10.). When VCC has passed over the POR threshold, the device is reset and is in Standby Power mode. Prior to selecting and issuing instructions to the memory, a valid and stable VCC voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). At Power-down (continuous decay of VCC), as soon as VCC drops from the normal operating voltage, below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. 5/28 M34C02 SIGNAL DESCRIPTION Serial Clock (SCL) This input signal is used to strobe all data in and out of the device. In applications where this signal is used by slave devices to synchronize the bus to a slower clock, the bus master must have an open drain output, and a pull-up resistor can be connected from Serial Clock (SCL) to VCC. (Figure 5. indicates how the value of the pull-up resistor can be calculated). In most applications, though, this method of synchronization is not employed, and so the pull-up resistor is not necessary, provided that the bus master has a push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal is used to transfer data in or out of the device. It is an open drain output that may be wire-OR’ed with other open drain or open collector signals on the bus. A pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5. indicates how the value of the pull-up resistor can be calculated). Chip Enable (E0, E1, E2) These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. These inputs must be tied to VCC or VSS to establish the Device Select Code. Figure 4. Chip Enable input connection VCC VCC M34Cxx M34Cxx Ei Ei VSS VSS Ai11650a Write Control (WC) This input signal is provided for protecting the contents of the whole memory from inadvertent write operations. Write Control (WC) is used to enable (when driven Low) or disable (when driven High) write instructions to the entire memory area or to the Protection Register. When Write Control (WC) is tied Low or left unconnected, the write protection of the first half of the memory is determined by the status of the Protection Register. Figure 5. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I²C Bus VCC Maximum RP value (kΩ) 20 16 RP 12 RP SDA MASTER 8 fc = 100kHz 4 fc = 400kHz C SCL C 0 10 100 1000 C (pF) AI01665b 6/28 M34C02 Figure 6. I2C Bus Protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition AI00792B Table 3. Device Select Code Device Type Identifier1 Chip Enable Address2 RW b7 b6 b5 b4 b3 b2 b1 b0 Memory Area Select Code (two arrays) 1 0 1 0 E2 E1 E0 RW Protection Register Select Code 0 1 1 0 E2 E1 E0 RW Note: 1. The most significant bit, b7, is sent first. 2. E0, E1 and E2 are compared against the respective external pins on the memory device. 7/28 M34C02 DEVICE OPERATION The device supports the I2C protocol. This is summarized in Figure 6.. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which will also provide the serial clock for synchronization. The memory device is always a slave in all communication. Start Condition Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in the High state. A Start condition must precede any data transfer command. The device continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock (SCL) for a Start condition, and will not respond unless one is given. Stop Condition Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable and driven High. A Stop condition terminates communication between the device and the bus master. A Read command that is followed by NoAck can be followed by a Stop condition to force the device into the Stand-by mode. A Stop condition at the end of a Write command triggers the internal EEPROM Write cycle. Acknowledge Bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) Low to acknowledge the receipt of the eight data bits. Data Input During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock (SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock (SCL) is driven Low. Memory Addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 3. (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable “Address” (E2, E1, E0). To address the memory array, the 4bit Device Type Identifier is 1010b; to address the Protection Register, it is 0110b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (E0, E1, E2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode. Table 4. Operating Modes Mode Current Address Read RW bit WC 1 Bytes 1 X 1 0 X Random Address Read Initial Sequence START, Device Select, RW = 1 START, Device Select, RW = 0, Address 1 1 X Sequential Read 1 X ≥1 Byte Write 0 VIL 1 START, Device Select, RW = 0 Page Write 0 VIL ≤ 16 START, Device Select, RW = 0 Note: 1. X = VIH or VIL. 8/28 reSTART, Device Select, RW = 1 Similar to Current or Random Address Read M34C02 CONTROL BYTE WORD ADDRESS STOP BUS ACTIVITY MASTER START Figure 7. Setting the Write Protection Register (WC = 0) DATA SDA LINE BUS ACTIVITY ACK ACK ACK VALUE VALUE (DON'T CARE) (DON'T CARE) AI01935B Setting the Software Write-Protection The M34C02 has a hardware write-protection feature, using the Write Control (WC) signal. This signal can be driven High or Low, and must be held constant for the whole instruction sequence. When Write Control (WC) is held Low, the whole memory array (addresses 00h to FFh) is write protected. When Write Control (WC) is held High, the write protection of the memory array is dependent on whether software write-protection has been set. Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh) to be permanently write protected irrespective of subsequent states of the Write Control (WC) signal. The write protection feature is activated by writing once to the Protection Register. The Protection Register is accessed with the device select code set to 0110b (as shown in Table 3.), and the E2, E1 and E0 bits set according to the states being applied on the E2, E1 and E0 signals. As for any other write command, Write Control (WC) needs to be held Low. Address and data bytes must be sent with this command, but their values are all ignored, and are treated as Don’t Care. Once the Protection Register has been written, the write protection of the first 128 Bytes of the memory is enabled, and it is not possible to unprotect these 128 Bytes, even if the device is powered off and on, and regardless the state of Write Control (WC). When the Protection Register has been written, the M34C02 no longer responds to the device type identifier 0110b in either read or write mode. Figure 8. Result of Setting the Write Protection FFh Standard Array Memory Area FFh Standard Array 80h 7Fh Standard Array 00h Default EEPROM memory area state before write access to the Protect Register Write Protected Array 80h 7Fh 00h State of the EEPROM memory area after write access to the Protect Register AI01936C 9/28 M34C02 Figure 9. Write Mode Sequences in a Non Write-Protected Area ACK BYTE ADDR R/W ACK ACK DEV SEL START PAGE WRITE DATA IN STOP DEV SEL START BYTE WRITE ACK ACK BYTE ADDR ACK DATA IN 1 DATA IN 2 R/W ACK ACK STOP DATA IN N AI01941 Write Operations Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 9., and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests. Byte Write After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device 10/28 replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 9.. Page Write The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as ‘rollover’ occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the locations are not modified. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. M34C02 Figure 10. Write Cycle Polling Flowchart using ACK WRITE Cycle in Progress START Condition DEVICE SELECT with RW = 0 NO ACK Returned YES First byte of instruction with RW = 0 already decoded by the device NO Next Operation is Addressing the Memory YES Send Address and Receive ACK ReSTART NO STOP START Condition YES DATA for the WRITE Operation DEVICE SELECT with RW = 1 Continue the WRITE Operation Continue the Random READ Operation Minimizing System Delays by Polling On ACK During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown in Table 17. and Table 18., but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 10., is: – – – AI01847C Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). 11/28 M34C02 Figure 11. Read Mode Sequences ACK DATA OUT STOP START DEV SEL NO ACK R/W ACK START DEV SEL * ACK BYTE ADDR R/W ACK START DEV SEL DATA OUT R/W ACK ACK NO ACK DATA OUT N DATA OUT 1 R/W ACK START DEV SEL * ACK BYTE ADDR R/W ACK ACK DEV SEL * START SEQUENTIAL RANDOM READ DEV SEL * NO ACK STOP SEQUENTIAL CURRENT READ ACK START RANDOM ADDRESS READ STOP CURRENT ADDRESS READ ACK DATA OUT 1 R/W NO ACK STOP DATA OUT N AI01942 Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 3rd bytes) must be identical. Read Operations Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read. Random Address Read A dummy Write is first performed to load the address into this address counter (as shown in Figure 11.) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, 12/28 and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition. Current Address Read For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 11., without acknowledging the byte. M34C02 Sequential Read This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 11.. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter ‘rolls-over’, and the device continues to output data from memory address 00h. Acknowledge in Read Mode For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode. USE WITHIN A DRAM DIMM In the application, the M34C02 is soldered directly in the printed circuit module. The 3 Chip Enable inputs (pins 1, 2 and 3) are wired at VCC or VSS through the DIMM socket (see Table 5.). The pullup resistors needed for normal behavior of the I2C bus are connected on the I2C bus of the motherboard (as shown in Figure 12.). The Write Control (WC) of the M34C02 can be left unconnected. However, connecting it to VSS is recommended, to maintain full read and write access. Programming the M34C02 When the M34C02 is delivered, full read and write access is given to the whole memory array. It is recommended that the first step is to use the test equipment to write the module information (such as its access speed, its size, its organization) to the first half of the memory, starting from the first memory location. When the data has been validated, the test equipment can send a Write command to the Protection Register, using the device select code ’01100000b’ followed by an address and data byte (made up of Don’t Care values) as shown in Figure 7.. The first 128 bytes of the memory area are then write-protected, and the M34C02 will no longer respond to the specific device select code ’0110000xb’. It is not possible to reverse this sequence. Table 5. DRAM DIMM Connections DIMM Position E2 E1 E0 0 VSS VSS VSS 1 VSS VSS VCC 2 VSS VCC VSS 3 VSS VCC VCC 4 VCC VSS VSS 5 VCC VSS VCC 6 VCC VCC VSS 7 VCC VCC VCC INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). 13/28 M34C02 Figure 12. Serial Presence Detect Block Diagram R = 4.7kΩ DIMM Position 7 E2 E1 E0 SCL SDA E0 SCL SDA VCC DIMM Position 6 E2 E1 VCC VSS DIMM Position 5 E2 E1 E0 SCL SDA VCC VSS VCC DIMM Position 4 E2 E1 VCC E0 SCL SDA VSS DIMM Position 3 E2 E1 VSS E0 SCL SDA VCC DIMM Position 2 E2 E1 E0 SCL SDA VSS VCC VSS DIMM Position 1 E2 E1 VSS E0 SCL SDA VCC DIMM Position 0 E2 E1 E0 SCL SDA VSS SCL line AI01937 SDA line From the motherboard I2C master controller Note: 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices. 2. Common clock and common data are shared across all the devices. 3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 kΩ) because these lines are open drain when used as outputs. 14/28 M34C02 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute Maximum Ratings Symbol Min. Max. Unit Ambient Operating Temperature –40 90 °C TSTG Storage Temperature –65 150 °C TLEAD Lead Temperature during Soldering 1 TA Parameter See Note: 1. °C VIO Input or Output Voltage –0.50 6.5 V VCC Supply Voltage –0.50 6.5 V VESD Electrostatic Discharge Voltage (Human Body model) 2 –4000 4000 V Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω) ECOPACK® 7191395 specification, and 15/28 M34C02 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7. Operating Conditions (M34C02-W) Symbol VCC TA Parameter Min. Max. Unit Supply Voltage 2.5 5.5 V Ambient Operating Temperature –40 85 °C Min. Max. Unit Supply Voltage 2.2 5.5 V Ambient Operating Temperature –40 85 °C Min. Max. Unit Supply Voltage 1.8 5.5 V Ambient Operating Temperature –40 85 °C Min. Max. Unit 1.7 3.6 V 0 70 °C Table 8. Operating Conditions (M34C02-L) Symbol VCC TA Parameter Table 9. Operating Conditions (M34C02-R) Symbol VCC TA Parameter Table 10. Operating Conditions (M34C02-F) Symbol VCC TA 16/28 Parameter Supply Voltage Ambient Operating Temperature M34C02 Table 11. AC Measurement Conditions Symbol CL Parameter Min. Load Capacitance Max. 100 Input Rise and Fall Times Unit pF 50 ns Input Levels 0.2VCC to 0.8VCC V Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V Figure 13. AC Measurement I/O Waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 12. Input Parameters Symbol Parameter1,2 Test Condition Min. Max. Unit CIN Input Capacitance (SDA) 8 pF CIN Input Capacitance (other pins) 6 pF 70 kΩ ZWCL WC Input Impedance VIN < 0.3 V 15 ZWCH WC Input Impedance VIN > 0.7VCC 500 Pulse width ignored (Input Filter on SCL and SDA) Single glitch tNS kΩ 100 ns Note: 1. TA = 25°C, f = 400kHz 2. Sampled only, not 100% tested. 17/28 M34C02 Table 13. DC Characteristics (M34C02-W) Symbol ILI Input Leakage Current (SCL, SDA, E0, E1,and E2) ILO Output Leakage Current ICC Supply Current ICC1 Test Condition (in addition to those in Table 7.) Parameter Min. Max. Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC=5V, fc=400kHz (rise/fall time < 30ns) 2 mA VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA VIN = VSS or VCC , VCC = 5 V 1 µA VIN = VSS or VCC , VCC = 2.5 V 0.5 µA Stand-by Supply Current VIL Input Low Voltage (1) –0.45 0.3VCC V VIH Input High Voltage (1) 0.7VCC VCC+1 V VOL Output Low Voltage 0.4 V Max. Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC =5V, fc=400kHz (rise/fall time < 30ns) 2 mA VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA VCC =2.2V, fc=400kHz (rise/fall time < 30ns) 1 mA VIN = VSS or VCC , VCC = 5 V 1 µA VIN = VSS or VCC , 2.2V ≤ VCC < 2.5V 0.5 µA IOL = 2.1 mA, VCC = 2.5 V Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm. Table 14. DC Characteristics (M34C02-L) Symbol Parameter ILI Input Leakage Current (SCL, SDA) ILO Output Leakage Current ICC ICC1 VIL Supply Current Stand-by Supply Current Min. Input Low Voltage (E2, E1, E0, SCL, SDA) –0.3 0.3VCC V Input Low Voltage (WC) –0.3 0.5 V 0.7VCC VCC+1 V IOL = 3mA, VCC = 5V 0.4 V IOL = 2.1mA, 2.2V ≤ VCC < 2.5V 0.4 V VIH Input High Voltage (E2, E1, E0, SCL, SDA, WC) VOL Output Low Voltage 18/28 Test Condition (in addition to those in Table 8.) M34C02 Table 15. DC Characteristics (M34C02-R) Symbol Parameter ILI Input Leakage Current (SCL, SDA, E0, E1 and E2) ILO Output Leakage Current ICC ICC1 VIL VIH VOL Supply Current Stand-by Supply Current Test Condition (in addition to those in Table 9.) Min. Max. Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC =5V, fc=400kHz (rise/fall time < 30ns) 2 mA VCC =2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA VCC =1.8V, fc=400kHz (rise/fall time < 30ns) 1 mA VIN = VSS or VCC , VCC = 5V 1 µA VIN = VSS or VCC , 1.8V ≤ VCC < 2.5V 0.5 µA 2.5V ≤ VCC ≤ 5.5V – 0.3 0.3 VCC V 1.8V ≤ VCC < 2.5V – 0.3 0.25 VCC V 0.7VCC VCC+1 V IOL = 3mA, VCC = 5V 0.4 V IOL = 2.1mA, 2.2V ≤ VCC < 2.5V 0.4 V IOL = 0.15mA, VCC = 1.8V 0.2 V Max.1 Unit VIN = VSS or VCC ±2 µA VOUT = VSS or VCC, SDA in Hi-Z ±2 µA VCC =1.7V, fc=100kHz (rise/fall time < 30ns) 1 mA VIN = VSS or VCC , VCC = 3.6V 1 µA VIN = VSS or VCC , 1.7V ≤ VCC < 2.5V 0.5 µA Input Low Voltage (1) Input High Voltage (1) Output Low Voltage Note: 1. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm. Table 16. DC Characteristics (M34C02-F) Symbol Parameter ILI Input Leakage Current (SCL, SDA, E0, E1 and E2) ILO Output Leakage Current ICC Supply Current ICC1 Stand-by Supply Current VIL Input Low Voltage (2) VIH Input High Voltage (2) VOL Output Low Voltage Test Condition (in addition to those in Table 10.) Min.1 2.5V ≤ VCC ≤ 3.6V – 0.3 0.3 VCC V 1.7V ≤ VCC < 2.5V – 0.3 0.25 VCC V 0.7VCC VCC+1 V IOL = 2.1mA, 2.2V ≤ VCC ≤ 3.6V 0.4 V IOL = 0.15mA, VCC = 1.7V 0.2 V Note: 1. Preliminary Data. 2. The voltage source driving only E0, E1 and E2 inputs must provide an impedance of less than 1kOhm. 19/28 M34C02 Table 17. AC Characteristics (M34C02-W, M34C02-L, M34C02-R) Test conditions specified in Table 11. and Table 7. or Table 8. Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock Frequency 400 kHz tCHCL tHIGH Clock Pulse Width High 600 ns tCLCH tLOW Clock Pulse Width Low 1300 ns tDL1DL2 2 tF tDXCX SDA Fall Time 20 tSU:DAT Data In Set Up Time 100 ns tCLDX tHD:DAT Data In Hold Time 0 ns tCLQX tDH Data Out Hold Time 200 ns tAA Clock Low to Next Data Valid (Access Time) 200 tCLQV 3 300 900 ns ns tCHDX 1 tSU:STA Start Condition Set Up Time 600 ns tDLCL tHD:STA Start Condition Hold Time 600 ns tCHDH tSU:STO Stop Condition Set Up Time 600 ns tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns tW tWR Write Time 10 ms Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. Table 18. AC Characteristics (M34C02-F) Test conditions specified in Table 11. and Table 9. or Table 10. Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock Frequency 100 kHz tCHCL tHIGH Clock Pulse Width High 4000 ns tCLCH tLOW Clock Pulse Width Low 4700 ns tDL1DL2 2 tF tDXCX SDA Fall Time 20 300 tSU:DAT Data In Set Up Time 250 ns tCLDX tHD:DAT Data In Hold Time 0 ns tCLQX tDH Data Out Hold Time 200 ns tCLQV 3 tAA Clock Low to Next Data Valid (Access Time) 200 tCHDX 1 tSU:STA Start Condition Set Up Time 4700 ns tDLCL tHD:STA Start Condition Hold Time 4000 ns tCHDH tSU:STO Stop Condition Set Up Time 4000 ns tDHDL tBUF Time between Stop Condition and Next Start Condition 4700 ns tW tWR Write Time 3500 10 ns ns ms Note: 1. For a reSTART condition, or following a Write cycle. 2. Sampled only, not 100% tested. 3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 20/28 M34C02 Figure 14. AC Waveforms tCHCL tCLCH SCL tDLCL SDA In tCHDX tCLDX START Condition SDA Input SDA tDXCX Change tCHDH tDHDL START STOP Condition Condition SCL SDA In tCHDH tW STOP Condition Write Cycle tCHDX START Condition SCL tCLQV SDA Out tCLQX Data Valid AI00795C 21/28 M34C02 PACKAGE MECHANICAL Figure 15. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B Note: Drawing is not to scale. Table 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data mm inches Symb. Typ. Min. A Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.008 0.014 D 9.27 9.02 10.16 0.365 0.355 0.400 E 7.87 7.62 8.26 0.310 0.300 0.325 E1 6.35 6.10 7.11 0.250 0.240 0.280 e 2.54 – – 0.100 – – eA 7.62 – – 0.300 – – eB L 22/28 Max. 10.92 3.30 2.92 3.81 0.430 0.130 0.115 0.150 M34C02 Figure 16. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Package Outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 Note: 1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 20. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Package Mechanical Data mm inches Symbol A Typ. Min. Max. Typ. Min. Max. 0.55 0.50 0.60 0.022 0.020 0.024 0.00 0.05 0.000 0.002 0.20 0.30 0.008 0.012 0.061 0.065 A1 b 0.25 D 2.00 D2 0.079 1.55 ddd E 0.010 1.65 0.05 3.00 E2 0.002 0.118 0.15 0.25 0.006 0.010 e 0.50 – – 0.020 – – L 0.45 0.40 0.50 0.018 0.016 0.020 L1 0.15 L3 N 0.006 0.30 8 0.012 8 23/28 M34C02 Figure 17. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM Note: Drawing is not to scale. Table 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data mm inches Symbol Typ. Min. A 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ. Min. 1.200 A1 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 – – 0.0256 – – E 6.400 6.200 6.600 0.2520 0.2441 0.2598 E1 4.400 4.300 4.500 0.1732 0.1693 0.1772 L 0.600 0.450 0.750 0.0236 0.0177 0.0295 L1 1.000 0° 8° α 24/28 Max. 0.0394 0° 8° M34C02 Figure 18. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8BM Note: Drawing is not to scale. Table 22. TSSOP8 3x3mm² – 8 lead Thin Shrink Small Outline, 3x3mm² body size, Data mm inches Symbol Typ. Min. A Max. Min. 1.100 A1 0.050 0.150 0.750 0.950 b 0.250 c A2 Typ. 0.850 Max. 0.0433 0.0020 0.0059 0.0295 0.0374 0.400 0.0098 0.0157 0.130 0.230 0.0051 0.0091 0.0335 D 3.000 2.900 3.100 0.1181 0.1142 0.1220 E 4.900 4.650 5.150 0.1929 0.1831 0.2028 E1 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 – – 0.0256 – – CP 0.100 L 0.550 L1 0.950 α 0.400 0.700 0.0039 0.0217 0.0157 0.0276 0° 6° 0.0374 0° 6° 25/28 M34C02 PART NUMBERING Table 23. Ordering Information Scheme Example: M34C02 – W MB 6 T P Device Type M34 = ASSP I2C serial access EEPROM Device Function 02 = 2 Kbit (256 x 8) Operating Voltage W = VCC = 2.5 to 5.5V (400kHz) L = VCC = 2.2 to 5.5V (400kHz) R = VCC = 1.8 to 5.5V (400kHz) F = VCC = 1.7 to 3.6V (100kHz) Package BN1= PDIP8 MB = UDFDFPN8 (MLP8) DW = TSSOP8 (169 mil width) DS = TSSOP8 (3x3mm² body size, MSOP8) Device Grade 6 = Industrial temperature range, –40 to 85 °C. Device tested with standard test flow 1 = Temperature range 0 to 70 °C. Device tested with standard test flow Option blank = Standard Packing T = Tape and Reel Packing Plating Technology blank = Standard SnPb plating P or G = ECOPACK® (RoHS compliant) Note: 1. Package available only on request. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 26/28 The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. M34C02 REVISION HISTORY Table 24. Revision History Date Rev. Description of Revision 27-Dec-1999 2.0 Adjustments to the formatting. 0 to 70°C temperature range removed from DC and AC tables. No change to description of device, or parameters 07-Dec-2000 2.1 New definition of lead soldering temperature absolute rating for certain packages 13-Mar-2001 2.2 -R voltage range added 18-Jul-2002 2.3 TSSOP8 (3x3mm² body size) package (MSOP8) added 22-May-2002 2.4 VFDFPN8 package (MLP8) added 21-Jul-2003 3.0 Document reformatted. -F voltage range added. 17-Mar-2004 4.0 Table of Contents added. MLP package changed. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified 14-Apr-2004 5.0 Typos corrected in Ordering Information example 26-Aug-2004 6.0 Device Grade clarified. Product List summary table added 30-Nov-2004 7.0 SO8 package removed. 8.0 M34C02-R operating frequency upgraded to 400 kHz. Modified Device Internal Reset, page 5, Figure 5., Maximum RP Value versus Bus Parasitic Capacitance (C) for an I²C Bus, Table 12., Input Parameters, ICC1 values in Table 13., DC Characteristics (M34C02-W), Table 15., DC Characteristics (M34C02-R), Table 16., DC Characteristics (M34C02-F) and moved M34C02-R to Table 17., AC Characteristics (M34C02-W, M34C02-L, M34C02-R). Added Figure 4., Chip Enable input connection. Added EcoPack® and Ambient Operating Temperature information. 14-Oct-2005 27/28 M34C02 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 28/28